Electrostatic discharge protection ggnmos structure

Abstract

The application provides a static discharge protection GGNMOS structure, which comprises a substrate, a deep isolation structure, a ring-shaped N-type well region, a first P-type well region, a second P-type well region, a first N-type heavily doped region, a second N-type heavily doped region, a third N-type heavily doped region, a first gate oxide layer, a second gate oxide layer, a first ring-shaped P-type heavily doped region, a second ring-shaped P-type heavily doped region, a third ring-shaped P-type heavily doped region, a ring-shaped N-type heavily doped region and a plurality of shallow isolation structures. The second ring-shaped P-type heavily doped region is arranged at the periphery of the first ring-shaped P-type heavily doped region, so that the second ring-shaped P-type heavily doped region, the ring-shaped N-type well region and the first P-type well region form SCR discharge current channels with the first N-type heavily doped region and the third N-type heavily doped region respectively, thereby improving the robustness of the static discharge protection GGNMOS structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of ESD protection circuit design of semiconductor integrated chips, and particularly relates to a static discharge protection GGNMOS structure. BACKGROUND

[0002] With the feature size of the manufacturing process of semiconductor integrated circuits becoming smaller and smaller, the size of the chip unit is also becoming smaller and smaller, and the anti-static ability of the chip is becoming more and more important. The destructive effect of electrostatic discharge on IC chips is more significant. Static electricity often causes a permanent damage to semiconductor components and computer systems, thereby affecting the circuit function of the integrated circuit and making the electronic product work abnormally, so some protection measures or functions must be designed to protect the chip from the damage caused by electrostatic discharge.

[0003] The design of the electrostatic discharge (ESD) protection device on the chip needs to consider two aspects: one is that the ESD protection device should be able to discharge large current; the other is that the ESD protection device should be able to clamp the pin end voltage of the chip to a safe low voltage level when the chip is subjected to ESD impact. Based on the above design considerations, the devices used for ESD protection mainly include diodes, GGNMOS (Gate Ground NMOS), GDPMOS (Gate Drain PMOS), silicon controlled rectifiers (SCR), etc. Among them, the SCR has single-direction, double-direction, turn-off and light control types, and has the advantages of small size, light weight, high efficiency, long service life, convenient control, etc., and is widely used in automatic control and high-power electric energy conversion occasions such as controllable rectification, voltage regulation, inversion and non-contact switch. The SCR is often used as an ESD protection device, especially for high-voltage ESD protection applications, and the SCR has the advantages of small area and high ESD capacity.

[0004] Currently, a conventional ESD protection GGNMOS device with P Ring (a ring-shaped P-type heavily doped region, a ring-shaped P-type well region located at the bottom of the ring-shaped P-type heavily doped region), N Ring (a ring-shaped N-type heavily doped region, a ring-shaped P-type well region located at the bottom of the ring-shaped N-type heavily doped region) generally includes: a Drain (an N-type heavily doped region, actually), an N Ring, a P Ring, a Bulk (a body region), a Source (an N-type heavily doped region, actually), a Gate (a gate), a P-type well region, and an N-type well region, etc., wherein the Source, the Drain (an N-type heavily doped region, actually), and the N Ring are short-circuited to form an Anode (anode) end, and the P Ring, the Bulk (a body region), the Source (an N-type heavily doped region, actually), and the Gate (a gate) are short-circuited to form a Cathode (cathode) end. When an ESD voltage is applied to the Anode end, an NPN formed by the Drain, the P-type well region, and the Source is turned on to form a main ESD current discharge channel. However, the robustness of such a conventional ESD protection GGNMOS device is poor, and a large chip area is consumed to achieve a high protection level. SUMMARY

[0005] The present application provides an ESD protection GGNMOS structure, which can solve at least one of the problems of poor robustness and large chip area consumption of a conventional ESD protection GGNMOS device.

[0006] In one aspect, an ESD protection GGNMOS structure is provided, which includes: a substrate, a deep isolation structure, a ring-shaped N-type well region, a first P-type well region, a second P-type well region, a first N-type heavily doped region, a second N-type heavily doped region, a third N-type heavily doped region, a first gate oxide layer, a second gate oxide layer, a first ring-shaped P-type heavily doped region, a second ring-shaped P-type heavily doped region, a third ring-shaped P-type heavily doped region, a ring-shaped N-type heavily doped region, and a plurality of shallow isolation structures.

[0007] The deep isolation structure covers the substrate, the ring-shaped N-type well region, the first P-type well region, and the second P-type well region are located on the deep isolation structure, the ring-shaped N-type well region surrounds the first P-type well region, and the second P-type well region surrounds the ring-shaped N-type well region.

[0008] The first N-type heavily doped region, the second N-type heavily doped region and the third N-type heavily doped region are arranged in the first P-type well region and close to the upper surface of the first P-type well region, the first gate oxide layer covers the surface of the first P-type well region between the first N-type heavily doped region and the second N-type heavily doped region, and the second gate oxide layer covers the surface of the first P-type well region between the second N-type heavily doped region and the third N-type heavily doped region.

[0009] The first annular P-type heavily doped region is located in the first P-type well region and surrounds the first N-type heavily doped region, the second N-type heavily doped region and the third N-type heavily doped region, the second annular P-type heavily doped region is located in the annular N-type well region and surrounds the first annular P-type heavily doped region, the annular N-type heavily doped region is located in the annular N-type well region and surrounds the second annular P-type heavily doped region, and the third annular P-type heavily doped region is located in the second P-type well region and surrounds the annular N-type heavily doped region.

[0010] The first annular P-type heavily doped region is located in the first P-type well region and surrounds the first N-type heavily doped region, the second N-type heavily doped region and the third N-type heavily doped region, the second annular P-type heavily doped region is located in the annular N-type well region and surrounds the first annular P-type heavily doped region, the annular N-type heavily doped region is located in the annular N-type well region and surrounds the second annular P-type heavily doped region, and the third annular P-type heavily doped region is located in the second P-type well region and surrounds the annular N-type heavily doped region.

[0011] The first N-type heavily doped region, the second N-type heavily doped region, the second annular P-type heavily doped region and the annular N-type heavily doped region are connected to the anode of an external power supply, and the first N-type heavily doped region, the third N-type heavily doped region, the first gate oxide layer, the second gate oxide layer, the first annular P-type heavily doped region and the third annular P-type heavily doped region are connected to the cathode of the external power supply.

[0012] Optionally, in the electrostatic discharge protection GGNMOS structure, the annular N-type heavily doped region and the second annular P-type heavily doped region are directly laterally contacted in the annular N-type well region.

[0013] Optionally, in the electrostatic discharge protection GGNMOS structure, the annular N-type heavily doped region and the second annular P-type heavily doped region have a certain spacing in the annular N-type well region.

[0014] Optionally, in the electrostatic discharge protection GGNMOS structure, the annular N-type heavily doped region and the second annular P-type heavily doped region have a certain spacing in the annular N-type well region.

[0015] Optionally, in the electrostatic discharge protection GGNMOS structure, the deep isolation structure comprises a deep N-type well region, the deep N-type well region is located in the substrate and close to the upper surface of the substrate, the annular N-type well region and the first P-type well region are located on the deep N-type well region, and the second P-type well region is located on the substrate.

[0016] Optionally, in the electrostatic discharge protection GGNMOS structure, the deep isolation structure comprises a deep N-type well region, the deep N-type well region is located in the substrate and close to the upper surface of the substrate, the annular N-type well region and the first P-type well region are located on the deep N-type well region, and the second P-type well region is located on the substrate.

[0017] Optionally, in the electrostatic discharge protection GGNMOS structure, the deep isolation structure comprises an N-type buried layer, an annular P-type buried layer and an epitaxial layer, the N-type buried layer and the annular P-type buried layer are located on the substrate, the annular P-type buried layer surrounds the N-type buried layer, the epitaxial layer covers part of the surface of the N-type buried layer, the first P-type well region covers the epitaxial layer, the annular N-type well region covers the remaining surface of the N-type buried layer, and the second P-type well region covers the annular P-type buried layer.

[0018] Optionally, in the electrostatic discharge protection GGNMOS structure, the epitaxial layer is of P-type or N-type.

[0019] Optionally, in the electrostatic discharge protection GGNMOS structure, the substrate is of P-type.

[0020] Optionally, in the electrostatic discharge protection GGNMOS structure, the electrostatic discharge protection GGNMOS structure further comprises a first blocking isolation layer and a second blocking isolation layer, the first blocking isolation layer covers the surface of the first P-type well region between the second N-type heavily doped region and the first gate oxide layer, and the second blocking isolation layer covers the surface of the first P-type well region between the second N-type heavily doped region and the second gate oxide layer.

[0021] The technical scheme of the present application has at least the following advantages:

[0022] (1) The application sets the second annular P-type heavily doped region outside the first annular P-type heavily doped region, so that the second annular P-type heavily doped region, the annular N-type well region, the first P-type well region and the first N-type heavily doped region (PNPN structure) form an SCR discharge current channel, and the second annular P-type heavily doped region, the annular N-type well region, the first P-type well region and the third N-type heavily doped region (PNPN structure) also form an SCR discharge current channel, thereby forming two SCR discharge current channels inside the GGNMOS structure, thereby improving the robustness of the electrostatic discharge protection GGNMOS structure.

[0023] (2) In the application, the second annular P-type heavily doped region, the annular N-type well region and the first P-type well region form SCR discharge current channels with the first N-type heavily doped region and the third N-type heavily doped region, respectively, so that the electrostatic discharge protection GGNMOS structure provided by the application can achieve a higher protection level without occupying a large chip area, meet the small size requirement of integrated circuits, and broaden the application field of the electrostatic discharge protection GGNMOS structure. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the specific embodiments or prior art of the present application, the drawings needed in the description of the specific embodiments or prior art will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0025] Figure 1 is a cross-sectional view of the electrostatic discharge protection GGNMOS structure of the first embodiment of the present application;

[0026] Figure 2 is a top view of the electrostatic discharge protection GGNMOS structure of the first embodiment of the present application;

[0027] Figure 3 is a cross-sectional view of the electrostatic discharge protection GGNMOS structure of the second embodiment of the present application;

[0028] Figure 4 is a cross-sectional view of the electrostatic discharge protection GGNMOS structure of the third embodiment of the present application;

[0029] Figure 5 is a top view of the electrostatic discharge protection GGNMOS structure of the third embodiment of the present application;

[0030] Figure 6 is a cross-sectional view of the electrostatic discharge protection GGNMOS structure of the fourth embodiment of the present application;

[0031] Figure 7 is a top view of the electrostatic discharge protection GGNMOS structure of Embodiment Four of the present application;

[0032] In the drawings, the following signs are explained as follows:

[0033] 100-substrate, 101-first annular P-type heavily doped region, 102-second annular P-type heavily doped region, 103-third annular P-type heavily doped region, 111-annular N-type heavily doped region, 112-first N-type heavily doped region, 113-second N-type heavily doped region, 114-third N-type heavily doped region, 121-shallow isolation structure, 122-shallow isolation structure, 123-shallow isolation structure, 124-shallow isolation structure, 131-annular N-type well region, 132-second P-type well region, 133-first P-type well region, 241-deep N-type well region, 150-deep isolation structure, 151-N-type buried layer, 152-annular P-type buried layer, 153-epitaxial layer, 171-first gate oxide layer, 172-second gate oxide layer, 181-annular barrier layer. DETAILED DESCRIPTION

[0034] The technical solutions in the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0035] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0036] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements, it can be wireless connection, or it can be wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0037] In addition, the technical features involved in the different embodiments of the application described below can be combined with each other as long as there is no conflict.

[0038] Embodiment one

[0039] The embodiment of the application provides a static discharge protection GGNMOS structure, please refer to Figure 1 and Figure 2 , Figure 1 is a sectional view of the static discharge protection GGNMOS structure of the embodiment one of the application, Figure 2 is a top view of the static discharge protection GGNMOS structure of the embodiment one of the application. The static discharge protection GGNMOS structure comprises a substrate 100, a deep isolation structure 150, an annular N-type well region 131, a first P-type well region 133, a second P-type well region 132, a first N-type heavily doped region 112, a second N-type heavily doped region 113, a third N-type heavily doped region 114, a first gate oxide layer 171, a second gate oxide layer 172, a first annular P-type heavily doped region 101, a second annular P-type heavily doped region 102, a third annular P-type heavily doped region 103, an annular N-type heavily doped region 111 and a plurality of shallow isolation structures 121 / 122 / 123.

[0040] The deep isolation structure 150 covers the substrate 100, the annular N-type well region 131, the first P-type well region 133 and the second P-type well region 132 are all located on the deep isolation structure 150, the annular N-type well region 131 surrounds the first P-type well region 133, and the second P-type well region 132 surrounds the annular N-type well region 131.

[0041] Further, the first N-type heavily doped region 112, the second N-type heavily doped region 113 and the third N-type heavily doped region 114 are arranged in the first P-type well region 133, and the upper surfaces of the first N-type heavily doped region 112, the second N-type heavily doped region 113 and the third N-type heavily doped region 114 are flush with the upper surface of the first P-type well region 133, the first gate oxide layer 171 covers the surface of the first P-type well region 133 between the first N-type heavily doped region 112 and the second N-type heavily doped region 113, and the second gate oxide layer 172 covers the surface of the first P-type well region 133 between the second N-type heavily doped region 113 and the third N-type heavily doped region 114.

[0042] The first annular P-type heavily doped region 101 is located in the first P-type well region 133 and the upper surface of the first annular P-type heavily doped region 101 is flush with the upper surface of the first P-type well region 133, and the first annular P-type heavily doped region 101 surrounds the first N-type heavily doped region 112, the second N-type heavily doped region 113 and the third N-type heavily doped region 114; the second annular P-type heavily doped region 102 is located in the annular N-type well region 131 and the upper surface of the second annular P-type heavily doped region 102 is flush with the upper surface of the annular N-type well region 131, and the second annular P-type heavily doped region 102 surrounds the first annular P-type heavily doped region 101; the annular N-type heavily doped region 111 is located in the annular N-type well region 131 and the upper surface of the annular N-type heavily doped region 111 is flush with the upper surface of the annular N-type well region 131, and the annular N-type heavily doped region 111 surrounds the second annular P-type heavily doped region 102; the third annular P-type heavily doped region 103 is located in the second P-type well region 132 and the upper surface of the third annular P-type heavily doped region 103 is flush with the upper surface of the second P-type well region 132, and the third annular P-type heavily doped region 103 surrounds the annular N-type heavily doped region 111.

[0043] Further, the first annular P-type heavily doped region 101 and the first N-type heavily doped region 112 and the third N-type heavily doped region 114 are provided with a shallow isolation structure 123; the first annular P-type heavily doped region 101 and the second annular P-type heavily doped region 102 are provided with a shallow isolation structure 122; and the annular N-type heavily doped region 111 and the third annular P-type heavily doped region 103 are also provided with a shallow isolation structure 121.

[0044] The second N-type heavily doped region 113, the second annular P-type heavily doped region 102 and the annular N-type heavily doped region 111 are connected to the anode of an external power supply; the first N-type heavily doped region 112, the third N-type heavily doped region 114, the first gate oxide layer 171, the second gate oxide layer 172, the first annular P-type heavily doped region 101 and the third annular P-type heavily doped region 103 are connected to the cathode of the external power supply.

[0045] In the embodiment, in the annular N-type well region 131, the annular N-type heavily doped region 111 and the second annular P-type heavily doped region 102 are directly laterally contacted.

[0046] Preferably, the conductivity type of the substrate 100 is P-type.

[0047] Preferably, the electrostatic discharge protection GGNMOS structure further comprises a first blocking isolation layer and a second blocking isolation layer (not shown), the first blocking isolation layer covers the surface of the first P-type well region 133 between the second N-type heavily doped region 113 and the first gate oxide layer 171, and the second blocking isolation layer covers the surface of the first P-type well region 133 between the second N-type heavily doped region 113 and the second gate oxide layer 172.

[0048] Further, the deep isolation structure 150 can comprise an N-type buried layer 151, a ring-shaped P-type buried layer 152, and an epitaxial layer 153, wherein the N-type buried layer 151 and the ring-shaped P-type buried layer 152 are both located on the substrate 100, the ring-shaped P-type buried layer 152 surrounds the N-type buried layer 151, the epitaxial layer 153 covers part of the surface of the N-type buried layer 151, the first P-type well region 133 covers the epitaxial layer 153, the ring-shaped N-type well region 131 covers the remaining surface of the N-type buried layer 151, and the second P-type well region 132 covers the ring-shaped P-type buried layer 152. The epitaxial layer 153 can be P-type or N-type.

[0049] In Embodiment One, the first N-type heavily doped region 112, the first P-type well region 133, and the second N-type heavily doped region 113 form an NPN transistor, and the third N-type heavily doped region 114, the first P-type well region 133, and the second N-type heavily doped region 113 form an NPN transistor. The second ring-shaped P-type heavily doped region 102, the ring-shaped N-type well region 131, the first P-type well region 133, and the first N-type heavily doped region 112 (PNPN structure) form an SCR discharge current channel, and the second ring-shaped P-type heavily doped region 102, the ring-shaped N-type well region 131, the first P-type well region 133, and the third N-type heavily doped region 114 (PNPN structure) also form an SCR discharge current channel. By arranging the second ring-shaped P-type heavily doped region 102 around the first ring-shaped P-type heavily doped region 101, the interior of the GGNMOS structure forms two SCR discharge current channels, thereby improving the robustness of the electrostatic discharge protection GGNMOS structure.

[0050] Further, in this application, the second ring-shaped P-type heavily doped region, the ring-shaped N-type well region, and the first P-type well region form SCR discharge current channels with the first N-type heavily doped region and the third N-type heavily doped region, respectively, so that the electrostatic discharge protection GGNMOS structure provided by this application can achieve a high protection level without occupying a large chip area, meet the small size requirement of integrated circuits, and broaden the application field of the electrostatic discharge protection GGNMOS structure.

[0051] Embodiment Two

[0052] Referring to Figure 3 , Figure 3 is a cross-sectional view of the electrostatic discharge protection GGNMOS structure of Embodiment Two of the present application, in Embodiment Two, the deep isolation structure 150 can be a deep N-well 241, the deep N-well 241 is located in the substrate 100 and close to the upper surface of the substrate 100, the annular N-well 131 and the first P-well 133 are both located on the deep N-well 241, and the second P-well 132 is located on the substrate 100.

[0053] Embodiment Three

[0054] Referring to Figure 4 and Figure 5 , Figure 4 is a cross-sectional view of the electrostatic discharge protection GGNMOS structure of Embodiment Three of the present application, Figure 5 is a top view of the electrostatic discharge protection GGNMOS structure of Embodiment Three of the present application, in the annular N-well 131, there is a certain interval between the annular N-type heavily doped region 111 and the second annular P-type heavily doped region 102.

[0055] In Embodiment Three, a shallow isolation structure 124 is arranged in the interval between the annular N-type heavily doped region 111 and the second annular P-type heavily doped region 102 to isolate the annular N-type heavily doped region 111 and the second annular P-type heavily doped region 102.

[0056] Embodiment Four

[0057] Referring to Figure 6 and Figure 7 , Figure 6 is a cross-sectional view of the electrostatic discharge protection GGNMOS structure of Embodiment Four of the present application, Figure 7 is a top view of the electrostatic discharge protection GGNMOS structure of Embodiment Four of the present application, in the annular N-well 131, there is a certain interval between the annular N-type heavily doped region 111 and the second annular P-type heavily doped region 102.

[0058] In Embodiment Four, the electrostatic discharge protection GGNMOS structure further comprises an annular barrier layer 181, the annular barrier layer 181 covers the surface of the annular N-well 131 between the annular N-type heavily doped region 111 and the second annular P-type heavily doped region 102, and the annular barrier layer 181 can isolate the annular N-type heavily doped region 111 and the second annular P-type heavily doped region 102.

[0059] The above description is only a description of the preferred embodiments of the present application, and is not intended to limit the scope of the present application. Any modification, change or improvement made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

[0060] It should be noted that the various embodiments described in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. In addition, the different parts between the embodiments can also be used in combination with each other, and the present application is not limited in this regard.

Claims

1. A GGNMOS structure for electrostatic discharge protection, characterized in that, include: Substrate, deep isolation structure, annular N-type well region, first P-type well region, second P-type well region, first heavily N-type doped region, second heavily N-type doped region, third heavily N-type doped region, first gate oxide layer, second gate oxide layer, first annular heavily P-type doped region, second annular heavily P-type doped region, third annular heavily P-type doped region, annular heavily N-type doped region, and multiple shallow isolation structures; The deep isolation structure covers the substrate, and the annular N-type well region, the first P-type well region, and the second P-type well region are all located on the deep isolation structure. The annular N-type well region surrounds the first P-type well region, and the second P-type well region surrounds the annular N-type well region. The first N-type heavily doped region, the second N-type heavily doped region, and the third N-type heavily doped region are spaced apart in the first P-type well region and close to the upper surface of the first P-type well region. The first gate oxide layer covers the surface of the first P-type well region between the first N-type heavily doped region and the second N-type heavily doped region, and the second gate oxide layer covers the surface of the first P-type well region between the second N-type heavily doped region and the third N-type heavily doped region. The first annular P-type heavily doped region is located in the first P-type well region and surrounds the first N-type heavily doped region, the second N-type heavily doped region, and the third N-type heavily doped region. The second annular P-type heavily doped region is located in the annular N-type well region and surrounds the first annular P-type heavily doped region. The annular N-type heavily doped region is located in the annular N-type well region and surrounds the second annular P-type heavily doped region. The third annular P-type heavily doped region is located in the second P-type well region and surrounds the annular N-type heavily doped region. A shallow isolation structure is provided between the first annular P-type heavily doped region and the first N-type heavily doped region, between the third N-type heavily doped region, between the first annular P-type heavily doped region and the second annular P-type heavily doped region, and between the annular N-type heavily doped region and the third annular P-type heavily doped region. The second N-type heavily doped region, the second annular P-type heavily doped region, and the annular N-type heavily doped region are all connected to the anode of an external power supply; the first N-type heavily doped region, the third N-type heavily doped region, the first gate oxide layer, the second gate oxide layer, the first annular P-type heavily doped region, and the third annular P-type heavily doped region are all connected to the cathode of an external power supply.

2. The electrostatic discharge protection GGNMOS structure according to claim 1, characterized in that, In the annular N-type well region, the annular N-type heavily doped region and the second annular P-type heavily doped region are in direct lateral contact.

3. The electrostatic discharge protection GGNMOS structure according to claim 1, characterized in that, In the annular N-type well region, there is a certain interval between the annular N-type heavily doped region and the second annular P-type heavily doped region.

4. The electrostatic discharge protection GGNMOS structure according to claim 3, characterized in that, A shallow isolation structure is provided in the gap between the annular N-type heavily doped region and the second annular P-type heavily doped region to isolate the annular N-type heavily doped region and the second annular P-type heavily doped region.

5. The electrostatic discharge protection GGNMOS structure according to claim 3, characterized in that, The electrostatic discharge protected GGNMOS structure further includes an annular barrier layer, which covers the surface of the annular N-type well region between the annular N-type heavily doped region and the second annular P-type heavily doped region.

6. The electrostatic discharge protection GGNMOS structure according to claim 1, characterized in that, The deep isolation structure includes: a deep N-type well region located in the substrate and close to the upper surface of the substrate; an annular N-type well region and the first P-type well region both located on the deep N-type well region; and a second P-type well region located on the substrate.

7. The electrostatic discharge protection GGNMOS structure according to claim 1, characterized in that, The deep isolation structure includes: an N-type buried layer, an annular P-type buried layer, and an epitaxial layer, wherein the N-type buried layer and the annular P-type buried layer are both located on the substrate, the annular P-type buried layer surrounds the N-type buried layer, the epitaxial layer covers a portion of the surface of the N-type buried layer, a first P-type well region covers the epitaxial layer, the annular N-type well region covers the remaining surface of the N-type buried layer, and a second P-type well region covers the annular P-type buried layer.

8. The electrostatic discharge protection GGNMOS structure according to claim 7, characterized in that, The conductivity type of the epitaxial layer is P-type or N-type.

9. The electrostatic discharge protection GGNMOS structure according to claim 1, characterized in that, The substrate has a P-type conductivity.

10. The electrostatic discharge protection GGNMOS structure according to claim 1, characterized in that, The electrostatic discharge protected GGNMOS structure further includes: a first barrier isolation layer and a second barrier isolation layer, wherein the first barrier isolation layer covers the surface of the first P-type well region between the second N-type heavily doped region and the first gate oxide layer, and the second barrier isolation layer covers the surface of the first P-type well region between the second N-type heavily doped region and the second gate oxide layer.

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