Phase change memory

Abstract

Various embodiments of the present disclosure relate to phase change memory devices. The present description relates to devices including phase change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase change material.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from French Patent Application No. 20 / 11087, filed on October 29, 2015, entitled “PHASE CHANGE MEMORY”, which is incorporated herein by reference to the fullest extent allowed by law. Technical Field

[0003] The present disclosure relates generally to electronic devices and methods of manufacturing the same, and more particularly to devices including phase change memory. Background Art

[0004] For example, in a typical phase-change memory, each memory cell includes a layer of phase-change material in contact with a resistive element. Phase-change materials are materials that can switch between a crystalline phase and an amorphous phase. This switching is caused by an increase in the temperature of the resistive element through which current is conducted. The difference in resistance between the amorphous and crystalline phases of the material is used to define at least two memory states, arbitrarily 0 and 1.

[0005] Memory is typically in the form of an array, consisting of word lines and bit lines, i.e., rows and columns. A memory cell containing binary information is located at each intersection of a row and column.

[0006] Data contained in a cell of a phase change memory is accessed or read, for example, by measuring the resistance between a bit line and a word line of the memory cell.

[0007] Phase-change memory cells are located, for example, in an interconnect network. An interconnect network refers to a stack of insulating layers that are formed during the so-called "back-end" manufacturing steps, with metal traces coupled together by conductive vias located therein. Typically, the levels of the interconnect network (each level comprising a conductive trace in an insulating layer and a conductive via in the insulating layer) have a constant height. Summary of the Invention

[0008] Embodiments overcome all or part of the disadvantages of known phase change memories.

[0009] An embodiment provides a device including phase change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase change material.

[0010] An embodiment provides a method of fabricating a device including phase change memory cells, the method comprising: for each cell, forming a first resistive element in lateral contact with a second element made of phase change material.

[0011] According to an embodiment, the second element has the shape of a spacer.

[0012] According to an embodiment, the second element has an L-shape.

[0013] According to an embodiment, the second element comprises a lower surface in contact with the third conductive element, the third element being surrounded by the first insulating layer.

[0014] According to an embodiment, the first element is separated from the first insulating layer and the third conductive element by an insulating portion.

[0015] According to an embodiment, the first element is a planar layer and a horizontal layer.

[0016] According to an embodiment, the first side wall of the first element is in contact with the substantially vertical portion of the second element.

[0017] According to an embodiment, a second side wall of the first element opposite to the first wall is in contact with the conductive tape.

[0018] According to an embodiment, a second side wall of the first element opposite to the first wall is in contact with a fourth selection element, the fourth element being covered by the conductive tape.

[0019] According to an embodiment, the device includes an interconnection network, and each memory cell is located between two levels of the interconnection network.

[0020] According to an embodiment, in some embodiments based on alloys of germanium, tellurium and antimony, the second element is made of an alloy based on chalcogenides, and in some embodiments of titanium nitride or titanium silicon nitride, the first element is made of metal.

[0021] According to an embodiment, the thickness of the first element is in the range of 2nm to 20nm, the size of the first element in the first horizontal direction is less than 70nm, the size of the first element in the second horizontal direction is in the range of 10nm to 50nm, the height of the second element is in the range of 30nm to 80nm, the size of the second element in the first horizontal direction is less than 70nm, and the size of the second element in the second horizontal direction is in the range of 10nm to 40nm.

[0022] According to an embodiment, a method includes forming a stack of layers, the stack including, in this order, a second insulating layer, a third layer made of a material of the first element, and a fourth insulating layer; forming a first cavity spanning the stack and exposing a first sidewall of the third layer; and forming a second element on the first wall.

[0023] According to an embodiment, the method includes forming a second cavity exposing a second side surface of the first element.

[0024] According to an embodiment, the method includes forming a strip on the second side surface of the first element.

[0025] According to an embodiment, the method includes forming a fourth selection element on the second side surface of the first element. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The foregoing features and advantages, as well as other features and advantages, will be described in detail below in the description of specific embodiments which are given by way of illustration and not limitation, in the accompanying drawings:

[0027] Figure 1A shows a cross-sectional view of an embodiment of a phase change memory cell;

[0028] Figure 1B shows a cross-sectional view of an embodiment of a phase change memory cell;

[0029] Figure 2 It shows a plurality of units (such as Figure 1A and Figure 1B a cross-sectional view of a device having a unit (unit);

[0030] Figure 3A Shows the manufacturing Figure 2 the results of the steps of the method of the embodiment;

[0031] Figure 3B Shows the manufacturing Figure 2 a result of another step of the method of an embodiment;

[0032] Figure 3C Shows the manufacturing Figure 2 a result of another step of the method of an embodiment;

[0033] Figure 3D Shows the manufacturing Figure 2 a result of another step of the method of an embodiment;

[0034] Figure 3E Shows the manufacturing Figure 2 a result of another step of the method of an embodiment;

[0035] Figure 3F Shows the manufacturing Figure 2 a result of another step of the method of an embodiment;

[0036] Figure 4 Shown Figure 1A 、 Figure 1B and Figure 2 A variation of the embodiment;

[0037] Figure 5 Shown Figure 1A 、 Figure 1B and Figure 2 A variation of the embodiment of ; and

[0038] Figure 6 Another embodiment of a phase change memory cell is shown. DETAILED DESCRIPTION

[0039] In the various drawings, like features are denoted by like reference numerals. In particular, common structural and / or functional features in various embodiments may have like references and may be provided with like structures, dimensions, and material properties.

[0040] For clarity, only the steps and elements that are useful for understanding the embodiments described herein are illustrated and described in detail.

[0041] Unless otherwise stated, when two elements are referred to as being connected together, this means a direct connection without any intervening elements other than conductors, and when two elements are referred to as being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0042] In the following disclosure, unless otherwise indicated, when reference is made to absolute position qualifiers, such as terms "front," "back," "top," "bottom," "left," "right," etc., or relative position qualifiers, such as terms "above," "below," "upper," "lower," etc., or directional qualifiers, such as "horizontal," "vertical," etc., reference is made to the orientation shown in the accompanying drawings.

[0043] Unless otherwise indicated, the expressions "about," "approximately," "substantially," and "approximately" are intended to mean within 10%, and in some embodiments, within 5%.

[0044] Figure 1A A cross-sectional view of one embodiment of a phase change memory cell 10 is shown. Figure 1B 1 shows a cross-sectional view of a phase change memory cell 10. More specifically, Figure 1A Shown along Figure 1B A cross-sectional view of a portion of the device including unit 10 along plane AA, and Figure 1B Shown along Figure 1A 1 is a cross-sectional view of a portion of the device including the unit cell 10 along plane BB.

[0045] Cell 10 is located in a back-end-of-the-line (BOL) level of a device, such as an interconnect network. The interconnect network can be the multiple conductive and dielectric layers that work together to create an integrated circuit. Cell 10 is located between a metal track level or metallization level MX and a metal track level or metallization level MX+1 of the interconnect network. Figure 1A and 1B An insulating layer 12 of an interconnect level MX located below the memory cell 10 and an insulating layer 14 of an interconnect level MX+1 located above the memory cell 10 are shown.

[0046] Conductive tracks 16 are located in the insulating layer 12 in the metallization layer MX. The tracks 16 pass through the layer 12, i.e. extend entirely along the height of the layer 12. For example, the tracks 16 extend along a line such as Figure 1A and Figure 1B For example, track 16 extends in direction X, on the x-axis, corresponding to the direction of the word lines. Thus, in some embodiments, track 16 is coupled to cells of the word lines.

[0047] Conductive tracks 18 are located in the insulating layer 14 in the metallization layer MX+1. The tracks 18 pass through the layer 14, i.e. extend entirely along the height of the layer 14. The tracks 18 are for example arranged along a line such as Figure 1A and Figure 1B . For example, track 18 extends along direction Y, on the y-axis, e.g., corresponding to the direction of the bit lines. Thus, in some embodiments, track 18 is coupled to the cells of the bit lines. In some embodiments, track 18 extends in a direction orthogonal to the direction along which track 16 extends.

[0048] In some embodiments, the material of insulating layers 12 and 14 has a very low dielectric constant, so-called “ultra-low-K” material.

[0049] Conductive tracks 16 and 18 are made of a conductive material (eg, metal). In some embodiments, the conductive traces are made of copper or tungsten.

[0050] In some embodiments, an insulating layer 20 made of silicon nitride is located on insulating layer 12 and on conductive tracks 16. Insulating layer 20 covers and contacts insulating layer 12, except for a cavity that passes completely through the layer at the level of each memory cell. Each cavity is filled with a conductive material to form a conductive element 22, such as a pad 22. Each pad 22 contacts conductive track 16, which in some embodiments is a single track 16. Figure 1A and 1B A single cell 10 is shown and a single pad 22 is shown. Each memory cell includes a pad 22, and in some embodiments, a single pad 22. In some embodiments, pad 22 is made of a conductive material (eg, metal, in some embodiments, tungsten).

[0051] In some embodiments, layers 12, 14, and 20 are planar and parallel layers. In other words, each layer in layers 12, 14, and 20 includes a lower surface and an upper surface, which are planar and horizontal and substantially parallel to each other. In addition, the upper and lower surfaces of different layers 12, 14, and 20 are parallel to each other in some embodiments. Tracks 16 and 18 and pads 22 completely pass through the corresponding layers 12, 14, and 20 in the vertical direction Z or z-axis. In some embodiments, tracks 16 and 18 and pads 22 each have an upper and lower surface, which are planar and horizontal and substantially parallel to each other. The lower and upper surfaces of tracks 16 and 18 and pads 22 are coplanar with the lower and upper surfaces of layers 12, 14, and 20, respectively.

[0052] As a variant, the pad 22 could be replaced by a conductive track extending on the track 16 , the conductive track being made of the material of the pad 22 .

[0053] The cell 10 includes an element 24 made of a phase change material. The element 24 is made of, for example, a chalcogenide-based alloy, such as a germanium, tellurium, and antimony (GST)-based alloy. The element 24 rests on and contacts the pad 22 of the cell 10 shown.

[0054] Element 24 has a spacer shape. More specifically, element 24 includes a lower or horizontal surface that contacts pad 22. The lower surface of element 24 is substantially planar. The lower surface of element 24 is horizontal, that is, it extends in the plane of the upper surface of pad 22. In other words, the lower surface of element 24 lies in a plane formed by directions X and Y. In direction X, i.e., the direction in which the word lines extend, element 24, in some embodiments, extends over a portion of the dimension of pad 22. Thus, in some embodiments, the dimension of the lower surface of element 24 in direction X is substantially equal to the dimension of pad 22, and in some embodiments, substantially equal to the dimension of the upper surface of pad 22. In direction Y, i.e., the direction in which the bit lines extend, element 24, in some embodiments, extends over a portion of the dimension of pad 22. Thus, in some embodiments, the dimension of the lower surface of element 24 in direction Y is smaller than the dimension of the upper surface of pad 22. For example, the lower surface of element 24 has a substantially parallelogram shape.

[0055] Element 24 includes a vertical surface, such as a surface that is substantially vertical in the z-axis. The vertical surface extends from the upper surface of pad 22 in direction Z or along the z-axis (orthogonal to directions X and Y). For example, the vertical surface extends in a plane that is substantially orthogonal to the plane of the lower surface. In some embodiments, the vertical surface is Figure 1B , ie the xz plane formed by the directions X and Z. For example, the vertical surfaces of the element 24 substantially have the shape of a parallelogram.

[0056] Element 24 includes a side surface. The side surface extends from the upper surface of pad 22 in direction Z. For example, the side surface extends in a plane that is substantially orthogonal to the plane of the lower surface. In some embodiments, the side surface extends in a plane that is substantially orthogonal to the plane of the lower surface. Figure 1A In some embodiments, the side surfaces of element 24 are each coplanar with the side surfaces of pad 22.

[0057] Element 24 includes another surface, which in some embodiments is in contact with all other surfaces. In some embodiments, the other surface is curved.

[0058] As a variant, if the conductive track 16 is made of a material that does not degrade the material of the element 24, such as tungsten, the element 24 can be located directly on the track 16. The element 24 is then located directly on the track 16 and the layer 20 and the pad 22 are then absent.

[0059] The pads 22 are useful where the tracks 16 are made of copper or another material that is capable of degrading the phase change material during device fabrication. It is then advantageous to ensure that the components 24 do not come into contact with the conductive tracks 16.

[0060] The battery 10 also includes a resistive element 26. The element 26 is Figure 1B 20 is shown by dashed lines. In some embodiments, resistive element 26 is made of a conductive material (e.g., metal) or titanium nitride or titanium silicon nitride. Resistive element 26 is a horizontally extending layer. In some embodiments, resistive element 26 extends in a plane substantially parallel to the upper surface of layer 20. In some embodiments, resistive element 26 includes an upper surface and a lower surface that are substantially parallel to each other and, in some embodiments, substantially parallel to the upper surface of layer 20. For example, element 26 has a substantially rectangular parallelepiped shape.

[0061] Resistive element 26 extends from element 24, and in some embodiments, extends from a vertical surface of element 24. Resistive element 26 is thus in contact with element 24. In some embodiments, a side surface of element 26 is in contact with a vertical surface of element 24. Thus, element 26 is in lateral contact with element 24. Element 26 is, for example, located entirely at the same distance from the upper surface of layer 20 as element 24. Element 26 is a planar, horizontal layer. Resistive element 26 extends in direction X over a dimension of element 24, as shown in FIG. Figure 1B As shown. In some embodiments, the side surfaces of element 26 are coplanar with the side surfaces of element 24. Therefore, element 26 is not located below or above element 24. Element 24 is not separated from rails 18 and 16 by element 26. A portion of element 24 is located above the level of element 26, and a portion is located below the level of element 26. Figure 1BThe horizontal dimension in the cross-sectional plane (ie, the dimension in the direction X) of the element 26 is, for example, less than 70 nm, for example, in the range of 20 nm to 70 nm, and in some embodiments substantially equal to 50 nm. Figure 1B The horizontal dimension in the cross-sectional plane (ie the dimension in direction X) is, for example, smaller than 70 nm, for example, in the range of 20 nm to 70 nm, and in some embodiments is substantially equal to 50 nm.

[0062] The horizontal dimension of the lower surface of the element 24, i.e. the dimension of the interface between the element 24 and the rail 16, is Figure 1A In the cross-sectional plane of the element 26, i.e. in the direction Y, for example, in the range of 10 nm to 40 nm. Figure 1A The horizontal dimension in the cross-sectional plane (ie, the dimension in the direction Y) is, for example, in the range of 10 nm to 50 nm.

[0063] The thickness of element 26, i.e., the distance between its upper surface and its lower surface along the z-axis, is less than the height of element 24, i.e., the dimension of the vertical surface of element 24 in the same direction as the thickness of element 26 (i.e., direction Z). In some embodiments, the thickness of element 26 is between three and five times less than the height of element 24. The height of element 24, i.e., its dimension in direction Z, is, for example, in the range of 30 nm to 80 nm, inclusive. The thickness of element 26, i.e., its dimension in direction Z, is, for example, in the range of 2 nm to 20 nm, inclusive.

[0064] Component 26 rests on a region or portion 28 of insulating material, such as silicon nitride. Component 26 is separated from layer 20 and pad 22 by region 28 of insulating material. Component 26 therefore does not contact layer 20, pad 22, layer 12, or track 16.

[0065] The value of the resistance between component 26 and pad 22 depends on the height of region 28, with the distance between component 26 and the lower surface of component 24 depending thereon. The height of portion 28 is therefore selected according to the desired resistance.

[0066] Components 26 and 24 are covered by an insulating layer 30, for example, made of silicon nitride. Layer 30 further covers backing pad 22 and a portion of layer 20. The lateral surface of component 26 is left exposed by layer 30. In other words, layer 30 does not cover one of the side surfaces of component 26. More specifically, in some embodiments, layer 30 does not cover the side surface of component 26 opposite the surface in contact with component 24.

[0067] For each bit line, the device includes a conductive strap 32. Strap 32 is made of, for example, a conductive material, such as a metal, in some embodiments, titanium nitride, tungsten, or copper, and does not contact element 24. Strap 32 includes a portion 32a that extends along layer 30 to element 26, and more specifically, to the exposed side surface of element 26. Strap 32 is thus in contact with element 26. Element 26 is thus connected to element 24 at one end and to strap 32 at the other end. In some embodiments, this portion 32a of strap 32 extends all the way to the upper surface of layer 20. The dimensions of element 26 are such that strap 32 does not contact pad 22, or, in the absence of layer 20 and pad 22, does not contact track 16.

[0068] In some embodiments, another portion of strap 32 extends over insulating layer 30 to reach another memory cell. Figure 1A and Figure 1B Shown in.

[0069] Each bit line is surrounded by an insulating layer 34, such as silicon nitride. Layer 34 surrounds the assembly including strip 32, insulating layer 30, portion 28, and elements 24 and 26. In some embodiments, layer 34 specifically covers the upper surface and upper surfaces of the sidewalls of strip 32. In some embodiments, strip 32, portion 28, and elements 24 and 26 of insulating layer 30 are coplanar.

[0070] Insulating layer 36 covers layer 34 and layer 20. In some embodiments, insulating layer 36 is made of a material with a very low dielectric constant ("ultra-low K"). Layer 36 corresponds to the layer in which the conductive vias that couple conductive trace MX located in layer 12 to trace MX+1 located in layer 14 are formed. Layer 36 separates the different bit lines.

[0071] Conductive via 38 , for example, crosses or extends through layer 36 and layer 34 to couple track MX+1 to conductive strip 32 .

[0072] It is possible to choose to form a vertical stack of the resistive element, phase change material and electrodes (i.e., strips 32). Thus, it is possible to choose to form a layer of phase change material on the resistive element and to form the electrodes on the layer of phase change material. However, each cell will have a larger size than about Figure 1A and Figure 1B The greater thickness of the described embodiments is typically greater than 150 nm with current technology. Therefore, it would be impossible to position memory cells in a standard interconnect network without locally or generally modifying the thickness of the network levels. Such modifications would result in changes in the resistance and capacitance of the links between the levels, which would result in modifications in the behavior of components (e.g., transistors) coupled by the interconnect network.

[0073] Figure 2 It shows a plurality of units (such as Figure 1A and Figure 1B A cross-sectional view of a device having a unit). Figure 2 It is along Figure 1A The cross-sectional view of the plane will not be described again. Figure 1A and 1B The same components as the components. Figure 2 Three memory cells of the same bit line are shown.

[0074] These units are similar to those previously described Figure 1A and Figure 1B The unit described is formed.

[0075] The cells are alternating. In other words, each memory cell corresponds to a Figure 2 The planes of the adjacent cells are orthogonal to the horizontal plane and have planar symmetry.

[0076] The elements 26 of two adjacent units face each other. Similarly, the elements 24 of two adjacent units face each other.

[0077] Each portion 32a of the strip 32 extending towards the layer 20 is in contact with the elements 26 of two adjacent cells. Thus, each portion 32a of the strip 32 extending towards the layer 20 allows contact of two memory cells. Thus, there are substantially twice as many portions 32a as there are cells 10.

[0078] Two adjacent cell elements 26 separated by a band 32 are not separated by a cell element 24. Similarly, two adjacent cell elements 24 separated only by a layer 30 are not separated by a cell element 26.

[0079] Figures 3A to 3F Shows some examples of manufacturing Figure 1A 、 Figure 1B and Figure 2 The implementation mode of the method of the embodiment is the result of the successive steps. Figures 3A to 3F It is along Figure 1A A cross-sectional view of the plane.

[0080] Figure 3A Shows the manufacturing Figure 2 The steps of the method of the embodiment are the results.

[0081] This step includes forming an interconnect level including tracks MX. More specifically, this step includes forming an insulating layer 12. In some embodiments, layer 12 is made of a so-called "ultra-low-K" material, i.e., a material with a low dielectric constant. A cavity is formed across layer 12 at the location of conductive tracks 16. The cavity is then filled with the material of tracks 16 (e.g., a metal, such as copper or tungsten in some embodiments) to form said tracks 16. The cavity is filled so that no material of tracks 16 is located outside the cavity.

[0082] An insulating layer 20 is then formed over layer 12 and track 16. In some embodiments, this layer is made of silicon nitride. A cavity is formed across layer 20 at the location of pad 22. The cavity is then at least partially located over track 16. The cavity is then filled with the material of pad 22 (e.g., tungsten) to form pad 22. The cavity is filled so that no material of pad 22 is located outside the cavity.

[0083] As a variant, as previously indicated, depending on the material of the track, the layer 20 and the pads 22 may not be formed. The steps described below are therefore performed directly on the layer 12 and the track 16.

[0084] Figure 3B Shows the manufacturing Figure 2 A result of another step of the method of an embodiment.

[0085] During this step, a layer stack 40 is formed on layer 20 and pad 22. Stack 40 comprises, in this order, from layer 20:

[0086] Insulation layer 42;

[0087] a conductive layer 44; and

[0088] Insulation layer 46.

[0089] The insulating layer 42 is formed by the portion 28 ( Figure 1A ) material, such as silicon nitride. Layer 44 is made of the material of resistor element 26, such as titanium nitride or titanium silicon nitride. In some embodiments, layer 46 is made of the same material as layer 42, such as silicon nitride.

[0090] The height of the stack 40 is substantially equal to the desired height of the vertical surface of the element 24 ( Figure 1A ). Figure 1A and Figure 1B As described, the height of layer 42 , which corresponds to the height of portion 28 , depends on the desired value of the resistance between component 26 and pad 22 .

[0091] Figure 3C Shows the manufacturing Figure 2 A result of another step of the method of an embodiment.

[0092] During this step, etching is performed to form cavity 48. Cavity 48 intersects stack 40. The bottom of cavity 48 is thus formed by layer 20 and pad 22.

[0093] Each cavity 48 extends along the direction of the word lines. Thus, each cavity 48 extends along two adjacent word lines. Furthermore, each cavity 48 extends between two adjacent word lines. Thus, each cavity 48 includes a wall extending from pad 22 and from layer 20 of one of the two adjacent word lines, and another wall extending from pad 22 and from layer 20 of the other of the two adjacent word lines. Thus, a portion of the wall of one of cavities 48 extends from each pad 22.

[0094] In some embodiments, stack 40 is only partially removed from pad 22. Thus, in some embodiments, stack 40 still partially extends over pad 22.

[0095] The walls of cavity 48 are formed by the side walls of the stacked layers, i.e., the side walls of layers 42, 44, and 46. Thus, layer 44 is exposed at the level of each wall of one of cavities 48. Thus, electrical connections can be made to layer 44 via each cavity 48.

[0096] Figure 3D Shows the manufacturing Figure 2 A result of another step of the method of an embodiment.

[0097] During this step, spacers 50 are formed on the walls of cavity 48. More specifically, this step comprises conformal formation of a layer (not shown) made of the material of spacers 50. Said layer (not shown) notably covers the walls and the bottom of cavity 48 and the upper surface of layer 46. This step then comprises a step of anisotropic etching of the layer (not shown) to remove the portion of the layer (not shown) situated on the upper surface of layer 46 and in the middle of the bottom of the cavity. Consequently, the portion situated on the walls of cavity 48 and at the foot of the walls of cavity 48 is not removed and forms spacers 50.

[0098] Spacers 50 extend all along the height of the walls of cavity 48 and over a portion of pad 22 and a portion of layer 20 situated at the foot of the walls. Thus, each spacer is in contact with pad 22 of a word line having a wall extending thereover and in contact with layer 44 exposed at the level of the wall.

[0099] The width of the spacer 50 (ie, Figure 3C The dimension of the spacer in the direction of the bottom of the cavity 48 in the cavities 48 depends on the height of the stack 40. Therefore, the thickness of the layer 46 is selected to obtain the desired spacer width.

[0100] A layer 52 made of insulating material is formed on the structure, ie on the upper surface of layer 46, on spacers 50, on pads 22 and on layer 20. Layer 52 is made of the material of layer 30, for example silicon nitride.

[0101] This step then includes a chemical mechanical planarization (CMP) step to obtain a substantially planar upper surface of layer 52. Layer 52 is deposited to a thickness sufficient to still cover layer 46, spacers 50, pads 22, and layer 20 after polishing.

[0102] Figure 3E Shows the manufacturing Figure 2 A result of another step of the method of an embodiment.

[0103] This step includes the formation of cavity 54. Cavity 54 spans layer 52 and stack 40. Cavity 54 reaches layer 20. The bottom of cavity 54 is formed by layer 20. The bottom of cavity 54 does not include pad 22.

[0104] The walls of cavity 54 are formed by the walls of insulating layers 42, 46, and 52 and the walls of conductive layer 44. Thus, etching of cavity 54 exposes the portion of layer 44 in cavity 54. The bottom and walls of cavity 54 include no conductor other than the exposed portion of layer 44.

[0105] Cavity 54 extends along the word line. Thus, in some embodiments, cavity 54 extends entirely along the length of the word line, and thus entirely along the length of stack 40.

[0106] Figure 3F Shows the manufacturing Figure 2 A result of another step of the method of an embodiment.

[0107] During this step, a metal layer 56 is formed over the entire structure. The layer 56 fills the cavity 54 and covers the layer 52. The material of the layer 56 is the material of the strip 32 ( Figure 1A and Figure 1B ). Thus, layer 56 is made of titanium nitride, tungsten or copper, for example.

[0108] In some embodiments, layer 56 is etched by CMP so that the upper surface of layer 56 is planar. Thus, after CMP, the thickness of layer 56, such as deposited, is large enough for layer 56 to cover layer 52 and completely fill cavity 54.

[0109] Figure 1A 、 Figure 1B and Figure 2 The method of manufacturing a memory cell further comprises steps not shown. In particular, the method comprises individualization of the cell. In other words, the method comprises etching a cavity (not shown) through the conductive layer 56, the insulating layer 52, the spacer 50 and the stack 40. The cavity (not shown) extends in the direction of the bit line, i.e. in the direction of the bit line. Figures 3A to 3F. Thus, a cavity (not shown) separates adjacent memory cells in the same word line. Thus, etching separates layer 56 into bands 32 that are distinct at each cell, layer 42 into portions 28 that are distinct at each cell, layer 44 into elements 26 that are distinct at each cell, and spacers 50 into elements 24 that are distinct at each cell.

[0110] The manufacturing method further includes forming an insulating layer 34 ( Figure 1A and 1B ). In particular, layer 34 covers the walls of the cavity (not shown) formed during the personalization of the cell, and covers the upper surface of strip 32.

[0111] The method may then include forming an insulating layer 36, for example, corresponding to the insulating layer separating layer 12 including track MX, and layer 14 including track MX+1. Thus, layer 36 is intersected, for example, by conductive vias connecting track MX and track MX+1. Then, a level of the interconnect network including track MX+1 is formed on layer 36.

[0112] about Figures 3A to 3F An advantage of the described embodiment is that the formation of the resistive element 26 comprises forming a substantially planar layer, rather than a layer located on the wall of the cavity (as is the case in the prior art), enabling better control of the layer thickness. Thus, a layer having a smaller thickness than in the case of a vertical resistive element can be formed. Furthermore, it is easier to accurately etch planar and horizontal layers than vertical layers.

[0113] Figure 4 Shown Figure 1A 、 Figure 1B and Figure 2 A variation of the embodiment.

[0114] Attachment Figure 4 The embodiment is different from the attached Figure 1A 、 1B 2, because the upper surface of layer 30 is not planar. More specifically, layer 30 includes cavities between two adjacent elements 24. In other words, the distance between the upper surface of layer 30 and the flat upper surface of layer 20 can be smaller than the distance between elements 24 at the level of elements 26. These cavities are filled with ribbon 32.

[0115] Figure 4 The embodiment of the present invention is realized by implementing Figures 3A to 3F The method described is obtained, in addition to being advantageous, for Figure 3D The chemomechanical steps are described.

[0116] Although the upper surface of layer 30 is not planar, tape 32 does not contact component 24 and pad 22. In other words, component 24 and pad 22 are separated from tape 32 by layer 30, although the cavity exists.

[0117] Figure 5 Shown Figure 1A 、 Figure 1B and Figure 2 A variation of the embodiment.

[0118] Attachment Figure 5 The embodiment is different from the attached Figure 1A 、 1B 2, because element 24 is replaced by element 24' made of a phase change material, element 24' is made of the same material as element 24 in some embodiments. In contrast to element 24, element 24' does not have the shape of a spacer, but has an L-shape. In other words, element 24' includes a horizontal portion extending above pad 22 and a vertical portion extending from the upper surface of pad 22 to the upper surface of layer 30.

[0119] In addition to about Figure 3D In addition to the steps described, make Figure 5 Methods of embodiments and with respect to Figures 3A to 3F The same method as described. Figure 5 In the method of an embodiment of the present invention, the step of forming element 24 is replaced by the step of forming element 24'. In some embodiments, the step of forming element 24' comprises depositing a conformal layer made of the material of element 24'. The layer covers, in particular, the bottom and walls of cavity 48 and the upper surface of layer 46. The layer has, for example, a thickness substantially equal to that of the vertical and horizontal portions of element 24' (i.e., at Figure 5 The layer is then etched to remove the portion of the layer located on the upper surface of layer 46 and the portion located at the center of the bottom of the cavity. In other words, the layer is then etched to leave only the portion extending along the wall of cavity 48 and the portion located at the foot of the wall of cavity 48 that is located on pad 22.

[0120] Figure 5 An advantage of the embodiment of is that it enables a better control of the thickness of the element 24 ′ and thus a better determination of the resistance of the element 24 ′.

[0121] Figure 6 Another embodiment of a phase change memory cell is shown.

[0122] Figure 6 Examples and Figure 1A 、 1B The difference from the embodiment of 2 is that it includes a selection element 60.

[0123] In some embodiments, element 60 has a spacer shape. Element 60 extends vertically on the sidewalls of portion 28, on the sidewalls of element 26, and on the sidewalls of layer 30. In some embodiments, element 60 extends all the way to the upper surface of layer 30. Element 60 extends horizontally on layer 20 at the foot of the sidewalls of portion 28.

[0124] Element 60 forms an element for selecting each cell. In other words, during writing to or reading from a cell, selection element 60 enables current to flow through element 26 of that cell. Thus, the selection element makes it possible to limit the current that flows through other memory cells (not selected) and that could interfere with reading from or writing to the cell.

[0125] In some embodiments, the selection element 60 is of the bidirectional threshold switching type (OTS). Element 60 is made, for example, of a chalcogenide material or an alloy of a chalcogenide material. For example, the element is made of germanium, selenium, antimony, or an alloy of one or more of these chemical elements. In some embodiments, element 60 is made of an alloy of a chalcogenide material that optimizes the operating parameters of the threshold switch or selection element, such as an alloy comprising:

[0126] Arsenic, ranging from 9 to 39 atomic percent,

[0127] Germanium, in the range of 10 to 40 atomic percent,

[0128] Silicon, in the range of 5 to 18 atomic percent,

[0129] Nitrogen in an atomic percentage range of 0% to 10%, and

[0130] An alloy of sulfur, selenium and tellurium.

[0131] In some embodiments, the ratio of the atomic percentage of sulfur to the atomic percentage of selenium in the alloy of sulfur, selenium and tellurium is in the range of 0.25 to 4, inclusive, and the ratio of the atomic percentage of sulfur to the atomic percentage of tellurium in the alloy of sulfur, selenium and tellurium is in the range of 0.11 to 1, inclusive. As a variant, the selection element can be made of another material so as to induce a rectifying effect, for example, to form a Schottky diode.

[0132] manufacture Figure 6 Methods of embodiments and with respect to Figures 3A to 3F The method described differs in that it includes Figure 3E and Figure 3F An additional step of forming element 60 is performed between the steps of

[0133] During this additional step, spacers are formed on the walls of cavity 54. More specifically, this step comprises conformal formation of a layer (not shown) made of the material of spacer 60. Said layer (not shown) notably covers the walls and the bottom of cavity 54 and the upper surface of layer 52. This step then comprises a step of anisotropic etching of the layer (not shown) to remove the portion of the layer (not shown) situated on the upper surface of layer 52 and in the middle of the bottom of cavity 54. Consequently, the portions situated on the walls of cavity 54 and at the foot of the walls of cavity 54 are not removed and form spacers.

[0134] The spacer extends along the entire height of the wall of cavity 54 and over a portion of layer 20 located at the foot of the wall.

[0135] The width of the spacer, ie its dimension in the direction of the bottom of cavity 54, depends on the height of cavity 54. Therefore, the thickness of layer 52 (particularly above stack 40) is chosen to obtain spacers on each side of the cavity that do not touch each other.

[0136] An advantage of the described embodiment is that the element 24 is confined, i.e. it is heated directly by itself when it conducts current, rather than indirectly by a resistive element which would heat up and transfer heat. Thus, power losses and thus power dissipation are reduced.

[0137] As a variant, the selection element 60 can be replaced by an L-shaped element, similar to the element 24, which can be replaced by an L-shaped element 24'. The modifications made to the manufacturing method are similar to those made with respect to Figure 5 Modifications as described.

[0138] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and those skilled in the art will recognize other variations.

[0139] Finally, actual implementation of the described embodiments and variations is well within the capabilities of those skilled in the art based on the functional indications given herein.

[0140] The device can be summarized as comprising phase change memory cells, each memory cell (10) comprising a first resistive element (26) in lateral contact with a second element (24) made of a phase change material.

[0141] The second element (24) may have the shape of a spacer.

[0142] The second member (24) may have an L-shape.

[0143] The second element (24) may include a lower surface in contact with a third conductive element (22), the third element being surrounded by the first insulating layer (20).

[0144] The first element (26) may be separated from the first insulating layer (20) and the third conductive element (22) by an insulating portion (28).

[0145] The first element (26) may be a planar layer and a horizontal layer.

[0146] The first side wall of the first element (26) may be in contact with the substantially vertical wall of the second element (24).

[0147] A second side wall of the first element (26) opposite the first wall may be in contact with the conductive tape (32).

[0148] A second side wall of the first element (26) opposite to the first wall can be in contact with a fourth selection element (60), which is covered by the conductive tape (32).

[0149] The device may comprise an interconnection network, and each memory cell (10) is located between two levels of the interconnection network.

[0150] In some embodiments, the second element (24) can be made of a chalcogenide-based alloy, in some embodiments, an alloy based on germanium, tellurium, and antimony, and the first element (26) can be made of a metal, in some embodiments, titanium nitride or titanium silicon nitride.

[0151] The thickness of the first element (26) may be in the range of 2 nm to 20 nm, the size of the first element in the first horizontal direction (X) may be less than 70 nm, the size of the first element (26) in the second horizontal direction (Y) may be in the range of 10 nm to 50 nm, the height of the second element may be in the range of 30 nm to 80 nm, the size of the second element (24) in the first horizontal direction (X) may be less than 70 nm, and the size of the second element (24) in the second horizontal direction (Y) may be in the range of 10 nm to 40 nm.

[0152] A method of fabricating a device including phase change memory cells (10) can be summarized as comprising forming, for each cell, a first resistive element (26) in lateral contact with a second element (24) made of phase change material.

[0153] The method may include forming a layer stack (40), the stack (40) including, in this order, a second insulating layer (42), a third layer (44) y made of the material of the first element (26), and a fourth insulating layer (46); forming a first cavity (48) through the stack (40) and exposing a first side wall of the third layer (44); and forming the second element (24) on the first wall.

[0154] The method may include forming a second cavity (54) exposing a second side surface of the first component (26).

[0155] The method may include forming a band (32) on the second side surface of the first element (26).

[0156] The method includes forming a fourth selection element (60) on a second side surface of the first element (26).

[0157] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to employ the concepts of the various embodiments to provide additional embodiments.

[0158] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents to which such claims are entitled. Therefore, the claims are not limited to the present disclosure.

Claims

1. A device comprising: A phase change memory cell, each memory cell of the phase change memory cell comprising: a first element of conductive material having a first surface opposite a second surface, the first surface contacting the second element of phase change material; and a first insulating layer, the first insulating layer covering and directly contacting the first element and the second element, the second surface of the first element being exposed from the first insulating layer, the first insulating layer being a continuous layer, Wherein the first element is a planar horizontal layer, and a portion of the second element is located above a level of the first element and a portion of the second element is located below the level of the first element. The device according to claim 1 , wherein the second element has a shape of a spacer. The device according to claim 1 , wherein the second element has an L-shape in cross section.

4. The device according to claim 1, comprising: a third element of conductive material, an upper surface of the third element contacting a lower surface of the second element; as well as a second insulating layer surrounding the third element, The second element includes a vertical surface extending from the upper surface of the third element, and the vertical surface is in transverse contact with the first element. 5 . The device of claim 4 , comprising a portion of the first insulating layer, the portion of the first insulating layer separating the first element from the second insulating layer and the third element.

6. The device according to claim 1, wherein The first element has a rectangular parallelepiped shape.

7. The device according to claim 1, wherein The first surface of the first element contacts the first surface of the second element, and the first surface of the second element is vertical.

8. The device of claim 7, comprising a conductive strap, wherein the second surface of the first element contacts the conductive strap.

9. The device of claim 7, comprising a fourth element of a chalcogenide material or a chalcogenide-based alloy and a conductive strip adjacent to the fourth element, wherein the second surface of the first element contacts the fourth element.

10. The device of claim 1, comprising a first metallization level and a second metallization level, wherein each of the memory cells is located between the first metallization level and the second metallization level.

11. The device of claim 1, wherein the phase change material of the second element is a chalcogenide-based alloy including germanium, tellurium, and antimony, and the conductive material of the first element is one or more of titanium nitride or titanium silicon nitride.

12. The device according to claim 1, wherein the thickness of the first element in the vertical direction is in the range of 2 nm to 20 nm, inclusive, the size of the first element in the first horizontal direction is less than 70 nm, the first horizontal direction is the length direction of the first element, the size of the first element in a second horizontal direction perpendicular to the first horizontal direction is in the range of 10 nm to 50 nm, inclusive, the height of the second element in the vertical direction is in the range of 30 nm to 80 nm, inclusive, the size of the second element in the first horizontal direction is less than 70 nm, and the size of the second element in the second horizontal direction is in the range of 10 nm to 40 nm, inclusive.

13. A structure comprising: a first metallization layer comprising a first conductive structure and a first dielectric layer adjacent to the first conductive structure; a second metallization layer comprising a second conductive structure and a second dielectric layer adjacent to the second conductive structure; A phase change element of a phase change material, located between the first metallization layer and the second metallization layer in a first direction, wherein the first direction is a vertical direction, the phase change element is electrically coupled to the first conductive structure, and the phase change element is separated from the second metallization layer by an insulating region in the first direction; a resistor element contacting the phase change element via a first edge surface of the resistor element in a second direction transverse to the first direction, the resistor element being spaced apart from both the first metallization layer and the second metallization layer in the first direction; as well as a first insulating layer covering and directly contacting the resistive element and the phase change element, a second edge surface of the resistive element opposite to the first edge surface being exposed from the first insulating layer, the first insulating layer being a continuous layer; Wherein the resistive element is a planar horizontal layer, and a portion of the phase change element is located above a level of the resistive element and a portion of the phase change element is located below the level of the resistive element.

14. The structure of claim 13, comprising a conductive pad structure between the phase change element and the first conductive structure in the first direction.

15. The structure of claim 14, comprising a switching element of a chalcogenide material or an alloy of said chalcogenide material, said switching element being in contact with said second edge surface of said resistive element opposite to said first edge surface.

16. A method of manufacturing a device including a phase change memory cell, the method comprising: forming a phase change element of phase change material over and electrically coupled to a metal structure in a metallization layer; forming a resistive element in lateral contact with the phase change element, the resistive element being separated from the metallization layer by a first insulating layer; as well as forming a continuous third insulating layer, the continuous third insulating layer covering and directly contacting the phase change element and the resistive element, wherein a lateral surface of the resistive element that is not in lateral contact with the phase change element is exposed from the continuous third insulating layer, Wherein the resistive element is a planar horizontal layer, and a portion of the phase change element is located above a level of the resistive element and a portion of the phase change element is located below the level of the resistive element.

17. The method according to claim 16, wherein: Forming the phase change element includes: forming a layer stack on the metallization layer, the layer stack comprising the first insulating layer, the material layer of the resistive element, and a second insulating layer; forming a first cavity through the stack and exposing a first sidewall of the material layer of the resistive element; and The phase change element is formed on the first sidewall.

18. The method of claim 17, comprising forming a second cavity exposing a second sidewall of the material layer of the resistive element. The method of claim 18 , comprising forming a contact structure on the second sidewall.

20. The method of claim 18, comprising forming a select element of a chalcogenide material or an alloy of the chalcogenide material on the second sidewall.

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