Buck-boost converter

By detecting and adjusting the turn-on and turn-off times of transistors, the low efficiency and switching breakdown risk caused by improper switching frequency in traditional buck-boost converters are resolved, achieving more efficient and stable power output.

CN114430232BActive Publication Date: 2026-02-03PEGATRON
View PDF 1 Cites 0 Cited by

Patent Information

Application Number
CN202111246884.5
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2020-10-29
Filing Date
2021-10-26
Publication Date
2026-02-03
Estimated Expiration
2041-10-26

AI Technical Summary

Technical Problem

Traditional buck-boost converters are inefficient when the switching frequency is too fast, and there is a risk of switch breakdown when the switching frequency is too slow, resulting in unstable output power.

Method used

The voltage level of the third control signal is detected by the voltage detection circuit, and the voltage control circuit adjusts the turn-on and turn-off times of the transistor according to the voltage drop indication signal to optimize the transistor switching process and improve switching efficiency.

Benefits of technology

This improves the operating efficiency of the buck-boost converter, avoids the risk of switch breakdown, and ensures the stability of the output power supply.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN114430232B_ABST
    Figure CN114430232B_ABST
Patent Text Reader

Abstract

A buck-boost converter includes an inductor, a first transistor, a second transistor, a third transistor, a fourth transistor, a voltage detection circuit, and a voltage control circuit. The first transistor is coupled to a first end of the inductor and receives a first control signal. The second transistor is coupled to the first end of the inductor and receives a second control signal. The third transistor is coupled to a second end of the inductor and receives a third control signal. The fourth transistor is coupled to the second end of the inductor and receives a fourth control signal. The detection circuit detects the third control signal to selectively provide a voltage drop indication signal. The voltage control circuit switches an on state of the third control signal in response to the voltage drop indication signal when a voltage conversion mode is a buck mode.
Need to check novelty before this filing date? Find Prior Art

Description

Technical Field

[0001] This invention relates to a DC-DC converter, and more particularly to a buck-boost converter. Background Technology

[0002] With the widespread use of portable electronic devices, DC-DC converters, which do not require AC conversion and have high conversion efficiency, are widely used in portable electronic devices that rely primarily on batteries for power. DC-DC converters can be broadly classified into buck converters, boost converters, and buck-boost converters. In a buck-boost converter, when operating in buck mode, the upper switch on the boost side needs to maintain sufficient electrical conduction. This is why, in traditional boost converters, the upper and lower switches alternately conduct at a fixed frequency. However, switching too frequently consumes too much energy, leading to decreased efficiency, while switching too slowly may risk switch shoot-through and even cause output power instability. Summary of the Invention

[0003] This invention provides a buck-boost converter that can improve the switching efficiency of transistors.

[0004] The buck-boost converter of the present invention includes an inductor, a first transistor, a second transistor, a third transistor, a fourth transistor, a voltage detection circuit, and a voltage control circuit. The inductor has a first terminal and a second terminal. The first transistor has a drain terminal for receiving an input voltage, a source terminal coupled to the first terminal of the inductor, and a gate terminal for receiving a first control signal. The second transistor has a drain terminal coupled to the first terminal of the inductor, a source terminal for receiving a ground voltage, and a gate terminal for receiving a second control signal. The third transistor has a drain terminal for providing an output voltage, a source terminal coupled to the second terminal of the inductor, and a gate terminal for receiving a third control signal. The fourth transistor has a drain terminal coupled to the second terminal of the inductor, a source terminal for receiving a ground voltage, and a gate terminal for receiving a fourth control signal. The voltage detection circuit is coupled to the gate terminal of the third transistor to receive the third control signal to detect the voltage level of the third control signal, and selectively provides a voltage drop indication signal based on the detection result of the third control signal. The voltage control circuit is coupled to the gate terminals of the first transistor, the second transistor, the third transistor, and the fourth transistor. When the buck-boost converter is operating in buck mode, the voltage control circuit reacts to the voltage drop indication signal to determine the voltage level of the third control signal to switch from the current level to the cutoff level.

[0005] Based on the above, the buck-boost converter of this embodiment detects the voltage level of the third control signal and switches the conduction of the third transistor and the fourth transistor in response to the voltage drop of the third control signal, thereby improving the operating efficiency of the buck-boost converter.

[0006] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a buck-boost converter according to an embodiment of the present invention.

[0008] Figure 2 The diagram shows the waveforms of the third and fourth control signals of a buck-boost converter according to an embodiment of the present invention.

[0009] Figure 3 This is a flowchart illustrating the operation of the third and fourth transistors of a buck-boost converter according to an embodiment of the present invention in buck mode.

[0010] The reference numerals in the attached figures are explained as follows:

[0011] 100: Buck-Boost Converter

[0012] 110: Voltage control circuit

[0013] 120: Voltage detection circuit

[0014] a: First end

[0015] AGND: Grounding voltage

[0016] b: Second end

[0017] C1: First capacitor

[0018] C2: Second capacitor

[0019] L1: Inductor

[0020] LGATE1: Second control signal

[0021] LGATE2: Fourth control signal

[0022] Loff: Cutoff level

[0023] Lon: On / off level

[0024] Q1: First transistor

[0025] Q2: Second transistor

[0026] Q3: Third transistor

[0027] Q4: The fourth transistor

[0028] R1-R4: Resistors

[0029] SVD: Voltage Drop Indication Signal

[0030] T0: Time point

[0031] T1: Switch time point

[0032] UGATE1: First control signal

[0033] UGATE2: Third control signal

[0034] VIN: Input voltage

[0035] VOUT: Output voltage

[0036] Vth: Preset voltage level

[0037] S310, S320, S330, S340, S350: Steps

[0038] ΔT: Delay time Detailed Implementation

[0039] Figure 1 This is a schematic diagram of a buck-boost converter according to an embodiment of the present invention. Please refer to... Figure 1 In this embodiment, the buck-boost converter 100 includes an inductor L1, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a voltage control circuit 110, a voltage detection circuit 120, a first capacitor C1, a second capacitor C2, and resistors R1-R4.

[0040] The first transistor Q1 has a drain terminal that receives the input voltage VIN, a source terminal that is coupled to the first terminal a of the inductor L1, and a gate terminal that receives the first control signal UGATE1. The second transistor Q2 has a drain terminal that is coupled to the first terminal a of the inductor L1, a source terminal that receives the ground voltage AGND, and a gate terminal that receives the second control signal LGATE1.

[0041] The third transistor Q3 has a drain terminal providing the output voltage VOUT, a source terminal coupled to the second terminal b of inductor L1, and a gate terminal receiving the third control signal UGATE2. The fourth transistor Q4 has a drain terminal coupled to the second terminal b of inductor L1, a source terminal receiving the ground voltage AGND, and a gate terminal receiving the fourth control signal LGATE2. The first capacitor C1 is coupled between the input voltage VIN and the ground voltage AGND. The second capacitor C2 is coupled between the output voltage VOUT and the ground voltage AGND.

[0042] The voltage control circuit 110 is coupled to the gate terminals of the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 through resistors R1-R4, respectively, and provides the first control signal UGATE1, the second control signal LGATE1, the third control signal UGATE2, and the fourth control signal LGATE2 to the gate terminals of the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 based on the voltage conversion mode of the buck-boost converter 100.

[0043] Furthermore, when the target voltage of the output voltage VOUT is greater than the current voltage of the output voltage VOUT, the buck-boost converter 100 can operate in boost mode; when the target voltage of the output voltage VOUT is less than the current voltage of the output voltage VOUT, the buck-boost converter 100 can operate in buck mode.

[0044] The voltage detection circuit 120 receives the third control signal UGATE2 to detect the voltage level of the third control signal UGATE2, and selectively sends a voltage drop indication signal SVD based on the detection result of the third control signal UGATE2. When the voltage conversion mode of the buck-boost converter 100 is buck mode, the voltage control circuit 110 reacts to the voltage drop indication signal SVD to determine the switching time point when the third control signal UGATE2 switches from the on level to the off level, that is, determines the switching time point when the third transistor Q3 switches from on to off.

[0045] Furthermore, when the buck-boost converter 100 operates in buck mode and a voltage drop indication signal SVD indicating that the voltage level of the third control signal UGATE2 is too low (i.e., insufficient energy) is sent, the voltage control circuit 110 will switch the third control signal UGATE2 from the on level to the off level upon receiving the voltage drop indication signal SVD. Simultaneously, the voltage control circuit 110 will switch the fourth control signal LGATE2 from the off level to the on level to reset the state of the gate terminal of the third transistor Q3. In this way, by detecting the voltage level of the control signal of the third transistor Q3, the timing of switching the conduction of the third transistor Q3 and the fourth transistor Q4 is determined based on the degree of voltage drop in the control signal of the third transistor Q3, thereby improving the operating efficiency of the buck-boost converter.

[0046] Next, after the third control signal UGATE2 switches to the off level, the voltage detection circuit 120 will switch the third control signal UGATE2 back to the on level after a preset time (e.g., a few microseconds) to turn on the third transistor Q3. Furthermore, when the voltage conversion mode is buck mode and the voltage control circuit 110 does not receive the voltage drop indication signal SVD, the third control signal UGATE2 will remain at the on level to continuously turn on the third transistor Q3.

[0047] In this embodiment of the invention, when the voltage conversion mode is boost mode, the first control signal UGATE1 is maintained at the on level, the second control signal LGATE1 is maintained at the off level, the third control signal UGATE2 is maintained at the off level, and the fourth control signal LGATE2 periodically switches between the off level and the on level to control the voltage level of the output voltage VOUT. When the voltage conversion mode is buck mode, the first control signal UGATE1 periodically switches between the off level and the on level to control the voltage level of the output voltage VOUT, the second control signal LGATE1 is maintained at the off level, the third control signal UGATE2 is maintained at the on level, and the fourth control signal LGATE2 is maintained at the off level.

[0048] In this embodiment, the first capacitor C1 and the second capacitor C2 are shown as one for illustration. However, in this embodiment of the invention, the number of the first capacitor C1 and the number of the second capacitor C2 can be determined according to the circuit requirements. That is, the number of the first capacitor C1 and the second capacitor C2 can be one or more, and this embodiment of the invention is not limited thereto.

[0049] Figure 2 The diagram shows the waveforms of the third and fourth control signals of a buck-boost converter according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2 In this embodiment, the voltage detection circuit 120 detects at time point T0 that the voltage level of the third control signal UGATE2 is lower than the preset voltage level Vth. At this time, the voltage detection circuit 120 provides the voltage drop indication signal SVD to the voltage control circuit 110. When the voltage control circuit 110 receives the voltage drop indication signal SVD, it switches the fourth control signal LGATE2 from the cutoff level Loff to the on level Lon at the switching time point T1. Then, after a delay time ΔT, it switches the third control signal UGATE2 from the current level (i.e., the preset voltage level Vth) to the cutoff level Loff. The delay time ΔT is related to the equivalent resistance and equivalent capacitance values ​​coupled to the gate terminal of the third transistor Q3, such as the resistance value of resistor R3 and the capacitance value of the capacitor (not shown) coupled to resistor R3.

[0050] In this embodiment of the invention, the preset voltage level Vth can be the middle level (i.e., the average value) between the conduction level Lon and the cutoff level Loff, or slightly higher than the middle level, which can be determined according to the circuit requirements.

[0051] Figure 3 This is a flowchart illustrating the operation of the third and fourth transistors of a buck-boost converter according to an embodiment of the present invention in buck mode. Please refer to... Figure 3 In this embodiment, when the buck-boost converter operates in buck mode, it first detects the voltage level of the third control signal of the third transistor (step S310) and determines whether the voltage level of the third control signal is less than a preset voltage level (step S320). If the voltage level of the third control signal is not less than the preset voltage level, that is, the determination result of step S320 is "no", it means that the third control signal is normal (step S330), and then returns to step S310; if the voltage level of the third control signal is less than the preset voltage level, that is, the determination result of step S320 is "yes", it means that the voltage level of the third control signal is too low, and then the third control signal is switched to the cutoff level (step S340) and the fourth control signal is switched to the on level (step S350), and returns to step S310 after a preset time. The order of steps S310, S320, S330, S340 and S350 is for illustrative purposes, and the embodiment of the present invention is not limited thereto. Furthermore, details of steps S310, S320, S330, S340, and S350 can be found in [reference needed]. Figure 1 and Figure 2 As shown in the examples, they will not be repeated here.

[0052] In summary, the buck-boost converter of this embodiment detects the voltage level of the third control signal and switches the conduction of the third transistor and the fourth transistor in response to the voltage drop of the third control signal, thereby improving the operating efficiency of the buck-boost converter.

[0053] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A buck-boost converter, comprising: An inductor having a first terminal and a second terminal; A first transistor has a drain terminal that receives an input voltage, a source terminal that is coupled to the first terminal of the inductor, and a gate terminal that receives a first control signal. A second transistor has a drain terminal coupled to the first terminal of the inductor, a source terminal receiving a ground voltage, and a gate terminal receiving a second control signal. A third transistor has a drain terminal that provides an output voltage, a source terminal that is coupled to the second terminal of the inductor, and a gate terminal that receives a third control signal. A fourth transistor has a drain terminal coupled to the second terminal of the inductor, a source terminal receiving the ground voltage, and a gate terminal receiving a fourth control signal; A voltage detection circuit, coupled to the gate terminal of the third transistor, is used to receive the third control signal to detect the voltage level of the third control signal, and selectively provide a voltage drop indication signal based on a detection result of the third control signal. as well as A voltage control circuit, coupled to the gate of the first transistor, the gate of the second transistor, the gate of the third transistor, and the gate of the fourth transistor, is configured to, when the buck-boost converter is operating in a buck mode, respond to the voltage drop indication signal and determine whether the voltage level of the third control signal is switched from a current level to a cutoff level.

2. The buck-boost converter as described in claim 1, characterized in that, When the voltage level of the third control signal is lower than a preset voltage level, the voltage detection circuit provides the voltage drop indication signal to the voltage control circuit, and when the voltage control circuit receives the voltage drop indication signal, it switches the voltage level of the third control signal from the current level to the cutoff level.

3. The buck-boost converter as described in claim 2, characterized in that, The preset voltage level is an intermediate level between the on-state level and the off-state level.

4. The buck-boost converter as described in claim 2, characterized in that, After the voltage level of the third control signal is switched to the cutoff level, the voltage detection circuit waits for a preset time before switching the voltage level of the third control signal from the cutoff level to a conduction level.

5. The buck-boost converter as described in claim 2, characterized in that, When the buck-boost converter operates in buck mode, the voltage level of the first control signal periodically switches between the cutoff level and a conduction level, the voltage level of the second control signal is maintained at the cutoff level, the voltage level of the third control signal is maintained at the conduction level, and the voltage level of the fourth control signal is maintained at the cutoff level.

6. The buck-boost converter as described in claim 5, characterized in that, The voltage control circuit responds by switching the voltage level of the third control signal from the current level to the cutoff level after the voltage drop indication signal switches the fourth control signal from the cutoff level to the on level.

7. The buck-boost converter as described in claim 2, characterized in that, When the voltage control circuit does not receive a voltage drop indication signal, it maintains the third control signal at a conduction level.

8. The buck-boost converter as described in claim 1, characterized in that, Also includes: At least one first capacitor is coupled between the input voltage and the ground voltage; as well as At least one second capacitor is coupled between the output voltage and the ground voltage.

Citation Information

Patent Citations

  • Switching converter with reduced dead-time

    US10784775B1