Sensor packaging structure and method

Abstract

The present invention relates to a sensor packaging structure and method, wherein the sensor packaging structure includes: a CMOS circuit substrate, including a CMOS circuit and a first electrical connection terminal; a detection structure, including a functional unit and an electrical lead-out terminal; a first cofferdam, located between the CMOS circuit and the detection structure, wherein the CMOS circuit, the first cofferdam and the detection structure form a first cavity, wherein the first cavity at least partially surrounds the functional unit; and an electrical connection structure, disposed in the area where the first cofferdam of the CMOS circuit is exposed, and connecting the electrical lead-out terminal to the first electrical connection terminal. The present invention achieves integrated packaging by bonding the CMOS circuit to the detection structure, thereby greatly reducing the package volume and improving the degree of integration; in addition, the first cofferdam and the electrical connection structure are separately disposed, and the electrical connection structure does not need to rely on the first cofferdam for formation, which is more flexible in terms of process and time, reduces the limitations of the CMOS circuit in the process conditions for forming the cavity and the electrical connection, expands the process window, and shortens the process time.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device manufacturing, and in particular to a sensor packaging structure and method. Background Art

[0002] With the development of Internet of Things technology and the improvement of people's quality of life, the application prospects of sensors are becoming more and more extensive. Their integrated packaging mainly integrates semiconductor chips such as MEMS chips, thermopile chips or filters with other functional devices or CMOS circuits. The resulting sensors have the advantages of small size, light weight, no need for refrigeration, high sensitivity, etc. They are widely used in security monitoring, medical treatment, life detection and consumer products, and their development is also more rapid.

[0003] The packaging of infrared sensors usually adopts TO packaging, that is, the detection chip is attached to the packaging base, and then the chip pads and the pins of the base are connected by wire bonding, and finally the cap and the base are sealed.

[0004] However, the infrared sensor's packaging structure has very long pins and a large packaging volume, which seriously restricts its application in miniaturized devices. Summary of the Invention

[0005] The object of the present invention is to provide a sensor packaging structure and method, which can integrate packaging, reduce volume and improve reliability.

[0006] In order to achieve the above object, the present invention provides a sensor packaging structure, comprising:

[0007] A CMOS circuit substrate, comprising a CMOS circuit and a first electrical connection terminal;

[0008] A detection structure, including a functional unit and electrical leads;

[0009] a first cofferdam located between the CMOS circuit and the detection structure, wherein the CMOS circuit, the first cofferdam and the detection structure form a first cavity, and the first cavity at least surrounds a portion of the functional unit;

[0010] The electrical connection structure is disposed in the area where the first cofferdam of the CMOS circuit is exposed, and connects the electrical lead-out terminal to the first electrical connection terminal.

[0011] The present invention also provides a sensor packaging method, comprising:

[0012] Providing a CMOS circuit substrate, including a CMOS circuit and a first electrical connection terminal;

[0013] forming a detection structure, the detection structure comprising a functional unit located on a first surface of a substrate and an electrical lead-out terminal located on a second surface of the substrate away from the first surface;

[0014] Providing a capping layer, wherein the capping layer is bonded to the first surface of the detection structure and forms a second cavity, wherein the second cavity at least partially surrounds the functional unit;

[0015] forming a first cofferdam connecting the CMOS circuit substrate and the second surface of the detection structure, wherein the first cofferdam, the CMOS circuit, and the detection structure form a first cavity, and the first cavity at least surrounds a portion of the functional unit;

[0016] An electrical connection structure is formed, wherein the electrical connection structure electrically connects the electrical lead-out terminal to the first electrical connection terminal, and the electrical connection structure is located in an area where the first cofferdam of the CMOS circuit is exposed.

[0017] The beneficial effects of the sensor packaging structure of the present invention are:

[0018] The CMOS circuit is bonded to the detection structure through a first cofferdam, and the detection structure and the CMOS circuit are electrically connected through an electrical connection structure, thereby achieving integrated packaging, greatly reducing the package volume and improving the integration level. The first cavity is formed by bonding to ensure that the first cavity has good sealing properties, thereby isolating it from the external environment, improving the sensitivity and accuracy of the sensor, and ensuring its quality and reliability. In addition, the first cofferdam and the electrical connection structure are set separately, and the electrical connection structure does not need to rely on the first cofferdam for formation. It is more flexible in terms of process and time, reducing the restrictions on the CMOS circuit in the process conditions of forming the cavity and electrical connection, expanding the process window, and shortening the process time.

[0019] The first cofferdam is made of metal material and has the same layer structure as the electrical connection structure. The small-sized first cofferdam can support the formation of the cavity and can be formed in the same process as the electrical connection structure, reducing the process steps and greatly shortening the process time.

[0020] Furthermore, by setting the sub-dam on the CMOS circuit substrate and the detection structure respectively, and then bonding them through a flat layer, the sealing of the first cavity is ensured; in addition, the structural strength of the sensor is improved through bonding, while the support is simplified, and the bonding material is easy to obtain, thereby reducing the packaging cost.

[0021] Furthermore, by setting the width of the first cofferdam, support for the detection structure can be achieved, a higher support capacity can be provided, and the first cofferdam can be prevented from being corroded or oxidized in the environment, thereby improving the reliability of the product.

[0022] Furthermore, since the melting point of the first cofferdam is relatively high, when the CMOS circuit and the detection structure are bonded through the first cofferdam, the first cofferdam is prone to overflow. By forming an anti-overflow ring around the first cofferdam, the metal overflow can be limited to a certain range, thereby avoiding overflow onto the CMOS circuit substrate or the detection structure.

[0023] Furthermore, sub-cavities are formed on the substrate corresponding to the functional elements of the array, thereby enhancing the heat insulation effect of the detection structure, thereby effectively preventing each functional unit from exchanging temperature with the outside in the direction of the substrate.

[0024] Furthermore, a second cofferdam bonds the capping layer to the detection structure, creating a closed second cavity between the detection structure and the capping layer. This cavity improves infrared transmittance while isolating the detection structure from the external environment, thereby preventing detection errors caused by the detection structure. Furthermore, it supports bonding to the CMOS circuit during the fabrication process.

[0025] Furthermore, since the melting point of the second cofferdam is relatively high, when the sealing structure and the detection structure are bonded through the second cofferdam, the second cofferdam is prone to overflow. By forming a first groove on the sealing layer and setting the second cofferdam in the first groove, the overflowing metal can be limited to a certain range, thereby avoiding overflow onto the detection structure.

[0026] Furthermore, dummy bumps are formed to support the capping layer, thereby ensuring that the capping layer and the functional unit are uniformly stressed during bonding, thereby avoiding cracking.

[0027] Furthermore, the position of the dummy bump corresponds to that of the electrical connection structure, which can balance the force on the device structure during bonding and avoid the occurrence of cracks due to uneven force on each layer during bonding; similarly, the position of the second cofferdam corresponds to that of the first cofferdam, which can balance the force on the device structure during bonding and avoid the occurrence of cracks due to uneven force on each layer during bonding.

[0028] Furthermore, by arranging the third electrical connection end on the outer side of the outer wall of the first cofferdam, the detection structure can be electrically connected to the outside through the third electrical connection end.

[0029] The beneficial effects of the sensor packaging method of the present invention are:

[0030] By separately forming the first cofferdam and the electrical connection structure, the CMOS circuit and the detection structure are bonded and electrically connected to achieve integrated packaging, thereby greatly reducing the package volume and improving the integration level. In addition, the electrical connection structure does not have to rely on the formation of the first cofferdam, and is more flexible in terms of process and time, reducing the restrictions on the CMOS circuit in the process conditions of forming the cavity and electrical connection, expanding the process window, and shortening the process time. When the CMOS circuit and the detection structure are bonded, the first cofferdam, the CMOS circuit, and the functional unit are enclosed to form a closed first cavity to ensure the sealing performance of the first cavity, thereby isolating it from the external environment and improving its reliability. In addition, the capping layer is bonded first to improve the supporting strength of the device and provide bearing conditions for the subsequent bonding of the COMS circuit.

[0031] Furthermore, since the CMOS circuit cannot be etched, an anti-overflow ring is formed on the CMOS circuit, so that the first cofferdam is formed in the annular groove of the anti-overflow ring. After the excess bonding material overflows, it will fill the gap between the groove and the cofferdam, thereby preventing metal from overflowing onto the CMOS circuit substrate or detection structure.

[0032] After providing the capping layer, the capping layer is etched to form a first groove, so that the subsequently formed second cofferdam is located within the first groove, thereby preventing the second cofferdam structure from overflowing during bonding. Furthermore, the capping layer is bonded to the detection structure via the second cofferdam to ensure the sealing performance of the second cavity and improve the infrared transmittance of the second cavity.

[0033] Furthermore, a dummy bump is formed between the CMOS circuit and the detection structure, and then bonded through the dummy bump to support the capping layer, so that the capping layer and the functional unit are evenly stressed during bonding, thus avoiding cracking.

[0034] Furthermore, after the CMOS circuit and the detection structure are connected, the detection structure is cut to set the third electrical connection end outside the outer wall of the first cofferdam, thereby facilitating the third electrical connection end to be electrically connected to the outside, and the connection method can be diversified. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0036] Figure 1 A schematic structural diagram of a sensor packaging structure provided by embodiment 1 of the present invention is shown;

[0037] Figure 2-Figure 7 The diagram shows the structures corresponding to different steps of the sensor packaging method according to the second embodiment of the present invention.

[0038] Description of reference numerals:

[0039] 1. CMOS circuit substrate; 11. CMOS circuit; 12. First electrical connection terminal; 13. Second electrical connection terminal; 2. Detection structure; 21. Functional unit; 22. Electrical lead terminal; 23. Substrate; 231. Sub-cavity; 24. Interconnection structure; 241. Wiring layer; 242. Third electrical connection terminal; 3. First cofferdam; 31. First sub-cofferdam; 32. Second sub-cofferdam; 4. First cavity; 5. Electrical connection structure; 6. Anti-overflow ring; 61. Annular groove; 7. Second cofferdam; 8. Capping layer; 81. First groove; 9. Second cavity; 10. Dummy bump. DETAILED DESCRIPTION

[0040] The sensor package structure and its manufacturing method of the present invention are further described in detail below, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and drawings. However, it should be noted that the technical solutions of the present invention can be implemented in a variety of different forms and are not limited to the specific embodiments described herein. The drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clarify the purpose of illustrating the embodiments of the present invention.

[0041] The terms "first", "second", etc. in the specification and claims are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It is to be understood that, where appropriate, these terms used in this manner are interchangeable, for example, to enable the embodiments of the invention described herein to operate in an order other than that described or shown herein. Similarly, if the method described herein comprises a series of steps, the order in which the steps are presented herein is not necessarily the only order in which the steps can be performed, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method. If a component in a particular figure is the same as a component in other figures, although these components can be easily identified in all figures, in order to make the description of the figures clearer, this specification will not mark all the same component numbers in each figure.

[0042] Example 1

[0043] Embodiment 1 provides a sensor packaging structure. Figure 1 This is a schematic diagram of a cross-sectional structure of a sensor packaging structure provided by Example 1 of the present invention, please refer to Figure 1 , the sensor packaging structure includes:

[0044] The CMOS circuit substrate 1 includes a CMOS circuit 11 and a first electrical connection terminal 12;

[0045] The detection structure 2 includes a functional unit 21 and an electrical lead-out terminal 22;

[0046] The first cofferdam 3 is located between the CMOS circuit 11 and the detection structure 2. The CMOS circuit 11, the first cofferdam 3 and the detection structure 2 form a first cavity 4. The first cavity 4 at least surrounds a portion of the functional unit 21.

[0047] The electrical connection structure 5 is disposed in the exposed area of ​​the first cofferdam 3 of the CMOS circuit 11 and connects the electrical lead-out terminal 22 to the first electrical connection terminal 12 .

[0048] In this embodiment, the detection structure 2 further includes a substrate 23, the functional unit 21 is disposed on a first surface of the substrate 23, the electrical lead-out terminal 22 is located on a second surface of the substrate 23 away from the functional unit 21, and the first cofferdam 3 is located on the second surface of the substrate 23. In other words, the functional unit 21 and the first cofferdam 3 are located on two opposite surfaces of the substrate 23. In addition, the electrical lead-out terminal 22 is electrically connected to the functional unit 21 via an interconnect structure 24, so that the functional unit 21 can be electrically connected to the CMOS circuit 11 via the electrical connection structure 5.

[0049] The detection structure 2 includes an array of functional units 21. A sub-cavity 231 corresponding to the functional unit 21 is formed on the substrate 23, and the sub-cavity 231 is connected to the first cavity 4. Specifically, when there is only one functional unit 21, the sub-cavity 231 corresponds to the functional unit 21, so that at least part of the functional area of ​​the functional unit 21 is exposed within the sub-cavity 231. When the functional units 21 are in an array, the number of sub-cavities 231 is set according to the number of functional units 21, and the positions are one-to-one corresponding, so that each functional unit 21 corresponds to a sub-cavity 231, thereby exposing at least part of the functional area of ​​each functional unit 21 to the corresponding sub-cavity 231, thereby achieving better thermal insulation. For example, in a thermal imaging sensor, the thermopile functional units are arranged in an array to form multiple thermal pixels, and each thermal pixel can correspond to a sub-cavity.

[0050] It should be noted that the interconnection structure 24 includes a wiring layer 241 and a third electrical connection terminal 242. The third electrical connection terminal 242 is located on the side of the functional unit 21 away from the substrate 23. A TSV hole penetrating the substrate 23 is formed by TSV technology, and then a wiring layer 241 is formed in the TSV hole, so that the wiring layer 241 is electrically connected to the electrical lead-out terminal 22 and the third electrical connection terminal 242 respectively, thereby electrically leading out the functional unit 21 to avoid the problem of poor reliability caused by exposure of the wiring layer 241.

[0051] In this embodiment, functional unit 21 comprises an array of thermopile structures, which include multiple thermocouple pairs. The thermocouple pairs are composed of two different materials connected in series. The two materials can be stacked or arranged in parallel. In addition, the two materials can be polysilicon and aluminum, or polysilicon and copper, or polysilicon with different doping levels. In other embodiments, functional unit 21, as the sensing structure of the sensor, can be a MEMS structure, a filter structure, etc. Functional unit 21 can also include at least some thermistors or at least some photoresistors.

[0052] To facilitate bonding of the CMOS circuit 11 and the detection structure 2, the first cofferdam 3 includes a first sub-cofferdam 31 and a second sub-cofferdam 32. The first sub-cofferdam 31 is disposed on the CMOS circuit substrate 1, and the second sub-cofferdam 32 is disposed on the detection structure 2. The first sub-cofferdam 31 and the second sub-cofferdam 32 are connected by a flat layer. It should be noted that the first sub-cofferdam 31 and the second sub-cofferdam 32 are annular structures with an opening therein. After the CMOS circuit 11 and the detection structure 2 are connected, the CMOS circuit 11, the first sub-cofferdam 31, the flat layer, the second sub-cofferdam 32, and the detection structure 2 enclose the opening to form a closed first cavity 4, thereby improving the sealing of the first cavity 4 and preventing interference from the external environment. In addition, when the functional unit is a thermopile structure, the first cavity 4 also has good thermal insulation properties, preventing the functional unit 21 from exchanging temperature with the outside world in the direction close to the substrate 23, thereby ensuring the quality and reliability of the sensor. The first cavity 4 can be formed in a circular, elliptical, or polygonal shape other than a rectangle, such as a pentagon or hexagon. In addition, by forming the first cofferdam 3 between the CMOS circuit substrate 1 and the detection structure 2, the airtightness and structural strength of the wafer-level packaging of the sensor can be effectively improved, and it is beneficial to the temperature concentration and interference shielding of the sensor, thereby improving the quality, reliability and yield of the wafer-level packaging of the sensor.

[0053] In this embodiment, the outer wall of the first cofferdam 3 is spaced a predetermined distance from the outer edge of the detection structure 2 or the CMOS circuit substrate 1 to ensure communication between the first cavity 4 and the sub-cavity on the substrate 1, thereby achieving improved thermal insulation. Furthermore, the width of the first cofferdam 3 is greater than 30 μm to provide sufficient support for the substrate 23. The ratio of the bonding surface area of ​​the first cofferdam 3 to the functional unit 21 to the surface area of ​​the functional unit 21 is greater than 10%. Furthermore, the ratio of the bonding surface area of ​​the first cofferdam 3 to the CMOS circuit substrate 1 to the surface area of ​​the CMOS circuit substrate 1 is greater than 10%, thereby enhancing the support provided by the first cofferdam to the functional unit 21 and / or the CMOS circuit substrate 1, thereby improving the sealing of the first cavity 4. The height of the first cofferdam 3 ranges from 1 to 20 μm, such as 5 μm, 10 μm, or 15 μm. Within this range, the first cofferdam 3 can provide support for the substrate 23, reduce temperature loss, and prevent corrosion or oxidation in the environment, thereby improving product reliability. The first cofferdam 3 is located outside at least a portion of the functional unit 21 and surrounds at least a portion of the functional unit 21. For example, taking a thermopile as an example, the thermopile has a hot end and a cold end, and the first cofferdam 3 surrounds the hot end of the thermopile. In addition, when the thermopile array is formed, the first cofferdam 3 surrounds a portion of the thermopile.

[0054] In this embodiment, the first cofferdam 3 includes one or a combination of metal materials, dielectric materials, and polymers. In this embodiment, the first cofferdam 3 includes a metal material, and the metal material includes a single layer, alloy, or a stacked film of aluminum, titanium, nickel, gold, chromium, copper, or platinum. In other embodiments, the first cofferdam 3 includes a dielectric material, and the dielectric material includes one or more materials selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, ethyl silicate, and polysilicon. In other embodiments, the first cofferdam 3 includes a polymer, such as a dry film, and the first cofferdam 3 is formed by a film lamination process. The first cofferdam 3 is formed on the CMOS circuit substrate 1, which enables the process of forming the CMOS circuit substrate 1 and the first cofferdam 3 to be separated from the process of forming the detection structure 2, thereby improving the packaging efficiency.

[0055] Correspondingly, the flat layer is a solder, such as tin, and the first sub-dam 31 and the second sub-dam 32 can be welded together through the flat layer, so that the CMOS circuit 11 and the detection structure 2 can be metal-bonded through the first sub-dam 31 and the second sub-dam 32. In other embodiments, when the first dam includes a dielectric material, the material of the flat layer includes silicon oxide, silicon nitride or silicon oxynitride, etc., and the first sub-dam 31 and the second sub-dam 32 are bonded by melting the flat layer. It should be noted that the flat layer is formed on the first sub-dam 31 and the second sub-dam 32 respectively, and then the flat layer is melted to bond the first sub-dam 31 and the second sub-dam 32. It should be noted that the flat layer needs to be flattened before bonding. In other embodiments, when the first dam 3 is a polymer, such as a dry film, the CMOS circuit 11 and the detection structure 2 are directly bonded together through the dry film.

[0056] When the first cofferdam 3 is made of metal, the electrical connection structure 5 can have the same layer structure as the first cofferdam 3. This facilitates the simultaneous formation of the electrical connection structure 5 when forming the first cofferdam 3, thus saving process steps. The material and structure of the electrical connection structure 5 can be similar to those of the first cofferdam 3 described above and will not be further described here. It should be noted that the electrical connection structure 5 is located outside the outer wall of the first cofferdam 3, so that the electrical connection structure 5 and the first cofferdam 3 are located at different positions within the CMOS circuit 11, thereby facilitating the separate formation of the electrical connection structure 5 and the first cofferdam 3.

[0057] In this embodiment, in order to prevent metal from overflowing onto the CMOS circuit substrate 11 or the detection structure 2 when the first sub-dam 31 and the second sub-dam 32 are bonded, a raised anti-overflow ring 6 is provided on the CMOS circuit substrate 1. The anti-overflow ring 6 has an annular groove 61. The first sub-dam 31 is located within the annular groove 61, and the distance between the surface of the first sub-dam 31 adjacent to the second sub-dam 32 and the CMOS circuit substrate 1 is less than the distance between the surface of the anti-overflow ring 6 adjacent to the second sub-dam 32 and the CMOS circuit substrate 1. Furthermore, the height difference between the first sub-dam 31 and the anti-overflow ring is not less than 1 μm. It should be noted that by making the surface of the first sub-dam 31 adjacent to the second sub-dam 32 lower than the surface of the anti-overflow ring 6 adjacent to the second sub-dam 32, so that the bonding plane between the first sub-dam 31 and the second sub-dam 32 is located within the annular groove 61, the metal overflows into the annular groove 6, thereby effectively preventing the metal from overflowing onto other components. In other embodiments, the overflow prevention ring is disposed on the detection structure 2, the second sub-cofferdam 32 is located in the annular groove, and the distance between the surface of the second sub-cofferdam 32 adjacent to the first sub-cofferdam 31 and the functional unit 21 is less than the distance between the surface of the overflow prevention ring adjacent to the first sub-cofferdam 31 and the functional unit 21. The arrangement of the second sub-cofferdam 32 and the overflow prevention ring is similar to the arrangement of the first sub-cofferdam 31 relative to the overflow prevention ring 6 described above, and will not be repeated here.

[0058] A second cofferdam 7 and a capping layer 8 are provided on the detection structure 2. The second cofferdam 7 is located between the detection structure 2 and the capping layer 8. The detection structure 2, the second cofferdam 7, and the capping layer 8 enclose a second cavity 9. The second cavity 9 at least partially surrounds the functional unit 21. It should be noted that when the functional unit 21 is a thermopile structure, the second cavity 9 surrounds a portion of the hot end of the thermopile to facilitate improving the transmittance of infrared light through the second cavity 9. It also serves as a heat insulator to prevent temperature exchange with the outside world, thereby improving device performance.

[0059] In this embodiment, the second cofferdam 7 is positioned corresponding to the first cofferdam 3. That is, the projection of the second cofferdam 7 on the plane of the detection structure 2 completely overlaps the projection of the first cofferdam 3 on the plane of the detection structure 2, thereby improving the structural strength of the device. The structure and material of the second cofferdam 7 and the second cavity 9 can be referred to as the first cofferdam 3 and first cavity 4 described above, and will not be repeated here.

[0060] In order to prevent the metal from overflowing onto the capping layer 8 or the detection structure 2 when the capping layer 8 and the detection structure 2 are connected through the second cofferdam 7, the capping layer 8 has a first groove 81, and the first groove 81 is located outside the second cavity 9. The second cofferdam 7 is arranged in the first groove 81 and has a gap between it and the inner wall of the first groove 81, so that the metal overflows into the first groove 81. In addition, in order to make the metal overflow into the first groove 81 as much as possible during bonding, the second cofferdam 7 includes a sub-cofferdam arranged in the first groove 81 and a sub-cofferdam arranged on the detection structure 2. The bonding surfaces of the two sub-cofferdams are located in the first groove 81, so that the metal overflows into the first groove 81 during bonding, and the metal is prevented from overflowing onto the capping layer 8 or the detection structure 2. The difference between the groove depth of the first groove 81 and the height of the second cofferdam 7 is not less than 1μm. In other embodiments, an anti-overflow ring with an annular groove is provided on the detection structure 2, and the bonding surfaces of the two sub-cofferdams are located in the annular groove of the anti-overflow ring.

[0061] The material of the capping layer 8 includes semiconductor materials, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors. It can also be double-sided polished silicon wafers (DSP), or a ceramic substrate 10 such as alumina, quartz or glass substrate 10. In this embodiment, the material of the capping layer 8 is a semiconductor material that can transmit infrared rays, thereby improving device performance. In other embodiments, the material of the capping layer 8 can also be an optical material, such as glass, a filter, a lens, etc., or a polymer material, such as a dry film, a molding compound, etc.

[0062] In this embodiment, in order to prevent the capping layer 8 and / or the functional unit 21 from being cracked due to stress during bonding, a dummy bump 10 is further provided between the capping layer 8 and the detection structure 2. The dummy bump 10 is provided in an area outside the second cofferdam 7, that is, the dummy bump 10 is provided on the periphery of the outer wall of the second cofferdam 7. Specifically, the dummy bump 10 is provided corresponding to the electrical connection structure 5. The corresponding arrangement of the dummy bump 10 and the electrical connection structure 5 can refer to the corresponding arrangement of the first cofferdam 3 and the second cofferdam 7 mentioned above, and will not be repeated here. When the second cofferdam 7 is a dielectric material or a polymer, the dummy bump 10 and the second cofferdam 7 can have the same layer structure, so that when the second cofferdam 7 is formed, the dummy bump 10 can be formed simultaneously, thereby saving process steps.

[0063] In addition, to facilitate electrical connection of the CMOS circuit 11 to the outside, a second electrical connection terminal 13 is provided on the CMOS circuit 11, which is located outside the outer wall of the first cofferdam 3. It should be noted that the first electrical connection terminal 12 can be located outside the outer wall of the first cofferdam 3 or inside the inner wall of the first cofferdam 3. When the first electrical connection terminal 12 is located inside the inner wall of the first cofferdam 3, it is necessary to form a wiring on the CMOS circuit to facilitate electrical connection of the first electrical connection terminal 12 to the second electrical connection terminal 13, thereby facilitating electrical connection of the detection structure 2 to the outside.

[0064] In summary, the embodiment of the present invention bonds the CMOS circuit to the detection structure through a first cofferdam, and then realizes the electrical connection between the detection structure and the CMOS circuit through an electrical connection structure, thereby realizing integrated packaging, greatly reducing the package volume and improving the integration level; the first cavity is formed by bonding to ensure that the first cavity has good sealing properties, thereby isolating the external environment, improving the sensitivity and accuracy of the sensor, and ensuring its quality and reliability. In addition, the first cofferdam and the electrical connection structure are set separately, and the electrical connection structure does not need to rely on the first cofferdam to form, which is more flexible in terms of process and time, reducing the limitations of the CMOS circuit in the process conditions of forming the cavity and electrical connection, expanding the process window, and shortening the process time.

[0065] Furthermore, the first cofferdam is made of metal material, and the electrical connection structure has the same layer structure. The small-sized first cofferdam can support the formation of the cavity and can be formed in the same process as the electrical connection structure, thereby reducing process steps and greatly shortening process time.

[0066] Furthermore, by setting the sub-dam on the CMOS circuit substrate and the detection structure respectively, and then bonding them through a flat layer, the sealing of the first cavity is ensured; in addition, the structural strength of the sensor is improved through bonding, while the support is simplified, and the bonding material is easy to obtain, thereby reducing the packaging cost.

[0067] Furthermore, by setting the width of the first cofferdam, support for the detection structure can be achieved, a higher support capacity can be provided, and the first cofferdam can be prevented from being corroded or oxidized in the environment, thereby improving the reliability of the product.

[0068] Furthermore, since the melting point of the first cofferdam is relatively high, when the CMOS circuit and the detection structure are bonded through the first cofferdam, the first cofferdam is prone to overflow. By forming an anti-overflow ring around the first cofferdam, the metal overflow can be limited to a certain range, thereby avoiding overflow onto the CMOS circuit substrate or the detection structure.

[0069] Furthermore, sub-cavities are formed on the substrate corresponding to the functional elements of the array, thereby enhancing the heat insulation effect of the detection structure, thereby better avoiding temperature exchange between each functional unit and the outside world in the direction of the substrate.

[0070] Furthermore, a second cofferdam bonds the capping layer to the detection structure, creating a closed second cavity between the detection structure and the capping layer. This cavity improves infrared transmittance while isolating the detection structure from the external environment, thereby preventing detection errors caused by the detection structure. Furthermore, it supports bonding to the CMOS circuit during the fabrication process.

[0071] Furthermore, since the melting point of the second cofferdam is relatively high, when the sealing structure and the detection structure are bonded through the second cofferdam, the second cofferdam is prone to overflow. By forming a first groove on the sealing layer and setting the second cofferdam in the first groove, the overflowing metal can be limited to a certain range, thereby avoiding overflow onto the detection structure.

[0072] Furthermore, dummy bumps are formed to support the capping layer, thereby ensuring that the capping layer and the functional unit are uniformly stressed during bonding, thereby avoiding cracking.

[0073] Furthermore, the position of the dummy bump corresponds to that of the electrical connection structure, which can balance the force on the device structure during bonding and avoid the occurrence of cracks due to uneven force on each layer during bonding; similarly, the position of the second cofferdam corresponds to that of the first cofferdam, which can balance the force on the device structure during bonding and avoid the occurrence of cracks due to uneven force on each layer during bonding.

[0074] Furthermore, by arranging the third electrical connection end on the outer side of the outer wall of the first cofferdam, the detection structure can be electrically connected to the outside through the third electrical connection end.

[0075] Example 2

[0076] Embodiment 2 provides a sensor packaging method, which includes:

[0077] S01: Providing a CMOS circuit substrate, including a CMOS circuit and a first electrical connection terminal;

[0078] S02: forming a detection structure, the detection structure including a functional unit located on a first surface of the substrate and an electrical lead-out terminal located on a second surface of the substrate away from the first surface;

[0079] S03: providing a capping layer, wherein the capping layer is bonded to the first surface of the detection structure to form a second cavity, and the second cavity at least surrounds a portion of the functional unit;

[0080] S04: forming a first cofferdam to connect the CMOS circuit substrate and the second surface of the detection structure, wherein the first cofferdam, the CMOS circuit, and the detection structure form a first cavity, and the first cavity at least surrounds a portion of the functional unit;

[0081] S05: forming an electrical connection structure, wherein the electrical connection structure electrically connects the electrical lead-out terminal to the first electrical connection terminal, and the electrical connection structure is located in an area where the first cofferdam of the CMOS circuit is exposed.

[0082] Steps S0N do not represent a sequential order.

[0083] Figures 2 to 7 This is a schematic structural diagram corresponding to the corresponding steps of the manufacturing method of a sensor packaging structure of this embodiment, with reference to Figures 2 to 7 The manufacturing method of the sensor packaging structure provided by this embodiment is described in detail.

[0084] refer to Figure 2 , providing a CMOS circuit substrate, including a CMOS circuit 11 and a first electrical connection end 12.

[0085] In this embodiment, the CMOS circuit substrate further includes a second electrical connection structure 13 located on the periphery of the CMOS circuit 11, so as to facilitate electrical connection of the CMOS circuit 11 to the outside world. It should be noted that the second electrical connection terminal 13 is formed after the CMOS circuit 11 is provided. In addition, the formed first electrical connection terminal 12 can be located on the periphery of the outer wall of the first cofferdam formed subsequently, or can be located on the inner periphery of the inner wall of the first cofferdam formed subsequently. It should be noted that when the second electrical connection terminal 13 is formed after the CMOS circuit 11 is provided, it is also necessary to form wiring on the CMOS circuit 11 so as to facilitate connection of the first electrical connection terminal 12 to the second electrical connection terminal 13 formed subsequently; similarly, when the formed first electrical connection terminal 12 is located on the inner periphery of the inner wall of the first cofferdam formed subsequently, it is also necessary to form wiring on the CMOS circuit 11 so as to facilitate connection of the first electrical connection terminal 12 to the second electrical connection terminal 13 formed subsequently, thereby facilitating electrical connection of the functional unit 21 to the outside world.

[0086] refer to Figure 3-Figure 6, forming a detection structure, the detection structure includes a functional unit 21 located on the first surface of the substrate 23 and an electrical lead-out terminal 22 located on the second surface of the substrate 23 away from the first surface.

[0087] In this embodiment, the method for forming the detection structure 2 includes: forming a functional unit 21 on the first surface of the substrate 23, referring to Figure 3 Forming an interconnect structure 24, the interconnect structure 24 passes through the substrate 23, and the functional unit 21 is electrically led to the electrical lead end 22, reference Figure 4-Figure 5 It should be noted that the functional unit 21 can refer to that described in Example 1, and regardless of the device structure of the functional unit 21, its formation method belongs to the existing technology and will not be repeated here. The interconnection structure 24 is formed after the capping layer 8 is bonded to the first surface of the detection structure.

[0088] refer to Figure 4 Before forming the interconnection structure, a capping layer 8 is provided and bonded to the first surface of the detection structure. The method for providing the capping layer 8 is described below. Figure 5 The method for forming the interconnect structure 24 includes: forming a third electrical connection terminal 242 located on a side of the functional unit 21 away from the substrate 23; forming a TSV hole penetrating the substrate 23 and the functional unit 21 to expose a portion of the third electrical connection terminal 242; forming a wiring layer 241 within the TSV hole, connecting the third electrical connection terminal 242 and covering a portion of the second surface of the substrate 23; and forming an electrical lead 22 on the wiring layer 24 covering the portion of the second surface of the substrate 23. It should be noted that the formation of the wiring layer 241 can refer to existing implementation methods and will not be repeated here.

[0089] refer to Figure 6 In order to achieve a better thermal insulation effect and prevent the functional unit 21 from exchanging temperature with the outside world along the substrate 23, after forming the interconnection structure 24, the second surface of the substrate 23 is etched to form a sub-cavity 231. The arrangement of the sub-cavity 231 relative to the functional unit 21 refers to Example 1 and will not be repeated here.

[0090] refer to Figure 4-Figure 6 , providing a capping layer 8 , the capping layer 8 is bonded to the first surface of the detection structure and forms a second cavity 9 , and the second cavity 9 at least surrounds a portion of the functional unit 21 .

[0091] In this embodiment, after forming the third electrical connection terminal 242 and before forming the TSV hole, a capping layer 8 is provided, and the capping layer 8 is bonded to the first surface of the detection structure.

[0092] Since the second cofferdam 7 in this embodiment is made of metal, and metal is prone to metal overflow during bonding, after providing the capping layer 8, the capping layer 8 is etched to form the first groove 81; when forming the second cofferdam 7, the second cofferdam 7 is at least partially within the first groove 81. The structure and materials of the second cofferdam 7 and the first groove 81 are similar to those described in Example 1 and will not be repeated here. In other embodiments, a raised anti-overflow ring with an annular groove can also be formed on the functional unit 21. The anti-overflow ring is formed after the second cofferdam 7 is formed on the functional unit 21; the formed second cofferdam is at least partially located within the annular groove of the anti-overflow ring.

[0093] In this embodiment, to ensure the sealing of the second cavity 9, the steps of forming the second cavity 9 include: forming a second cofferdam 7, bonding the capping layer 8 and the detection structure 2 via the second cofferdam 7, and enclosing the second cofferdam 7, the detection structure 2, and the capping layer 8 to form the second cavity 9, which at least partially surrounds the functional unit 21. It should be noted that the structure and beneficial effects of the second cavity 9 refer to those described in Example 1 and will not be repeated here.

[0094] Specifically, the method for forming the second cofferdam 7, which connects the capping layer 8 and the detection structure 2, includes: forming a sub-cofferdam on the functional unit 21 after forming the third electrical connection terminal 242 and before forming the TSV hole; forming a sub-cofferdam on the capping layer 8 when providing the capping layer 8; and bonding the sub-cofferdam on the capping layer 8 and the sub-cofferdam on the functional unit 21 through the planar layer, thereby bonding the capping layer 8 to the first surface of the detection structure 2. The materials and beneficial effects of the second cofferdam 7 are described in Example 1 and are not further elaborated here.

[0095] In this embodiment, the method for forming a sub-dam on the capping layer 8 includes: forming a seed layer to cover the first groove 81 and the surface of the capping layer 8; forming a resistor layer to cover the seed layer; etching the resistor layer to expose the seed layer within the first groove 81; forming a sub-dam by electroplating to fill the first groove 81 and connect to the seed layer; etching the resistor layer to form an opening; and removing the seed layer and the resistor layer outside the first groove 81. It should be noted that when the sub-dam is formed within the first groove 81, the capping layer 8 serves as a support structure when bonding the functional unit 21 to the capping layer 8.

[0096] The method for forming a sub-dam on the functional unit 21 includes: forming a seed layer to cover the surface of the functional unit 21 away from the substrate 23; forming a resistor layer to cover the seed layer; etching the resistor layer to expose a portion of the seed layer; electroplating to form a sub-dam to fill the first groove 81 and connect the seed layer; etching the resistor layer to form an opening; and removing the seed layer and the resistor layer outside the first groove 81.

[0097] It should be noted that the sub-cofferdams formed on the capping layer 8 and the functional unit 21 respectively have openings. When the capping layer 8 and the functional unit 21 are bonded through the sub-cofferdams, the capping layer, the sub-cofferdams and the functional unit enclose the openings to form a closed second cavity 9. In addition, in order to ensure the sealing of the second cavity 9, the sub-cofferdams formed on the capping layer 8 and the sub-cofferdams formed on the functional unit 21 also form flat layers respectively and are bonded through the flat layers. The material of the flat layer is as described in Example 1 and will not be repeated here. It should be noted that before the two sub-cofferdams are bonded, other existing process operations can be performed on the capping layer 8 to increase the supporting strength of the capping layer 8.

[0098] In other embodiments, an anti-overflow ring is formed on the functional unit 21. Before forming the second cofferdam 7, an anti-overflow ring is formed on the surface of the functional unit 21, and then a sub-cofferdam is formed on the functional unit 21. The method for forming the sub-cofferdam on the capping layer 8 can be referred to and will not be repeated here. It should be noted that when the anti-overflow ring is provided on the functional unit 21, the capping layer 8 is bonded to the functional unit 21 using the functional unit 21 as a supporting structure. Before the two sub-cofferdams are bonded, other existing process operations can be performed on the functional unit to improve the supporting strength of the functional unit 21.

[0099] In addition, since the capping layer 8 and the functional unit 21 are susceptible to damage due to stress during bonding, a dummy bump 10 is formed between the capping layer 8 and the detection structure 2. The dummy bump 10 connects the detection structure 2 and the capping layer 8 so that the capping layer 8 and the functional unit 21 are evenly stressed. The dummy bump 10 can be formed before or after the second cofferdam 7 is formed, or it can be formed when the second cofferdam 7 is formed. When the material of the dummy bump 10 is the same as that of the second cofferdam 7, the dummy bump 10 can be formed simultaneously with the second cofferdam 7. It should be noted that when the dummy bump 10 is formed simultaneously with the second cofferdam 7, the steps for forming the dummy bump 10 are the same as those for forming the second cofferdam 7. The formed dummy bump 10 has the same layer structure as the second cofferdam 7, and the dummy bump 10 and the second cofferdam 7 are made of the same material. The specific materials and structures can be referred to in Example 1. The method for forming the dummy bump 10 can be referred to the method for forming the second cofferdam 7, and will not be repeated here.

[0100] refer to Figure 7 , forming a first cofferdam 3, connecting the CMOS circuit substrate 1 and the second surface of the detection structure 2, the first cofferdam 3 and the CMOS circuit 11, and the detection structure 2 enclose a first cavity 4, and the first cavity 4 at least surrounds part of the functional unit 21.

[0101] In this embodiment, the steps of forming the first bank 3 include: forming a first sub-bank 31 on the CMOS circuit substrate; forming a second sub-bank 32 on the detection structure 2; and bonding the first sub-bank 31 and the second sub-bank 32 via a planarization layer. It should be noted that the first sub-bank 31 can be formed after providing the CMOS circuit substrate, and the second sub-bank 32 can be formed after forming the detection structure 2. The structures, materials, and beneficial effects of the first sub-bank 31, the second sub-bank 32, and the planarization layer refer to those in Example 1 and are not further described here. It should be noted that the first cofferdam 3 can be arranged corresponding to the second cofferdam 7, that is, the projection of the first cofferdam 3 formed on the plane where the detection structure 2 is located completely overlaps with the projection of the second cofferdam 7 on the plane where the detection structure 2 is located. In addition, before forming the first sub-cofferdam 31 on the CMOS circuit substrate, it is necessary to form an isolation layer on the CMOS circuit substrate, and then etch the isolation layer corresponding to the position of the second cofferdam 7 to form a groove; then form the first sub-cofferdam in the groove, so that the first sub-cofferdam 31 and the second sub-cofferdam 32 are bonded to form the first cofferdam 3 corresponding to the position of the second cofferdam 7. When forming the second sub-cofferdam 32 on the detection structure, more specifically, when forming the second sub-cofferdam 32 on the substrate 23, an etch stop layer can also be formed between the second sub-cofferdam 32 and the substrate 23. The specific formation steps can refer to the method for forming the first sub-cofferdam 31 on the CMOS circuit substrate, and will not be repeated here.

[0102] Before forming the first cofferdam 3, an anti-overflow ring 6 is formed on the CMOS circuit 11 and / or the detection structure 2. The anti-overflow ring 6 has an annular groove therein. When forming the first cofferdam 3, the first cofferdam 3 is at least partially formed within the annular groove of the anti-overflow ring 6. The steps of forming the anti-overflow ring 6 and forming the first cofferdam 3 within the anti-overflow ring can be referred to in the method for forming the anti-overflow ring on the surface of the functional unit 21 described above and will not be repeated here. It should be noted that the anti-overflow ring 6 can be formed on the surface of the CMOS circuit 11 or on the second surface of the substrate 23.

[0103] Continue to refer Figure 7 , forming an electrical connection structure 5 , the electrical connection structure 5 electrically connects the electrical lead-out terminal 22 with the first electrical connection terminal 12 , and the electrical connection structure 5 is located in the exposed area of ​​the first cofferdam 3 of the CMOS circuit 11 .

[0104] In this embodiment, the first cofferdam 3 is made of metal material, and the electrical connection structure 5 has the same layer structure as the first cofferdam 3, so that the electrical connection structure 5 is formed simultaneously when the first cofferdam 3 is formed, thereby saving process steps and improving production efficiency. The material and structure of the electrical connection structure 5 and the metal material and structure of the first cofferdam 3 are not repeated here. It should be noted that before forming the electrical connection structure 5, another anti-overflow ring can be formed on the CMOS circuit substrate so that the formed first electrical connection end is located in the annular groove of the anti-overflow ring, so that the formed electrical connection structure 5 is located in the annular groove of the anti-overflow ring and is electrically connected to the first electrical connection end 12; alternatively, the anti-overflow ring can also be formed on the detection structure, and the formation method of the anti-overflow ring can refer to the formation method of the anti-overflow ring on the periphery of the first cofferdam 3, which will not be repeated here. In other embodiments, the first cofferdam 3 is made of dielectric material or polymer, and the electrical connection structure 5 can be formed before or after the formation of the first cofferdam 3. It should be noted that when forming the electrical connection structure 5 , it is necessary to form the electrical connection structure 5 according to the position of the dummy bump 10 relative to the functional unit 21 , so that the formed electrical connection structure 5 corresponds to the dummy bump 10 .

[0105] Since the CMOS circuit substrate 1 also includes a second electrical connection structure 13 located outside the CMOS circuit 11, after connecting the CMOS circuit 11 and the detection structure 2, the detection structure 2 and the capping layer 8 are cut so that the second electrical connection structure 13 is located outside the coverage of the detection structure 2, thereby facilitating electrical connection with the outside world.

[0106] To sum up, the embodiment of the present invention forms the first cofferdam and the electrical connection structure separately to bond and electrically connect the CMOS circuit and the detection structure to achieve integrated packaging, thereby greatly reducing the package volume and improving the integration. In addition, the electrical connection structure does not have to rely on the formation of the first cofferdam, and is more flexible in process and time, reducing the restrictions on the CMOS circuit in the process conditions of forming the cavity and electrical connection, expanding the process window, and shortening the process time; when the CMOS circuit is bonded to the detection structure, the first cofferdam is used to enclose the CMOS circuit and the functional unit to form a closed first cavity to ensure the sealing performance of the first cavity, thereby isolating it from the external environment and improving its reliability; in addition, the capping layer is bonded first to improve the support strength of the device and provide bearing conditions for the subsequent bonding of the COMS circuit.

[0107] Furthermore, since the CMOS circuit cannot be etched, an anti-overflow ring is formed on the CMOS circuit, so that the first cofferdam is formed in the annular groove of the anti-overflow ring. After the excess bonding material overflows, it will fill the gap between the groove and the cofferdam, thereby preventing metal from overflowing onto the CMOS circuit substrate or detection structure.

[0108] After providing the capping layer, the capping layer is etched to form a first groove, so that the subsequently formed second cofferdam is located within the first groove, thereby preventing the second cofferdam structure from overflowing during bonding. Furthermore, the capping layer is bonded to the detection structure via the second cofferdam to ensure the sealing performance of the second cavity and improve the infrared transmittance of the second cavity.

[0109] Furthermore, a dummy bump is formed between the CMOS circuit and the detection structure, and then bonded through the dummy bump to support the capping layer, so that the capping layer and the functional unit are evenly stressed during bonding, thus avoiding cracking.

[0110] Furthermore, after the CMOS circuit and the detection structure are connected, the detection structure is cut to set the third electrical connection end outside the outer wall of the first cofferdam, thereby facilitating the third electrical connection end to be electrically connected to the outside, and the connection method can be diversified.

[0111] It should be noted that the various embodiments in this specification are described in a related manner. Similar portions between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, since the structural embodiments are generally similar to the method embodiments, their description is relatively simple. For related portions, refer to the description of the method embodiments.

[0112] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A sensor packaging structure, characterized in that: include: A CMOS circuit substrate, comprising a CMOS circuit and a first electrical connection terminal; A detection structure, including a functional unit and electrical leads; a first cofferdam located between the CMOS circuit and the detection structure, wherein the CMOS circuit, the first cofferdam and the detection structure form a first cavity, and the first cavity at least surrounds a portion of the functional unit; an electrical connection structure, disposed in the region of the CMOS circuit where the first cofferdam is exposed, and connecting the electrical lead-out terminal to the first electrical connection terminal; The detection structure also includes a substrate, the functional unit is arranged on the first surface of the substrate, the electrical lead-out end is located on the second surface of the substrate away from the functional unit, the electrical lead-out end is electrically connected to the functional unit through an interconnection structure, and the first cofferdam is located on the second surface of the substrate.

2. The sensor packaging structure according to claim 1, characterized in that: The first cofferdam comprises one or a combination of metal material, dielectric material, and polymer.

3. The sensor packaging structure according to claim 1, wherein: The first cofferdam includes a first sub-cofferdam and a second sub-cofferdam. The first sub-cofferdam is arranged on the CMOS circuit substrate, and the second sub-cofferdam is arranged on the detection structure. The first sub-cofferdam and the second sub-cofferdam are connected through a flat layer.

4. The sensor packaging structure according to claim 1 or 3, characterized in that: The first cofferdam and the electrical connection structure have the same layer structure.

5. The sensor packaging structure according to claim 1, wherein: An outer wall of the first cofferdam is at a set distance from an outer edge of the detection structure or the CMOS circuit substrate.

6. The sensor packaging structure according to claim 1, characterized in that: The width of the first cofferdam is greater than 30 μm; The ratio of the bonding surface area of ​​the first cofferdam and the functional unit to the surface area of ​​the functional unit bonding surface is greater than 10%; and / or the ratio of the bonding surface area of ​​the first cofferdam and the CMOS circuit substrate to the surface area of ​​the CMOS circuit substrate bonding surface is greater than 10%.

7. The sensor packaging structure according to claim 3, characterized in that: The CMOS circuit substrate is provided with a raised anti-overflow ring, which has an annular groove inside the anti-overflow ring, the first sub-cofferdam is located in the annular groove, and the distance from the surface of the first sub-cofferdam adjacent to the second sub-cofferdam to the CMOS circuit substrate is smaller than the distance from the surface of the anti-overflow ring adjacent to the second sub-cofferdam to the CMOS circuit substrate; or, the detection structure is provided with a raised anti-overflow ring, which has an annular groove inside the anti-overflow ring, the second sub-cofferdam is located in the annular groove, and the distance from the surface of the first sub-cofferdam adjacent to the detection structure is smaller than the distance from the surface of the anti-overflow ring adjacent to the first sub-cofferdam to the detection structure.

8. The sensor packaging structure according to claim 7, characterized in that: A height difference between the first sub-cofferdam or the second sub-cofferdam and the anti-overflow ring is not less than 1 μm.

9. The sensor packaging structure according to claim 1, wherein: The detection structure includes functional units of an array, and sub-cavities corresponding to the functional units are opened on the substrate, and the sub-cavities are connected to the first cavity.

10. The sensor packaging structure according to claim 1, wherein: The detection structure is provided with a second cofferdam and a capping layer, the second cofferdam is located between the detection structure and the capping layer, the detection structure, the second cofferdam and the capping layer form a second cavity, and the second cavity at least surrounds part of the functional unit.

11. The sensor packaging structure according to claim 10, characterized in that: The capping layer has a first groove, the first groove is located outside the second cavity, the second cofferdam is arranged in the first groove, and a gap is formed between the second cofferdam and the inner wall of the first groove.

12. The sensor packaging structure according to claim 10, characterized in that: A dummy bump is further provided between the capping layer and the detection structure, and the dummy bump is arranged in an area outside the second cofferdam.

13. The sensor packaging structure according to claim 12, characterized in that: The second cofferdam is arranged corresponding to the first cofferdam; and / or the dummy bump is arranged corresponding to the electrical connection structure.

14. The sensor packaging structure according to claim 1, wherein: The CMOS circuit is further provided with a second electrical connection terminal, which is located outside the outer wall of the first cofferdam.

15. A sensor packaging method, characterized in that: include: Providing a CMOS circuit substrate, including a CMOS circuit and a first electrical connection terminal; forming a detection structure, the detection structure comprising a functional unit located on a first surface of a substrate and an electrical lead-out terminal located on a second surface of the substrate away from the first surface; Providing a capping layer, wherein the capping layer is bonded to the first surface of the detection structure and forms a second cavity, wherein the second cavity at least partially surrounds the functional unit; forming a first cofferdam connecting the CMOS circuit substrate and the second surface of the detection structure, wherein the first cofferdam, the CMOS circuit, and the detection structure form a first cavity, and the first cavity at least surrounds a portion of the functional unit; An electrical connection structure is formed, wherein the electrical connection structure electrically connects the electrical lead-out terminal to the first electrical connection terminal, and the electrical connection structure is located in a region of the CMOS circuit where the first cofferdam is exposed.

16. The sensor packaging method according to claim 15, characterized in that: The first bank forming step includes forming a first sub-bank on the CMOS circuit substrate and forming a second sub-bank on the detection structure, wherein the first sub-bank and the second sub-bank are bonded via a planar layer.

17. The sensor packaging method according to claim 15, characterized in that: Before forming the first cofferdam, forming an anti-overflow ring on the CMOS circuit and / or the detection structure, wherein the anti-overflow ring has an annular groove; When forming the first cofferdam, the first cofferdam is at least partially formed in the annular groove of the anti-overflow ring.

18. The sensor packaging method according to claim 15, characterized in that: The method for forming the detection structure includes: forming the functional unit on the first surface of the substrate; An interconnection structure is formed, wherein the interconnection structure penetrates the substrate and electrically leads the functional unit to the electrical lead-out terminal.

19. The sensor packaging method according to claim 15, wherein: Before the first cofferdam connects the CMOS circuit substrate and the second surface of the detection structure, the second surface of the substrate is etched to form a sub-cavity.

20. The sensor packaging method according to claim 15, wherein: The step of forming the second cavity includes: forming a second cofferdam, the sealing layer and the detection structure are bonded through the second cofferdam, the second cofferdam, the detection structure and the sealing layer form a second cavity, and the second cavity at least partially surrounds the functional unit.

21. The sensor packaging method according to claim 20, characterized in that: After providing the capping layer, etching the capping layer to form a first groove; When the second cofferdam is formed, the second cofferdam is at least partially within the first groove.

22. The sensor packaging method according to claim 20, characterized in that: Before the capping layer and the detection structure are bonded together through the second cofferdam, a dummy bump is formed, wherein the dummy bump connects the detection structure and the capping layer.

23. The sensor packaging method according to claim 22, characterized in that: The steps of forming at least one of the second cofferdam, the electrical connection structure and the dummy bump are the same as the method of forming the first cofferdam.

24. The sensor packaging method according to claim 22, wherein: The first cofferdam formed corresponds to the second cofferdam; and / or the electrical connection structure formed corresponds to the dummy bump.

25. The sensor packaging method according to claim 15, characterized in that: The CMOS circuit substrate includes a second electrical connection structure located at the periphery of the CMOS circuit; After connecting the CMOS circuit and the detection structure, the detection structure is cut so that the second electrical connection structure is located outside the coverage range of the detection structure.

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