A chip-level test verification system and chip detection method

Abstract

The present invention provides a chip-level test verification system, including: a host computer, which issues test instructions, global test bit streams and designated test bit streams; a first data processing module, which receives the global test bit stream and transmits it to a storage module; a storage module, which stores the global test bit stream output by the first data processing module; a test control module, which receives the designated test bit stream and controls the first data processing module to read the configuration information corresponding to the designated test bit stream to configure the chip under test; a comparison module, which receives the stimulus information corresponding to the designated test bit stream read by the test control module to configure the chip under test; sampling the output data of the chip under test, comparing it with the expected data in the stimulus information corresponding to the designated test bit stream, and storing the sampled data and sampling time with inconsistent comparison results. The system maximizes the reduction of test costs when entering the mass production stage from the initial production stage. The present invention also provides a chip detection method, which can also achieve the above effect.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and in particular to a chip-level testing and verification system and a chip detection method. Background Art

[0002] At present, there are generally two ways to test FPGA: one is to independently develop a test system, which should include functions such as configuring FPGA, loading test vectors, and reading test responses. This method often requires large investments, takes a long time, and is difficult to guarantee test accuracy. In addition, the developed test platform has poor portability and can only be used for research and verification. Another method is to use ATE (Automatic Test Equipment) to test FPGA, first configure the FPGA, and then test the configured circuit. In this way, multiple configuration tests of FPGA chips can be completed in the same operation process, reducing operation links, improving the test efficiency of FPGA chips, and realizing industrial testing of FPGA chips.

[0003] Traditional semiconductor mass production tests are all developed and implemented based on ATE. As a general test platform, ATE provides a variety of hardware boards (power supply, digital channels, analog / RF channels...) and a good software development environment, which can support mass production tests of certain types of semiconductor products. The advantages of ATE are universality, high test reliability, friendly operation interface, control handler / prober / TP, and complete test data analysis tools.

[0004] It is difficult to cover all fault points by relying solely on structural testing of DFT (Discrete Fourier Transform) for complex SoC chips, especially faults that can only be triggered under special conditions under some complex control combinations (such as requiring a certain power domain to enter sleep and then wake up, which may not be able to wake up due to timing or other reasons). They must be covered with complex functional patterns similar to system applications; if the boot process of the SoC is complex and time-consuming, ATE testing will generally use test mode to skip to save time, and special procedures are also required to test boot; for some HSIO interfaces, ATE generally avoids using expensive high-speed boards to test BERT and complete HSIO sequences, and mostly uses loopback to do it, so it is impossible to test HSIO. These requirements require system level test to improve test coverage and ensure delivery quality.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] Based on this, the present invention provides a chip-level test verification system and a chip detection method, which solves the problem of high testing cost when the chip enters the mass production stage from the initial production stage.

[0007] An embodiment of the present invention provides a chip-level test and verification system, the system comprising:

[0008] The host computer is used to issue test instructions and provide global test bit streams and specified test bit streams;

[0009] A first data processing module is used to receive the test instruction and the global test bit stream issued by the host computer, divide the global test bit stream into address information, configuration information and stimulus information, and transmit them to the storage module;

[0010] A storage module, used for storing the address information, the configuration information and the excitation information output by the first data processing module;

[0011] A test control module, for receiving the test instruction and the designated test bit stream issued by the host computer, and controlling the first data processing module to read the address information, configuration information and stimulus information corresponding to the designated test bit stream from the storage module according to the test instruction and the designated test bit stream; configuring the chip under test according to the read configuration information corresponding to the designated test bit stream; and transmitting the read stimulus information corresponding to the designated test bit stream to the comparison module;

[0012] A comparison module is used to receive the stimulus information corresponding to the specified test bit stream read by the test module, configure the chip under test according to the stimulus information corresponding to the specified test bit stream read; and sample the output data of the chip under test, compare the sampled output data with the expected data in the stimulus information corresponding to the specified test bit stream read, and transmit the sampled data and sampling time with inconsistent comparison results to the test control module and the host computer.

[0013] Furthermore, the system also includes a second data processing module, which receives the excitation information corresponding to the specified test bit stream read by the test control module, divides the read excitation information corresponding to the specified test bit stream into excitation data and expected data, and transmits the excitation data and the expected data to the comparison module.

[0014] Furthermore, the system also includes a delay module, which is used to receive the expected data from the second data processing module, delay the expected data, and transmit the delayed expected data to the comparison module.

[0015] Furthermore, the system also includes an error data storage module, which is used to receive the adopted data and sampling time with inconsistent comparison results of the comparison module, store and convert them into data that conforms to the interface protocol, and transmit them to the comparison module, the test control module and the host computer after the test verification system is completed.

[0016] Furthermore, the first data processing module includes:

[0017] A data read / write module receives the test instruction and the global test bit stream of the host computer, reads the information of the global test bit stream, divides the global test bit stream into address information, configuration information and stimulus information according to the read information, and transmits the information to the storage module;

[0018] The first data processing main state machine module receives the test instruction and the specified test bit stream issued by the test control module, and controls the data read / write module to read the address information, configuration information and stimulus information corresponding to the specified test bit stream according to the test instruction and the specified test bit stream, and transmits them to the test control module.

[0019] Furthermore, the first data processing module also includes:

[0020] The serial-to-parallel conversion module receives the test instruction and the global test bit stream from the host computer, performs serial-to-parallel conversion on the global test bit stream, and transmits the serial-to-parallel conversion to the data read / write module.

[0021] Furthermore, the storage module includes an address information storage module, a configuration information storage module, and an incentive information storage module.

[0022] Furthermore, the test control module includes:

[0023] The encoding / decoding module receives the test instruction and the specified test bit stream from the host computer, and decodes the test instruction and the specified test bit stream; at the same time, encodes the sampling data and sampling time of the inconsistent comparison results transmitted by the test control module to the host computer;

[0024] A test control main state machine module receives the test instruction and the specified test bit stream decoded by the JTAG encoding / decoding module, controls the first data processing main state machine module, and enables the first data processing main state machine module to schedule the data reading / writing module, read the address information, configuration information and stimulus information corresponding to the specified test bit stream from the storage module, transmit the read configuration information corresponding to the specified test bit stream to the configuration module, and transmit the read stimulus information corresponding to the specified test bit stream to the comparison module;

[0025] The configuration control module receives the configuration information corresponding to the designated test bit stream read by the test control main state machine module, and configures the chip under test.

[0026] The present invention also provides a method for performing chip detection based on any one of the above chip-level test and verification systems, the method comprising:

[0027] Initialize the test verification system;

[0028] Loading the global test bit stream to the first data processing module, performing serial-to-parallel conversion, dividing it into address information, configuration information and stimulus information, and then storing it;

[0029] Loading the specified test bit stream into the test control module, and acquiring address information, configuration information and stimulus information corresponding to the specified test bit stream in the stored address information, configuration information and stimulus information according to the specified test bit stream;

[0030] Loading the starting address and length of the configuration information corresponding to the specified test bit stream in the acquired storage address information, configuration information and stimulus information onto the configuration data bus of the chip under test, so that the chip under test enters a state to be tested;

[0031] The starting address and length of the stimulus information corresponding to the specified test bit stream in the acquired storage address information, configuration information and stimulus information are loaded onto the stimulus data bus of the chip under test, so that the chip under test enters the test state;

[0032] Sample the data output by the chip under test, compare the sampled data with the expected data in the stimulus information corresponding to the specified test bit stream, store the sampled data and sampling time with inconsistent comparison results, and convert them into data that conforms to the interface protocol.

[0033] Furthermore, before loading the configuration information, the starting address and the length of the stimulus information corresponding to the specified test bit stream in the acquired storage address information, configuration information and stimulus information onto the configuration data bus and the stimulus data of the chip under test, it also includes:

[0034] Configure a functional bit stream for the chip under test, connect it to the input pin and output pin of the chip under test, then input the clock waveform, compare whether the output is correct, and determine whether the chip under test and the test verification system are connected normally.

[0035] The present invention provides a chip-level test verification system and a chip detection method for chip screening mass production and large-scale production screening testing, which can maximize the reduction of test costs when entering the mass production stage from the initial production stage, and break away from the higher test costs based on ATE; at the same time, the number of test configurations in the present application is smaller, the number of test IOs used is small, the test time is short, and the test efficiency and test coverage are high. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1 A schematic diagram of a chip-level test and verification system;

[0038] Figure 2 is a schematic diagram of a first data processing module;

[0039] Figure 3 This is a schematic diagram of the test control module;

[0040] Figure 4 A schematic diagram of another chip-level test verification system;

[0041] Figure 5 A schematic diagram of another chip-level test and verification system;

[0042] Figure 6 A schematic diagram of another chip-level test and verification system;

[0043] Figure 7 A schematic diagram of a method for chip detection based on a chip-level test and verification system. DETAILED DESCRIPTION

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by technicians in the technical field of the present application; the terms used in the specification of the application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application; the terms "including" and "having" and any variations thereof in the specification and claims of the present application and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of the present application or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0045] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0046] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0047] In the following description, use of suffixes such as “module,” “part,” or “unit” used to refer to elements is merely for facilitating description of the present application, and has no specific meaning by itself.

[0048] like Figure 1 The figure shows a schematic diagram of a chip-level test and verification system, the test and verification system comprising:

[0049] The host computer is used to issue test instructions and provide global test bit streams and specified test bit streams;

[0050] A first data processing module is used to receive the test instruction and the global test bit stream issued by the host computer, divide the global test bit stream into address information, configuration information and stimulus information, and transmit them to the storage module;

[0051] like Figure 2 The figure shows a schematic diagram of a first data processing module, comprising:

[0052] The serial-to-parallel conversion module receives the test instruction and the global test bit stream from the host computer, performs serial-to-parallel conversion on the global test bit stream, and transmits the serial-to-parallel conversion to the data read / write module.

[0053] The serial-to-parallel conversion module may receive the test instruction and the global test bit stream from the host computer via an SPI interface.

[0054] The serial-to-parallel conversion module can convert the received global test bit stream into parallel port data of a certain data width for easy storage. For example, when the data width of the storage module is 16 bits, the serial-to-parallel conversion module can convert the global test bit stream into 16-bit parallel port data.

[0055] The data reading / writing module receives the parallel port data converted by the serial-to-parallel conversion module, reads the information of the parallel port data, divides the parallel port data into address information, configuration information and excitation information according to the read information, and transmits the parallel port data to the storage module.

[0056] The first data processing main state machine module receives the test instruction and the specified test bit stream issued by the test control module, controls the data read / write module according to the test instruction and the specified test bit stream, reads the address information, configuration information and stimulus information corresponding to the specified test bit stream, and transmits them to the test control module.

[0057] It can be understood that before transmitting the global test bit stream to the first data processing module, the host computer needs to check whether the first data processing module is running. If the first data processing module is running, the first data processing module and the storage module are not configured. If the first data processing module is not running, the first data processing module and the storage module are configured, and the storage module is set. At the same time, the host computer detects whether the storage module is set. If the storage module is set, the global test bit stream is transmitted to the serial-to-parallel conversion module for serial-to-parallel conversion, and then converted into parallel port data and transmitted to the data read / write module. The data read / write module reads the information of the parallel port data, and divides the parallel port data into address information, configuration information and excitation information according to the read information, and then transmits it to the storage module. Among them, the address information is global information and applies to all vectors; if a single configuration bit stream and excitation information are stored in accordance with the configuration bit stream starting bit address, configuration bit length, excitation starting address, excitation length, and configuration and loading of the excitation clock frequency, voltage deviation, delay data starting address, and delay duration. At the same time, there are some test vectors that do not require corresponding stimulus information, only configuration information. In this case, you only need to set the length of the configuration information to 0. The configuration information is that the data read / write module removes the header information from all the configuration information, splices it, and transmits it to the storage module. The stimulus information is to splice the stimulus information into a binary file and then transmit it to the storage module.

[0058] A storage module, used to store the address information, the configuration information and the incentive information output by the data processing module; wherein, it includes an address information storage module, a configuration information storage module and an incentive information storage module, the address information storage module stores the address information output by the first data processing module, the configuration information storage module stores the configuration information output by the first data processing module, and the incentive information storage module stores the incentive information output by the first data processing module.

[0059] A test control module is used to receive the test instruction and the specified test bit stream issued by the host computer, and according to the test instruction and the specified test bit stream, control the first data processing module to read the address information, configuration information and stimulus information corresponding to the specified test bit stream from the storage module; configure the chip under test according to the read configuration information corresponding to the specified test bit stream; and transmit the read stimulus information corresponding to the specified test bit stream to the comparison module.

[0060] like Figure 3 The following is a schematic diagram of the test control module, including:

[0061] The encoding / decoding module receives the test instruction and the specified test bit stream from the host computer, decodes the test instruction and the specified test bit stream; and at the same time, encodes the sampling data and sampling time with inconsistent comparison results transmitted by the test control module to the host computer.

[0062] The encoding / decoding module receives the test instruction and the designated test bit stream from the host computer by communicating with the host computer through a JTAG interface.

[0063] The test control main state machine module receives the test instruction and the specified test bit stream decoded by the encoding / decoding module, controls the first data processing main state machine module, and enables the first data processing main state machine module to schedule the data reading / writing module, read the address information, configuration information and stimulus information corresponding to the specified test bit stream from the storage module, transmit the read configuration information corresponding to the specified test bit stream to the configuration module, and transmit the read stimulus information corresponding to the specified test bit stream to the comparison module.

[0064] The configuration control module receives the configuration information corresponding to the designated test bit stream read by the test control main state machine module, and configures the chip under test.

[0065] It can be understood that the test instruction and the specified test bit stream are transmitted to the encoding / decoding module, the encoding / decoding module decodes the test instruction and the specified test bit stream, and then transmits the decoded test instruction and the specified test bit stream to the test control main state machine module, the test control main state machine module transmits the received signal to the first data processing main state machine module, the first data processing main state machine module controls the data read / write module to read the address information, configuration information and stimulus information corresponding to the specified test bit stream according to the received signal, and then transmits them to the first data processing main state machine module and the test control main state machine module in sequence, the test control main state machine module transmits the configuration information corresponding to the specified test bit stream to the configuration control module, and the configuration control module configures the chip under test according to the received configuration information corresponding to the specified test bit stream.

[0066] A comparison module is used to receive the stimulus information corresponding to the specified test bit stream read by the test module, configure the chip under test according to the stimulus information corresponding to the specified test bit stream read; and sample the output data of the chip under test, compare the sampled output data with the expected data in the stimulus information corresponding to the specified test bit stream read, and transmit the sampled data and sampling time with inconsistent comparison results to the test control module and the host computer.

[0067] like Figure 4 Another chip-level test verification system is shown, the system also includes a second data processing module, the second data processing module receives the stimulus information corresponding to the specified test bit stream read by the test control module, divides the read stimulus information corresponding to the specified test bit stream into stimulus data and expected data, and transmits the stimulus data and the expected data to the comparison module.

[0068] like Figure 5 Another chip-level test verification system is shown, the system further comprising a delay module for receiving the expected data from the second data processing module, delaying the expected data, and transmitting the delayed expected data to the comparison module. The delay period of the expected data is 2-5, the period is in the form of a parameter and can be changed. In the embodiment of the present application, 2 periods are selected.

[0069] like Figure 6 Another chip-level test verification system is shown, the system also includes an error data storage module, which is used to receive the adopted data and sampling time of the comparison result of the comparison module, store and convert them into data that conforms to the interface protocol, and transmit them to the comparison module, the test control module and the host computer after the test verification system is finished. When the sampled output data is compared with the expected data in the excitation information corresponding to the specified test bit stream and is inconsistent, the chip address, site index, bit stream index, timestamp, result type, and error value of the storage chip are stored.

[0070] like Figure 7 A method for performing chip detection based on a chip-level test verification system as described above is shown, and the method includes:

[0071] S1: Initialize the test verification system;

[0072] Before initialization, check the power-on status of each module, and after power-on is completed, initialize the system.

[0073] S2: Load the global test bit stream to the first data processing module for serial-to-parallel conversion, classification and storage;

[0074] After the test verification system is initialized, the global test bit stream is loaded into the first data processing module, the global test bit stream is first converted into parallel data, and then the parallel data is divided into address information, configuration information and stimulus information and then stored;

[0075] S3: Load the specified test bit stream into the test control module, and obtain the address information, configuration information and stimulus information corresponding to the specified test bit stream in S2 according to the specified test bit stream;

[0076] Before loading the configuration information, the starting address and the length of the stimulus information and the stimulus information corresponding to the specified test bit stream in the acquired storage address information, configuration information and stimulus information to the configuration data bus and the stimulus data of the chip under test, the method further includes:

[0077] Configure a functional bit stream for the chip under test, connect it to the input pin and output pin of the chip under test, then input the clock waveform, compare whether the output is correct, and determine whether the chip under test and the test verification system are connected normally.

[0078] S4: loading the starting address and length of the configuration information corresponding to the specified test bit stream in the stored address information, configuration information and stimulus information obtained in S3 onto the configuration data bus of the chip under test, so that the chip under test is in a state to be tested;

[0079] Loading the starting address and length of the stimulus information corresponding to the specified test bit stream in the stored address information, configuration information and stimulus information obtained in S3 onto the stimulus data bus of the chip under test, so that the chip under test enters a test state;

[0080] S5: Sample the data output by the chip under test, compare the sampled data with the expected data in the acquired storage address information, configuration information and stimulus information corresponding to the specified test bit stream, and save the sampled data and sampling time records with inconsistent comparison results, including the chip address, site index, bit stream index, timestamp, result type, and error value of the chip under test. At the same time, the host computer can store the chip under test in bins according to the adopted data test type.

[0081] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0082] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0083] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A chip-level test and verification system, characterized in that: The system comprises: The host computer is used to issue test instructions and provide global test bit streams and specified test bit streams; A first data processing module is used to receive the test instruction and the global test bit stream issued by the host computer, divide the global test bit stream into address information, configuration information and stimulus information, and transmit them to the storage module; A storage module, used for storing the address information, the configuration information and the excitation information output by the first data processing module; A test control module, for receiving the test instruction and the designated test bit stream issued by the host computer, and controlling the first data processing module to read the address information, configuration information and stimulus information corresponding to the designated test bit stream from the storage module according to the test instruction and the designated test bit stream; configuring the chip under test according to the read configuration information corresponding to the designated test bit stream; and transmitting the read stimulus information corresponding to the designated test bit stream to the comparison module; A comparison module is used to receive the stimulus information corresponding to the specified test bit stream read by the test module, configure the chip under test according to the stimulus information corresponding to the specified test bit stream read; and sample the output data of the chip under test, compare the sampled output data with the expected data in the stimulus information corresponding to the specified test bit stream read, and transmit the sampled data and sampling time with inconsistent comparison results to the test control module and the host computer.

2. A chip-level test and verification system according to claim 1, characterized in that: The system also includes a second data processing module, which receives the stimulus information corresponding to the specified test bit stream read by the test control module, divides the read stimulus information corresponding to the specified test bit stream into stimulus data and expected data, and transmits the stimulus data and the expected data to the comparison module.

3. A chip-level test and verification system according to claim 2, characterized in that: The system further comprises a delay module, which is used for receiving the expected data from the second data processing module, delaying the expected data, and transmitting the delayed expected data to the comparison module.

4. A chip-level test and verification system according to claim 3, characterized in that: The system also includes an error data storage module for receiving the adopted data and sampling time with inconsistent comparison results of the comparison module, storing and converting them into data that conforms to the interface protocol, and transmitting them to the comparison module, the test control module and the host computer after the test verification system is completed.

5. A chip-level test and verification system according to claim 4, characterized in that: The first data processing module comprises: A data read / write module receives the test instruction and the global test bit stream of the host computer, reads the information of the global test bit stream, divides the global test bit stream into address information, configuration information and stimulus information according to the read information, and transmits the information to the storage module; The first data processing main state machine module receives the test instruction and the specified test bit stream issued by the test control module, and controls the data read / write module to read the address information, configuration information and stimulus information corresponding to the specified test bit stream according to the test instruction and the specified test bit stream, and transmits them to the test control module.

6. A chip-level test and verification system according to claim 5, characterized in that: The first data processing module also includes: The serial-to-parallel conversion module receives the test instruction and the global test bit stream from the host computer, performs serial-to-parallel conversion on the global test bit stream, and transmits the serial-to-parallel conversion to the data read / write module.

7. A chip-level test and verification system according to claim 6, characterized in that: The storage module includes an address information storage module, a configuration information storage module, and an incentive information storage module.

8. The chip-level test and verification system according to claim 5, characterized in that: The test control module comprises: The encoding / decoding module receives the test instruction and the specified test bit stream from the host computer, and decodes the test instruction and the specified test bit stream; at the same time, encodes the sampling data and sampling time of the inconsistent comparison results transmitted by the test control module to the host computer; A test control main state machine module receives the test instruction and the designated test bit stream decoded by the encoding / decoding module, controls the first data processing main state machine module, and enables the first data processing main state machine module to schedule the data reading / writing module, read the address information, configuration information and stimulus information corresponding to the designated test bit stream from the storage module, transmit the read configuration information corresponding to the designated test bit stream to the configuration module, and transmit the read stimulus information corresponding to the designated test bit stream to the comparison module; The configuration control module receives the configuration information corresponding to the designated test bit stream read by the test control main state machine module, and configures the chip under test.

9. A method for chip detection based on the chip-level test verification system according to any one of claims 1 to 8, characterized in that: The method comprises: Initialize the test verification system; Loading the global test bit stream to the first data processing module, performing serial-to-parallel conversion, dividing it into address information, configuration information and stimulus information, and then storing it; Loading the specified test bit stream into the test control module, and acquiring address information, configuration information and stimulus information corresponding to the specified test bit stream in the stored address information, configuration information and stimulus information according to the specified test bit stream; Loading the starting address and length of the configuration information corresponding to the specified test bit stream in the acquired storage address information, configuration information and stimulus information onto the configuration data bus of the chip under test, so that the chip under test enters a state to be tested; The starting address and length of the stimulus information corresponding to the specified test bit stream in the acquired storage address information, configuration information and stimulus information are loaded onto the stimulus data bus of the chip under test, so that the chip under test enters the test state; Sample the data output by the chip under test, compare the sampled data with the expected data in the stimulus information corresponding to the specified test bit stream, store the sampled data and sampling time with inconsistent comparison results, and convert them into data that conforms to the interface protocol.

10. The method for performing chip detection on a chip-level test verification system according to claim 9, characterized in that: Before loading the configuration information, the starting address and the length of the stimulus information and the stimulus information corresponding to the specified test bit stream in the acquired storage address information, configuration information and stimulus information to the configuration data bus and the stimulus data of the chip under test, the method further includes: Configure a functional bit stream for the chip under test, connect it to the input pin and output pin of the chip under test, then input the clock waveform, compare whether the output is correct, and determine whether the chip under test and the test verification system are connected normally.

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