High-speed serial RapidIO universal test system and method

Abstract

The present invention belongs to the field of radar test technology, and discloses a high-speed serial RapidIO universal test system and method. The system of the present invention includes a universal RapidIO tester, a universal RapidIO test adapter, and a universal VPX bus test plug-in box; the universal RapidIO tester provides a plurality of X1 mode serial RapidIO test channels; the universal RapidIO test adapter includes a plurality of VPX bus connectors to realize signal switching between the RapidIO signal of the tested UUT and the test channel of the RapidIO tester; the universal VPX bus test plug-in box provides the working power supply and backplane connection of the tested UUT, and the front and rear connector signals of the test slot are fully connected according to the VPX bus standard definition. The present invention can solve the problem of the universal test of the RapidIO high-speed digital circuit module based on the VPX bus in the radar system.

Description

Technical Field

[0001] The invention belongs to the technical field of radar testing, and in particular relates to a high-speed serial RapidIO universal testing system and method. Background Art

[0002] RapidIO technology is an international standard for point-to-point embedded system interconnection. It provides efficient and reliable interconnection and data exchange within high-performance embedded processor systems and between embedded systems. It is widely used in modern communication systems and electronic weapons and equipment such as radars. High-speed serial RapidIO technology is a branch of RapidIO technology. Currently, mainstream embedded processor system designs mostly use serial RapidIO technology.

[0003] In actual testing, RapidIO is very complex and diverse in actual electronic system applications. Even in the same system, there are multiple varieties of UUTs, and the RapidIO bus signals are distributed on different connectors of the VPX bus. The data transmission rate and working channel mode are also very different. At present, there are some mature test methods for RapidIO testing, but they are limited to the testing of physical characteristics such as signal integrity, eye diagram, receiving performance and bit error rate. There is no general technology and method for testing logical functions such as RapidIO data transmission and switching. Correspondingly, for high-speed digital circuit modules based on VPX bus in radar systems, high-speed serial RapidIO technology is widely used, and there is currently a lack of effective general functional testing methods. For the large number of debugging, testing, maintenance, repair and verification requirements of radar modules, in actual debugging and testing, the method adopted is to place the high-speed digital module with RapidIO function in a dedicated test plug-in box with corresponding interconnection, and use other dedicated high-speed test modules and dedicated interface modules (rear plug-in boards) to realize the test path establishment and test resource configuration of RapidIO bus signals to complete the debugging and functional testing of RapidIO. This method has the following problems:

[0004] 1. The testing methods are not unified. Each module uses its own testing and debugging procedures, and the testing process development cost is high;

[0005] 2. Limited by the system interconnection topology, dedicated modules or dedicated interface modules must be used to complete the test, and dedicated plug-in boxes must be used. Building a test system is very complicated and the test system design cost is high. Each dedicated module or dedicated interface module requires a dedicated test method and test process, and the test process development cost is high.

[0006] Therefore, there is an urgent need and necessity to study RapidIO general test methods and test technologies. Summary of the invention

[0007] The purpose of the present invention is to provide a high-speed serial RapidIO universal test system and method to address the deficiencies in the prior art, so as to solve the problem of RapidIO universal test of high-speed digital circuit modules based on VPX bus in radar systems, standardize RapidIO test methods, save test costs and system design costs, simplify test system composition, and improve the comprehensive guarantee capability and guarantee level of a new generation of radars.

[0008] Specifically, the present invention is implemented by adopting the following technical solutions.

[0009] On the one hand, the present invention provides a high-speed serial RapidIO universal test system, including a universal RapidIO tester, a universal RapidIO test adapter, and a universal VPX bus test plug-in box;

[0010] The universal RapidIO tester includes a main test module, an Ethernet port, and an optical fiber interface; the universal RapidIO tester provides a plurality of X1 mode serial RapidIO test channels through the optical fiber interface, and the number of the test channels reaches the maximum number of serial channels for high-speed serial data transmission and reception of the VPX bus tested module; the main test module includes a high-performance embedded processor and at least one high-performance FPGA; the high-performance embedded processor receives and parses host computer instructions through the Ethernet port, and controls the working state of the main test module according to the instruction content; the FPGA provides high-speed serial RapidIO test resources and multiple RapidIO test channels to complete high-speed serial data transmission and reception;

[0011] The universal RapidIO test adapter includes a plurality of VPX bus connectors; the universal RapidIO test adapter realizes signal switching between the RapidIO signal of the UUT under test and the test channel of the RapidIO tester, forming a point-to-point communication path of the RapidIO electrical interface; all high-speed serial interfaces of the VPX bus connector are fully expanded and realized in the form of an optical fiber interface externally;

[0012] The universal VPX bus test plug-in box provides working power and backplane connection for the UUT under test; the backplane is based on the VPX bus and includes at least one test slot; the P1 to P6 connectors of the test slot have no interconnection relationship with other slots, and the front and rear connector signals of the test slot are fully connected according to the VPX bus standard definition to meet the test requirements.

[0013] Furthermore, the high-performance embedded processor is a CPU processor.

[0014] Furthermore, the FPGA implements dynamic selection of data transmission rate.

[0015] Furthermore, the high-speed serial RapidIO test resources are implemented using the IP core module inside the FPGA, and the RapidIO physical layer link connection is implemented using the GT resources inside the FPGA, wherein each FPGA provides 32 high-speed X1 mode RapidIO test channels; the optical fiber interface uses a 24-in-1 optoelectronic module to complete the conversion between optoelectronic signals, which is divided into sending and receiving; the sending part of all GT interfaces of the FPGA uses several 24-in-1 optoelectronic sending modules to design the optical fiber interface, and the receiving part of all GT interfaces uses several 24-in-1 optoelectronic receiving modules to design the optical fiber interface.

[0016] Furthermore, each VPX bus connector is calculated as 16 X1 channels, with a total of up to 96 X1 channels, and the optical fiber interface is designed using 4 24-in-1 optoelectronic transmitting modules and 4 24-in-1 optoelectronic receiving modules.

[0017] Furthermore, the physical dimensions of the adapter are in the form of a 6U standard rear plug-in board extending outward, so that the optical fiber interface connectors are closely arranged at the outer edge of the rear plug-in board.

[0018] On the other hand, the present invention also provides a high-speed serial RapidIO universal test method, which is implemented by using the above-mentioned high-speed serial RapidIO universal test system, and includes the following steps:

[0019] Complete the RapidIO channel configuration of the FPGA in the main test module of the universal RapidIO tester and complete the initialization data configuration;

[0020] The high-performance embedded processor receives configuration data and test instructions, parses them, and controls the FPGA to complete the corresponding initialization operations;

[0021] The high-performance embedded processor selects the corresponding test data according to the test instructions, first establishes a RapidIO link with the UUT under test through a universal RapidIO test adapter, and then sends the test data to the UUT under test;

[0022] A high performance embedded processor receives the test results of the UUT under test.

[0023] The beneficial effects of the high-speed serial RapidIO universal test system and method of the present invention are as follows:

[0024] The universal RapidIO tester provides 96 X1-mode serial RapidIO test channels, which can complete up to 96 high-speed serial data transmission and reception, and can meet the maximum number of serial bus channels of the VPX bus module under test, solving the problem of insufficient test resources, providing a universal functional test method for high-speed serial RapidIO, and standardizing the RapidIO test method;

[0025] It communicates with the host computer through the Ethernet port and uses 8 24-in-1 photoelectric conversion modules as external test fiber interfaces, which can realize 96-channel X1 mode RapidIO transceiver debugging and testing. The RapidIO channel mode and data channel transmission baud rate are configurable, which can adapt to the test requirements of different modules under test and meet the test requirements of different channel modes and different data transmission rates. It has the ability to generalize test resources and get rid of the constraints of dedicated test resources. The VPX bus full expansion design solves the problem of uneven distribution of VPX bus high-speed serial signals of different UUTs, gets rid of the restrictions of using dedicated interface modules and dedicated plug-in boxes, reduces the cost of test system construction, and no longer requires multiple dedicated test modules, dedicated interface modules and multiple dedicated test chassis; simplifies the development process of RapidIO debugging and testing, and provides universal equipment and convenient methods for test system design;

[0026] The design of the all-in-one optical fiber interface reduces the channel size and ensures the signal quality during long-distance transmission, which is beneficial to the test system design and improves the comprehensive guarantee level and comprehensive guarantee capability of the radar system and modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a test block diagram of the high-speed serial RapidIO universal test system of this embodiment. (a), (b), and (c) are block diagrams of the high-speed serial RapidIO universal test system testing the circuit modules UUT1, UUT2, and UUT3 in the universal VPX bus test plug-in box.

[0028] Figure 2 FIG. 4 is a schematic block diagram of a universal RapidIO tester of this embodiment.

[0029] Figure 3 It is a functional block diagram of the universal RapidIO main test module of this embodiment.

[0030] Figure 4 FIG. 4 is a schematic diagram of a universal RapidIO test adapter according to the present embodiment.

[0031] Specific implementation

[0032] The present invention is further described in detail below in conjunction with embodiments and with reference to the accompanying drawings.

[0033] Embodiment 1:

[0034] One embodiment of the present invention is a high-speed serial RapidIO universal test system and test method for testing a VPX bus high-speed digital module, namely a circuit under test (UUT).

[0035] like Figure 1 As shown, the high-speed serial RapidIO universal test system of this example includes: a universal RapidIO tester, a universal RapidIO test adapter, and a universal VPX bus test plug-in box. The high-speed serial RapidIO universal test system can perform RapidIO transceiver debugging and testing on different circuit modules under test UUT1, UUT2, and UUT3 in the universal VPX bus test plug-in box.

[0036] 1. Universal RapidIO Tester

[0037] The main function of the universal RapidIO tester is to provide 96 X1-mode serial RapidIO test channels through a fiber optic interface, which can complete up to 96 high-speed serial data transmission and reception. 96 channels is the maximum number of serial bus channels to meet the VPX bus module under test, solving the problem of insufficient test resources. It is understandable that 48 or other X1-mode serial RapidIO test channels with less than 96 channels can also be used, as long as the number of serial channels that can meet the high-speed serial data transmission and reception of all modules under test is achieved according to actual test needs.

[0038] The general RapidIO tester is designed as a 1U rack-mountable device, consisting of a main test module, Ethernet port, and fiber optic interface. Figure 2 As shown, preferably, it can also include a fan, a power module, etc. The universal RapidIO tester communicates with the host computer through the Ethernet port; 8 24-in-1 photoelectric conversion modules are used as external test optical fiber interfaces, which can realize 96-way X1 mode RapidIO transceiver debugging and testing. The RapidIO channel mode can be configured as X1, X2, X4, and X8, and the data channel transmission baud rate can be configured as 1.25Gbps, 2.5Gbps, 3.125Gbps, 5Gbps, and 6.25Gbps. After the high-speed serial RapidIO universal test system of this embodiment has the above-mentioned configuration capability, it can adapt to the test requirements of different modules under test, meet the test requirements of multiple serial RapidIO channel modes and different data transmission rates, have the ability to generalize test resources, and get rid of the constraints of dedicated test resources.

[0039] The main test module is the core component of the general RapidIO tester, which is designed and implemented with a high-performance embedded processor + at least one high-performance FPGA as the main architecture. The FPGA is determined by the number of RapidIO test channels required. Figure 3As shown in the figure, the main test module is implemented by the main architecture design of CPU processor + 3 FPGAs. Among them, the main function of the CPU processor (i.e., high-performance embedded processor) is to control the working state of the main test module, receive and parse the host computer instructions through the Ethernet port, and implement specific operation control according to the instruction content. The main function of FPGA is to provide high-speed serial RapidIO test resources and multiple RapidIO test channels. Each FPGA provides 32 X1 mode serial RapidIO test channels, which can complete up to 96 high-speed serial data transmission and reception, and can meet the maximum number of serial bus channels of the VPX bus tested module, solving the problem of insufficient test resources. FPGA realizes dynamic selection of data transmission rate to meet the test requirements of different data transmission rates. High-speed serial RapidIO test resources are implemented by FPGA internal IP core modules, and RapidIO physical layer link connection is implemented by FPGA internal GT (high-speed serial transceiver) resources, among which each FPGA provides 32 high-speed X1 mode RapidIO test channels. The 24-in-1 optical module is used to complete the conversion between optical and electrical signals, which is divided into two modules: sending and receiving. The TX (transmit) part of all 96 GT interfaces of FPGA uses 4 24-in-1 photoelectric transmit modules to design the optical fiber interface, and the RX (receive) part of all 96 GT interfaces uses 4 24-in-1 photoelectric receive modules to design the optical fiber interface. Through the combination of the above two optical port connectors (transmit optical module and receive optical module), the 96-channel X1 mode RapidIO transceiver combination debugging and testing are realized. The all-in-one (24-in-1) optical fiber interface reduces the channel size, ensures the signal quality during long-distance transmission, and is conducive to test system design.

[0040] 2. Universal RapidIO Test Adapter

[0041] The universal RapidIO test adapter is used to realize the signal transfer between the RapidIO signal of the VPX bus high-speed digital module under test (UUT) and the test channel of the RapidIO tester, forming a point-to-point communication path of the RapidIO electrical interface. The 6U high VPX bus (VITA 46.3 standard) connector includes 7 connectors, serial numbered P0-P6. P0 is mainly used for power supply, and each connector in P1-P6 supports the definition of up to 16 groups of high-speed serial transceiver signals. The universal RapidIO test adapter fully expands all standard agreed high-speed serial interface definition pins (from P1 to P6) of the standard 6U high VPX bus connector, and implements the design in the form of an optical fiber interface. Each connector is calculated as 16 X1 channels, with a total of up to 96 X1 channels. The optical fiber interface is designed using 4 24-in-1 optoelectronic transmitter modules and 4 24-in-1 optoelectronic receiver modules. The physical size of the adapter adopts the form of extending the 6U standard rear plug board outward, and the optical fiber interface connectors are closely arranged on the outer edge of the rear plug board. The optical port connector can be selected according to the specific UUT test needs to save costs, such as Figure 4 The VPX bus full extension design solves the problem of uneven distribution of VPX bus high-speed serial signals of different UUTs, and breaks away from the limitation of using dedicated interface modules and dedicated plug-in boxes.

[0042] 3. Universal test box

[0043] The universal test plug-in box provides a test working environment for providing UUT working power, heat dissipation, and backplane connection. The universal test plug-in box backplane is based on the VPX bus and includes at least one test slot. The P1-P6 connectors of the test slot have no interconnection relationship with other slots. The front and rear connector signals of the test slot are fully connected according to the standard definition to meet the test requirements.

[0044] In another embodiment, the VPX bus high-speed digital module is the module under test (UUT), and there are 4 X4 serial RapidIO bus signals on the VPX bus P1 connector and 4 X4 serial RapidIO bus signals on the P3 connector. The data transmission baud rate is 2.5 Gbps. Each of the 4 X4 serial RapidIO bus signals on the P1 and P3 connectors of the UUT is connected to the P1 and P3 connectors of the universal RapidIO test adapter through the backplane, and then to the XS1-XS4 optical ports of the universal RapidIO test adapter; then connected to the XS1-XS4 optical ports of the universal RapidIO tester through optical fiber cables, and then to the GT interfaces of FPGA1 and FPGA2 of the universal RapidIO tester, and then to the RapidIO functional IP core modules inside FPGA1 and FPGA2, forming all RapidIO test paths.

[0045] The execution process of the high-speed serial RapidIO universal test method of this embodiment is as follows:

[0046] 1. Start the test software of the host computer, complete the RapidIO channel configuration of the FPGA in the main test module of the universal RapidIO tester, complete the initialization data configuration such as data transmission rate selection, and send the configuration data and test instructions to the high-performance embedded processor (CPU) in the main test module through the Ethernet port.

[0047] 2. The high-performance embedded processor receives the configuration data and test instructions sent by the host computer, parses them, and controls the FPGA to complete the corresponding initialization operations.

[0048] 3. When testing, the high-performance embedded processor selects the corresponding test data according to the test instructions, first establishes a RapidIO link with the UUT under test through the universal RapidIO test adapter, and then sends the test data to the UUT under test.

[0049] 4. The high-performance embedded processor receives the test results of the UUT and completes the final result processing.

[0050] The present invention leads out all the serial RapidIO bus signals that may be distributed on all the VPX buses through the universal RapidIO test adapter on the rear plug-in board, and connects them to the test resources of the universal RapidIO tester through optical fiber, thereby realizing the universal test of RapidIO; reducing the variety of test system hardware, such as special test modules, special interface modules, special plug-in boxes, etc., standardizing the test method, reducing the development process, saving the test cost, and simplifying the system design.

[0051] For example, if the RapidIO bus signals of UUT1, UUT2, and UUT3 are distributed on different connectors of the VPX bus, when using the previous test method, it is necessary to equip a dedicated plug-in box, a dedicated module, and a dedicated interface module (later plug-in) with corresponding interconnection relationships to realize the establishment of the test path of the RapidIO bus signal and the configuration of test resources. The present invention overcomes the above problems, and fully expands the standard definition pins of all serial RapidIO bus signals that may be distributed on all VPX buses, all of which are led out through the universal RapidIO test adapter that is later inserted, and connected to the test resource channel of the RapidIO tester through an optical fiber cable, thereby realizing the universal test of RapidIO. It reduces the variety of test system hardware, such as dedicated modules, dedicated interface modules, dedicated plug-ins, etc., standardizes the test method, reduces the development process, saves the test cost, and simplifies the system design.

[0052] In some embodiments, certain aspects of the above-mentioned techniques may be implemented by one or more processors of a processing system executing software. The software includes one or more executable instruction sets stored or otherwise tangibly implemented on a non-transitory computer-readable storage medium. The software may include instructions and certain data that manipulate one or more processors to perform one or more aspects of the above-mentioned techniques when executed by one or more processors. Non-transitory computer-readable storage media may include, for example, magnetic or optical disk storage devices, solid-state storage devices such as flash memory, cache, random access memory (RAM), or other non-volatile memory devices. The executable instructions stored on the non-transitory computer-readable storage medium may be source code, assembly language code, object code, or other instruction formats interpreted or otherwise executed by one or more processors.

[0053] Computer-readable storage media may include any storage medium or combination of storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact disks (CDs), digital versatile disks (DVDs), Blu-ray disks), magnetic media (e.g., floppy disks, tapes, or magnetic hard drives), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or micro-electromechanical system (MEMS)-based storage media. Computer-readable storage media may be embedded in a computing system (e.g., system RAM or ROM), fixedly attached to a computing system (e.g., a magnetic hard drive), removably attached to a computing system (e.g., an optical disk or a universal serial bus (USB)-based flash memory), or coupled to a computer system via a wired or wireless network (e.g., network accessible storage (NAS)).

[0054] Please note that not all activities or elements in the general description above are required, that a portion of a particular activity or device may not be required, and that one or more further activities or included elements may be performed in addition to those described. Further, the order in which the activities are listed is not necessarily the order in which they are performed. Moreover, these concepts have been described with reference to specific embodiments. However, those of ordinary skill in the art recognize that various modifications and changes may be made without departing from the scope of the present disclosure as set forth in the following claims. Therefore, the specification and drawings are to be regarded as illustrative rather than restrictive, and all such modifications are included within the scope of the present disclosure.

[0055] Benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, benefits, advantages, solutions to problems, and any features that may cause any benefit, advantage, or solution to occur or become more apparent should not be interpreted as key, essential, or essential features of any or all claims in any or other aspects. In addition, the specific embodiments disclosed above are merely illustrative, as the disclosed subject matter may be modified and implemented in different but equivalent ways that are obvious to those skilled in the art having the benefit of the teachings herein. Except as described in the claims below, there is no intention to limit the details of construction or design shown herein. It is therefore apparent that the specific embodiments disclosed above may be changed or modified, and all such variations are considered to be within the scope of the disclosed subject matter.

Claims

1. A high-speed serial RapidIO universal test system, characterized in that: Including universal RapidIO tester, universal RapidIO test adapter, universal VPX bus test plug-in box; The universal RapidIO tester includes a main test module, an Ethernet port, and an optical fiber interface; the universal RapidIO tester provides a plurality of X1 mode serial RapidIO test channels through the optical fiber interface, and the number of the test channels reaches the maximum number of serial channels for high-speed serial data transmission and reception of the module under test of the VPX bus; the main test module includes a high-performance embedded processor and at least one high-performance FPGA; the high-performance embedded processor receives and parses host computer instructions through the Ethernet port, and controls the working state of the main test module according to the instruction content; the FPGA provides high-speed serial RapidIO test resources and multiple RapidIO test channels to complete high-speed serial data transmission and reception; the high-speed serial RapidIO test resources are implemented by the IP core module inside the FPGA, and the RapidIO physical layer link connection is implemented by the GT resources inside the FPGA, wherein each FPGA provides 32 high-speed X1 mode RapidIO test channels; the optical fiber interface uses a 24-in-1 optoelectronic module to complete the conversion between optoelectronic signals, which is divided into two types: transmission and reception; the transmission part of all GT interfaces of the FPGA uses a plurality of 24-in-1 optoelectronic transmission modules to design the optical fiber interface, and the receiving part of all GT interfaces uses a plurality of 24-in-1 optoelectronic receiving modules to design the optical fiber interface; The universal RapidIO test adapter includes a plurality of VPX bus connectors; the universal RapidIO test adapter realizes signal switching between the RapidIO signal of the UUT under test and the test channel of the RapidIO tester, and constitutes a point-to-point communication path of the RapidIO electrical interface; Fully expand all high-speed serial interfaces of the VPX bus connector and implement them in the form of optical fiber interfaces; The universal VPX bus test plug-in box provides working power and backplane connection for the UUT under test; the backplane is based on the VPX bus and includes at least one test slot; the P1 to P6 connectors of the test slot have no interconnection relationship with other slots, and the front and rear connector signals of the test slot are fully connected according to the VPX bus standard definition to meet the test requirements.

2. The high-speed serial RapidIO universal test system according to claim 1, characterized in that: The high performance embedded processor is a CPU processor.

3. The high-speed serial RapidIO universal test system according to claim 2, characterized in that: The FPGA realizes dynamic selection of data transmission rate.

4. The high-speed serial RapidIO universal test system according to claim 2, characterized in that: Each VPX bus connector is calculated as 16 X1 channels, with a total of up to 96 X1 channels. The optical fiber interface is designed using four 24-in-1 optoelectronic transmitting modules and four 24-in-1 optoelectronic receiving modules.

5. The high-speed serial RapidIO universal test system according to claim 1, characterized in that: The physical size of the adapter adopts the form of extending the 6U standard rear plug-in board outward, and the optical fiber interface connectors are closely arranged at the outer edge of the rear plug-in board.

6. A high-speed serial RapidIO universal test method, implemented by using the high-speed serial RapidIO universal test system according to any one of claims 1 to 5, characterized in that: The following steps are involved: Complete the RapidIO channel configuration of the FPGA in the main test module of the universal RapidIO tester and complete the initialization data configuration; The high-performance embedded processor receives configuration data and test instructions, parses them, and controls the FPGA to complete the corresponding initialization operations; The high-performance embedded processor selects the corresponding test data according to the test instructions, first establishes a RapidIO link with the UUT under test through a universal RapidIO test adapter, and then sends the test data to the UUT under test; A high performance embedded processor receives the test results of the UUT under test.

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