Electronic device

Abstract

An electronic device according to an embodiment of the present application can include a display layer defining an active area and a peripheral area adjacent to the active area, a sensor layer disposed above the display layer and including a plurality of sensing electrodes and an antenna pattern, a cover layer disposed below the display layer and defining an opening portion overlapping the antenna pattern, and a driving chip providing a signal to the antenna pattern through the opening portion defined in the cover layer.

Description

Technical Field

[0001] This invention relates to an electronic device with improved display and sensing performance, and also to an electronic device including a wireless signal sensing and transmission module. Background Technology

[0002] Electronic devices may include electronic modules. For example, an electronic device may be a portable terminal or a wearable device, and an electronic module may include an antenna module, a camera module, or a battery module. As portable terminals become thinner and wearable devices become smaller, the space available for installing electronic modules is gradually decreasing. Furthermore, as electronic devices become more functional and develop towards higher specifications, the number of electronic modules included in electronic devices is increasing. Summary of the Invention

[0003] The purpose of this invention is to provide an electronic device with improved display and sensing performance.

[0004] An electronic device according to an embodiment of the present invention may include: a display layer defining an active region and a peripheral region adjacent to the active region; a sensing layer disposed on the display layer and including a plurality of sensing electrodes and an antenna pattern; a cover layer disposed below the display layer and defining an opening overlapping the antenna pattern; and a driving chip providing a signal to the antenna pattern through the opening defined in the cover layer.

[0005] The antenna pattern may include a first portion and a second portion extending from the first portion.

[0006] When viewed on a plane, the first part overlaps with the active region, and the second part overlaps with the surrounding region.

[0007] Alternatively, the antenna pattern may have a mesh structure.

[0008] It is possible that a first opening is defined in the first part, and a second opening is defined in the second part, wherein the size of the first opening is larger than the size of the second opening.

[0009] Alternatively, the electronic device may further include: a transmission unit on which the driving chip is mounted, the transmission unit being attached to the underside of the cover layer.

[0010] Alternatively, the transmission unit may include a first surface and a second surface facing the first surface, wherein the first surface has a ground coplanar waveguide (GCPW) structure.

[0011] Alternatively, the second surface may be curved and face each other, with the driver chip disposed on the first surface.

[0012] Alternatively, the driving chip may be configured adjacent to the opening.

[0013] It is possible that the antenna pattern defines an opening, and when viewed in a plane, at least a portion of the opening overlaps with the opening portion.

[0014] Alternatively, the antenna pattern may be configured on the same layer as a portion of the plurality of sensing electrodes.

[0015] Alternatively, the electronic device may further include an anti-reflective layer disposed on the sensing layer.

[0016] Alternatively, when viewed in a plane, the opening may overlap with the active region.

[0017] Alternatively, the driver chip may be disposed beneath the cover layer.

[0018] An electronic device according to an embodiment of the present invention may include: a display layer defining an active region and a peripheral region adjacent to the active region, and including a first surface and a second surface facing the first surface; a sensing layer facing the first surface and including an antenna pattern overlapping the active region; a cover layer facing the second surface and defining an opening overlapping the active region; and a driver chip disposed under the cover layer and indirectly supplying power to the antenna pattern through the opening.

[0019] Alternatively, the antenna pattern may have a mesh structure.

[0020] Alternatively, the electronic device may further include: a transmission unit on which the driving chip is mounted, the transmission unit being disposed below the cover layer.

[0021] Alternatively, the transmission unit may have a ground coplanar waveguide (GCPW) structure.

[0022] It is possible that the antenna pattern defines an opening, and when viewed in a plane, at least a portion of the opening overlaps with the opening portion.

[0023] Alternatively, the sensing layer may further include a plurality of sensing electrodes, and the antenna pattern may be configured on a layer identical to a portion of the plurality of sensing electrodes.

[0024] Alternatively, the electronic device may further include an anti-reflective layer disposed on the sensing layer.

[0025] (Invention Effects)

[0026] According to the present invention, an electronic device may include: a display layer, a sensing layer including an antenna pattern, an anti-reflective layer, a cover layer, a transmission unit, and a driving chip. The transmission unit, on which the driving chip is mounted, may be integrated beneath the cover layer disposed below the display layer. The driving chip can indirectly supply power to the antenna pattern through the cover layer. No external structure connected to the driving chip for supplying power to the antenna pattern may be disposed between the display layer and the anti-reflective layer, or between the sensing layer and the anti-reflective layer. Therefore, the image display performance of the electronic device can be improved, and the external input sensing performance of the electronic device can be improved. Attached Figure Description

[0027] Figure 1a This is a perspective view of an electronic device according to an embodiment of the present invention.

[0028] Figure 1b This is a cross-sectional view of an electronic device according to an embodiment of the present invention.

[0029] Figure 2a This is a perspective view of an electronic device according to an embodiment of the present invention.

[0030] Figure 2b This is a cross-sectional view of an electronic device according to an embodiment of the present invention.

[0031] Figure 3 This is a schematic cross-sectional view of an electronic device according to an embodiment of the present invention.

[0032] Figure 4a This is a plan view of the display layer according to an embodiment of the present invention.

[0033] Figure 4b It is along an embodiment of the present invention Figure 1a The I-I' section is a cross-sectional view of the portion corresponding to the display layer.

[0034] Figure 5a This is a plan view of the sensing layer according to an embodiment of the present invention.

[0035] Figure 5b It is along an embodiment of the present invention Figure 5a The cross-sectional view taken from section II-II'.

[0036] Figure 5c It is along an embodiment of the present invention Figure 5a The cross-sectional view taken from section III-III'.

[0037] Figure 6 This illustrates an embodiment of the present invention. Figure 5a Plan view of area AA'.

[0038] Figure 7This is a cross-sectional view showing an electronic device according to an embodiment of the present invention.

[0039] Figure 8 This is an exploded perspective view showing an electronic device according to an embodiment of the present invention.

[0040] Figure 9 This is a graph showing the S-parameters of the antenna pattern according to a frequency according to an embodiment of the present invention.

[0041] Figure 10 This is a graph showing the total gain of the antenna pattern at a frequency according to an embodiment of the present invention.

[0042] Figure 11 This is a graph showing the radial pattern of an antenna pattern according to an embodiment of the present invention.

[0043] Figures 12a to 12e This is a plan view of an antenna pattern according to an embodiment of the present invention.

[0044] Figure 13 This is an exploded perspective view showing an electronic device according to an embodiment of the present invention.

[0045] (Explanation of reference numerals in the attached diagram)

[0046] DD: Electronic Device; DP: Display Layer

[0047] IS: Sensing layer; ANT: Antenna pattern

[0048] MP: Covering layer; OP-MP: Opening.

[0049] IC: Driver chip; RPP: Anti-reflective layer

[0050] FP: Teleportation Department Detailed Implementation

[0051] In this specification, when a constituent element (or region, layer, part, etc.) is referred to as being "on", "connected to", or "combined with" other constituent elements, it means that it can be directly configured / connected / combined with other constituent elements or that a third constituent element can be configured between them.

[0052] The same reference numerals refer to the same constituent elements. Furthermore, in the drawings, the thickness, scale, and dimensions of the constituent elements are enlarged for the purpose of effectively illustrating the technical content.

[0053] "And / or" includes all combinations of more than one structure that can define an association.

[0054] The terms "first," "second," etc., can be used to describe various constituent elements, but the constituent elements cannot be limited by the terms. The terms are used only for the purpose of distinguishing one constituent element from others. For example, a first constituent element can be named a second constituent element without departing from the scope of the invention, and similarly, a second constituent element can be named a first constituent element. Unless explicitly stated differently in the context, singular expressions include plural expressions.

[0055] In addition, terms such as "below," "lower side," "above," and "upper side" are used to describe the relational relationships of the structures shown in the accompanying drawings. These terms are relative concepts and are explained based on the directions indicated in the accompanying drawings.

[0056] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Additionally, terms identical to those defined in commonly used dictionaries shall be interpreted as having the same meaning as in the context of the related art, and shall not be interpreted as having an idealized or overly formal meaning, unless expressly defined herein.

[0057] Terms such as “including” or “having” should be understood to specify the presence of the features, figures, steps, actions, constituent elements, components, or combinations thereof described in the specification, without precluding the presence or additional possibility of one or more other features or figures, steps, actions, constituent elements, components, or combinations thereof.

[0058] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0059] Figure 1a This is a perspective view of an electronic device according to an embodiment of the present invention. Figure 1b This is a cross-sectional view of an electronic device according to an embodiment of the present invention.

[0060] Reference Figure 1a as well as Figure 1b The electronic device DD can be a device activated by an electrical signal. For example, the electronic device DD can be a mobile phone, tablet computer, car navigation system, game console, or wearable device, but is not limited to these. Figure 1a The electronic device DD is illustrated as an example of a mobile phone.

[0061] The electronic device DD can display an image IM via a display surface DD-IS. The display surface DD-IS may include an active area DD-AA and a peripheral area DD-NAA adjacent to the active area DD-AA. The active area DD-AA may be the area where the image IM is displayed. The peripheral area DD-NAA may be the area where the image IM is not displayed. The image IM may include both moving and still images. Figure 1a The image IM example shows a clock window and icon images.

[0062] The active region DD-AA can be parallel to the plane defined by the first direction DR1 and the second direction DR2 intersecting the first direction DR1. The normal direction of the active region DD-AA, i.e. the thickness direction of the electronic device DD, can indicate the third direction DR3.

[0063] The front (or top) and back (or bottom) of each component or unit described below can be divided by a third direction DR3. The third direction DR3 can be a direction intersecting the first direction DR1 and the second direction DR2. For example, the first direction DR1, the second direction DR2, and the third direction DR3 can be orthogonal to each other. Furthermore, in this specification, the surface defined by the first direction DR1 and the second direction DR2 can be defined as a plane, and "viewed from a plane" can be defined as being viewed from the third direction DR3.

[0064] An electronic device DD may include a display layer DP, a sensing layer IS, and a window WP.

[0065] The display layer (DP) can be a structure that substantially generates the image (IM). The display layer (DP) can be a light-emitting display layer, without particular limitation. For example, the display layer (DP) can include an organic light-emitting display layer, a quantum dot display layer, a micro-LED display layer, or a nano-LED display layer.

[0066] The sensing layer IS can be disposed on the display layer DP. The sensing layer IS can be formed on the display layer DP through a continuous process. Alternatively, the sensing layer IS can be bonded to the display layer DP via an adhesive component. The adhesive component can include conventional adhesives or bonding agents. For example, the adhesive component can be a transparent adhesive component such as a pressure-sensitive adhesive film (PSA), an optically clear adhesive film (OCA), or an optically clear resin (OCR).

[0067] The sensing layer IS defines a sensing region SP and an antenna region AP. The sensing region SP can be configured with a sensing sensor to detect external inputs applied from the outside. These external inputs can be user inputs, which may include various forms of external input such as a part of the user's body, light, heat, a pen, or pressure. When viewed in a plane, the sensing region SP may overlap with the active region DD-AA.

[0068] The antenna region AP can be configured to transmit, receive, or transmit / receive multiple wireless communication signals, such as antenna patterns for multiple radio frequency signals. The antenna region AP can be configured adjacent to the periphery of the sensing region SP. Multiple antenna region APs can be provided. In this case, the antenna region APs can extend from at least both sides of the sensing region SP. The sensing layer IS can include one sensing region SP and one or more but no more than four antenna region APs. However, this is exemplary, and the sensing region SP and antenna region APs according to an embodiment of the present invention are not limited thereto.

[0069] When viewed in a planar plane, at least a portion of the antenna region AP can overlap with the active region DD-AA. Even if the electronic device DD is miniaturized or thinned, or the area of ​​the surrounding region DD-NAA is reduced, the space for configuring the antenna region AP can be ensured because the area of ​​the active region DD-AA is guaranteed. The antenna region AP can be formed simultaneously with the sensing region SP. However, this is exemplary; according to an embodiment of the present invention, the antenna region AP can also be formed using a different process than the sensing region SP.

[0070] The window WP can be disposed on the sensing layer IS. The window WP can contain an optically transparent insulating material. For example, the window WP can contain glass or plastic. The window WP can have a multilayer structure or a single-layer structure. For example, the window WP can include multiple plastic films bonded by adhesive, or it can include a glass substrate and plastic films bonded by adhesive.

[0071] Figure 2a This is a perspective view of an electronic device according to an embodiment of the present invention. Figure 2b This is a cross-sectional view of an electronic device according to an embodiment of the present invention. In the description... Figure 2a as well as Figure 2b At that time, targeting through Figure 1a as well as Figure 1b The constituent elements are described, and the same reference numerals are used in the accompanying drawings, and the description of these elements is omitted.

[0072] Reference Figure 2a as well as Figure 2bThe electronic device DDa can display the image IM through the display surface DD-ISa. The display surface DD-ISa may include an active area DD-AAa and a peripheral area DD-NAA adjacent to the active area DD-AAa.

[0073] The active region DD-AAa may define a first active region FA and a second active region BA that bends from the first active region FA. Multiple second active regions BA may be provided. In this case, the multiple second active regions BA may be provided by bending from at least both sides of the first active region FA. The active region DD-AAa may include one first active region FA and one or more but no more than four second active regions BA. However, this is exemplary, and the active region DD-AAa according to an embodiment of the present invention is not limited thereto.

[0074] The electronic device DDa may include a display layer DPa, a sensing layer ISa, and a window WPa.

[0075] The display layer DPa, which overlaps with the second active region BA, can be bent. The sensing layer ISa defines the sensing region SPa and the antenna region APa. When viewed in a plane, the sensing region SPa can overlap with a portion of the first active region FA and the second active region BA. The antenna region APa can overlap with another portion of the second active region BA.

[0076] Figure 3 This is a schematic cross-sectional view of an electronic device according to an embodiment of the present invention.

[0077] Reference Figure 3 The electronic device DD may include a window WP, an adhesive layer OCA, an anti-reflective layer RPP, a sensing layer IS, a display layer DP, and a cover layer MP.

[0078] The window WP can constitute the appearance of the electronic device DD. The window WP can protect the internal structure of the electronic device DD from external impacts and essentially provide the display surface DD-IS (refer to...) of the electronic device DD. Figure 1a The structure of ).

[0079] The adhesive layer OCA can be disposed beneath the window WP. The window WP and the anti-reflective layer RPP can be bonded together via the adhesive layer OCA. The adhesive layer OCA can include conventional adhesives or adhesives. For example, the adhesive layer OCA can be an optically clear adhesive film, an optically clear resin, or a pressure-sensitive adhesive film.

[0080] An anti-reflective layer RRP can be disposed below a window WP. The anti-reflective layer RRP can reduce the reflectivity of natural light (or sunlight) incident from above the window WP. According to an embodiment of the present invention, the anti-reflective layer RRP may include a phase retarder and a polarizer. The phase retarder may be a film type or a liquid crystal coating type, and may include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer may be a film type or a liquid crystal coating type. The film type may include an extended synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged in a predetermined pattern. The phase retarder and polarizer may also include a protective film. The phase retarder and polarizer themselves or the protective film may be defined as the base layer of the anti-reflective layer RRP.

[0081] The adhesive layer OCA can be configured beneath the anti-reflective layer RPP. The anti-reflective layer RPP and the sensing layer IS can be bonded together through the adhesive layer OCA.

[0082] The display layer (DP) can be configured below the sensing layer (IS). The display layer (DP) may include a substrate layer (SUB), a display circuit layer (DP-CL), an image realization layer (DP-OLED), and a thin-film encapsulation layer (TFL). These will be described later.

[0083] A capping layer (MP) can be configured below the display layer (DP). The capping layer MP can block noise generated from the display layer DP and aid in heat dissipation. Additionally, the capping layer MP can block electromagnetic waves. For example, the capping layer MP can be a copper (Cu) sheet. However, this is exemplary, and the capping layer MP can include various layers. For example, the capping layer MP can be a graphite sheet. The capping layer MP can define the opening OP-MP (refer to...) that radiates signals transmitted from the waveguide. Figure 8 For the opening OP-MP (refer to...) Figure 8 (This will be discussed later.)

[0084] Figure 4a This is a plan view of the display layer according to an embodiment of the present invention.

[0085] Reference Figure 4a In the display layer, DP can define the active region DP-AA and the surrounding region DP-NAA adjacent to the active region DP-AA. The active region DP-AA can be the displayed image IM (refer to...). Figure 1a The active area DP-AA can be configured with multiple pixels PX. The peripheral area DP-NAA can be an area for configuring drive circuitry or drive wiring, etc. When viewed in a plane, the active area DP-AA can be connected to the electronic device DD (refer to...). Figure 1a The active region DD-AA (reference) Figure 1a ) or electronic device DDa (refer to Figure 2a The active region DD-AAa (refer to) Figure 2a The DP-NAA region overlaps with the DD-NAA region (see reference). Figure 1a as well as Figure 2a )overlapping.

[0086] The display layer (DP) may include a substrate layer (SUB), multiple pixel layers (PX), multiple signal routing layers (GL, DL, PL, EL), multiple display pads (PDD), and multiple sensor pads (PDT).

[0087] Each of the multiple pixels (PX) can display one of the primary colors or one of the mixed colors. The primary colors can include red, green, or blue. The mixed colors can include various hues such as white, yellow, cyan, or magenta. However, the hue displayed by each pixel (PX) is not limited to these.

[0088] Multiple signal traces GL, DL, PL, and EL can be configured on the substrate layer SUB. These traces can be connected to multiple pixels PX to transmit electrical signals to them. The multiple signal traces GL, DL, PL, and EL may include multiple scan traces GL, multiple data traces DL, multiple power traces PL, and multiple light emission control traces EL. However, this is exemplary, and the structure of the multiple signal traces GL, DL, PL, and EL according to an embodiment of the present invention is not limited thereto. For example, the multiple signal traces GL, DL, PL, and EL according to an embodiment of the present invention may also include initialization voltage traces.

[0089] The power pattern VDD can be configured in the peripheral area DP-NAA. The power pattern VDD can be connected to multiple power lines PL. The display layer DP includes the power pattern VDD, thereby allowing the same power signal to be provided to multiple pixels PX.

[0090] Multiple display pads (PDDs) can be configured in the peripheral area DP-NAA. The multiple display pads (PDDs) may include a first pad (PD1) and a second pad (PD2). Multiple first pads (PD1) can be provided. The multiple first pads (PD1) can be respectively connected to multiple data routes (DL). The second pads (PD2) can be connected to the power pattern (VDD) and electrically connected to multiple power routes (PL). The display layer (DP) can provide externally supplied electrical signals to multiple pixels (PX) through the multiple display pads (PDDs). Alternatively, the multiple display pads (PDDs) may include pads for receiving other electrical signals in addition to the first pads (PD1) and second pads (PD2), and are not limited to any particular embodiment.

[0091] The driving circuit DIC can be mounted on the peripheral area DP-NAA. The driving circuit DIC can be a timing control circuit in chip form. Multiple data routes DL can be electrically connected to multiple first pads PD1 via the driving circuit DIC. However, this is exemplary; according to an embodiment of the present invention, the driving circuit DIC can be mounted on a film different from the display layer DP. In this case, the driving circuit DIC can be electrically connected to multiple display pads PDD via the film.

[0092] Multiple sensing pad PDTs can be configured in the peripheral area DP-NAA. These multiple sensing pad PDTs can be integrated with the sensing layer IS (see reference hereinafter). Figure 3 The multiple sensing electrodes are electrically connected respectively. The multiple sensing pads PDT may include multiple first sensing pads TD1 and multiple second sensing pads TD2.

[0093] Figure 4b It is along an embodiment of the present invention Figure 4a The cross-sectional view taken from I-I'.

[0094] Reference Figure 4b The display layer (DP) may include a substrate layer (SUB), a display circuit layer (DP-CL), an image realization layer (DP-OLED), and a thin-film encapsulation layer (TFL). The display layer (DP) may include multiple insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. The insulating layer, semiconductor layer, and conductive layer can be formed by coating, deposition, or other methods. Subsequently, the insulating layer, semiconductor layer, and conductive layer can be selectively patterned using photolithography. In this way, semiconductor patterns, conductive patterns, signal lines, etc., included in the display circuit layer (DP-CL) and the image realization layer (DP-OLED) can be formed. The substrate layer (SUB) can be a base substrate supporting the display circuit layer (DP-CL) and the image realization layer (DP-OLED).

[0095] The substrate SUB may include a synthetic resin layer. The synthetic resin layer may comprise a thermosetting resin. The substrate SUB may have a multilayer structure. For example, the substrate SUB may include a first synthetic resin layer and silicon dioxide (SiO₂) disposed on the first synthetic resin layer. x The silicon oxide layer comprises an amorphous silicon (a-Si) layer disposed on the silicon oxide layer and a second synthetic resin layer disposed on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer may be referred to as substrate barrier layers.

[0096] The first and second synthetic resin layers may each comprise a polyimide resin. Additionally, each of the first and second synthetic resin layers may comprise at least one of the following: acrylate resin, methacrylate resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin. Furthermore, in this specification, "~~" resin refers to resins containing the functional group "~~". Additionally, the substrate SUB may comprise a glass substrate or an inorganic / inorganic composite material substrate, etc.

[0097] At least one inorganic layer may be disposed on top of the substrate layer SUB. The inorganic layer may comprise at least one of alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed as multiple layers. The multilayer inorganic layer may include a barrier layer and / or a buffer layer. In this embodiment, the display layer DP is shown as including a buffer layer BFL.

[0098] The display circuit layer DP-CL can be disposed on the substrate layer SUB. The display circuit layer DP-CL can provide signals for driving the light-emitting element OLED included in the image implementation layer DP-OLED. The display circuit layer DP-CL may include a buffer layer BFL, a first transistor T1, a second transistor T2, a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, a fifth insulating layer 50, and a sixth insulating layer 60.

[0099] The buffer layer (BFL) can improve the adhesion between the substrate layer (SUB) and the semiconductor pattern. The buffer layer (BFL) may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer can be stacked alternately.

[0100] Semiconductor patterns can be configured on top of the buffer layer BFL. The semiconductor patterns may contain polycrystalline silicon. However, they are not limited to this; the semiconductor patterns may also contain amorphous silicon or metal oxide.

[0101] Figure 4bOnly a portion of the semiconductor pattern is shown; other areas of the pixel PX on the plane may also be configured with semiconductor patterns. The semiconductor pattern can span multiple pixels PX and be arranged according to a specific rule. The semiconductor pattern can have different electrical properties depending on whether it is doped or not. The semiconductor pattern may include a first region with high conductivity and a second region with low conductivity. The first region can be doped with either N-type or P-type dopant. For example, a P-type transistor may include a doped region doped with P-type dopant, and an N-type transistor may include a doped region doped with N-type dopant. The second region can be an undoped region or doped at a lower concentration than the first region.

[0102] The conductivity of the first region can be greater than that of the second region, essentially functioning as an electrode or signal line. The second region can essentially be equivalent to the active region (or channel) of a transistor. In other words, one part of the semiconductor pattern can be the active region of a transistor, another part can be the source or drain of a transistor, and yet another part can be a connecting electrode or a connecting signal line.

[0103] Multiple pixel PX (reference) Figure 4a Each pixel can have an equivalent circuit including seven transistors, one capacitor, and a light-emitting element; the equivalent circuit diagram of a pixel can be deformed in various forms. Figure 4b In the example shown, multiple pixels PX (reference) are included. Figure 4a Each transistor has two transistors T1 and T2, and a light-emitting element OLED. The first transistor T1 may include a source S1, an active region A1, a drain D1, and a gate G1. The second transistor T2 may include a source S2, an active region A2, a drain D2, a gate G2, and an upper electrode UE.

[0104] Alternatively, the source S1, active region A1, and drain D1 of the first transistor T1 can be formed from a semiconductor pattern, and the source S2, active region A2, and drain D2 of the second transistor T2 can be formed from a semiconductor pattern. The sources S1 and S2, and the drains D1 and D2 can extend in opposite directions from the active regions A1 and A2 in cross-section. Figure 4b A portion of the connection signal line SCL, formed from a semiconductor pattern, is shown. Although not shown separately, the connection signal line SCL can be electrically connected on the plane to the drain D2 of the second transistor T2.

[0105] The first insulating layer 10 can be disposed on the buffer layer BFL. The first insulating layer 10 can overlap multiple pixels PX and cover the semiconductor pattern. The first insulating layer 10 can be an inorganic layer and / or an organic layer, and can have a single-layer or multi-layer structure. The first insulating layer 10 can contain at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer 10 can be a single-layer silicon oxide layer. Not only the first insulating layer 10, but the insulating layer of the display circuit layer DP-CL described later can also be an inorganic layer and / or an organic layer, and can have a single-layer or multi-layer structure. The inorganic layer can contain at least one of the above-mentioned substances.

[0106] Gates G1 and G2 can be disposed on the first insulating layer 10. Gates G1 and G2 can be part of a metal pattern. Gates G1 and G2 can overlap with active regions A1 and A2. In the process of doping semiconductor patterns, gates G1 and G2 can be the same as the mask.

[0107] The second insulating layer 20 can be disposed on top of the first insulating layer 10. The second insulating layer 20 can cover the gates G1 and G2. The second insulating layer 20 can overlap multiple pixels PX. The second insulating layer 20 can be an inorganic layer and / or an organic layer, and can have a single-layer or multi-layer structure. In this embodiment, the second insulating layer 20 can be a single-layer silicon oxide layer.

[0108] The upper electrode UE can be disposed on the second insulating layer 20. The upper electrode UE can overlap with the gate G2. The upper electrode UE can be part of a metal pattern. A portion of the gate G2 and the upper electrode UE overlapping therewith can define a capacitor. However, this is exemplary, and the upper electrode UE can also be omitted according to an embodiment of the present invention.

[0109] The third insulating layer 30 can be disposed on the second insulating layer 20. The third insulating layer 30 can cover the upper electrode UE. In this embodiment, the third insulating layer 30 can be a single layer of silicon oxide. A first connection electrode CNE1 can be disposed on the third insulating layer 30. The first connection electrode CNE1 can be connected to the connection signal line SCL through the contact hole CNT-1 that passes through the first to third insulating layers 10, 20, and 30.

[0110] The fourth insulating layer 40 may be disposed on top of the third insulating layer 30. The fourth insulating layer 40 may cover the first connecting electrode CNE1. The fourth insulating layer 40 may be a single layer of silicon oxide.

[0111] A fifth insulating layer 50 may be disposed on top of a fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer. A second connecting electrode CNE2 may be disposed on the fifth insulating layer 50. The second connecting electrode CNE2 may be connected to the first connecting electrode CNE1 through a contact hole CNT-2 that penetrates both the fourth insulating layer 40 and the fifth insulating layer 50.

[0112] The sixth insulating layer 60 may be disposed on top of the fifth insulating layer 50. The sixth insulating layer 60 may cover the second connecting electrode CNE2. The sixth insulating layer 60 may be an organic layer.

[0113] The image implementation layer DP-OLED may include a first electrode AE, a pixel defining film PDL, and a light-emitting element OLED.

[0114] The first electrode AE ​​can be disposed on the sixth insulating layer 60. The first electrode AE ​​can be connected to the second connecting electrode CNE2 through the contact hole CNT-3 penetrating the sixth insulating layer 60.

[0115] An opening OP can be defined in the pixel defining film PDL. The opening OP of the pixel defining film PDL can expose at least a portion of the first electrode AE.

[0116] Active region DP-AA (reference) Figure 3 The light-emitting region PXA may include a light-emitting region PXA and a light-shielding region NPXA adjacent to the light-emitting region PXA. The light-shielding region NPXA may surround the light-emitting region PXA. In this embodiment, the light-emitting region PXA is correspondingly defined within a portion of the area of ​​the first electrode AE ​​exposed through the opening OP.

[0117] A hole control layer (HCL) can be configured together in the light-emitting region (PXA) and the light-blocking region (NPXA). The HCL may include a hole transport layer and a hole injection layer. An emissive layer (EML) can be configured on top of the HCL. The EML can be configured in the region corresponding to the opening (OP). That is, the EML can be formed separately for each pixel.

[0118] An electronic control layer (ECL) can be disposed on top of the light-emitting layer (EML). The ECL may include an electron transport layer and an electron injection layer. A hole control layer (HCL) and the ECL can be co-formed on multiple pixels using an open mask. A second electrode (CE) can be disposed on the ECL. The second electrode (CE) can have a monolithic shape. The second electrode (CE) can be co-located on multiple pixels (PX).

[0119] The thin-film encapsulation layer (TFL) can be disposed on top of and cover the image realization layer (DP-OLED). The TFL may include a first inorganic layer, an organic layer, and a second inorganic layer sequentially stacked along the third direction DR3. However, this is exemplary, and the TFL according to an embodiment of the present invention is not limited thereto. For example, the TFL according to an embodiment of the present invention may further include multiple inorganic layers and multiple organic layers.

[0120] The first inorganic layer can prevent external moisture or oxygen from penetrating the image realization layer of the DP-OLED. For example, the first inorganic layer may contain silicon nitride, silicon oxide, or a compound combining the above.

[0121] The organic layer can be disposed on the first inorganic layer to provide a flat surface. Any irregularities formed on the first inorganic layer or particles present on the first inorganic layer can be covered by the organic layer. For example, the organic layer may include an acrylic organic layer, but is not limited thereto.

[0122] The second inorganic layer may be disposed on the organic layer and cover the organic layer. The second inorganic layer may encapsulate moisture or other substances released from the organic layer, preventing them from flowing to the outside. The second inorganic layer may comprise silicon nitride, silicon oxide, or a compound combining these.

[0123] Figure 5a This is a plan view of the sensing layer according to an embodiment of the present invention. Figure 5b It is along an embodiment of the present invention Figure 5a The cross-sectional view taken from section II-II'. Figure 5c It is along an embodiment of the present invention Figure 5a The cross-sectional view taken from section III-III'.

[0124] Reference Figures 5a to 5c In the sensing layer IS, the active region IS-AA and the surrounding region IS-NAA can be defined. The active region IS-AA can be a region activated by an electrical signal. When viewed in a plane, the active region IS-AA can be connected to the display layer DP (refer to...). Figure 4a The active region DP-AA (refer to) Figure 4a The IS-NAA area overlaps with the display layer DP (refer to...). Figure 4a The surrounding area of ​​DP-NAA (refer to) Figure 4a )overlapping.

[0125] The active region IS-AA may include a first active region IS-AA1 and a second active region IS-AA2. Multiple sensing electrodes TE1 and TE2 may be configured in the first active region IS-AA1. The first portion PT1 of multiple antenna patterns ANT may be configured in the second active region IS-AA2. A dummy pattern may also be configured in the second active region IS-AA2. The dummy pattern can reduce the reflectivity difference between the portion with the antenna pattern ANT and the portion without the antenna pattern ANT. Therefore, it is possible to prevent the antenna pattern ANT from being identified from the outside. When viewed in a plane, the first active region IS-AA1 may be adjacent to the sensing region SP (refer to...). Figure 1b When viewed in a plane, the second active region IS-AA2 and the surrounding region IS-NAA can overlap with the antenna region AP (refer to...). Figure 1b Overlap. The antenna pattern ANT can be floated.

[0126] The sensing layer IS may include a substrate insulating layer IS-IL0, multiple sensing electrodes TE1, TE2, multiple sensing lines TL1, TL2, and multiple antenna patterns ANT.

[0127] The substrate insulating layer IS-IL0 can be an inorganic layer comprising any one of silicon nitride, silicon oxynitride, and silicon oxide. Alternatively, the substrate insulating layer IS-IL0 can be an organic layer comprising epoxy resin, acrylic resin, or imide resin. The substrate insulating layer IS-IL0 can be formed directly on the display layer DP (see reference). Figure 1b Above. Alternatively, the substrate insulating layer IS-IL0 can be connected to the display layer DP (see reference). Figure 1b They are joined together by adhesive components.

[0128] Multiple sensing electrodes TE1 and TE2 can be configured in the sensing area SP. These electrodes TE1 and TE2 may include multiple first sensing electrodes TE1 and multiple second sensing electrodes TE2. The sensing layer IS can obtain information about external inputs by detecting changes in capacitance between the multiple first sensing electrodes TE1 and the multiple second sensing electrodes TE2.

[0129] Each of the plurality of first sensing electrodes TE1 may extend along a first direction DR1. The plurality of first sensing electrodes TE1 may be arranged along a second direction DR2. Each of the plurality of first sensing electrodes TE1 may include a plurality of sensing patterns SP1 and a plurality of bridging patterns BP1.

[0130] Each of the plurality of second sensing electrodes TE2 may extend along a second direction DR2. The plurality of second sensing electrodes TE2 may be arranged along a first direction DR1. Each of the plurality of second sensing electrodes TE2 may include a plurality of first portions SP2 and a plurality of second portions BP2.

[0131] exist Figure 5a The example shown depicts two bridging patterns BP1 connected to two adjacent sensing patterns SP1, but the plurality of bridging patterns BP1 and the plurality of sensing patterns SP1 according to an embodiment of the present invention are not limited thereto. For example, two adjacent sensing patterns SP1 can also be connected by a single bridging pattern BP1.

[0132] Multiple second portions BP2 can be configured on a different layer than multiple bridging patterns BP1. The multiple bridging patterns BP1 can be insulated from and intersect with multiple second sensing electrodes TE2. For example, the multiple second portions BP2 can be insulated from and intersect with each of the multiple bridging patterns BP1.

[0133] Multiple bridging patterns BP1 can be disposed on the substrate insulating layer IS-IL0. The first insulating layer IS-IL1 can be disposed on the multiple bridging patterns BP1. The first insulating layer IS-IL1 can have a single-layer or multi-layer structure. The first insulating layer IS-IL1 can contain inorganic materials, organic materials, or composite materials.

[0134] Multiple sensing patterns SP1, multiple first portions SP2, and multiple second portions BP2 can be disposed on the first insulating layer IS-IL1. The multiple sensing patterns SP1, multiple first portions SP2, and multiple second portions BP2 can have a mesh structure.

[0135] Multiple contact holes (CNTs) can be formed by penetrating the first insulating layer IS-IL1 through the third-direction DR3. Two adjacent sensing patterns SP1 in the multiple sensing patterns SP1 can be electrically connected to the bridging pattern BP1 through the multiple contact holes (CNTs).

[0136] The second insulating layer IS-IL2 can be disposed on multiple sensing patterns SP1, multiple first portions SP2, and multiple second portions BP2. The second insulating layer IS-IL2 can have a single-layer or multi-layer structure. The second insulating layer IS-IL2 can contain inorganic materials, organic materials, or composite materials.

[0137] exist Figure 5b The example illustrates a bottom bridging structure in which multiple bridging patterns BP1 are disposed under multiple sensing patterns SP1, multiple first portions SP2, and multiple second portions BP2, but is not limited thereto. For example, the sensing layer IS may also have a top bridging structure in which multiple bridging patterns BP1 are disposed above multiple sensing patterns SP1, multiple first portions SP2, and multiple second portions BP2.

[0138] Multiple antenna patterns ANT can be configured on the same layer as a portion of multiple sensing electrodes TE1, TE2. Multiple antenna patterns ANT can be configured on a first insulating layer IS-IL1. For example, multiple antenna patterns ANT can be configured on the same layer as multiple sensing patterns SP1, multiple first portions SP2, and multiple second portions BP2. However, this is exemplary, and the configuration relationship of multiple antenna patterns ANT according to an embodiment of the present invention is not limited thereto. For example, multiple antenna patterns ANT can also be configured on the same layer as multiple bridging patterns BP1. Multiple antenna patterns ANT can have a mesh structure.

[0139] According to the present invention, multiple antenna patterns ANT can be configured on the same layer as a portion of the multiple sensing electrodes TE1, TE2 that sense external inputs, instead of being configured on separate layers. Therefore, it is possible to reduce the size of the electronic device DD (refer to...). Figure 1a The thickness of the electronic device DD (refer to) is reduced, and the thickness of the electronic device DD (refer to) is reduced. Figure 1a The weight of ).

[0140] Multiple antenna patterns ANT can contain a portion of the same material as a portion of the multiple sensing electrodes TE1, TE2, and are formed using the same process. For example, the multiple first sensing electrodes TE1 and the multiple antenna patterns ANT can contain carbon nanotubes, metals and / or metal alloys or composites thereof, and can have a single-layer structure or a multilayer structure of sequentially stacked titanium (Ti), aluminum (Al), and titanium (Ti). However, this is exemplary; according to an embodiment of the present invention, the multiple antenna patterns ANT can also contain materials different from the multiple first sensing electrodes TE1, and can also be formed using separate processes. For example, the multiple first sensing electrodes TE1 can have a multilayer structure of sequentially stacked titanium (Ti), aluminum (Al), and titanium (Ti), and the multiple antenna patterns ANT can contain carbon nanotubes, metals and / or metal alloys or composites thereof, and can have a single-layer or multilayer structure. For example, the metal material can be silver (Ag), copper (Cu), aluminum (Al), gold (Au), or platinum (Pt), but is not limited thereto.

[0141] Multiple antenna patterns ANT may include a first part PT1 and a second part PT2. The first part PT1 may be related to the sensing area SP (refer to...). Figure 1b The second part PT2 can extend from the first part PT1 in the first direction DR1. The first part PT1 and the second part PT2 can be provided integrally. The second part PT2 can be the remaining part of the antenna pattern ANT other than the first part PT1.

[0142] The first part PT1 can be configured in the active region IS-AA. When viewed in a planar view, the first part PT1 can be connected to the display layer DP (see reference). Figure 4a The active region DP-AA (refer to) Figure 4a )overlapping.

[0143] The second part, PT2, can be configured in the surrounding IS-NAA area. When viewed in a planar view, the second part, PT2, can be integrated with the display layer DP (see reference). Figure 4a The surrounding area of ​​DP-NAA (refer to) Figure 4a )overlapping.

[0144] Multiple antenna patterns ANT may also include at least one ground electrode disposed beneath the substrate insulating layer IS-ILO. However, this is exemplary, and the ground electrode according to one embodiment of the invention is not limited thereto. For example, the ground electrode according to one embodiment of the invention may be the display layer DP (refer to...) Figure 4b The second electrode CE (refer to) Figure 4b ).

[0145] The multiple sensing lines TL1 and TL2 may include multiple first sensing lines TL1 and multiple second sensing lines TL2. The multiple first sensing lines TL1 may be electrically connected to multiple first sensing electrodes TE1 respectively. The multiple second sensing lines TL2 may be electrically connected to multiple second sensing electrodes TE2 respectively.

[0146] Multiple first sensing pads TD1 (reference) Figure 4a Multiple first sensing lines TL1 can be electrically connected via contact holes. Multiple second sensing pads TD2 (refer to...) Figure 4a It can be electrically connected to multiple second sensing lines TL2 through contact holes.

[0147] Figure 6 This illustrates an embodiment of the present invention. Figure 5a Plan view of area AA'.

[0148] Reference Figure 6 The antenna pattern ANT can have a quadrilateral shape defined by a first direction DR1 and a second direction DR2.

[0149] The antenna pattern ANT can have a mesh structure. A first opening HA1 can be defined in the first portion PT1. A second opening HA2 can be defined in the second portion PT2. The size of the first opening HA1 can be larger than the size of the second opening HA2. The first opening HA1 can be connected to the light-emitting area PXA (reference). Figure 4b The first opening HA1 can be larger than the light-emitting area PXA (reference). Figure 4b (size).

[0150] Figure 7 This is a cross-sectional view showing an electronic device according to an embodiment of the present invention. Figure 8 This is an exploded perspective view showing an electronic device according to an embodiment of the present invention.

[0151] Reference Figure 7 as well as Figure 8 The display layer DP may include a first surface SF1 and a second surface SF2. The first surface SF1 and the second surface SF2 may face each other. The first surface SF1 may be referred to as the top of the display layer DP, and the second surface SF2 may be referred to as the bottom of the display layer DP.

[0152] The sensing layer IS can face the first surface SF1.

[0153] The cladding layer MP can face the second surface SF2. The cladding layer MP can be separated from the display layer DP and the sensing layer IS by the third direction DR3. The cladding layer MP can define the opening OP-MP. When viewed in a plane, the opening OP-MP can overlap with the antenna pattern ANT. The opening OP-MP can overlap with the active region DP-AA (refer to...). Figure 4a )overlapping.

[0154] The driver chip IC can be configured below the overlay layer MP. The driver chip IC can provide signals to the antenna pattern ANT. The driver chip IC can control the operation of the antenna pattern ANT. For example, the driver chip IC can adjust the power supplied to multiple antenna pattern ANTs configured in the antenna region AP to adjust the beam orientation of the multiple antenna pattern ANTs, and can concentrate the frequency signal in a specific direction to increase energy. Furthermore, a desired radiation pattern can be formed, thereby improving radiation efficiency. In one embodiment of the present invention, the driver chip IC may also be referred to as a beamforming chip IC.

[0155] The transfer unit FP can be integrated below the cover layer MP. When viewed in a planar view, the transfer unit FP can overlap with the opening OP-MP. The transfer unit FP can include a first surface and a second surface facing the first surface. A driver chip IC can be disposed on the first surface. Alternatively, the transfer unit FP can be curved, and the second surface of the transfer unit FP can face each other.

[0156] The transmitter unit FP may have a ground coplanar waveguide (GCPW) structure. A first slot HM1 and a second slot HM2, spaced apart from the first slot HM1 in a second direction DR2, can be defined on the first surface of the transmitter unit FP. When viewed in a plane, the first slot HM1 and the second slot HM2 may overlap with the opening OP-MP.

[0157] The transport section FP and the cover layer MP can be bonded together by an adhesive component. An adhesive component can be disposed between the transport section FP and the cover layer MP. The adhesive component may include anisotropic conductive film (ACF). However, this is exemplary; according to an embodiment of the invention, the adhesive component may comprise various materials that bond the transport section FP and the cover layer MP. For example, the adhesive component may include a pressure-sensitive adhesive film (PSA), an optically clear adhesive film (OCA), or an optically clear resin (OCR), etc. When viewed in a planar plane, the adhesive component may not overlap with the opening OP-MP.

[0158] The driver chip IC can transmit signals via the transmission line SGL configured between the first slot HM1 and the second slot HM2. When viewed in planar view, the transmission line SGL may not overlap with the opening OP-MP. The signal can be provided to the antenna pattern ANT through the opening OP-MP defined in the cover layer MP. For example, the signal can be radiated to the antenna pattern ANT through the opening OP-MP. The signal can indirectly power the antenna pattern ANT through the opening OP-MP. Indirect power supply can mean signal transmission without a direct connection to the antenna pattern ANT.

[0159] According to the present invention, the electronic device DD can supply power to the antenna pattern ANT through the opening OP-MP defined by the structure for cutting off electromagnetic waves, namely the cover layer MP. The electronic device DD may not include a separate structure for supplying power to the antenna pattern ANT. Therefore, the thickness of the electronic device DD can be reduced.

[0160] Unlike the present invention, the transmission section with the driving chip mounted can be electrically connected to the sensing layer IS and bend towards the back of the display layer DP. The driving chip can directly power the antenna pattern ANT. In this case, due to the transmission section disposed on the sensing layer IS, the performance of the anti-reflective layer RRP may be reduced, and the image IM (refer to) of the electronic device DD may be affected. Figure 1aDisplay performance may be reduced. Furthermore, due to the transmission unit disposed above the sensing layer IS, the external input sensing performance of the electronic device DD may be reduced. However, according to the present invention, the transmission unit FP can be incorporated below the overlay layer MP disposed below the display layer DP. The driver chip IC can indirectly supply power to the antenna pattern ANT through the overlay layer MP. Between the display layer DP and the anti-reflective layer RPP, a structure connecting to the driver chip IC for supplying power to the antenna pattern ANT may not be configured. Therefore, the image IM (refer to) of the electronic device DD can be improved. Figure 1a This improves display performance. Furthermore, a structure connecting the sensor chip IC to power the antenna pattern ANT can be omitted between the sensing layer IS and the anti-reflective layer RPP. Therefore, the external input sensing performance of the electronic device DD can be enhanced.

[0161] Furthermore, according to the present invention, the transmission unit FP can be integrated under the overlay layer MP disposed below the display layer DP. The transmission unit FP may not be disposed between the display layer DP and the anti-reflective layer RPP, or between the sensing layer IS and the anti-reflective layer RPP. Therefore, the transmission unit FP is not exposed to the outside, preventing its durability from decreasing due to external impacts.

[0162] Figure 9 This is a graph showing the S-parameters of the antenna pattern according to a frequency according to an embodiment of the present invention.

[0163] Reference Figure 8 as well as Figure 9 S11 can be one of the S-parameters. S11 can be a value expressing the ratio of the magnitude of the reflected signal to the magnitude of the input signal. For example, S11 can be the reflection coefficient of the antenna pattern ANT. When judging the operation of the antenna pattern ANT, a negative value of S11 can be used as a benchmark. A negative value of S11 means that the magnitude of the reflected signal is smaller than the input signal. The smaller the value of S11, the smaller the reflected signal, and the smaller the reflected signal, the more likely the antenna pattern ANT is operating in the corresponding frequency band. For example, referring to the first curve G1, the antenna pattern ANT can operate at 27.8 GHz.

[0164] Figure 10 This is a graph showing the total gain of the antenna pattern at a frequency according to an embodiment of the present invention.

[0165] Reference Figure 8 as well as Figure 10The antenna pattern ANT can be electrically connected to the driver chip IC via the overlay layer MP. The antenna pattern ANT can be indirectly powered by the driver chip IC to operate at a specific frequency. For example, referring to the second curve G2, the antenna pattern ANT can maintain a total antenna gain of approximately -1 dB at that specific frequency. For example, the specific frequency could be 27.8 GHz. Therefore, an antenna pattern ANT with reduced losses can be provided when transmitting, receiving, or transmitting frequency signals.

[0166] Figure 11 This is a graph showing the radial pattern of an antenna pattern according to an embodiment of the present invention.

[0167] Reference Figure 8 as well as Figure 11 The third curve, G3, illustrates the radiation pattern of the frequency signal emitted by the antenna pattern ANT. When the antenna gain is close to 0 dB in the radiation pattern, it can be said that the frequency signal is radiated in the corresponding direction. In this direction, 0 can refer to the third direction DR3. Therefore, the antenna pattern ANT can be indirectly powered from the driver chip IC to radiate a frequency signal to the third direction DR3 at 27.8 GHz. Thus, it can be said that the frequency signal is directional towards the third direction DR3.

[0168] Figures 12a to 12e This is a plan view of an antenna pattern according to an embodiment of the present invention. In the description... Figures 12a to 12e At that time, targeting through Figure 6 The constituent elements are described, and the same reference numerals are used in the accompanying drawings, and the description of these elements is omitted.

[0169] Reference Figure 12a The antenna pattern ANT-1 can have a quadrilateral shape defined by a first direction DR1 and a second direction DR2. The antenna pattern ANT-1 can include a first portion PT1 and a second portion PT2-1. The first portion PT1 can be associated with the active region IS-AA (refer to...). Figure 5a The second part, PT2-1, overlaps with the surrounding IS-NAA area (see reference). Figure 5a The first opening AN-OP1 can be defined in the second part PT2-1. The first opening AN-OP1 may include a first portion extending in the second direction DR2, a second portion extending from one end of the first portion in the first direction DR1, and a third portion extending from one end of the second portion in the second direction DR2. When viewed in a plane, at least a portion of the first opening AN-OP1 may overlap with the covering layer MP (refer to...). Figure 8 The opening OP-MP (refer to) Figure 8(overlap). According to the present invention, the first opening AN-OP1 can deform the radiation pattern of the antenna pattern ANT-1. Therefore, when transmitting, receiving or transmitting frequency signals, an antenna pattern ANT-1 with enhanced radiation performance can be provided.

[0170] Reference Figure 12b The antenna pattern ANT-2 can have a quadrilateral shape defined by a first direction DR1 and a second direction DR2. The antenna pattern ANT-2 can include a first portion PT1 and a second portion PT2-2. The first portion PT1 can be associated with the active region IS-AA (refer to...). Figure 5a The second part, PT2-2, overlaps with the surrounding IS-NAA area (see reference). Figure 5a The second opening AN-OP2 can be defined in the second part PT2-2. The second opening AN-OP2 may include a first portion extending in the first direction DR1, a second portion extending from one end of the first portion in the second direction DR2, and a third portion extending from one end of the second portion in the first direction DR1. When viewed in a plane, at least a portion of the second opening AN-OP2 may overlap with the covering layer MP (refer to...). Figure 8 The opening OP-MP (refer to) Figure 8 (overlap). According to the present invention, the second opening AN-OP2 can deform the radiation pattern of the antenna pattern ANT-2. Therefore, when transmitting, receiving or transmitting frequency signals, an antenna pattern ANT-2 with enhanced radiation performance can be provided.

[0171] Reference Figure 12c The antenna pattern ANT-3 can have a quadrilateral shape defined by a first direction DR1 and a second direction DR2. The antenna pattern ANT-3 can include a first portion PT1 and a second portion PT2-3. The first portion PT1 can be associated with the active region IS-AA (refer to...). Figure 5a The second part, PT2-3, may overlap with the surrounding area IS-NAA (refer to...). Figure 5a The second part PT2-3 may define a third opening AN-OP3. Multiple third openings AN-OP3 may be provided. The third opening AN-OP3 may extend from one side of the antenna pattern ANT-3 towards the first direction DR1. According to the present invention, the third opening AN-OP3 can deform the radiation pattern of the antenna pattern ANT-3. Therefore, when transmitting, receiving, or transmitting / receiving frequency signals, an antenna pattern ANT-3 with enhanced radiation performance can be provided.

[0172] Reference Figure 12dThe antenna pattern ANT-4 can have a bow-tie shape. However, the shape of the antenna pattern ANT-4 is not particularly limited and can have various shapes. For example, the shape of the antenna pattern ANT-4 can also be triangular or circular. According to the present invention, the shape of the antenna pattern ANT-4 can be modified to reflect the radiation pattern of the antenna pattern ANT-4. Therefore, when transmitting, receiving, or transmitting frequency signals, the antenna pattern ANT-4 can provide enhanced radiation performance.

[0173] The antenna pattern ANT-4 may include a first part PT1-4 and a second part PT2-4. The first part PT1-4 may be associated with the active region IS-AA (see reference). Figure 5a The second part, PT2-4, overlaps with the surrounding IS-NAA area (see reference). Figure 5a The openings overlap. The first opening HA1 can be defined in the first part PT1-4, and the second opening HA2 can be defined in the second part PT2-4.

[0174] Reference Figure 12e The antenna pattern ANT-5 can have a quadrilateral shape defined by a first direction DR1 and a second direction DR2. The antenna pattern ANT-5 can include a first portion PT1 and a second portion PT2-5. The first portion PT1 can be associated with the active region IS-AA (see reference). Figure 5a The second part, PT2-5, overlaps with the surrounding IS-NAA area (see reference). Figure 5a The second opening HA2-5 can be defined in the second part PT2-5. The size of the first opening HA1 can be the same as the size of the second opening HA2-5. According to the present invention, the radiation pattern of the antenna pattern ANT-5 can be deformed according to the sizes of the openings HA1 and HA2-5 defined in the antenna pattern ANT-5. Therefore, when transmitting, receiving or transmitting frequency signals, an antenna pattern ANT-5 with enhanced radiation performance can be provided.

[0175] Figure 13 This is an exploded perspective view showing an electronic device according to an embodiment of the present invention. (In the description...) Figure 13 At that time, targeting through Figure 8 The constituent elements are described, and the same reference numerals are used in the accompanying drawings, and the description of these elements is omitted.

[0176] Reference Figure 13 The overlay layer MP-1 can be separated from the display layer DP and the sensing layer IS by a third direction DR3. An opening OP-MP1 can be defined within the overlay layer MP-1. When viewed in a plane, the opening OP-MP1 can overlap with the antenna pattern ANT. The opening OP-MP1 can also overlap with the active region DP-AA (see reference). Figure 4a )overlapping.

[0177] The driver chip IC-1 can be configured below the cover layer MP-1, MP-U. The driver chip IC-1 can be configured adjacent to the opening OP-MP1. The surface of the driver chip IC-1 facing the MP-U below can be a ground coplanar waveguide (GCPW) structure.

[0178] The driver chip IC-1 and the cover layer MP-1 can be bonded together using an adhesive component. The adhesive component may include anisotropic conductive film (ACF). However, this is exemplary; according to an embodiment of the invention, the adhesive component may comprise various materials that bond the delivery portion FP and the cover layer MP. For example, the adhesive component may include a pressure-sensitive adhesive film (PSA), an optically clear adhesive film (OCA), or an optically clear resin (OCR), etc. When viewed in a planar plane, the adhesive component may not overlap with the opening OP-MP1.

[0179] The driver chip IC-1 can transmit signals through the ground coplanar waveguide (GCPW) structure. The driver chip IC-1 can provide signals to the antenna pattern ANT through the opening OP-MP1 defined in the cover layer MP-1. The signal can be radiated to the antenna pattern ANT through the opening OP-MP1. Therefore, the signal can indirectly power the antenna pattern ANT through the opening OP-MP1.

[0180] According to the present invention, a driver chip IC-1 that provides signals to an antenna pattern ANT can be disposed below the cover layer MP-1, MP-U. The driver chip IC-1 can be disposed adjacent to the opening OP-MP1. The signal provided from the driver chip IC-1 can be disposed adjacent to the opening OP-MP1 that radiates the signal to the antenna pattern ANT. This prevents signal loss that may occur during signal transmission from the driver chip IC-1 to the opening OP-MP1. Therefore, the gain of the frequency signals transmitted, received, or transmitted / received by the antenna pattern ANT can be improved.

[0181] Furthermore, according to the present invention, the driver chip IC-1 can indirectly supply power to the antenna pattern ANT through the cover layer MP-1. Between the display layer DP and the anti-reflective layer RPP, and between the sensing layer IS and the anti-reflective layer RPP, a structure connecting to the driver chip IC-1 for supplying power to the antenna pattern ANT is not required. Therefore, the image IM (refer to) of the electronic device DD-1 can be improved. Figure 1a It improves display performance and enhances the external input sensing performance of the DD-1 electronic device.

[0182] The above description refers to preferred embodiments of the present invention. Those skilled in the art or with ordinary knowledge of the art will understand that various modifications and alterations can be made to the present invention without departing from the concept and scope of the invention as set forth in the claims. Therefore, the technical scope of the present invention should not be limited by the details described in the specification, but rather determined by the claims.

Claims

1. An electronic device, comprising: include: The display layer defines the active region and the surrounding region adjacent to the active region; A sensing layer, disposed on the display layer, includes multiple sensing electrodes and an antenna pattern; A cover layer is disposed below the display layer and defines an opening that overlaps with the antenna pattern; as well as The driver chip provides signals to the antenna pattern through the opening defined in the cover layer.

2. The electronic device according to claim 1, wherein, The antenna pattern includes a first portion and a second portion extending from the first portion. When viewed on a plane, the first portion overlaps with the active region, and the second portion overlaps with the surrounding region.

3. The electronic device according to claim 2, wherein, The antenna pattern has a mesh structure.

4. The electronic device according to claim 3, wherein, The first part defines a first opening, and the second part defines a second opening. The size of the first opening is larger than the size of the second opening.

5. The electronic device according to claim 1, wherein, The electronic device further includes: a transmission unit on which the driver chip is mounted. The transmission unit is attached to the underside of the cover layer.

6. The electronic device according to claim 5, wherein, The conveying unit includes a first surface and a second surface facing the first surface. The first surface has a grounded coplanar waveguide structure.

7. The electronic device according to claim 6, wherein, The second face is curved and faces each other. The driver chip is disposed on the first surface.

8. The electronic device according to claim 1, wherein, The driver chip is configured adjacent to the opening.

9. The electronic device according to claim 1, wherein, The opening is defined by the antenna pattern. When viewed in a plane, at least a portion of the opening overlaps with the opening portion.

10. The electronic device according to claim 1, wherein, The antenna pattern is configured on the same layer as a portion of the plurality of sensing electrodes.

11. The electronic device according to claim 1, wherein, The electronic device further includes an anti-reflective layer disposed on the sensing layer.

12. The electronic device according to claim 1, wherein, When viewed in a plane, the opening overlaps with the active region.

13. The electronic device according to claim 1, wherein, The driver chip is disposed under the cover layer.

14. An electronic device, wherein, include: The display layer defines an active region and a surrounding region adjacent to the active region, and includes a first surface and a second surface facing the first surface. The sensing layer faces the first surface and includes an antenna pattern that overlaps with the active region. A cover layer, facing the second surface, defines an opening that overlaps with the active region; as well as The driver chip is disposed under the cover layer and indirectly supplies power to the antenna pattern through the opening.

15. The electronic device according to claim 14, wherein, The antenna pattern has a mesh structure.

16. The electronic device according to claim 14, wherein, The electronic device further includes: a transmission unit on which the driver chip is mounted. The transmission unit is disposed below the cover layer.

17. The electronic device according to claim 16, wherein, The transmission unit has a grounded coplanar waveguide structure.

18. The electronic device according to claim 14, wherein, The opening is defined by the antenna pattern. When viewed in a plane, at least a portion of the opening overlaps with the opening portion.

19. The electronic device according to claim 14, wherein, The sensing layer also includes multiple sensing electrodes. The antenna pattern is configured on the same layer as a portion of the plurality of sensing electrodes.

20. The electronic device according to claim 14, wherein, The electronic device further includes an anti-reflective layer disposed on the sensing layer.

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