Word line driving circuit of memory and timing control method

Abstract

The application provides a word line driving circuit of a memory, which comprises a plurality of row decoding drivers connected with a plurality of pre-decoders, each of the row decoding drivers comprises a power supply selection circuit and a plurality of decoding driving circuits; the word line driving circuit controls the word line of a magnetic random memory; the power supply selection circuit has two input terminals for each decoding driving circuit, one of the input terminals is connected to a driving selection signal provided by the plurality of pre-decoders; the other input terminal of the power supply selection circuit is connected to a read-write selection signal, and the output terminal is connected to a common node; the power supply selection circuit selects the write voltage or the read voltage of the word line according to the input row pre-decoding signal and the read-write selection signal; when the read-write selection signal is in the read state and the row pre-decoding signal is valid, the word line driving circuit selects the read voltage as the power supply voltage. The word line driving circuit has the advantages of simple structure, low manufacturing cost and high reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of memory technology, in particular to a word line driving circuit and a timing control method for memory. BACKGROUND

[0002] In a write operation of a magnetoresistive random access memory (MRAM), a current is applied to the MRAM from a bit line to a source line, and a magnetic tunnel junction (MTJ) is written into a p state (low resistance state); or a current is applied to the MRAM from the source line to the bit line, and the MTJ is written into an ap state (high resistance state). Since the write current is large, it is related to the size of a switch transistor in an MRAM cell, and increasing the size of the switch transistor increases the area of the entire column of the MRAM, so a method of overvoltage on the gate voltage of the transistor is used to increase the driving current. In a read operation of the MRAM, a small current is required, and overvoltage is not required. Therefore, the word line driving circuit of the MRAM chip needs to be able to output a dual-voltage waveform to provide different operating voltages VDD in read / write operations. Some manufacturers use a common voltage VCOM to switch the potential to change the operating voltage of the word line driving circuit.

[0003] As disclosed in US Patent Application No. US20130314980A1, the power supply VCOM input of the word line driving circuit is switched, Vwl is used in the write operation, and Vcore is used in the read operation. However, the word line driving circuit generally has a large scale, and in this technology, the parasitic capacitance of VCOM is relatively large, and a long time is required for switching of VCOM. This causes the switch transistor in the MRAM cell to be in an overvoltage state for a relatively long time during the read operation, which affects the reliability of the transistor. On the other hand, due to the large parasitic capacitance of VCOM, a large power consumption is wasted in switching of VCOM during the read operation. SUMMARY

[0004] To solve the above technical problems, the purpose of the present application is to provide a word line driving circuit which, through a pre-decoder and a matching corresponding power supply switching circuit, realizes selection and control of the word line by the word line driving circuit under a reduced component architecture word line driving circuit structure. The word line driving circuit has the advantages of simple structure, low manufacturing cost, high reliability, high read / write speed, effective reduction of read operation power consumption, and reduction of the overall chip area.

[0005] The purpose of the present application and the solution to the technical problems are achieved by using the following technical solutions.

[0006] The word line driving circuit according to the present application is suitable for the architecture of a magnetic random access memory (MRAM) chip, and comprises a plurality of row decode drivers each comprising a power supply selection circuit and a plurality of row pre-decoders connected to the row decode drivers. The word line driving circuit controls the word lines of the MRAM. The power supply selection circuit has two input terminals, one of which is connected to a driving selection signal provided by the plurality of pre-decoders, and the other of which is connected to a read-write selection signal. The output terminal of the power supply selection circuit is connected to a common node. The power supply selection circuit selects a write voltage or a read voltage for the word line according to the input row pre-decoder signal and the read-write selection signal. When the read-write selection signal is in a read state and the row pre-decoder signal is valid, the word line driving circuit selects the read voltage as the power supply voltage; otherwise, the word line driving circuit selects the write voltage as the power supply voltage.

[0007] The technical problem of the present application can also be solved by the following technical measures.

[0008] Optionally, when the read enable signal from outside the chip arrives, the read-write selection signal remains in the write state for a set time, so that the selected word line is applied with the write voltage; after the set time, the read-write selection signal becomes in the read state.

[0009] Optionally, the input circuit of each row decode driver is an NAND gate circuit, and the output circuit of the row decode driver is a buffer circuit or an inverter circuit, the input terminal of which is connected to the output terminal of the NAND gate circuit.

[0010] Optionally, the power supply selection circuit comprises an NAND gate, the input terminals of which are connected to the read-write selection signal and the driving selection signal, respectively; a NOT gate, the input terminal of which is connected to the output terminal of the NAND gate; a write enable switch, the gate of which is connected to the output terminal of the NOT gate, the source of which is connected to a first potential, and the drain of which is connected to the common node; and a read enable switch, the gate of which is connected to the output terminal of the NAND gate, the source of which is connected to a second potential, and the drain of which is connected to the common node.

[0011] Optionally, the write enable switch and the read enable switch are p-type field effect transistors or n-type field effect transistors.

[0012] Optionally, the read-write selection signal is generated by a read-write enable circuit, which comprises a first NOT gate, the input terminal of which is connected to a write control signal of the MRAM; an NAND gate, one input terminal of which is connected to the output terminal of the first NOT gate, and the other input terminal of which is connected to a power supply switch control enable signal; and a second NOT gate, the input terminal of which is connected to the output terminal of the NAND gate, and the output terminal of which generates the read-write selection signal.

[0013] Another object of the present application is to provide a memory comprising any of the word line driving circuits described above.

[0014] The application further provides a timing control method of a memory, which comprises the following steps: a plurality of pre-decoders select a region decoding circuit to work according to an address signal; a read-write enable circuit generates a read-write selection signal according to a write control signal of the memory and a power switch control enable signal; and the row decoding driver selects a write voltage or a read voltage of a word line according to the read-write selection signal and the input row pre-decoding signal, and the read-write selection signal selects the read voltage when the read-write selection signal is in a read state and the row pre-decoding signal is valid, and selects the write voltage otherwise.

[0015] The application solves the technical problem by using the following technical measures.

[0016] Optionally, when the read enable signal from outside the chip arrives, the read-write selection signal remains in the write state for a set time, so that the selected word line is applied with the write voltage; and after the set time, the read-write selection signal becomes in the read state.

[0017] Optionally, in the read operation, the time length of adjusting the potential of the output circuit to the second potential is controlled by controlling the enable time of the power switch control enable signal, so as to accelerate the pull-up speed of the word line and improve the read speed.

[0018] Optionally, the time length is adjusted so that the peak difference between the rising potential of the output circuit and the second potential is close to or equal to 0V.

[0019] The application reduces the area of the external power switch circuit by changing the circuit of the region decoding circuit. Although the power switch circuit is added in each group of region decoding circuits, the circuit is relatively small because it is shared by part or all of the decoding driver circuits, and has little effect on the area of each group of region decoding circuits, so the total chip area of the word line driving circuit can be reduced. In addition, the parasitic capacitance of the common node VPP is only 1 / n in the read operation, where n is the number of region decoding circuits. In the continuous read-write operation, VPP needs to be charged and discharged between VDD1 and VDD2, and the reduction of the parasitic capacitance of VPP can effectively save the power consumption in the read operation. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0021] Figure 1 The structure of the word line driving circuit of the exemplary memory;

[0022] Figure 2 A structure diagram of a word line driving circuit of a memory of an embodiment of the present application;

[0023] Figure 3 A structure diagram of a region decoding circuit of an embodiment of the present application;

[0024] Figure 4 A structure diagram of a read / write enable circuit of an embodiment of the present application;

[0025] Figure 5 A timing diagram of a timing control method of a memory of an embodiment of the present application. DETAILED DESCRIPTION

[0026] Reference will now be made to the drawings, wherein like numerals refer to like components throughout. The following description is based on the exemplified embodiments of the present application and should not be taken as limiting the other embodiments of the present application not detailed herein.

[0027] The following description of several embodiments is with reference to the accompanying drawings, which illustrate specific embodiments to which the present application can be practiced. Directional terms as used in the present application, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "lateral" and the like, are made in reference to the accompanying drawings. The directional terms are used to illustrate and understand the present application, not to limit the present application.

[0028] The terms "first", "second", "third", and the like, as used in "the specification and claims of this application, and the aforementioned drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of use in either order. Moreover, the terms "comprise", "have" and "include" and variations thereof, as used in the specification and claims of this application, are intended to cover a non-exclusive inclusion. That is, a process, method, article, or apparatus that comprises, has, or includes an item or list of items for doing an act, unless restricted or limited otherwise by context, covers one or more

[0029] The terminology used in the present application is only used to describe specific embodiments, and is not intended to show the concept of the present application. Unless the context clearly dictates otherwise, the expression used in the singular form encompasses the expression used in the plural form. In the present application, it should be understood that terms such as "include", "have", and "contain" are intended to indicate the possibility of existence of the features, numbers, steps, actions or combinations thereof disclosed in the present application, and are not intended to exclude the possibility of existence or addition of one or more other features, numbers, steps, actions or combinations thereof. The same reference numerals in the drawings refer to the same parts.

[0030] The accompanying drawings and description are to be regarded as illustrative in nature and are not intended to limit the scope of the application. In the drawings, like reference numerals are used to indicate like components. Also, for the purpose of understanding and ease of description, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited thereto.

[0031] In the drawings, the configuration range of the apparatus, system, component, circuit is exaggerated for clarity, understanding and ease of description. It will be understood that when a component is referred to as being "on" another component, the component can be directly on the other component, or there can be an intervening component.

[0032] In addition, in the specification, unless explicitly described to the contrary, the word "comprise" will be understood to mean including but not limited to any of the components. Furthermore, in the specification, "on" means above or below the target component, and does not mean necessarily on the top based on the direction of gravity.

[0033] To further illustrate the technical means and effects taken by the present application to achieve the predetermined object, the specific implementation, structure, features and effects of a word line driving circuit of a memory according to the present application are described in detail below in combination with the drawings and specific embodiments.

[0034] Figure 1 The structure diagram of an exemplary word line driving circuit of a memory. As shown in Figure 1 The patent application discloses switching the power supply VCOM input of the row decoder, using Vwl during the write operation and Vcore during the read operation. This patent can solve the problem of different output voltages of the MRAM read-write row decoder, but since the row decoder is generally relatively large in design, the VCOM parasitic capacitance is also relatively large, and the VCOM switching requires a relatively long time. This causes the switch transistor in the MRAM cell to be in an overvoltage state for a considerable period of time during the read operation, affecting the reliability of the transistor. On the other hand, due to the large VCOM parasitic capacitance, there is also a considerable power consumption waste during the VCOM switching during the read operation.

[0035] Figure 2 The structure diagram of a word line driving circuit of a memory according to an embodiment of the present application. Figure 3 The structure diagram of a region decoding circuit according to an embodiment of the present application.

[0036] As shown in Figure 2 , the word line driving circuit is suitable for the magnetic random memory chip architecture, and is usually implemented in two parts, a first part is a pre-decoder 120, and a second part is a local-decoder 140, and the two parts are connected to form a plurality of pairs of decoding circuits.

[0037] Optionally, the number of the pre-decoders 120 is two or more, all the pre-decoders 120 have n address input terminals in common, each of the pre-decoders 120 has k control output terminals, and the outputs of the pre-decoders 120 are used as address selection signals (AIN) and drive selection signals (BIN) of the local-decoders 140 according to functions. Wherein n is a positive integer greater than or equal to 1, k is 2 n , k = 2, 4, 8, 16, etc., and common layouts are k = 8, 16.

[0038] Optionally, the local-decoders 140 are connected to the pre-decoders 120 correspondingly, and can be divided into k groups. For example, two 2-4 pre-decoders are connected to four area decoder groups to form a 4-16 word line driving circuit.

[0039] As shown in Figure 3 , each of the local-decoders 140 includes a power selection circuit 141 and a plurality of decoding driving circuits 144. The power selection circuit 141 and each of the decoding driving circuits 144 individually has two input terminals, one of which is connected to the drive selection signals (BIN) provided by the plurality of pre-decoders 120. The other input terminal of the power selection circuit 141 is connected to a read-write selection signal VPPSW, and the output terminal is connected to a common node VPP. The other input terminal of the power selection circuit 141 is connected to the read-write selection signal VPPSW, and the output terminal is connected to the common node VPP. The power selection circuit 141 selects a write voltage or a read voltage of a word line according to an input row pre-decoding signal and the read-write selection signal VPPSW. When the read-write selection signal VPPSW is in a read state and the row pre-decoding signal is valid, the word line driving circuit selects the read voltage as the power voltage, and otherwise, the write voltage is selected.

[0040] In an embodiment of the present application, when a read enable signal REN outside the chip reaches, the read-write selection signal VPPSW still remains in a write state for a set time, so that the selected word line is applied with the write voltage; after the set time, the read-write selection signal VPPSW becomes in a read state.

[0041] In an embodiment of the present application, as shown in Figure 3As shown, the input circuit of each row decoder driver 144 is a NAND gate circuit 145, and the output circuit 146 of the row decoder driver 144 is a buffer circuit or an inverting circuit, the input of which is connected to the output of the NAND gate circuit.

[0042] In one embodiment of this application, such as Figure 3 As shown, the power selection circuit 141 includes: a NAND gate 142, a NOT gate 143, a write enable switch M1, and a read enable switch M2. The input of the NAND gate 142 is connected to the read / write selection signal VPPSW and the drive selection signal (BIN), respectively. The input of the NOT gate 143 is connected to the output of the NAND gate 142. The gate of the write enable switch M1 is connected to the output (WEN) of the NOT gate 143, its source is connected to the first potential VDD1, and its drain is connected to the common node VPP. The gate of the read enable switch M1 is connected to the output (REN) of the NAND gate 142, its source is connected to the second potential VDD2, and its drain is connected to the common node VPP. The first potential VDD1 and the second potential VDD2 are opposite potentials. The write enable switch M1 and the read enable switch M2 are p-type field-effect transistors or n-type field-effect transistors.

[0043] Figure 4 This is a schematic diagram of the read / write enable circuit according to an embodiment of this application, as shown below. Figure 4 The read / write selection signal VPPSW is generated by the read / write enable circuit 150, which includes: a first NOT gate 151, whose input is connected to the write control signal WE of the memory; a NAND gate 152, one input is connected to the output of the first NOT gate 151, and the other input is connected to the power switch control enable signal RE0V; and a second NOT gate 153, whose input is connected to the output of the NAND gate 152, and whose output generates the read / write selection signal VPPSW.

[0044] In one embodiment of this application, a memory is provided, which includes any of the aforementioned word line driving circuits. It should be understood that the power switch control enable signal RE0V is generated by delaying the read control signal RE through a certain logic circuit. Both the write control signal WE and the read control signal RE serve as external input signals to the memory.

[0045] Figure 5A timing diagram of a timing control method of a memory according to an embodiment of the present application. In the diagram, WE is a write control signal of the memory, which is used to control the read / write operation of the memory. When WE is high, it corresponds to a write operation; when WE is low, it corresponds to a read operation. AIN represents an input memory address, and WL represents one of the decoder output waveforms. The method comprises: the plurality of pre-decoders 120 selecting a row decode driver to work according to an address signal; generating a read / write selection signal VPPSW according to the write control signal WE of the memory and a power switch control enable signal RE0V through a read / write enable circuit 150; and the row decode driver 140 selecting a write voltage or a read voltage of a word line according to the read / write selection signal VPPSW and the power selection circuit 141 selecting the read voltage or the write voltage of the word line according to an input row pre-decode signal and the read / write selection signal VPPSW. When the read / write selection signal VPPSW is in a read state and the row pre-decode signal is valid, the word line driving circuit selects the read voltage as the power voltage; otherwise, it selects the write voltage as the power voltage.

[0046] As mentioned above, when the read enable signal REN from outside the chip arrives, the read / write selection signal VPPSW remains in the write state for a set time, so that the selected word line is applied with the write voltage; after the set time, the read / write selection signal VPPSW becomes in the read state.

[0047] In some embodiments, during a read operation, the time length T1 of adjusting the potential input into the output circuit 146 to the second potential VDD2 is controlled by controlling the enable timing of the power switch control enable signal RE0V. In this way, the speed of pulling up the word line can be accelerated, and the read speed can be improved. Further, the peak difference V1 between the rising potential input into the output circuit and the second potential VDD2 is close to or equal to 0V by adjusting the time length T1.

[0048] The present application reduces the area of the external power switch circuit by changing the circuit of the row decode driver. Although the power switch circuit is added in each group of row decode drivers, this part of the circuit is generally shared by part or all of the decode driver circuits, and the size is relatively small, so the area of each group of row decode drivers is not greatly affected, and thus the overall chip area of the word line driving circuit can be reduced. Secondly, during a read operation, the parasitic capacitance of the common node VPP is only 1 / n, where n is the number of row decode drivers. During continuous read / write operations, VPP needs to be charged and discharged between VDD1 and VDD2, and the reduction of the parasitic capacitance of VPP can effectively save the power consumption during the read operation.

[0049] The phrases "in one embodiment of the present application" and "in various embodiments" are used repeatedly. This phrase generally does not refer to the same embodiment; however, it can refer to the same embodiment. The words "comprise", "have", and "include" and the like are synonymous, unless the context clearly indicates otherwise.

[0050] The above merely provides specific examples of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed with specific examples, it is not intended to limit the present application. Any person skilled in the art, without departing from the technical scope of the present application, can make some minor changes or modifications to the above disclosed technical content to obtain equivalent embodiments with equivalent changes. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the technical scope of the present application, shall still fall within the scope of the technical solutions of the present application.

Claims

1. A memory word line driving circuit suitable for a magnetic random access memory chip architecture, the word line driving circuit comprising a plurality of row decoder drivers each comprising a power selection circuit and a plurality of pre-decoders connected thereto, wherein: the word line driving circuit controls word lines of the magnetic random access memory; the power selection circuit is connected to each row decoder driver via two inputs, one of which is connected to an address selection signal provided by each row pre-decoder and the other of which is connected to a read / write selection signal provided by each row pre-decoder, and the power selection circuit has an output connected to a common node; the power selection circuit selects a write voltage or a read voltage for the word line in dependence on a drive selection signal input and the read / write selection signal, the word line driving circuit power voltage selecting the read voltage when the read / write selection signal is in a read state and the drive selection signal is active, and the word line driving circuit power voltage selecting the write voltage when the read / write selection signal is in the read state and the drive selection signal is inactive; the read / write selection signal remains in the write state for a set time after a read enable signal from outside the chip is received, so that the selected word line is applied with the write voltage; and the read / write selection signal changes to the read state after the set time. the input circuit of each row decoder driver is a NAND gate circuit, and the output circuit of each row decoder driver is a buffer circuit or an inverter circuit having an input connected to an output of the NAND gate circuit. the power selection circuit comprises: a NAND gate having inputs connected to the read / write selection signal and the address selection signal; a NOT gate having an input connected to an output of the NAND gate; a write enable switch having a gate connected to an output of the NOT gate, a source connected to a first potential, and a drain connected to the common node; and a read enable switch having a gate connected to an output of the NAND gate, a source connected to a second potential, and a drain connected to the common node. the write enable switch and the read enable switch are p-type field effect transistors or n-type field effect transistors.

2. The word line drive circuit of claim 1, wherein the read / write selection signal is generated by a read / write enable circuit comprising: a first NOT gate having an input connected to a write control signal of the memory; a NAND gate having one input connected to an output of the first NOT gate and another input connected to a power switch control enable signal; and a second NOT gate having an input connected to an output of the NAND gate and an output generating the read / write selection signal.

7. A memory comprising the word line driving circuit of any one of claims 1 to 5.

3. The word line driver circuit of claim 1, wherein, 8. A timing control method for a memory comprising the word line driving circuit of claim 1, the timing control method comprising: selecting, by the plurality of pre-decoders, a row decoder driver to operate in dependence on an address signal; generating, by a read / write enable circuit, a read / write selection signal in dependence on a write control signal of the memory and a power switch control enable signal; and selecting, by the power selection circuit, a write voltage or a read voltage for the word line in dependence on a drive selection signal input and the read / write selection signal, the word line driving circuit power voltage selecting the read voltage when the read / write selection signal is in a read state and the drive selection signal is active, and the word line driving circuit power voltage selecting the write voltage when the read / write selection signal is in the read state and the drive selection signal is inactive.

4. The word line driver circuit of claim 1, wherein, ​ ​ ​ ​ ​ 5. The word line driver circuit of claim 4, wherein, ​ 6. The word line driver circuit of claim 1, wherein, ​ ​ ​ ​ ​ ​ ​ ​ ​ 9. The method of claim 8, wherein the memory is a synchronous dynamic random access memory (SDRAM). When a read enable signal from outside the chip arrives, the read / write selection signal remains in the write state for a set time, so that the selected word line is applied with a write voltage; After the set time, the read / write selection signal becomes a read state.

10. The method of claim 9, wherein the memory is a synchronous dynamic random access memory (SDRAM). In the read operation, the time length of the potential adjustment of the output circuit of the row decode driver to the second potential is controlled by controlling the enable timing of the power switch control enable signal; And by adjusting the time length, the peak difference between the rising potential of the output circuit of the row decode driver and the second potential is close to or equal to 0V.

Images