Memory device and method of operation thereof

Abstract

A memory device and an operating method thereof are provided. The memory device includes a memory block including a plurality of memory cells and a plurality of selection transistors, a peripheral circuit for performing a programming operation on a selected selection transistor among the plurality of selection transistors in a selection transistor programming operation, and a control logic for controlling the peripheral circuit to perform the selection transistor programming operation. In the selection transistor programming operation, the peripheral circuit applies a coupling voltage having a positive potential to a source line of the memory block.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0146924, filed on November 5, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to an electronic device, and more specifically, to a memory device and a method of operating the same. Background Technology

[0004] The paradigm of recent computing environments has evolved into ubiquitous computing environments where computing systems can be used anytime, anywhere. This has facilitated the increasing use of portable electronic devices such as mobile phones, digital cameras, and laptops. These portable electronic devices typically include memory systems that utilize memory devices (i.e., data storage devices). Data storage devices serve as either the main memory device or auxiliary memory device in portable electronic devices.

[0005] Because they lack mechanical drive components, data storage devices utilizing memory offer excellent stability and durability, high data access speeds, and low power consumption. Examples of memory systems with these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces, solid-state drives (SSDs), and so on.

[0006] Memory devices are typically classified as volatile memory devices and non-volatile memory devices.

[0007] Non-volatile memory devices have relatively slow write and read speeds, but they retain stored data even when power supply is interrupted. Therefore, non-volatile memory devices are used to store data to be retained regardless of whether power is supplied. Examples of non-volatile memory include read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Flash memory is classified into NOR flash memory and NAND flash memory. Summary of the Invention

[0008] The embodiments may provide a memory device and a method of operating the memory device, the memory device being able to improve the threshold voltage distribution of the select transistor in the programming operation of the select transistor.

[0009] According to one aspect of this disclosure, a memory device is provided, the memory device comprising: a memory block including a plurality of memory cells and a plurality of select transistors; peripheral circuitry configured to perform a programming operation on a selected select transistor among the plurality of select transistors in a select transistor programming operation; and control logic configured to control the peripheral circuitry to perform the select transistor programming operation, wherein in the select transistor programming operation, the peripheral circuitry applies a coupling voltage having a positive potential to the source line of the memory block.

[0010] According to another aspect of this disclosure, a memory device is provided, comprising: a memory block including a plurality of memory cells and a plurality of drain-select transistors; peripheral circuitry configured to perform a programming operation on a selected drain-select transistor among the plurality of drain-select transistors in a select transistor programming operation; and control logic configured to control the peripheral circuitry to perform the select transistor programming operation, wherein in the select transistor programming operation, the peripheral circuitry applies a coupling voltage having a positive potential to the source line of the memory block, and wherein, due to coupling caused by the coupling voltage, the potential level of a second bit line connected to an unselected drain-select transistor among the plurality of drain-select transistors is increased.

[0011] According to another aspect of this disclosure, a method for operating a memory device includes: applying a programming enable voltage to a first bit line connected to a selected drain select transistor among a plurality of drain select transistors connected to a selected drain select line; applying a first programming disable voltage to a second bit line connected to an unselected drain select transistor among the plurality of drain select transistors; applying a coupling voltage to a source line having a potential higher than the first programming disable voltage; and programming the selected drain select transistor by sequentially applying a pass voltage and a programming voltage to the selected drain select line. Attached Figure Description

[0012] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, these exemplary embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0013] In the accompanying drawings, dimensions may be enlarged for clarity. It should be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or there may be one or more intermediate elements. Throughout the text, similar reference numerals refer to similar elements.

[0014] Figure 1 This is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0015] Figure 2 It is a diagram. Figure 1 The block diagram of the memory device shown is shown.

[0016] Figure 3 It is a diagram. Figure 2 A diagram of the memory block shown.

[0017] Figure 4 This is a diagram illustrating an embodiment of a three-dimensional configuration of a memory block.

[0018] Figure 5 This is a flowchart illustrating the selection transistor programming operation of a memory device according to an embodiment of the present disclosure.

[0019] Figure 6 It is a waveform diagram of the signal, illustrating the selection transistor programming operation according to an embodiment of the present disclosure.

[0020] Figure 7 This is a block diagram illustrating another embodiment of the memory system disclosed herein.

[0021] Figure 8 This is a block diagram illustrating another embodiment of the memory system disclosed herein.

[0022] Figure 9 This is a block diagram illustrating another embodiment of the memory system disclosed herein.

[0023] Figure 10 This is a block diagram illustrating another embodiment of the memory system disclosed herein. Detailed Implementation

[0024] The specific structural or functional descriptions disclosed herein are merely illustrative and intended to describe embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0025] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can readily implement the technical spirit of the present disclosure.

[0026] Figure 1This is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0027] refer to Figure 1 The memory system 1000 may include a memory device 1100 and a memory controller 1200, the memory device 1100 being configured to store data and the memory controller 1200 being configured to control the memory device 1100 under the control of the host 2000.

[0028] The host 2000 can communicate with the storage system 1000 using interface protocols such as Peripheral Component Interconnect-Fast (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or Serial Attached SCSI (SAS). Furthermore, the interface protocol between the host 2000 and the storage system 1000 is not limited to the examples described above and can be one of other interface protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), and Electronic Integrated Drive (IDE).

[0029] The memory controller 1200 can control the overall operation of the memory system 1000 and control the data exchange between the host 2000 and the memory device 1100. For example, the memory controller 1200 can control the memory device 1100 to program or read data according to a request from the host 2000. In a programming operation, the memory controller 1200 can transmit the command CMD, address ADD, and data to be programmed DATA corresponding to the programming operation to the memory device 1100. Furthermore, in a reading operation, the memory controller 1200 can receive and temporarily store the data DATA read from the memory device 1100, and transmit the temporarily stored data DATA to the host 2000.

[0030] The memory device 1100 can perform programming, reading, or erasing operations under the control of the memory controller 1200.

[0031] In some embodiments, the memory device 1100 may include Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), or Flash Memory.

[0032] Figure 2 It is a diagram. Figure 1 The block diagram of the memory device shown is shown.

[0033] refer to Figure 2The memory device 1100 may include a memory cell array 100 in which data is stored. The memory device 1100 may include peripheral circuitry 200 configured to: perform programming operations for storing data in the memory cell array 100, perform read operations for outputting the stored data, and perform erase operations for erasing the stored data. The memory device 1100 may include control logic 300, which is configured in a memory controller (…). Figure 1 The peripheral circuit 200 is controlled under the control of 1200 shown in the figure.

[0034] Memory cell array 100 may include multiple memory blocks MB1 to MBk 110 (k is a positive integer), wherein local lines LL and bit lines BL1 to BLm (m is a positive integer) may be connected to each of the memory blocks MB1 to MBk 110. For example, local line LL may include a first select line, a second select line, and a plurality of word lines arranged between the first select line and the second select line. Furthermore, local line LL may include dummy lines arranged between the first select line and the word line and between the second select line and the word line. The first select line may be a source select line, and the second select line may be a drain select line. For example, local line LL may include word lines, drain select lines, and source select lines, and a source line SL. For example, local line LL may further include dummy lines. For example, local line LL may further include pipe lines. Local line LL may be connected to each of the memory blocks MB1 to MBk 110, and bit lines BL1 to BLm may be commonly connected to memory blocks MB1 to MBk 110. Memory blocks MB1 to MBk 110 can be implemented in a two-dimensional or three-dimensional structure. For example, in a memory block 110 with a two-dimensional structure, memory cells can be arranged in a direction parallel to the substrate (not shown). For example, in a memory block 110 with a three-dimensional structure, memory cells can be stacked in a direction perpendicular to the substrate (not shown).

[0035] Each memory block MB1 through MBk 110 includes a drain select transistor connected to a drain select line. The drain select transistor is connected between bit lines BL1 through BLm and the memory cell, and the bit lines BL1 through BLm can be connected to the memory cell in response to an operating voltage applied through the drain select line. The drain select transistor can be programmed to have a set threshold voltage value, which can be defined as the programming operation of the select transistor.

[0036] The peripheral circuit 200 can be configured to perform programming, reading, and erasing operations on the selected memory block 110 under the control of the control logic 300. Furthermore, the peripheral circuit 200 can be configured to perform selection transistor programming operations on the drain selection transistors included in the selected memory block 110.

[0037] For example, peripheral circuitry 200 may include voltage generation circuitry 210, row decoder 220, page buffer group 230, column decoder 240, input / output circuitry 250, pass / fail check circuitry 260, and source line driver 270.

[0038] The voltage generation circuit 210 can generate various operating voltages Vop for programming, reading, and erasing operations in response to the operation signal OP_CMD. Furthermore, the voltage generation circuit 210 can selectively discharge the local line LL in response to the operation signal OP_CMD. For example, the voltage generation circuit 210 can generate programming voltage, verification voltage, and pass voltage under the control of the control logic 300.

[0039] The row decoder 220 can transmit the operating voltage Vop to the local line LL connected to the selected memory block 110 in response to the row decoder control signal AD_signals. For example, in a select transistor programming operation, in response to the row decoder control signal AD_signals, the row decoder 220 can apply the programming voltage generated by the voltage generation circuit 210 to the selected drain select line in the local line LL, and apply the through voltage generated by the voltage generation circuit 210 to the word line. In a select transistor programming operation, the row decoder 220 can apply a ground voltage to the unselected drain select line and source select line.

[0040] Page buffer group 230 may include multiple page buffers PB1 to PBm 231 connected to bit lines BL1 to BLm. Page buffers PB1 to PBm 231 may operate in response to page buffer control signal PBSIGNALS. For example, in a programming operation, page buffers PB1 to PBm 231 may temporarily store the data to be programmed based on temporarily stored data and control the potential level of bit lines BL1 to BLm. Additionally, in a read operation or a program verification operation, page buffers PB1 to PBm may sense the voltage or current of bit lines BL1 to BLm.

[0041] In a select transistor programming operation, page buffers PB1 to PBm 231 can apply a first programming disable voltage or a programming enable voltage to the corresponding bit lines BL1 to BLm. For example, in a select transistor programming operation, page buffers PB1 to PBm 231 can apply a programming enable voltage to the bit line connected to the drain select transistor to be programmed, and can apply a first programming disable voltage to the bit line connected to the unprogrammed drain select transistor.

[0042] In response to the column address CADD, the column decoder 240 can transfer data between the input / output circuitry 250 and the page buffer group 230. For example, the column decoder 240 can exchange data with the page buffer 231 via the data line DL, or with the input / output circuitry 250 via the column line CL.

[0043] The input / output circuit 250 can transmit data from the memory controller (…). Figure 1 The command CMD and address ADD (as shown in 1200) are transmitted to the control logic 300, or the data DATA is exchanged with the column decoder 240.

[0044] During a read operation or a program verification operation, the pass / fail check circuit 260 can generate a reference current in response to the enable bit VRY_BIT<#>, and output a pass signal PASS or a failure signal FAIL by comparing the sensed voltage VPB received from the page buffer group 230 with a reference voltage generated by the reference current. The sensed voltage VPB can be a controlled voltage based on the number of memory cells determined to have passed during the program verification operation.

[0045] The source line driver 270 can be connected to the memory cells included in the memory cell array 100 via the source line SL, and control the voltage applied to the source line SL. The source line driver 270 can receive the source line control signal CTRL_SL from the control logic 300, and control the source line voltage applied to the source line SL based on the source line control signal CTRL_SL.

[0046] In a select transistor programming operation, the source line driver 270 may apply a coupling voltage to the source line SL. The coupling voltage may be a voltage with a positive potential. The coupling voltage may be a voltage with a potential higher than the core supply voltage of the memory device 1100. The coupling voltage may be a voltage with a potential higher than the first programming disable voltage. In a select transistor programming operation, the coupling voltage may be a voltage used to allow an increase in the potential level of the bit line through coupling.

[0047] In response to commands CMD and ADD, control logic 300 can control peripheral circuitry 200 by outputting operation signals OP_CMD, line decoder control signals AD_signals, page buffer control signals PBSIGNALS, and enable bit VRY_BIT<#>. During a select transistor programming operation, control logic 300 can control source line driver 270 to apply a coupling voltage to source line SL. For example, during a select transistor programming operation, control logic 300 can control page buffer group 230 to apply a first programming disable voltage to the bit lines BL1 to BLm connected to the unprogrammed drain select transistor, and then control source line driver 270 to apply the coupling voltage to source line SL. Control logic 300 can control page buffer group 230 such that bit lines BL1 to BLm are floating when the coupling voltage is applied to source line SL. Therefore, during the selection transistor programming operation, the page buffer group 230 increases the potential level of the bit lines BL1 to BLm connected to the unprogrammed drain selection transistor to the potential level of the first programming disable voltage, and then increases it to the potential level of the second programming disable voltage, which is higher than the first programming disable voltage.

[0048] Figure 3 It is a diagram. Figure 2 A diagram of the memory block shown.

[0049] refer to Figure 3 In memory block 110, multiple word lines arranged parallel to each other can be connected between a first select line and a second select line. The first select line can be a source select line SSL, and the second select line can be a drain select line DSL. More specifically, memory block 110 can include multiple serial lines ST connected between bit lines BL1 to BLm and the source line SL. Bit lines BL1 to BLm can be connected to serial lines ST individually, and the source line SL can be connected together to serial lines ST. Serial lines ST can be configured identically to each other, and therefore, a serial line ST connected to the first bit line BL1 will be described in detail as an example.

[0050] A string ST may include a source selection transistor SST, multiple memory cells F1 to F16, and a drain selection transistor DST, which are connected in series between the source line SL and the first bit line BL1. A string ST may include at least one source selection transistor SST and at least one drain selection transistor DST, and a string ST may include multiple memory cells, the number of which is greater than the number of memory cells F1 to F16 shown in the figure.

[0051] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells F1 to F16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gate of the source select transistor SST included in different strings of ST can be connected to the source select line SSL. The gate of the drain select transistor DST included in different strings of ST can be connected to the drain select line DSL, and the gate of the memory cells F1 to F16 included in different strings of ST can be connected to multiple word lines WL1 to WL16. A group of memory cells connected to the same word lines among the memory cells included in different strings of ST can be called a page PPG. Therefore, a page PPG whose number corresponds to the number of word lines WL1 to WL16 can be included in memory block 110.

[0052] Figure 4 This is a diagram illustrating an embodiment of a memory block configured in three dimensions according to the present disclosure.

[0053] refer to Figure 4 The memory cell array 100 may include multiple memory blocks MB1 to MBk 110. Memory block 110 may include multiple strings ST11 to ST1m and ST21 to ST2m. In one embodiment, each of the multiple strings ST11 to ST1m and ST21 to ST2m may be formed in an "I" shape or a "U" shape. In the first memory block MB1, m strings may be arranged in the row direction (X direction). Although in Figure 4 The diagram illustrates the arrangement of two strings in the column direction (Y direction), but this is for ease of description, and three or more strings can be arranged in the column direction (Y direction).

[0054] Each of the multiple strings ST11 to ST1m and ST21 to ST2m may include at least one source selection transistor SST, a first memory cell to an nth memory cell MC1 to MCn, and at least one drain selection transistor DST.

[0055] The source select transistor SST of each string can be connected between the source line SL and memory cells MC1 to MCn. Source select transistors of strings arranged in the same row can be connected to the same source select line. The source select transistors of strings ST11 to ST1m arranged in the first row can be connected to the first source select line SSL1. The source select transistors of strings ST21 to ST2m arranged in the second row can be connected to the second source select line SSL2. In another embodiment, the source select transistors of strings ST11 to ST1m and ST21 to ST2m can be connected to a common source select line.

[0056] The first memory cells to the nth memory cells MC1 to MCn in each string can be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first memory cells to the nth memory cells MC1 to MCn can be connected to the first word line to the nth word line WL1 to WLn, respectively.

[0057] In this embodiment, at least one of the first to nth memory cells MC1 to MCn can be used as a dummy memory cell. When a dummy memory cell is provided, the voltage or current of the corresponding string can be stably controlled. Therefore, the reliability of the data stored in memory block 110 can be improved.

[0058] The drain select transistor (DST) of each string can be connected between the bit line and memory cells MC1 to MCn. The drain select transistors (DST) of strings arranged in the row direction can be connected to drain select lines extending in the row direction. The drain select transistors (DST) of strings ST11 to ST1m in the first row can be connected to the first drain select line DSL1. The drain select transistors (DST) of strings ST21 to ST2m in the second row can be connected to the second drain select line DSL2.

[0059] Figure 5 This is a flowchart illustrating the selection transistor programming operation of a memory device according to an embodiment of the present disclosure.

[0060] Figure 6 It is a waveform diagram of the signal, illustrating the selection transistor programming operation according to an embodiment of the present disclosure.

[0061] The following will refer to Figures 2 to 6 A method is described for performing a selection transistor programming operation on a memory device according to embodiments of the present disclosure.

[0062] In step S510, page buffers PB1 to PBm 231, under the control of control logic 300, apply a programming enable voltage (e.g., VSS) to the first bit line BL (PGM) for a specific time. This first bit line BL (PGM) is connected to the selected drain select transistor DST among the drain select transistors DST included in the selected memory block (e.g., MB1) to which programming operations are to be performed. Furthermore, page buffers PB1 to PBm 231, under the control of control logic 300, apply a first programming disable voltage VH1 to the second bit line BL (Inhibit) for a specific time. This second bit line BL (Inhibit) is connected to the unselected drain select transistor DST among the drain select transistors DST included in the selected memory block (e.g., MB1) to which programming operations are not performed. The first programming disable voltage VH1 can be the core power supply voltage of the memory device 1100. Therefore, the second bit line BL (Inhibit) can be charged to the level of the first programming disable voltage VH1.

[0063] Page buffers PB1 to PBm 231 apply a programming enable voltage VSS or a first programming disable voltage VH1 to the bit lines BL1 to BLm of the selected memory block (e.g., MB1) for a specific period of time, and then control the bit lines BL1 to BLm to be in a floating state.

[0064] In step S520, the source line driver 270 can apply a coupling voltage Vcp to the source line SL under the control of the control logic 300. The coupling voltage Vcp can be a voltage with a potential higher than the first programming inhibit voltage VH1. The coupling voltage Vcp can also be a voltage with a potential higher than the core supply voltage. Therefore, due to the coupling phenomenon caused by the coupling voltage Vcp applied to the source line SL, the second bit line BL(Inhibit), which is controlled to be in a floating state after being charged to the level of the first programming inhibit voltage VH1, can be increased to the voltage of the second programming inhibit voltage VH2. The second programming inhibit voltage VH2 has a potential higher than the first programming inhibit voltage VH1.

[0065] Due to the coupling phenomenon caused by the coupling voltage Vcp applied to the source line SL, the potential of the first line BL(PGM), which is controlled to be in a floating state after the first line BL(PGM) is charged to the level of the programming allow voltage VSS, can be increased to a specific level.

[0066] In step S530, the voltage generation circuit 210 generates and outputs the pass voltage Vpass and the programming voltage Vpgm under the control of the control logic 300, and the line decoder 220 sequentially applies the pass voltage Vpass and the programming voltage Vpgm generated by the voltage generation circuit 210 to the selected drain selection line Sel DSL of the selected memory block MB1.

[0067] For example, the line decoder 220 applies the pass voltage Vpass generated by the voltage generation circuit 210 to the selected drain select line Sel DSL and word lines WL (WL1 to WLn), and programs the drain select transistor connected to the first bit line BL (PGM) in the drain select transistor DST connected to the selected drain select line Sel DSL by applying the programming voltage Vpgm generated by the voltage generation circuit 210 to the selected drain select line Sel DSL after a certain time.

[0068] During a portion of the time period during which a voltage Vpass is applied to the selected drain selection line Sel DSL, page buffers PB1 to PBm231 can control the potential of the first line BL(PGM) to the level of the programming enable voltage VSS by applying a programming enable voltage VSS to the first bit line BL(PGM) for a specific time. Page buffers PB1 to PBm231 can apply a first programming disable voltage VH1 to the second bit line BL(Inhibit), but the second bit line BL(Inhibit) maintains the level of the second programming disable voltage VH2.

[0069] While the programming voltage Vpgm is applied to the selected drain select line Sel DSL, the second bit line BL (Inhibit) can maintain the level of the second programming inhibit voltage VH2, which has a higher potential than the first programming inhibit voltage VH1. Therefore, the increase in the threshold voltage of the drain select transistor DST connected to the selected drain select line Sel DSL and connected to the second bit line BL (Inhibit) is suppressed, preventing any programming operation on it.

[0070] Subsequently, the line decoder 220 discharges the selected drain select line SelDSL, to ground, which has been programmed with a voltage Vpgm, and discharges the word lines WL1 to WLn, to ground, which have been programmed with a pass voltage Vpass. Then, the source driver 270 discharges the source lines SL, to ground, which have been coupled with a voltage Vcp. The potential level of the source line SL can be discharged in multiple steps.

[0071] In the transistor selection programming operation, the line decoder 220 can apply the ground voltage VSS to the unselected drain selection line Unsel DSL and source selection line SSL.

[0072] Figure 7 This is a block diagram illustrating another embodiment of a memory system according to the present disclosure.

[0073] refer to Figure 7 The memory system 30000 can be implemented as a cellular phone, smartphone, tablet PC, personal digital assistant (PDA), or wireless communication device. The memory system 30000 may include a memory device 1100 and a memory controller 1200 capable of controlling the operation of the memory device 1100. The memory controller 1200, under the control of the processor 3100, can control the data access operations of the memory device 1100, such as programming, erasing, and reading operations.

[0074] Under the control of the memory controller 1200, the data programmed in the memory device 1100 can be output through the display 3200.

[0075] The radio transceiver 3300 can transmit / receive radio signals via the antenna ANT. For example, the radio transceiver 3300 can convert the radio signals received via the antenna ANT into signals that can be processed by the processor 3100. Therefore, the processor 3100 can process the signals output from the radio transceiver 3300 and transmit the processed signals to the memory controller 1200 or the display 3200. The memory controller 1200 can transmit the signals processed by the processor 3100 to the memory device 1100. Furthermore, the radio transceiver 3300 can convert the signals output from the processor 3100 into radio signals and output the converted radio signals to external devices via the antenna ANT. The input device 3400 is a device capable of inputting control signals for controlling the operation of the processor 3100 or data to be processed by the processor 3100, and can be implemented as an indicating device, such as a touchpad or computer mouse, keypad, or keyboard. The processor 3100 can control the operation of the display 3200, so that data output from the memory controller 1200, data output from the radio transceiver 3300, or data output from the input device 3400 can be output through the display 3200.

[0076] In some embodiments, the memory controller 1200, capable of controlling the operation of the memory device 1100, can be implemented as part of the processor 3100, or can be implemented as a chip separate from the processor 3100. Furthermore, it can utilize... Figure 1The memory controller 1200 shown is implemented using the memory controller 1200, and can be utilized Figure 2 The memory device 1100 shown is implemented as memory device 1100.

[0077] Figure 8 This is a block diagram illustrating another embodiment of a memory system according to the present disclosure.

[0078] refer to Figure 8 The memory system 40000 can be implemented as a personal computer (PC), tablet PC, netbook, e-reader, personal digital assistant (PDA), portable multimedia player (PMP), MP3 player, or MP4 player.

[0079] The memory system 40000 may include a memory device 1100 and a memory controller 1200 capable of controlling the data processing operations of the memory device 1100.

[0080] Based on the data input via input device 4200, processor 4100 can output data stored in memory device 1100 via display 4300. For example, input device 4200 can be implemented as an indicating device, such as a touchpad or computer mouse, keypad or keyboard.

[0081] The processor 4100 can control the overall operation of the memory system 40000 and can control the operation of the memory controller 1200. In some embodiments, the memory controller 1200, which is capable of controlling the operation of the memory device 1100, can be implemented as part of the processor 4100, or it can be implemented as a chip separate from the processor 4100. Furthermore, it can utilize... Figure 1 The memory controller 1200 shown is implemented using the memory controller 1200, and can be utilized Figure 2 The memory device 1100 shown is implemented as memory device 1100.

[0082] Figure 9 This is a block diagram illustrating another embodiment of a memory system according to the present disclosure.

[0083] refer to Figure 9 The memory system 50000 can be implemented as an image processing device, such as a digital camera, a mobile terminal with a digital camera attached, a smartphone with a digital camera attached, or a tablet PC with a digital camera attached.

[0084] The memory system 50000 may include a memory device 1100 and a memory controller 1200 capable of controlling data processing operations (e.g., programming operations, erasing operations, or reading operations) of the memory device 1100.

[0085] The image sensor 5200 of the memory system 50000 can convert optical images into digital signals, and the converted digital signals can be transmitted to the processor 5100 or the memory controller 1200. Under the control of the processor 5100, the converted digital signals can be output through the display 5300, or stored in the memory device 1100 through the memory controller 1200. Furthermore, under the control of the processor 5100 or the memory controller 1200, the data stored in the memory device 1100 can be output through the display 5300.

[0086] In some embodiments, the memory controller 1200, capable of controlling the operation of the memory device 1100, can be implemented as part of the processor 5100, or can be implemented as a chip separate from the processor 5100. Furthermore, it can utilize... Figure 1 The memory controller 1200 shown is implemented using the memory controller 1200, and can be utilized Figure 2 The memory device 1100 shown is implemented as memory device 1100.

[0087] Figure 10 This is a block diagram illustrating another embodiment of a memory system according to the present disclosure.

[0088] refer to Figure 10 The memory system 70000 can be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 1100, a memory controller 1200, and a card interface 7100.

[0089] The memory controller 1200 can control data exchange between the memory device 1100 and the card interface 7100. In some embodiments, the card interface 7100 may be a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface, but this disclosure is not limited thereto. Furthermore, it is possible to utilize... Figure 1 The memory controller 1200 shown is implemented using the memory controller 1200, and can be utilized Figure 2 The memory device 1100 shown is implemented as memory device 1100.

[0090] According to the protocol of host 60000, card interface 7100 can provide an interface for data exchange between host 60000 and memory controller 1200. In some embodiments, card interface 7100 can support Universal Serial Bus (USB) protocol and chip-to-chip (IC) USB protocol. Card interface 7100 can be hardware capable of supporting the protocol used by host 60000, software embedded in the hardware, or signal transmission scheme.

[0091] When the memory system 70000 is connected to the host interface 6200 of the host 60000 (such as a PC, tablet PC, digital camera, digital audio player, cellular phone, console video game hardware, or digital set-top box), the host interface 6200 can perform data communication with the memory device 1100 through the card interface 7100 and the memory controller 1200 under the control of the microprocessor 6100.

[0092] According to this disclosure, during the programming operation of the selection transistor, the increase in the threshold voltage of the unselected selection transistor is suppressed, thereby improving the width of the threshold voltage distribution of the selection transistor.

[0093] In embodiments of this disclosure, the memory device may include a memory block, peripheral circuitry, and control logic. The memory block may include a plurality of memory cells and a plurality of drain-select transistors connected to a selected drain-select line. The peripheral circuitry may be configured to perform a programming operation on a selected drain-select transistor among the plurality of drain-select transistors, and the control logic may be configured to control the peripheral circuitry to perform a programming operation on the selected drain-select transistor. The peripheral circuitry may apply a coupling voltage to the source line having a positive potential higher than the positive potential of an unselected drain-select transistor, and the peripheral circuitry may program the selected drain-select transistor by sequentially applying a pass voltage and a programming voltage to the selected drain-select line.

[0094] While this disclosure has been shown and described with reference to certain exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the exemplary embodiments described above, but should be determined by the appended claims and their equivalents.

[0095] In the above embodiments, all steps may be selectively performed, or some steps may be omitted. In each embodiment, the steps need not be performed in the described order and may be rearranged. The embodiments disclosed in this specification and accompanying drawings are merely examples to facilitate understanding of this disclosure, and this disclosure is not limited thereto. That is, it will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure.

[0096] Furthermore, exemplary embodiments of this disclosure have been described in the accompanying drawings and specification. Although specific terminology is used herein, it is only for the purpose of explaining embodiments of this disclosure. Therefore, this disclosure is not limited to the embodiments described above, and many variations are possible within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein.

Claims

1. A memory device, comprising: A memory block, the memory block comprising a plurality of memory cells and a plurality of selection transistors; In the selection transistor programming operation, the peripheral circuit performs a programming operation on the selected selection transistor among the plurality of selection transistors. as well as Control logic, which controls the peripheral circuitry to perform the selection transistor programming operation. In the selected transistor programming operation, the peripheral circuit applies a positively coupled voltage to the source line of the memory block, and The selection transistor mentioned above is a drain selection transistor connected to the bit line.

2. The memory device according to claim 1, wherein the peripheral circuitry comprises: A voltage generation circuit that generates a pass voltage and a programmable voltage; A row decoder that applies the pass voltage and the programming voltage generated by the voltage generation circuit to the select line and word line of the memory block; Page buffer groups, connected to the bit lines, in the select transistor programming operation, the page buffer groups apply a programming enable voltage to the first bit line of the bit line connected to the selected drain select transistor to which the programming operation is to be performed, and the page buffer groups apply a first programming disable voltage to the second bit line of the bit line connected to the unselected drain select transistor to which the programming operation is not performed; as well as A source line driver, during the selected transistor programming operation, applies the coupling voltage to the source line.

3. The memory device of claim 2, wherein the row decoder applies the pass voltage and the programming voltage sequentially to the selected drain select line in the select line.

4. The memory device of claim 3, wherein the page buffer set applies the programming enable voltage to the first bit line and applies the first programming disable voltage to the second bit line before the through voltage is applied to the selected drain select line.

5. The memory device of claim 4, wherein the page buffer group applies the programming enable voltage and the first programming disable voltage to the first bit line and the second bit line, respectively, and then controls the first bit line and the second bit line to be in a floating state.

6. The memory device of claim 5, wherein the source line driver applies the coupling voltage to the source line from the time period during which the first bit line and the second bit line are in the floating state.

7. The memory device of claim 6, wherein, due to coupling caused by the coupling voltage applied to the source line, the potential level of the second bit line in the floating state is increased to the voltage of a second programming disable voltage, the second programming disable voltage having a higher potential than the first programming disable voltage.

8. The memory device of claim 7, wherein during the period in which the through voltage is applied to the selected drain select line, the page buffer group controls the potential of the first bit line to a level having the programming enable voltage by applying the programming enable voltage to the first bit line in the floating state for a specific time period.

9. A memory device, comprising: A memory block, the memory block comprising a plurality of memory cells and a plurality of drain-select transistors; In the selection transistor programming operation, the peripheral circuit performs a programming operation on the selected drain selection transistor among the plurality of drain selection transistors. as well as Control logic, which controls the peripheral circuitry to perform the selection transistor programming operation. In the selected transistor programming operation, the peripheral circuit applies a positively coupled voltage to the source line of the memory block, and Due to the coupling phenomenon caused by the coupling voltage, the potential level of the second bit line connected to the unselected drain select transistor among the plurality of drain select transistors is increased.

10. The memory device of claim 9, wherein the peripheral circuitry comprises: A voltage generation circuit that generates a pass voltage and a programmable voltage; A row decoder that applies the pass voltage and the programming voltage generated by the voltage generation circuit to the select line and word line of the memory block; Page buffer group, the page buffer group being connected to the bit line of the memory block, wherein during the select transistor programming operation, the page buffer group applies a programming enable voltage to the first bit line of the bit line connected to the selected drain select transistor to which the programming operation is to be performed, and the page buffer group applies a first programming disable voltage to the second bit line of the bit line connected to the unselected drain select transistor to which the programming operation is not performed; as well as A source line driver, during the selected transistor programming operation, applies the coupling voltage to the source line.

11. The memory device of claim 10, wherein the row decoder applies the pass voltage and the programming voltage sequentially to the selected drain select line in the select lines.

12. The memory device of claim 11, wherein before the pass voltage is applied to the selected drain select line, the page buffer group applies the programming enable voltage to the first bit line and the first programming disable voltage to the second bit line for a specific time period, and then controls the first bit line and the second bit line to be in a floating state.

13. The memory device of claim 12, wherein from the time period during which the first bit line and the second bit line are in the floating state, the source line driver applies the coupling voltage to the source line, the coupling voltage having a potential higher than the potential of the first programming disable voltage.

14. The memory device of claim 13, wherein during the period in which the through voltage is applied to the selected drain select line, the page buffer group controls the potential of the first bit line to a level having the programming enable voltage by applying the programming enable voltage to the first bit line in the floating state for a specific time period.

15. A method for operating a memory device, the method comprising: A programming enable voltage is applied to a first bit line, which is connected to the selected drain select transistor among a plurality of drain select transistors connected to a selected drain select line, and a first programming disable voltage is applied to a second bit line, which is connected to the unselected drain select transistor among the plurality of drain select transistors. A coupling voltage is applied to the source line, the coupling voltage having a potential higher than the first programming disable voltage; as well as The selected drain selection transistor is programmed by sequentially applying a pass voltage and a programming voltage to the selected drain selection line.

16. The method of claim 15, wherein when the coupling voltage is applied to the source line, the first bit line and the second bit line are controlled to be in a floating state.

17. The method of claim 16, wherein the potential level of the second bit line in the floating state is increased due to coupling caused by the coupling voltage applied to the source line.

18. The method of claim 17, wherein the coupling voltage has a potential level higher than the potential level of the first programming disable voltage.

19. The method of claim 15, wherein during the period in which the through voltage is applied to the selected drain select line, the programming allows the voltage to be applied to the first bit line for a specific time period.

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