Semiconductor structure and its formation method

Abstract

This invention provides a semiconductor structure and a method for forming the same. The method includes: providing a substrate, the substrate including a substrate itself, discrete fins located on the substrate, and a shielding layer filling trenches between adjacent fins; using the shielding layer as a mask, performing ion implantation on the fins to form well regions; and removing the shielding layer of a first height to form a remaining shielding layer, the top surface of the remaining shielding layer being lower than the top surface of the fins. In the semiconductor structure formation method provided by this invention, since the shielding layer of a first height is removed before heat treatment of the substrate including the remaining shielding layer, the portion of the fin parallel to the removed shielding layer is not affected by the internal stress of the previously parallel portion of the shielding layer during heat treatment, thereby improving the performance of the obtained semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. Transistors, as the most basic semiconductor devices, are currently widely used. Therefore, as the density and integration of semiconductor devices increase, the feature size of planar transistors is also becoming smaller and smaller.

[0003] To better adapt to the reduction in feature size, semiconductor technology has gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as FinFETs.

[0004] Fin field-effect transistors can improve the integration of semiconductor devices, and the gate structure of fin field-effect transistors can control the transistor channel from both sides of the fin, thereby increasing the control of the gate structure over the transistor channel carriers, which is beneficial to reduce leakage current and improve short-channel effect.

[0005] In the manufacturing process of FinFETs, the lattice morphology of the fins has a significant impact on the process window and device performance. Ideally, the desired lattice state of the fins is a single crystal state. However, due to the influence of crystal formation conditions, atomic thermal motion, and other processing conditions, deviations from the ideal crystal structure are often observed. Specifically, ion implantation and heat treatment are required during fin fabrication. During heat treatment, the internal stress of the shielding layer can easily lead to dislocations in the final fin lattice, thus affecting the performance of the resulting semiconductor device. Summary of the Invention

[0006] The technical problem solved by the embodiments of the present invention is how to improve the performance of semiconductor devices.

[0007] To address the above problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising:

[0008] A substrate is provided, the substrate including a substrate, discrete fins located on the substrate, and a shielding layer filling fin trenches between adjacent fins;

[0009] Using the shielding layer as a mask, ion implantation is performed on the fin to form a trap region;

[0010] Remove the first-height shielding layer to form a remaining shielding layer, the top surface of which is lower than the top surface of the fin;

[0011] The substrate, including the remaining shielding layer, is subjected to heat treatment.

[0012] Optionally, the substrate further includes a protective layer that at least covers the sidewalls of the fin, the shielding layer filling the fin grooves between adjacent protective layers;

[0013] The heat treatment of the substrate including the remaining shielding layer further includes:

[0014] Remove the protective layer above the top surface of the remaining shielding layer to expose the sidewall of the fin.

[0015] Optionally, the protective layer also covers the substrate surface between adjacent fins.

[0016] Optionally, the step of providing the substrate includes:

[0017] An initial substrate is provided, and a substrate and discrete fins are formed on the substrate;

[0018] A protective layer is formed, which conformally covers the sidewalls of the fins and the substrate surface between adjacent fins.

[0019] Optionally, the material of the protective layer is different from the material of the shielding layer.

[0020] Optionally, the material of the protective layer includes silicon nitride or silicon carbide.

[0021] Optionally, the thickness of the protective layer is 50 angstroms to 100 angstroms.

[0022] Optionally, the process for forming the protective layer is plasma-assisted chemical vapor deposition.

[0023] Optionally, the top surface of the shielding layer is flush with the top surface of the fin.

[0024] Optionally, the material of the shielding layer is silicon oxide.

[0025] Optionally, the substrate further includes an isolation layer that at least covers the sidewalls of the fin, and the protective layer covers the isolation layer;

[0026] The step of removing the protective layer above the top surface of the remaining shielding layer to expose the sidewall of the fin further includes:

[0027] Remove the protective layer and the isolation layer above the top surface of the remaining shielding layer to expose the sidewall of the fin.

[0028] Optionally, the isolation layer also covers the substrate surface between adjacent fins.

[0029] Optionally, the step of providing the substrate includes:

[0030] An initial substrate is provided, and a substrate and discrete fins are formed on the substrate;

[0031] An isolation layer is formed, which conformally covers the sidewalls of the fins and the substrate surface between adjacent fins;

[0032] A protective layer is formed, which conformally covers the isolation layer.

[0033] Optionally, the material of the isolation layer includes silicon oxide.

[0034] Optionally, the process for forming the isolation layer includes an on-site vapor generation process.

[0035] Optionally, the thickness of the isolation layer is 10 angstroms to 100 angstroms.

[0036] This invention also provides a semiconductor structure, comprising:

[0037] Substrate;

[0038] Discrete fins located on the substrate, wherein ion-implanted trap regions are formed in the fins;

[0039] The remaining shielding layer fills the fin groove between adjacent fins, the top surface of the remaining shielding layer being lower than the top surface of the fin.

[0040] Optionally, it may also include the protective layer that at least covers the sidewalls of the fin.

[0041] Optionally, the material of the protective layer includes silicon nitride or silicon carbide.

[0042] Optionally, the thickness of the protective layer is 50 angstroms to 100 angstroms.

[0043] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0044] The semiconductor structure formation method provided in this embodiment of the invention includes providing a substrate, wherein the substrate includes a substrate, discrete fins located on the substrate, and a shielding layer filling the fin trenches between adjacent fins. Using the shielding layer as a mask, ion implantation is performed on the fins to form well regions. Then, a first-height shielding layer is removed to form a remaining shielding layer, the top surface of which is lower than the top surface of the fins. Finally, the substrate including the remaining shielding layer is heat-treated. Because the first-height shielding layer is removed before heat-treating the substrate including the remaining shielding layer, the portion of the fin parallel to the removed shielding layer is not affected by the internal stress of the previously parallel portion of the shielding layer during heat treatment. This avoids warping of the fin shape and reduces the possibility of dislocation formation in the fins, thereby improving the performance of the obtained semiconductor device. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0046] Figures 1-4 This is a schematic diagram of the steps in a method for forming a semiconductor structure.

[0047] Figures 5-10 This is a schematic diagram of the steps in the semiconductor structure formation method provided in the embodiments of the present invention. Detailed Implementation

[0048] As is known from the background art, in the existing semiconductor structure formation methods, during heat treatment, the internal stress of the substrate can easily cause dislocations in the lattice of the finally formed fins, thereby affecting the performance of the obtained semiconductor device.

[0049] The following section provides a detailed explanation of a method for forming a semiconductor structure. Please refer to [link / reference]. Figure 1-4 , Figures 1-4 This is a schematic diagram of the steps involved in forming a semiconductor structure.

[0050] like Figure 1 As shown, a substrate is provided, wherein the substrate includes a substrate 10, discrete fins 20 located on the substrate 10, and a remaining hard mask layer 30 located above the fins 20.

[0051] In order to improve the quality of the fin 20 when etching the fin 20, a hard mask layer is usually formed above the fin 20. The hard mask layer is first etched to obtain a remaining hard mask layer 30, and then the fin 20 is etched using the remaining hard mask layer 30 as a mask.

[0052] like Figure 2 As shown, an isolation layer 40 is formed using oxidation processes such as thermal oxidation, and the material of the isolation layer 40 is silicon oxide.

[0053] The isolation layer 40 is formed on the sidewall of the fin to protect the fin. Due to the presence of the remaining hard mask layer 30, the top surface of the fin 20 is not exposed. Therefore, when the isolation layer 40 is formed using the oxidation process, the isolation layer 40 will not be formed on the top surface of the fin 20.

[0054] like Figure 3 As shown, a shielding layer 50 is filled, and the material of the shielding layer 50 is the same as that of the isolation layer 40, which is silicon oxide.

[0055] Since it is difficult to make the directly filled shielding layer 50 flush with the top surface of the fin 20, an amount of shielding layer material exceeding the required amount can be filled, and then chemical mechanical polishing technology can be used to obtain... Figure 3 The structure of the shielding layer 50 is such that if the remaining hard masking layer 30 remains above the fin 20, the remaining hard masking layer 30 can be removed while removing the excess shielding layer material to expose the top surface of the fin 20.

[0056] Then, using the shielding layer 50 as a mask, ion implantation is performed on the fin 20 to form a trap region, and the substrate including the shielding layer 50 is heat-treated. Since the shielding layer 50 is made of silicon oxide, it can serve as a mask during ion implantation.

[0057] like Figure 4 As shown, part of the shielding layer 50 is removed, exposing the sidewall of the fin 20.

[0058] After ion implantation, part of the shielding layer 50 is removed to expose the sidewall of the fin 20, preparing for subsequent processes.

[0059] However, during ion implantation, the implanted atoms pass through the spaces between atoms in the fin 20, which damages the lattice of the fin 20. Furthermore, the implanted ions do not occupy lattice points in the crystal. Therefore, in order to repair the lattice damage and allow the implanted atoms to enter and activate the lattice points of the crystal, the substrate, including the shielding layer 50, needs to be heat-treated.

[0060] However, during the heat treatment process, due to the different coefficients of thermal expansion and contraction between the fin 20 and the shielding layer 50, the shape of the fin 20 will be affected when the temperature changes, which will further affect the performance of the obtained semiconductor device.

[0061] To address the above problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising:

[0062] A substrate is provided, the substrate including a substrate, discrete fins located on the substrate, and a shielding layer filling fin trenches between adjacent fins;

[0063] Using the shielding layer as a mask, ion implantation is performed on the fin to form a trap region;

[0064] Remove the first-height shielding layer to form a remaining shielding layer, the top surface of which is lower than the top surface of the fin;

[0065] The substrate, including the remaining shielding layer, is subjected to heat treatment.

[0066] In the semiconductor structure formation method provided by the embodiments of the present invention, since the first height of the shielding layer is removed before the substrate including the remaining shielding layer is heat-treated, the portion of the fin parallel to the removed shielding layer will not be affected by the internal stress of the previously parallel portion of the shielding layer during the heat treatment process. This can prevent the shape of this portion of the fin from warping and reduce the possibility of dislocation in the fin, thereby improving the performance of the obtained semiconductor device.

[0067] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. In the various drawings, the same elements are represented by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps can be depicted in one figure.

[0068] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.

[0069] In this application, the term "semiconductor structure" refers to the collective term for the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed. Many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the device, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without adhering to these specific details.

[0070] Unless otherwise specified below, the various parts of a semiconductor device may be made of materials known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as GaAs, InP, GaN, and SiC, and group IV semiconductors such as Si and Ge. The dielectric material may be made of silicon oxide or a material with a dielectric constant greater than silicon oxide, including, for example, other oxides, nitrides, oxynitrides, silicates, aluminates, and titanates.

[0071] For the specific steps of the semiconductor structure formation method provided in this embodiment of the invention, please refer to... Figures 5-10 , Figures 5-10 This is a schematic diagram of the steps in the semiconductor structure formation method provided in the embodiments of the present invention.

[0072] like Figures 5-8 As shown, a substrate is provided, the substrate including a substrate 10, discrete fins 20 located on the substrate 10, and a shielding layer 50 filling the fin trenches between adjacent fins 20.

[0073] The substrate can provide a processing foundation and support platform for the subsequent processing of semiconductor structures.

[0074] In one specific embodiment, in order to form the fin 20 and improve the quality of the obtained fin 20, an initial substrate can be provided first, and then a hard mask layer can be formed on the initial substrate. The hard mask layer is first etched to obtain a remaining hard mask layer 30, and then the remaining hard mask layer 30 is used as a mask for etching to obtain the fin 20 and the substrate 10 located below the fin 20.

[0075] Of course, in other embodiments, other processes can be used to form the fin 20. If other processes are used to form the fin 20, the remaining hard mask layer 30 may not be formed above the fin 20.

[0076] The substrate 10 and the fin 20 can be made of various semiconductor materials, such as GaAs, InP, GaN, and SiC in group III-V semiconductors, and Si, Ge in group IV semiconductors, and their compounds.

[0077] In order to protect the fin 20 when the shielding layer 50 at the first height is removed, a protective layer 60 may also be formed on the sidewall of the fin 20.

[0078] Therefore, as Figure 7 and Figure 8 As shown, in one specific embodiment, the substrate further includes a protective layer 60 that at least covers the sidewalls of the fin 20, and the shielding layer 50 fills the fin grooves between adjacent protective layers 60.

[0079] Of course, since the fin 20 needs to be exposed when the semiconductor structure is formed, a portion of the protective layer 60 needs to be removed. The specific steps will be explained later.

[0080] In order to facilitate the formation of the protective layer 60, such as Figure 6 and Figure 7 As shown, in one specific embodiment, the protective layer 60 also covers the surface of the substrate 10 between adjacent fins 20.

[0081] Since the protective layer 60 not only covers the sidewalls of the fin 20, but also the surface of the substrate 10 between adjacent fins 20, it is easy to form using a conformal covering method, without the need to subsequently remove other parts of the protective layer 60.

[0082] There are various methods for forming the protective layer 60. In one specific embodiment, the step of providing the substrate may include:

[0083] An initial substrate is provided to form a substrate 10 and discrete fins 20 located on the substrate 10;

[0084] A protective layer 60 is formed, which conformally covers the sidewalls of the fin 20 and the surface of the substrate 10 between adjacent fins 20.

[0085] The method for forming the protective layer 60 described above has fewer process steps and is less difficult, thereby reducing costs.

[0086] The protective layer 60 can also conformally cover the top surface of the fin 20, and the protective layer 60 conformally covering the top surface of the fin 20 can be removed in subsequent steps.

[0087] Of course, such as Figure 7 As shown, when a residual hard mask layer 30 is formed above the fin 20, the protective layer 60 is not formed directly on the top surface of the fin 20, but rather conformally covers the residual hard mask layer 30.

[0088] The protective layer 60 that conformally covers the remaining hard mask layer 30 can also be removed in subsequent processes.

[0089] Of course, the protective layer 60 may also cover the remaining hard mask layer 30 without conformal coverage.

[0090] In order to ensure that the protective layer 60 is not removed when the shielding layer 50 is removed to form the remaining shielding layer 51, in one specific embodiment, the material of the protective layer 60 may be different from the material of the shielding layer 50.

[0091] In this way, by selecting a material different from the shielding layer 50, it is ensured that the protective layer 60 is not removed when the shielding layer 50 is removed in the future. Thus, during the heat treatment process, the sidewall of the fin 20 is still covered with the protective layer 60, thereby maintaining the shape of the fin 20 and preventing the fin 20 from deforming.

[0092] To ensure that the protective layer 60 is not easily removed during the subsequent removal of the shielding layer 50 to form the remaining shielding layer 51, in this embodiment, the material of the protective layer 60 includes silicon nitride or silicon carbide. Silicon nitride or silicon carbide has high mechanical strength and is less likely to react with other substances suitable for removing the shielding layer 50, allowing the protective layer 60 to better maintain its shape during the removal of the shielding layer 50.

[0093] The processing technology of the protective layer 60 can be selected as needed. In one specific embodiment, the protective layer 60 is formed by plasma-assisted chemical vapor deposition (PCVD). PCVD has a relatively high deposition rate and requires a relatively low deposition temperature, making it less likely to deform the substrate. The resulting protective layer 60 has a relatively uniform composition and high forming quality.

[0094] When the protective layer 60 is too thick, it can hinder the formation and processing of the subsequent shielding layer 50; when the protective layer 60 is too thin, it is difficult to exert its protective function, and its formation is also more difficult. Therefore, in one specific embodiment, the thickness of the protective layer 60 is 50-100 angstroms. At this thickness, the formation of the protective layer 60 is less difficult, and its protective function is also better.

[0095] To improve the angle between the smooth fin 20 and the substrate 10, suppress edge leakage, and improve the surface properties of the fin 20 after etching, an isolation layer 40 can be formed on the sidewall of the fin 20 after etching and before forming the protective layer 60. Therefore, as... Figure 6 and Figure 7 As shown, in one specific embodiment, the substrate may further include an isolation layer 40 that at least covers the sidewalls of the fin 20, and the protective layer 60 covers the isolation layer 40.

[0096] Similarly, since the fins 20 need to be exposed when the semiconductor structure is formed, a portion of the isolation layer 40 needs to be removed. The specific steps will be explained later.

[0097] In order to facilitate the formation of the isolation layer 40, such as Figure 5 As shown, in one specific embodiment, the isolation layer 40 also covers the surface of the substrate 10 between adjacent fins 20.

[0098] Since the isolation layer 40 not only covers the sidewalls of the fin 20, but also the surface of the substrate 10 between adjacent fins 20, it is easy to form by conformal covering or oxidation, without the need to remove other parts of the isolation layer 40 later.

[0099] There are various methods for forming the isolation layer 40. In one specific embodiment, the step of providing the substrate includes:

[0100] The step of providing the substrate includes:

[0101] An initial substrate 10 is provided, and a substrate 10 and discrete fins 20 located on the substrate 10 are formed;

[0102] An isolation layer 40 is formed, which conformally covers the sidewalls of the fin 20 and the surface of the substrate 10 between adjacent fins 20;

[0103] A protective layer 60 is formed, which conformally covers the isolation layer 40.

[0104] The method for forming the isolation layer 40 and the protective layer 60 described above has simple process steps and relatively low process difficulty, thereby reducing costs.

[0105] like Figure 6 As shown, when a residual hard mask layer 30 is formed above the fin 20, the isolation layer 40 is not directly formed on the top surface of the fin 20. The isolation layer 40 does not conformally cover the residual hard mask layer 30. In this case, the protective layer 60 can be formed by selective deposition or by reacting with part of the isolation layer 40.

[0106] Of course, the isolation layer 40 can also conformally cover the remaining hard mask layer 30, and then the isolation layer 40 conformally covering the remaining hard mask layer 30 can be removed in subsequent processes.

[0107] The material of the isolation layer 40 can be selected as needed. In order to improve the function of the isolation layer 40 in smoothing the angle between the fin 20 and the substrate 10, suppressing edge leakage, and improving the surface characteristics of the fin 20 after etching, in one specific embodiment, the material of the isolation layer 40 can be silicon oxide. When the material of the isolation layer 40 is silicon oxide, the formation difficulty is relatively low and the formation process is relatively simple.

[0108] When the material of the isolation layer 40 is silicon oxide and the material of the fin 20 is silicon, in one specific embodiment, the process for forming the isolation layer 40 includes an in-situ vapor generation process. By using the in-situ vapor generation process to form the isolation layer 40, the thickness of the isolation layer 40 can be made more uniform, and the temperature can be raised and lowered quickly, reducing the heat treatment time.

[0109] The thickness of the isolation layer 40 can be set as needed. If the isolation layer 40 is too thick, it can hinder the formation and processing of the subsequent shielding layer 50 and protective layer 60; if the isolation layer 40 is too thin, it is difficult to effectively utilize its function of smoothing the angle between the fin 20 and the substrate 10, suppressing edge leakage, and improving the surface properties of the fin 20 after etching, and its formation is also more difficult. Therefore, in one specific embodiment, the thickness of the isolation layer 40 is 10 angstroms to 100 angstroms. At this thickness, the formation of the isolation layer 40 is less difficult, and the function of smoothing the angle between the fin 20 and the substrate 10, suppressing edge leakage, and improving the surface properties of the fin 20 after etching is also better.

[0110] like Figure 8 As shown, a shielding layer 50 is formed to fill the fin grooves between adjacent fins 20.

[0111] The shielding layer 50 is mainly used as a mask for ion implantation, and can also be used as a dielectric layer in a semiconductor structure to prevent leakage.

[0112] Since the shielding layer 50 is mainly used as a mask for ion implantation, the shielding layer 50 needs to expose the top surface of the fin 20.

[0113] The height of the top surface of the shielding layer 50 can be higher or lower than the top surface of the fin 20, or it can be flush with the top surface of the fin 20. When the height of the top surface of the shielding layer 50 is flush with the top surface of the fin 20, the ion implantation effect is better, the range of the resulting well region deviates less from the preset range, and the processing difficulty is also lower, requiring no etching.

[0114] Since it is difficult to make the directly filled shielding layer 50 flush with the top surface of the fin 20, an amount of shielding layer material exceeding the required amount can be filled, and then chemical mechanical polishing technology can be used to obtain... Figure 8 The structure of the shielding layer 50 is such that if the remaining hard masking layer 30 remains above the fin 20, the remaining hard masking layer 30 can be removed while removing the excess shielding layer material to expose the top surface of the fin 20.

[0115] The shielding layer 50 can be made of various materials, such as silicon oxide, silicon aluminum nitride, and other metallic materials. Since the remaining shielding layer 51 formed subsequently can act as a dielectric material, it provides a certain dielectric effect.

[0116] Please continue to refer to this. Figure 8 Using the shielding layer 50 as a mask, ion implantation is performed on the fin 20 to form a trap region (not shown in the figure).

[0117] The shielding layer 50 serves as a mask during ion implantation. During ion implantation, the shielding layer 50 has a strong blocking effect on ions, and the ions implanted into the shielding layer 50 will not enter the substrate 10 below the shielding layer 50. However, the blocking effect of the fin portion 20 is weak, and the ions implanted into the fin portion 20 enter the fin portion 20 or the substrate 10 below it.

[0118] like Figure 9 As shown, the first-height shielding layer 50 is removed to form a residual shielding layer 51, the top surface of which is lower than the top surface of the fin 20. Because the top surface of the residual shielding layer 51 is lower than the top surface of the fin 20, the influence of the internal stress of the shielding layer 50 on the fin 20 can be reduced in subsequent heat treatment steps, thus reducing the deformation of the fin 20 and improving the performance of the resulting semiconductor structure.

[0119] The first height can be less than or equal to the height of the shielding layer 50. However, in order to prevent the fin 20 from warping or dislocation in subsequent heat treatment steps, the top surface of the remaining shielding layer 51 is lower than the top surface of the fin 20.

[0120] When removing the shielding layer 50, either wet etching or dry etching processes can be used. When the protective layer 60 is present, the material selected for removing the shielding layer 50 using a wet etching process should not react with the protective layer 60.

[0121] Please continue to refer to this. Figure 9 The substrate, including the remaining shielding layer 51, is subjected to heat treatment.

[0122] The purpose of heat-treating the substrate, including the shielding layer 50, is to repair damage to the crystal lattice and to allow implanted atoms to enter and activate the crystal lattice points. The heat treatment process can be annealing or other heat treatment processes.

[0123] During the heat treatment process, the portion of the fin 20 parallel to the removed shielding layer 50 will not be affected by the internal stress of the portion of the shielding layer 50 that was previously parallel to it. This can prevent the shape of this portion of the fin 20 from warping and reduce the possibility of dislocation in the fin 20, thereby improving the performance of the obtained semiconductor device.

[0124] like Figure 10 As shown, when the protective layer 60 or the isolation layer 40 is present, the protective layer 60 or the isolation layer 40 above the top surface of the remaining shielding layer 51 is removed to expose the sidewall of the fin 20.

[0125] To facilitate further processing of the semiconductor structure, the protective layer 60 or isolation layer 40 above the top surface of the remaining shielding layer 51 needs to be removed to expose the sidewall of the fin 20.

[0126] The protective layer 60 or the isolation layer 40 can be removed by wet etching, but the selected process must not damage the fin 20.

[0127] The semiconductor structure provided in the embodiments of the present invention will be described below. The semiconductor structure described below can be considered as a semiconductor structure obtained by the semiconductor structure formation method provided in the embodiments of the present invention. The content of the semiconductor structure described below can be referred to in correspondence with the content of the semiconductor structure formation method described above.

[0128] Please continue to refer to this. Figure 9 The present invention also provides a semiconductor structure, comprising:

[0129] Substrate 10;

[0130] Discrete fins 20 are located on the substrate 10, and ion-implanted trap regions are formed in the fins 20;

[0131] The remaining shielding layer 51 fills the fin grooves between adjacent fins 20, and the top surface of the remaining shielding layer 51 is lower than the top surface of the fin 20.

[0132] In the semiconductor structure provided by the embodiments of the present invention, since the top surface of the remaining shielding layer 51 is lower than the top surface of the fin 20, during the heat treatment process, the portion of the fin 20 parallel to the removed shielding layer 50 will not be affected by the internal stress of the previously parallel portion of the shielding layer 50. This can prevent the shape of this portion of the fin 20 from warping and reduce the possibility of dislocations in the fin 20, thereby improving the performance of the obtained semiconductor device.

[0133] Optionally, in one embodiment, the semiconductor structure further includes a protective layer 60 that at least covers the sidewalls of the fin 20. The protective layer 60 can protect the fin 20 during the formation of the remaining shielding layer 51 and heat treatment, thus better maintaining the structure of the fin 20.

[0134] In one specific embodiment, the protective layer 60 also covers the surface of the substrate 10 between adjacent fins 20. Since the protective layer 60 covers not only the sidewalls of the fins 20 but also the surface of the substrate 10 between adjacent fins 20, it is easy to form using a conformal covering method, eliminating the need for subsequent removal of other parts of the protective layer 60.

[0135] In one specific embodiment, the protective layer 60 is made of silicon nitride or silicon carbide. Because silicon nitride or silicon carbide has high mechanical strength and is less likely to react with other suitable substances for removing the shielding layer 50, the protective layer 60 can better maintain its shape and protect the fin 20.

[0136] In one specific embodiment, the thickness of the protective layer 60 is 50-100 angstroms. In this case, the formation of the protective layer 60 is relatively easy, and the protective effect of the protective layer 60 is also relatively good.

[0137] In one specific embodiment, the protective layer 60 is formed by plasma-assisted chemical vapor deposition (PCVD). During PCVD, the deposition rate of the protective layer 60 is relatively high, and the required deposition temperature is relatively low, making it less likely to deform the substrate. Furthermore, the resulting protective layer 60 has a relatively uniform composition and high forming quality.

[0138] In one specific embodiment, the remaining shielding layer 51 is made of silicon oxide. Thus, the remaining shielding layer 51 can serve as a dielectric material, providing a certain dielectric effect.

[0139] In one embodiment, the substrate further includes an isolation layer 40 that at least covers the sidewalls of the fin 20, and the protective layer 60 covers the isolation layer 40. The isolation layer 40 can improve the smoothing of the angle between the fin 20 and the substrate 10, suppress edge leakage current, and improve the surface properties of the fin 20 after etching.

[0140] In one specific embodiment, the isolation layer 40 also covers the surface of the substrate 10 between adjacent fins 20. Since the isolation layer 40 covers not only the sidewalls of the fins 20 but also the surface of the substrate 10 between adjacent fins 20, it is easy to form using conformal covering or oxidation methods, without the need for subsequent removal of other parts of the isolation layer 40.

[0141] In one specific embodiment, the material of the isolation layer 40 includes silicon oxide. When the material of the isolation layer 40 is silicon oxide, it can improve the function of the isolation layer 40 in smoothing the angle between the fin 20 and the substrate 10, suppressing edge leakage current, and improving the surface properties of the fin 20 after etching.

[0142] In one specific embodiment, the process for forming the isolation layer 40 includes an on-site steam generation process. By using an on-site steam generation process to form the isolation layer 40, the thickness of the isolation layer 40 can be made more uniform, and the temperature can be rapidly increased and decreased, thereby reducing the heat treatment time.

[0143] In one specific embodiment, the thickness of the isolation layer 40 is 10 angstroms to 100 angstroms. In this case, the formation of the isolation layer 40 is relatively easy, and the angle between the smooth fin 20 and the substrate 10 of the isolation layer 40 also has a better function in suppressing edge leakage and improving the surface properties of the fin 20 after etching.

[0144] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is accorded the widest scope consistent with the principles and novel features disclosed herein.

[0145] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the embodiments of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, comprising: providing a substrate, the substrate comprising a substrate, discrete fins on the substrate, and a blocking layer filling fin trenches between adjacent fins; wherein the substrate further comprises an isolation layer covering at least sidewalls of the fins and a protective layer covering the isolation layer, the blocking layer filling fin trenches between adjacent protective layers; the material of the protective layer being different from the material of the blocking layer; performing ion implantation on the fins with the blocking layer as a mask to form a well region; removing the blocking layer of a first height to form a remaining blocking layer, a top surface of the remaining blocking layer being lower than a top surface of the fins; performing a thermal treatment on the substrate comprising the isolation layer, the protective layer, and the remaining blocking layer.

2. The method of forming a semiconductor structure of claim 1, wherein, the performing a thermal treatment on the substrate comprising the remaining blocking layer further comprises: removing the protective layer above the top surface of the remaining blocking layer to expose sidewalls of the fins.

3. The method of forming a semiconductor structure of claim 2, wherein, the protective layer further covers the substrate surface between adjacent fins.

4. The method of forming a semiconductor structure of claim 3, wherein, the providing a substrate comprises: providing an initial substrate to form a substrate and discrete fins on the substrate; forming a protective layer conformally covering sidewalls of the fins and the substrate surface between adjacent fins.

5. The method of forming a semiconductor structure of claim 1, wherein, the material of the protective layer comprises silicon nitride or silicon carbide.

6. The method of forming a semiconductor structure of claim 1, wherein, the thickness of the protective layer is 50 angstroms-100 angstroms.

7. The method of forming a semiconductor structure of claim 4, wherein, the process of forming the protective layer is a plasma assisted chemical vapor deposition process.

8. The method of forming a semiconductor structure of claim 1, wherein, a top surface of the blocking layer is flush with a top surface of the fins.

9. The method of forming a semiconductor structure of claim 1, wherein, the material of the blocking layer is silicon oxide.

10. The method of forming a semiconductor structure of claim 2, wherein, the removing the protective layer above the top surface of the remaining blocking layer to expose sidewalls of the fins further comprises: removing the protective layer and the isolation layer above the top surface of the remaining blocking layer to expose sidewalls of the fins.

11. The method of forming a semiconductor structure of claim 10, wherein, the isolation layer further covers the substrate surface between adjacent fins.

12. The method of forming a semiconductor structure of claim 11, wherein, the providing a substrate comprises: providing an initial substrate to form a substrate and discrete fins on the substrate; forming an isolation layer conformally covering sidewalls of the fins and the substrate surface between adjacent fins; forming a protective layer conformally covering the isolation layer.

13. The method of forming a semiconductor structure of claim 1, wherein, the material of the isolation layer comprises silicon oxide.

14. The method of forming a semiconductor structure of claim 13, wherein, the process of forming the isolation layer comprises an in-situ vapor generation process.

15. The method of forming a semiconductor structure of claim 14, wherein, the thickness of the isolation layer is 10 angstroms-100 angstroms.

16. A semiconductor structure, characterized by comprising: a substrate; discrete fins on the substrate, the fins having ion-implanted well regions formed therein; a remaining blocking layer filling fin trenches between adjacent fins, a top surface of the remaining blocking layer being lower than a top surface of the fins; an isolation layer covering at least sidewalls of the fins and a protective layer covering the isolation layer, the material of the protective layer being different from the material of the blocking layer.

17. The semiconductor structure of claim 16, wherein, the material of the protective layer comprises silicon nitride or silicon carbide.

18. The semiconductor structure of claim 16, wherein, the thickness of the protective layer is 50 angstroms-100 angstroms.

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