Thin film transistor and method of manufacturing the same

Abstract

The application provides a thin film transistor and a manufacturing method thereof, which comprises the following steps: providing a substrate; forming a buffer layer on the substrate; forming a first metal layer on the surface of the buffer layer and performing a patterning process on the first metal layer to form a gate electrode; forming a gate insulating layer on the gate electrode; forming an active layer on the gate insulating layer, wherein the active layer comprises an undoped amorphous silicon layer and an amorphous silicon doped layer on the undoped amorphous silicon layer; performing dehydrogenation and crystallization processes on partial areas of the active layer to generate a single crystal silicon layer corresponding to the position of the gate electrode, wherein the area of the single crystal silicon layer is defined as a channel region, and the areas on both sides of the channel region are source contact regions and drain contact regions; and forming a source electrode on the surface of the source contact region and a drain electrode on the surface of the drain contact region.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a thin film transistor manufacturing method and a thin film transistor manufactured by the method. BACKGROUND

[0002] Flexible Organic Light Emitting Diode (OLED) display technology is an important direction of future display development, and has been widely used in many fields. At present, the thin film transistor device in flexible OLED display mostly adopts Low Temperature Poly Silicon technology (LTPS), although the mobility can be greatly improved, but the device needs to adopt a top gate structure, the process is complex, and the preparation cost is high. At the same time, since the polycrystalline silicon thin film transistor contains many grain boundaries, in the application of flexible display, after bending for many times, film layer cracks are easy to produce, which affects the product life.

[0003] Therefore, the prior art has defects and needs to be solved urgently. SUMMARY

[0004] The present application provides a thin film transistor manufacturing method and a thin film transistor, which can solve the problem that flexible display devices are not easy to produce film layer cracks after bending for many times.

[0005] To solve the above problems, the technical scheme provided by the present application is as follows:

[0006] A thin film transistor manufacturing method, comprising:

[0007] providing a substrate;

[0008] forming a buffer layer on the substrate;

[0009] forming a first metal layer on the surface of the buffer layer and patterning the first metal layer to form a gate electrode;

[0010] forming a gate insulating layer on the gate electrode;

[0011] forming an active layer on the gate insulating layer, the active layer comprising an undoped amorphous silicon layer and an amorphous silicon doped layer on the undoped amorphous silicon layer;

[0012] dehydrogenating and crystallizing part of the undoped amorphous silicon layer and the amorphous silicon doped layer of the active layer to generate a single crystal silicon layer corresponding to the position of the gate electrode; or dehydrogenating and crystallizing part of the undoped amorphous silicon layer of the active layer to generate a single crystal silicon layer corresponding to the position of the gate electrode;

[0013] forming a metal layer on the surface of the active layer;

[0014] etching the metal layer to form a source and a drain, and a channel region between the source and the drain; and

[0015] depositing a passivation layer on the source, the drain and the channel region.

[0016] In some embodiments of the present application, the active layer comprises an undoped amorphous silicon layer on the surface of the gate insulating layer and an amorphous silicon doped layer on the undoped amorphous silicon layer, the amorphous silicon doped layer comprising two layers of different concentration doped layers.

[0017] In some embodiments of the present application, the step of forming the active layer on the gate insulating layer comprises: first depositing an undoped amorphous silicon layer on the surface of the gate insulating layer and then depositing an amorphous silicon doped layer on the undoped amorphous silicon layer and a single crystal silicon layer generated by dehydrogenation and crystallization treatment of a local region of the active layer corresponding to the position of the gate electrode, the amorphous silicon doped layer comprising two layers of different concentration doped layers.

[0018] In some embodiments of the present application, the method of dehydrogenation and crystallization treatment of the active layer to generate the single crystal silicon layer corresponding to the position of the gate electrode comprises providing a semiconductor solid-state laser, and irradiating the region of the active layer corresponding to the position of the gate electrode with a laser beam of a preset energy value emitted by the semiconductor solid-state laser.

[0019] In some embodiments of the present application, the gate electrodes formed on the surface of the buffer layer are arranged in an array, and the provided semiconductor solid-state laser comprises a plurality of laser light sources arranged in an array at intervals, and the interval between adjacent laser light sources is equal to the interval between the centers of adjacent gate electrodes.

[0020] In some embodiments of the present application, the preset energy value of the laser beam emitted by the laser light source is greater than 400 KW / cm 2 .

[0021] In some embodiments of the present application, the thickness of the active layer is between 30 nm and 100 nm.

[0022] A thin film transistor comprises:

[0023] a substrate;

[0024] a buffer layer provided on the substrate;

[0025] a gate electrode provided on the buffer layer;

[0026] a gate insulating layer provided on the buffer layer and the gate electrode;

[0027] an active layer disposed on the gate insulating layer, the active layer comprising a channel region corresponding to the gate electrode and a source contact region and a drain contact region located on both sides of the channel region, wherein a portion of the active layer located at the channel region comprises a monocrystalline silicon layer, and a portion of the active layer located at the source contact region and the drain contact region each comprises an amorphous silicon doped layer disposed on the surface of the gate insulating layer, and the monocrystalline silicon layer of the channel region is connected to the end of the amorphous silicon doped layer of the source contact region and the drain contact region or the amorphous silicon doped layer of the source contact region and the drain contact region is disposed on the monocrystalline silicon layer at both ends of the channel region.

[0028] a source electrode disposed on the source contact region and a drain electrode disposed on the drain contact region, and

[0029] a passivation layer disposed on the gate insulating layer.

[0030] In some embodiments of the present application, the source contact region and the drain contact region comprise an amorphous silicon layer disposed on the surface of the gate insulating layer, the amorphous silicon doped layer is disposed on the surface of the amorphous silicon layer, and the monocrystalline silicon layer of the channel region is connected to the end of the amorphous silicon doped layer of the source contact region and the drain contact region or the amorphous silicon doped layer of the source contact region and the drain contact region is disposed on the monocrystalline silicon layer at both ends of the channel region.

[0031] In some embodiments of the present application, the thickness of the monocrystalline silicon layer is between 30 nm and 100 nm.

[0032] The thin film transistor manufacturing method and the thin film transistor formed by the method provided by the present application are characterized in that a monocrystalline silicon layer corresponding to the position of the gate electrode is generated by dehydrogenation and crystallization treatment of a partial region of the active layer to form a monocrystalline silicon thin film transistor. Compared with the polycrystalline silicon thin film transistor formed by quasi-molecular laser irradiation in the prior art, the monocrystalline silicon thin film transistor has no grain boundary, so that no film layer cracks are generated after the monocrystalline silicon thin film transistor is repeatedly bent, and the quality of the flexible display panel is improved. BRIEF DESCRIPTION OF DRAWINGS

[0033] The technical solutions and other beneficial effects of the present application will become apparent through the following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings.

[0034] Figure 1 A cross-sectional schematic view of a substrate and a first metal layer formed on the substrate according to the first embodiment of the present application.

[0035] Figure 2 A cross-sectional schematic view of the first metal layer on the substrate being formed into a gate electrode. Figure 1

[0036] A cross-sectional schematic view of the first metal layer on the substrate being formed into a gate electrode.Figure 3 Fig. 1 is a schematic diagram of a thin film transistor according to the present application. Figure 2 Fig. 2 is a schematic diagram of a cross section of a gate electrode and a buffer layer of the thin film transistor of Fig. 1.

[0037] Figure 4 Fig. 3 is a schematic diagram of a cross section of a gate insulating layer formed on a surface of the gate electrode and the buffer layer of Fig. 2, and an undoped amorphous silicon layer and an amorphous silicon doped layer formed on the gate insulating layer. Figure 3 Fig. 4 is a schematic diagram of a cross section of a semiconductor solid laser irradiating a laser beam on a local region of the undoped amorphous silicon layer and the amorphous silicon doped layer of Fig. 3 to perform dehydrogenation and crystallization.

[0038] Figure 5 Fig. 5 is a schematic diagram of a cross section of a semiconductor solid laser crystallizing a channel region corresponding to one of the gate electrodes.

[0039] Figure 6 Fig. 6 is a schematic diagram of a cross section of a second metal layer formed on surfaces of a source contact region, a drain contact region and the channel region on the basis of Fig. 5. Figure 5 Fig. 7 is a schematic diagram of a cross section of a semiconductor solid laser irradiating a laser beam on the second metal layer of Fig. 6 to form a source and a drain.

[0040] Figure 7 Fig. 8 is a schematic diagram of a cross section of a semiconductor solid laser irradiating a laser beam on the second metal layer of Fig. 7 to form the source and the drain. Figure 6 Fig. 9 is a schematic diagram of a cross section of a passivation layer formed on surfaces of the source and the drain on the basis of Fig. 8.

[0041] Figure 8 Fig. 10 is a schematic diagram of a cross section of a via hole formed in the passivation layer. Figure 7 Fig. 11 is a schematic diagram of a cross section of a thin film transistor obtained by removing a glass substrate on the basis of Fig. 10.

[0042] Figure 9 Fig. 12 is a schematic diagram of a thin film transistor provided by a second embodiment of the present application.

[0043] Figure 10 Fig. 13 is a schematic diagram of a cross section of a thin film transistor obtained by removing a glass substrate on the basis of Fig. 12. Figure 9 Fig. 14 is a schematic diagram of a thin film transistor provided by a third embodiment of the present application.

[0044] Figure 11 Fig. 15 is a schematic diagram of a cross section of a thin film transistor obtained by removing a glass substrate on the basis of Fig. 14.

[0045] BRIEF DESCRIPTION OF DRAWINGS

[0046] 100, 200 - thin film transistor; 1 - substrate; 10 - glass substrate;

[0047] 12 - semiconductor solid laser; 120 - laser light source; 53 - first lightly doped layer;

[0048] 54 - second heavily doped layer; 2 - buffer layer; 30 - first metal layer;

[0049] 3 - gate electrode; 4 - gate insulating layer; 122 - laser beam;

[0050] 40 - oxide layer of silicon; 42 - nitride layer of silicon; 5 - active layer; 50 - un-doped amorphous silicon layer;

[0051] 52 - amorphous silicon doped layer; 6 - monocrystalline silicon layer; 501 - channel region; 503 - source contact region;

[0052] 505 - drain contact region; 7 - second metal layer; 8 - passivation layer; 80 - via; 71 - source; 72 - drain. DETAILED DESCRIPTION

[0053] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0054] In the description of the present application, it should be understood that the terms "longitudinal", "transverse", "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0055] The present application can repeatedly refer to numbers and / or letters in different examples, and such repetition is for the purpose of simplification and clarity, and in itself does not indicate the relationship between the various embodiments and / or arrangements discussed. The thin film transistor and the manufacturing method thereof of the present application will be described in detail below in combination with specific embodiments.

[0056] Please refer to Figures 1-9 , Figures 1-9 A manufacturing method of a thin film transistor 100 provided for a first embodiment of the present application includes the following steps:

[0057] S1: Please refer to Figure 1 , a substrate 1 is provided; in the present embodiment, the substrate 1 is preferably a flexible polyimide (PI, Polyimide) substrate 1. The substrate 1 is formed on a glass substrate 10.

[0058] S2: Please continue to refer to Figure 1 A buffer layer 2 is formed on the substrate 1; the buffer layer 2 is used to buffer the damage of the substrate 1 caused by the high temperature of crystallization in the preparation process of the thin film transistor 100. The buffer layer 2 is made of insulating material, for example, the material of the buffer layer 2 can include any one of single layer film formed by silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3) and the like or composite film layer formed by any multiple.

[0059] S3: Please refer to Figure 2 and Figure 4 A first metal layer 30 is formed on the surface of the buffer layer 2 and the first metal layer 30 is subjected to patterning treatment to form a gate electrode 3. The gate electrode 3 is arranged in an array. The material of the first metal layer 30 can be metal or alloy, and the metal or alloy layer can be formed by at least two of metal molybdenum (Mo), metal aluminum (Al), metal copper (Cu), metal tungsten (W) or an alloy of metal molybdenum (Mo), metal aluminum (Al), metal copper (Cu), metal tungsten (W). Preferably, the material of the first metal layer 30 is Mo.

[0060] S4: Please refer to Figure 3 A gate insulating layer 4 is formed on the buffer layer 2 and the gate electrode 3. The material of the gate insulating layer 4 is not limited in the present application, for example, it can be a silicon oxide layer 40 (SiOx), a silicon nitride layer 42 (SiNx), a silicon oxynitride layer (SiON) and the like. Preferably, the gate insulating layer 4 includes a silicon nitride layer 42 disposed on the buffer layer 2 and a silicon oxide layer 40 disposed on the silicon nitride layer 42. The silicon nitride layer 42 has a large dielectric constant and good insulation effect; the silicon oxide layer 40 acts as a barrier layer to prevent hydrogen ions in the silicon nitride layer 42 from diffusing to the active layer 5 during dehydrogenation.

[0061] S5: Please continue to refer to Figure 3 An active layer 5 is formed on the gate insulating layer 4, and the active layer 5 includes an undoped amorphous silicon layer 50 and an amorphous silicon doped layer 52 disposed on the undoped amorphous silicon layer 50. In the present embodiment, the thickness of the active layer 5 is between 30 nm and 100 nm. Within this thickness range, it is beneficial for the active layer 5 to include the undoped amorphous silicon layer 50 and the amorphous silicon doped layer 52 in the region corresponding to the position of the gate electrode 3 to be annealed to form a single crystal silicon layer 6 during subsequent crystallization. The amorphous silicon doped layer 52 can be an n-type or p-type doped semiconductor layer, which is not limited herein.

[0062] In the present embodiment, please refer to Figure 4The amorphous silicon doped layer 52 includes at least two doped layers with different concentrations. In the basic embodiment, the amorphous silicon doped layer 52 includes a first lightly doped layer 53 and a second heavily doped layer 54. In other embodiments, a multi-concentration gradient semiconductor composite layer (e.g., a first N-type heavily doped amorphous silicon layer, a first N-type lightly doped amorphous silicon layer, a second N-type heavily doped amorphous silicon layer, and a second N-type lightly doped amorphous silicon layer) can be used instead of the original single doped layer to increase the energy barrier between the source / drain and the semiconductor composite layer, to increase the potential barrier for hole transport, and to reduce the leakage current of the back channel in the switching device.

[0063] S6: Please continue to refer to Figures 4-5 , Figure 4 A schematic diagram of dehydrogenation and crystallization of the non-doped amorphous silicon layer and the local region of the amorphous silicon doped layer on the substrate 1 by using a semiconductor solid laser to irradiate a laser beam; Figure 5 A schematic diagram of dehydrogenation and crystallization of the active layer at a position corresponding to one of the gate electrodes 3 by using a semiconductor solid laser. After dehydrogenation and crystallization of the partial region of the active layer 5, a single crystal silicon layer 6 corresponding to the position of the gate electrode 3 is generated.

[0064] In this embodiment, the semiconductor solid laser 12 emits a laser beam 122 with a preset energy value to irradiate and dehydrogenate the region of the active layer 5 corresponding to the position of the gate electrode 3. The semiconductor solid laser 12 includes a plurality of laser light sources 120 arranged in an array with a spacing equal to the spacing between the centers of adjacent gate electrodes 3. That is, only the region irradiated by the laser light source 120 is dehydrogenated and crystallized, so that the dehydrogenation and crystallization of the local region of the active layer 5 are achieved. When dehydrogenating, the preset energy value of the laser beam 122 emitted by the laser light source 120 is less than 50 kW / cm 2 . Preferably, the energy value of the laser beam 122 is between 10 kW / cm 2 and 50 kW / cm 2 . The number of laser light sources 120 can be set according to the size of the thin film transistor substrate. For example, the semiconductor solid laser 12 includes 1000 laser light sources 120 arranged in an array, so that the crystallization of the active layer of 1000 channel regions can be achieved by one-time irradiation of the 1000 laser light sources 120.

[0065] When crystallizing, the preset energy value of the laser beam 122 emitted by the laser light source 120 is greater than 400 kW / cm 2 . In this embodiment, the thickness of the active layer 5 is between 30 nm and 100 nm. The thickness of the active layer 5 is within this range, and the energy of the laser beam 122 emitted by the laser beam 122 is greater than 400 kW / cm2 Since the energy of the laser beam 122 emitted by the semiconductor solid laser 12 is greater than the energy of the existing excimer laser beam, the laser beam 122 can be quickly collimated to be incident to the predetermined region of the active layer 5, so that the local region of the active layer 5 corresponding to each gate electrode 3 reaches the annealing temperature to generate the single crystal silicon layer 6, so that the material of the channel region 501 of the thin film transistor 100 is single crystal silicon. Since the scanning speed of the laser beam 122 emitted by the semiconductor solid laser 12 reaches 800 mm / s, the crystallization time is very fast, so the crystallization time is also saved, and the cost is reduced.

[0066] In the present embodiment, both dehydrogenation and crystallization are protected by nitrogen, vacuum or rare gas.

[0067] S7: Please refer to Figures 6-7 The second metal layer 7 is formed on the surface of the active layer 5 by a physical vapor deposition (PVD) process, and the second metal layer 7 is patterned to form the source electrode 71 and the drain electrode 72, and the region between the source electrode 71 and the drain electrode 72 is the channel region 501. Therefore, the part of the active layer 5 in the channel region 501 includes the single crystal silicon layer 6, and the part of the active layer 5 in the source contact region 503 and the drain contact region 505 includes the undoped amorphous silicon layer 50 on the surface of the gate insulating layer 4 and the amorphous silicon doped layer 52 on the undoped amorphous silicon layer 50. The material of the second metal layer 7 includes but is not limited to one or more of Al, Mo, Cu, Ag, Cr, Ti, AlNi, MoTi and other metal materials. Preferably, the material of the second metal layer 7 can be Mo / Al / Mo laminated composite material, which not only meets the low resistance characteristics of the source electrode 71 and the drain electrode 72, but also prevents the source electrode 71 and the drain electrode 72 from being oxidized by water vapor.

[0068] S8: Please refer to Figure 8 A passivation layer 8 is deposited on the source electrode 71, the drain electrode 72 and the channel region 501. The passivation layer 8 usually needs to use inorganic insulating materials such as SiOx, SiNx, SiOxNy, Al2O3, TiOx, Y2O3, etc. At the same time, in the field of AMOLED, in order to make the subsequent OLED preparation conditions more excellent, organic insulating layers such as resin materials and acrylic materials can also be used.

[0069] S9: Please refer to Figure 9 Via holes 80 are formed in the passivation layer 8 by etching process, and the via holes 80 are used for electrical connection between the subsequent pixel electrode and the drain electrode 72.

[0070] S10: Please refer to Figure 10 The glass substrate 10 is removed by laser stripping technology to obtain the thin film transistor 100.

[0071] Please continue to refer to Figure 10 The present application also relates to a thin film transistor 100, comprising a substrate 1, a buffer layer 2 disposed on the substrate 1, a gate electrode 3 disposed on the buffer layer 2, a gate insulating layer 4 disposed on the buffer layer 2 and the gate electrode 3, an active layer 5 disposed on the gate insulating layer 4, a source electrode 71 and a drain electrode 72 disposed on the active layer 5, and a passivation layer 8 disposed on the source electrode 71 and the drain electrode 72, wherein a via hole 80 is formed in the passivation layer 8.

[0072] In the present embodiment, the active layer 5 comprises a channel region 501 corresponding to the gate electrode 3, and a source contact region 503 and a drain contact region 505 located on both sides of the channel region 501, wherein the part of the active layer 5 located in the channel region 501 comprises a single crystal silicon layer 6, the part of the active layer 5 located in the source contact region 503 and the drain contact region 505 each comprises an undoped amorphous silicon layer 50 disposed on the surface of the gate insulating layer 4 and an amorphous silicon doped layer 52 disposed on the undoped amorphous silicon layer 50, and the single crystal silicon layer 6 is connected to the amorphous silicon doped layer 52 located in the source contact region 503 and the drain contact region 505; the source electrode 71 is disposed on the source contact region 503, and the drain electrode 72 is disposed on the drain contact region 505.

[0073] The single crystal silicon layer 6 of the channel region 501 is connected to the end of the amorphous silicon doped layer 52 of the source contact region 503 and the drain contact region 505. The thickness of the single crystal silicon layer 6 is between 30 nm and 100 nm.

[0074] Please refer to Figure 11 , Figure 11A thin film transistor 200 is provided in the second embodiment of the present application. The thin film transistor 200 provided in the second embodiment has substantially the same structure as the thin film transistor 100 provided in the first embodiment, and the difference is that the amorphous silicon doped layer 52 located at the source contact region 503 and the amorphous silicon doped layer 52 located at the drain contact region 505 both cover the surface of the monocrystalline silicon layer 6 located at both ends of the channel region 501. This is because the amorphous silicon doped layer 52 is formed after the dehydrogenation and crystallization treatment of the undoped amorphous silicon layer 50, that is, in the manufacturing process of the thin film transistor 200, the deposited undoped amorphous silicon layer 50 is first subjected to dehydrogenation and crystallization treatment to form a monocrystalline silicon layer 6, then the amorphous silicon doped layer 52 is deposited on the surface of the monocrystalline silicon layer 6 and the undoped amorphous silicon layer 50, and finally the amorphous silicon doped layer 52 is etched at the position corresponding to the gate electrode 3 to form the channel region 501. Because the thickness of the active layer to be crystallized cannot be too thick, otherwise it is difficult to form a monocrystalline silicon layer in the local region during crystallization, in this embodiment, the thickness of the undoped amorphous silicon layer 50 is in the range of 30nm to 100nm, and preferably 50nm.

[0075] In summary, the present application forms a bottom-gate type monocrystalline silicon thin film transistor by locally irradiating the amorphous silicon layer with laser to remove hydrogen and crystallize the local region through BLDA (Blue Laser Diode Annealing) local laser crystallization technology. Compared with the low-temperature polycrystalline silicon thin film transistor formed by irradiating with excimer laser in the prior art, which contains many grain boundary bends and is prone to cracking, the present application forms a monocrystalline silicon thin film transistor, which does not have grain boundaries, so that the monocrystalline silicon thin film transistor will not produce film layer cracks after multiple bending, thereby improving the quality of the flexible display panel.

[0076] In summary, although the present application has been disclosed with preferred embodiments as above, the above preferred embodiments are not intended to limit the present application, and those skilled in the art can make various modifications and improvements without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application is defined by the scope of the claims.

Claims

1. A method for manufacturing a thin film transistor, characterized in that: include: providing a substrate; forming a buffer layer on the substrate; forming a first metal layer on the surface of the buffer layer and patterning the first metal layer to form a gate electrode; forming a gate insulating layer on the gate electrode; forming an active layer on the gate insulating layer, wherein the active layer comprises an undoped amorphous silicon layer and an amorphous silicon doped layer located on the undoped amorphous silicon layer; Dehydrogenation and crystallization are performed on the undoped amorphous silicon layer and the partial region of the amorphous silicon doped layer of the active layer to generate a single crystal silicon layer corresponding to the position of the gate electrode; the amorphous silicon doped layer is formed before the step of generating the single crystal silicon layer; forming a metal layer on the surface of the active layer; Etching the metal layer to form a source electrode and a drain electrode, wherein the area between the source electrode and the drain electrode is a channel region; and Depositing a passivation layer on the source, drain and channel region; The step of generating the single crystal silicon layer further comprises: providing a semiconductor solid laser, using the semiconductor solid laser to emit a laser beam with a preset energy value to irradiate the area of ​​the active layer corresponding to the position of the gate electrode; during dehydrogenation, the preset energy value of the laser beam emitted by the semiconductor solid laser is less than 50KW / cm 2 During crystallization, the preset energy value of the laser beam emitted by the semiconductor solid laser is greater than 400KW / cm 2 .

2. The method for manufacturing a thin film transistor according to claim 1, wherein: The amorphous silicon doping layer includes at least two doping layers with different doping concentrations.

3. The method for manufacturing a thin film transistor according to claim 1, wherein: The gate electrodes formed on the surface of the buffer layer are arranged in an array. The provided semiconductor solid-state laser includes a plurality of laser light sources that are spaced apart and arranged in an array. The spacing between adjacent laser light sources is equal to the spacing between the centers of adjacent gate electrodes.

4. The method for manufacturing a thin film transistor according to claim 3, wherein: The thickness of the active layer used for dehydrogenation and crystallization is between 30 nm and 100 nm.

5. A thin film transistor, characterized in that: include: substrate; a buffer layer disposed on the substrate; a gate electrode disposed on the buffer layer; a gate insulating layer disposed on the buffer layer and the gate electrode; an active layer disposed on the gate insulating layer, the active layer comprising a channel region corresponding to the gate electrode and a source contact region and a drain contact region located on both sides of the channel region, wherein the portion of the active layer located in the channel region comprises a single crystal silicon layer, and the portions of the active layer located in the source contact region and the drain contact region each comprise an undoped amorphous silicon layer disposed on a surface of the gate insulating layer and an amorphous silicon doped layer disposed on the undoped amorphous silicon layer, and the single crystal silicon layer in the channel region is connected to ends of the amorphous silicon doped layers in the source contact region and the drain contact region; a source electrode provided on the source contact region and a drain electrode provided on the drain contact region, and A passivation layer is provided on the gate insulating layer.

6. The thin film transistor according to claim 5, wherein The thickness of the single crystal silicon layer is between 30 nm and 100 nm.

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