A method for manufacturing a semiconductor device and a semiconductor device

Abstract

This invention provides a method for fabricating a semiconductor device and the semiconductor device itself. The method includes: forming a contact structure on a semiconductor substrate, the contact structure being electrically connected to a capacitor; forming an etch stop layer above the contact structure; forming a stack of a sacrificial layer and a support layer above the etch stop layer; each of the sacrificial layer and the support layer comprising at least one layer; performing ion implantation on the support layer after each formation of the support layer, and annealing the ion-implanted support layer; forming a hard mask layer above the topmost support layer; implanting ions into the support layer to release the stress between Si-O bonds through ion collisions, thereby removing residual film pressure in the support layer; and annealing the support layer to form a highly dense film, preventing bending, cracking, or lifting of the capacitor electrodes in the semiconductor device. This eliminates the need to adjust the deposition conditions of the support layer or reduce the process window of the support layer, ensuring the stability of the fabrication process and the overall performance of the semiconductor device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor fabrication technology, and particularly relates to a method for fabricating a semiconductor device and the semiconductor device itself. Background Technology

[0002] In the fabrication of semiconductor devices, to increase the capacitance of semiconductor devices, it is generally achieved by using materials with a large dielectric constant or by increasing the effective area of ​​the capacitor electrodes.

[0003] To increase the effective area of ​​capacitor electrodes, the height of the capacitor column structure is usually increased, and then the capacitor column structure is supported by a superimposed support layer. However, while increasing the height, it is easy to cause the electrodes to bend, crack, or lift up.

[0004] In order to overcome the above problems, the existing technology generally prepares a support layer that meets the stress and density requirements by reducing the process window of the capacitor preparation process. That is, the process parameters in each process must be very strict to achieve this. Although this can reduce the phenomenon of electrode bending, cracking or lifting, the process stability cannot be guaranteed due to the reduction of the process window. Summary of the Invention

[0005] To address the problems existing in the prior art, this invention provides a method for fabricating a semiconductor device and a semiconductor device in order to solve the technical problem in the prior art where, in order to increase the capacitance of a semiconductor device by expanding the effective area of ​​the capacitor electrode, it is necessary to strictly limit the process windows of each process to avoid phenomena such as bending, cracking or lifting of the capacitor electrode. This results in the inability to ensure the stability of the fabrication process, which in turn affects the overall performance of the semiconductor device.

[0006] This invention provides a method for fabricating a semiconductor device, the method comprising:

[0007] A semiconductor substrate is provided, on which a contact structure is formed, the contact structure being electrically connected to a capacitor;

[0008] An etching stop layer is formed above the contact structure;

[0009] A sacrificial layer and a support layer are sequentially formed above the etching stop layer; each of the sacrificial layer and the support layer includes at least one layer, and the sacrificial layer and the support layer are stacked in an interleaved manner.

[0010] In this process, after each formation of the support layer, the support layer is ion implanted, and the ion-implanted support layer is then annealed.

[0011] A hard mask layer is formed above the topmost support layer.

[0012] Optionally, the stack of sacrificial layer and support layer sequentially formed above the etch stop layer includes:

[0013] The sacrificial layer is formed above the etching stop layer using LPCVD, PECVD, or spin coating processes.

[0014] The support layer is formed on top of the sacrificial layer using the LPCVD process, the PECVD process, the PVD process, or the ALD process; wherein both the sacrificial layer and the support layer include at least one layer.

[0015] Optionally, the material of the support layer is SiN, SiBN, SiCN, or SiON.

[0016] Optionally, the step of performing ion implantation on the support layer after each formation of the support layer includes:

[0017] At least one of Ar, H, He, N, O, C, Si and B ions is implanted into the support layer formed each time.

[0018] Optionally, the annealing treatment of the support layer after ion implantation includes:

[0019] The support layer after ion implantation is annealed using furnace tube annealing, rapid thermal annealing (RTP), or laser annealing; wherein the annealing temperature is 600–1100°C.

[0020] Optionally, the material of the etching stop layer is SiN, SiBN, or SiCN.

[0021] Optionally, the hard mask layer is a composite layer formed of a dielectric and a disposable polymer; wherein the dielectric includes at least one of SiO2, SiN, polycrystalline silicon, and SiON; and the disposable polymer includes at least one of photoresist, amorphous carbon layer ACL, and spin hard mask SOH.

[0022] Optionally, the semiconductor device is a dynamic memory; the method further includes: patterning the hard mask layer; using the patterned hard mask layer as a mask, etching the stacked layers to form capacitor holes and exposing the contact structure.

[0023] Optionally, a lower electrode, a capacitor dielectric layer, and an upper electrode are formed within the capacitor hole.

[0024] Optionally, the semiconductor substrate includes a buried channel transistor, one of the source / drain regions of the transistor being in contact with a bit line, and the other source / drain region being electrically connected to the contact structure.

[0025] The present invention also provides a semiconductor device, the semiconductor device comprising:

[0026] Semiconductor substrate;

[0027] Contact structures located on the semiconductor substrate;

[0028] A capacitor electrically connected to the contact structure, the capacitor comprising a lower electrode, a dielectric layer, and an upper electrode;

[0029] The lower electrode includes a support structure, which is subjected to ion implantation and annealing treatment in sequence. The implanted ions include at least one of Ar, H, He, N, O, C, Si and B ions. The support structure includes at least one support layer.

[0030] Optionally, the material of the support layer is SiN, SiBN, SiCN, or SiON.

[0031] Optionally, the support structure may further include at least one or more combinations of Ar, H, and He ions.

[0032] This invention provides a method for fabricating a semiconductor device and the semiconductor device itself. The method includes: providing a semiconductor substrate, on which a contact structure is formed, the contact structure being electrically connected to a capacitor; forming an etch stop layer above the contact structure; and sequentially forming a stack of a sacrificial layer and a support layer above the etch stop layer; each of the sacrificial layer and the support layer comprises at least one layer, and the sacrificial layer and the support layer are staggered; wherein, after each formation of the support layer, ion implantation is performed on the support layer, and the ion-implanted support layer is annealed; the topmost support layer... A hard mask layer is formed on top. Then, by injecting ions into the support layer, the Si-O network can be broken through ion collisions, releasing the stress between Si-O bonds and removing residual film pressure from the support layer. Next, the support layer is annealed to form a highly dense film, ensuring suitable tensile stress and preventing bending, cracking, or lifting of the capacitor electrodes in the semiconductor device. Furthermore, this method does not require adjusting the deposition conditions of the support layer, i.e., it does not require reducing the process window of the support layer, thus ensuring the stability of the fabrication process and consequently the overall performance of the semiconductor device. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0034] Figure 2 This is a cross-sectional schematic diagram of a semiconductor device when both the sacrificial layer and the support layer are two layers, provided as an embodiment of the present invention during the fabrication of the semiconductor device.

[0035] Figure 3 This invention provides another cross-sectional view of the semiconductor device after its fabrication is completed, as part of an embodiment of the invention. Detailed Implementation

[0036] To address the technical problem in existing technologies where increasing the effective area of ​​capacitor electrodes to increase the capacitance of semiconductor devices requires strict control of process windows to prevent bending, cracking, or lifting of the capacitor electrodes, which leads to compromised process stability and affects the overall performance of the semiconductor device, this invention provides a method for fabricating a semiconductor device and the semiconductor device itself.

[0037] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0038] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0039] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0040] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] This embodiment provides a method for fabricating a semiconductor device, which can be a dynamic memory, and the molding structure of the MIM capacitor in the semiconductor device can be 20nm or less. The following will be discussed in conjunction with the appendix. Figure 1-3 The embodiments of the present invention will be described in detail below.

[0042] ,refer to Figure 1 First, a semiconductor substrate is provided. A buried channel transistor is formed on the semiconductor substrate, including staggered, inclined strip-shaped active regions 101 and gate lines 102 (word lines) located within the substrate; the gate lines 102 and the active regions 101 constitute the transistor. A portion of the active regions 101 located on both sides of the gate contacts the bit line 103, and the other portion leads out to a memory node contact portion 104, on which a contact structure for connection to the capacitor to be formed is formed; this contact structure is also called a landing pad.

[0043] Next, an etch stop layer is formed above the contact structure.

[0044] For reference Figure 2 First, an etch stop layer 201 can be formed above the contact structure by depositing SiN, SiBN, SiCN or other nitride materials; that is, the material of the etch stop layer is SiN, SiBN or SiCN.

[0045] Then, a sacrificial layer and a support layer are formed above the etch stop layer 201; the sacrificial layer and the support layer are in a cross-stacked relationship, and each of the sacrificial layer and the support layer includes at least one layer. Among them, the oxide layer can be used as the sacrificial layer, and the oxide layer can be formed by growing SiH4, TEOS or SOD; the material of the support layer can be SiN, SiBN, SiCN, SiON or other nitriding media.

[0046] For example, continue to refer to Figure 2 If both the sacrificial layer and the support layer are two layers, then a first sacrificial layer 202, a first support layer 203, a second sacrificial layer 204, and a second support layer 205 will be formed sequentially above the etched layer. That is, the sacrificial layer and the support layer are stacked in an overlapping manner, with the support layer located above the sacrificial layer. Here, the number of sacrificial layers and support layers can be determined according to actual needs.

[0047] As an optional embodiment, a stack of sacrificial and support layers is formed above the etch stop layer, including:

[0048] A sacrificial layer is formed above the etch stop layer 201 using LPCVD, plasma enhanced chemical vapor deposition (PECVD), or spin coating processes.

[0049] A support layer is formed on top of the sacrificial layer using LPCVD, PECVD, physical vapor deposition (PVD), or atomic layer deposition (ALD) processes; the number of sacrificial layers includes at least one layer, and the number of support layers includes at least one layer.

[0050] To eliminate stress within the support layer and remove residual membrane pressure, ion implantation is required after each support layer formation.

[0051] As an optional embodiment, ion implantation is performed within the support layer, including:

[0052] At least one of Ar, H, He, N, O, C, Si and B ions is implanted into the support layer formed each time.

[0053] It is worth noting that when performing ion implantation into the support layer, ion implantation can be performed in a partial area or in the entire support layer. When there are multiple support layers, ion implantation can be performed on all of them or on at least one of them. Here, the ion implantation energy and implantation concentration can be adjusted according to the specific implantation process.

[0054] In order to effectively remove the residual membrane pressure in the support layer and form a membrane with high density, thereby giving the support layer the most suitable tensile stress, after each ion implantation into the support layer, the support layer after ion implantation needs to be annealed.

[0055] As an optional embodiment, the support layer after ion implantation is annealed, including:

[0056] The support layer after ion implantation is annealed using furnace annealing, rapid thermal treatment (RTP), or laser annealing. The annealing temperature is 600–1100℃, preferably 700–900℃, and the annealing time is 10–30 min.

[0057] The optimal annealing temperature and optimal annealing time are different for different annealing processes.

[0058] To improve the resolution of photolithography and its long-term corrosion resistance, a hard mask layer is formed above the topmost support layer after annealing the support layer. The hard mask layer is a composite layer formed of a dielectric and a disposable polymer; wherein the dielectric includes at least one of SiO2, SiN, polysilicon, and SiON; and the disposable polymer includes at least one of photoresist, amorphous carbon layer (ACL), and spin on hard mask (SOH).

[0059] When the support layer consists of at least two layers, the following example illustrates the situation:

[0060] For example, refer to Figure 2 When the support layer comprises two layers: a first support layer 203 and a second support layer 205

[0061] At this time, the topmost support layer is the second support layer 205; then correspondingly, the hard mask layer also includes two layers, namely the first hard mask layer 26 and the second hard mask layer 27; above the first support layer 23 is the second sacrificial layer 24, above the second sacrificial layer 24 is the second support layer 25, above the second support layer 25 is the first hard mask layer 26, and above the first hard mask layer 26 is the second hard mask layer 27.

[0062] After the hard mask layer is formed, it needs to be patterned. Using the patterned hard mask layer as a mask, the stacked layers are etched to form capacitor holes, exposing the contact structure. Then, the lower electrode, capacitor dielectric layer, and upper electrode are formed in the capacitor holes. This completes the fabrication of the semiconductor device.

[0063] Furthermore, this embodiment also provides a semiconductor device, such as... Figure 3 As shown, the semiconductor device includes: a semiconductor substrate 301, a contact structure 302, a capacitor 303, and a support structure 304; wherein,

[0064] Contact structure 302 is located above semiconductor substrate 301;

[0065] The capacitor 303 is electrically connected to the contact structure 302. The capacitor 303 includes a lower electrode, a capacitor dielectric layer and an upper electrode. The lower electrode is surrounded by a support structure 304, which includes at least one support layer.

[0066] The support structure undergoes ion implantation and annealing processes sequentially. The implanted ions include at least one of Ar, H, He, N, O, C, Si, and B ions. The support structure also includes at least one or more combinations of Ar, H, and He ions. The specific methods for fabricating the semiconductor device have been described in detail above and will not be repeated here.

[0067] It should be noted that during the fabrication of semiconductor devices, the sacrificial layer, etch stop layer, and hard mask layer are the last layers that need to be removed. Figure 3 The semiconductor device structure shown does not display a sacrificial layer, etch stop layer, or hard mask layer. After the semiconductor device is fabricated, a support structure is formed by at least one support layer to support the lower electrode of capacitor 303.

[0068] The method for fabricating the semiconductor device provided by this invention and the beneficial effects that the semiconductor device can bring are at least:

[0069] This invention provides a method for fabricating a semiconductor device and the semiconductor device itself. The method includes: providing a semiconductor substrate, on which a contact structure is formed, the contact structure being electrically connected to a capacitor; forming an etch stop layer above the contact structure; and sequentially forming a stack of a sacrificial layer and a support layer above the etch stop layer; each of the sacrificial layer and the support layer comprises at least one layer, and the sacrificial layer and the support layer are staggered; wherein, after each formation of the support layer, ion implantation is performed on the support layer, and the ion-implanted support layer is annealed; on the topmost support layer... A hard mask layer is formed. Then, by injecting ions into the support layer, ion collisions can be used to break the Si-O network within the support layer, releasing the stress between Si-O bonds and thus removing residual film pressure from the support layer. Next, the support layer is annealed to form a highly dense film, ensuring that the support layer has suitable tensile stress and preventing bending, cracking, or lifting of the capacitor electrodes in the semiconductor device. Furthermore, this method does not require adjusting the deposition conditions of the support layer, i.e., it does not require reducing the process window of the support layer, thus ensuring the stability of the fabrication process and consequently the overall performance of the semiconductor device.

[0070] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The method includes: A semiconductor substrate is provided, on which a contact structure is formed, the contact structure being electrically connected to a capacitor; An etching stop layer is formed above the contact structure; A sacrificial layer and a support layer are formed above the etching stop layer; each of the sacrificial layer and the support layer includes at least one layer, and the sacrificial layer and the support layer are stacked in an interleaved manner. In this process, after each formation of the support layer, the support layer is ion implanted and then annealed; ion collisions are used within the support layer to break the Si-O network and release the stress between the Si-O bonds. A hard mask layer is formed above the topmost support layer; The step of performing ion implantation on the support layer after each formation of the support layer includes: At least one of Ar, H, He, N, O, C, Si and B ions is implanted into the support layer formed each time.

2. The method as described in claim 1, characterized in that, The stack of sacrificial and support layers formed sequentially above the etching stop layer includes: The sacrificial layer is formed above the etching stop layer using LPCVD, PECVD, or spin coating processes. The support layer is formed on top of the sacrificial layer using the LPCVD process, the PECVD process, the PVD process, or the ALD process.

3. The method as described in claim 1, characterized in that, The material of the support layer is SiN, SiBN, SiCN or SiON.

4. The method as described in claim 1, characterized in that, The annealing process performed on the support layer after ion implantation includes: The support layer after ion implantation is annealed using furnace tube annealing, rapid thermal processing (RTP), or laser annealing; wherein the annealing temperature is 600~1100℃.

5. The method as described in claim 1, characterized in that, The material of the etching stop layer is SiN, SiBN or SiCN.

6. The method as described in claim 1, characterized in that, The hard mask layer is a composite layer formed of a dielectric and a disposable polymer; wherein the dielectric includes at least one of SiO2, SiN, polycrystalline silicon and SiON; and the disposable polymer includes at least one of photoresist, amorphous carbon layer ACL and spin hard mask SOH.

7. The method as described in claim 1, characterized in that, The semiconductor device is a dynamic memory; the method further includes: patterning the hard mask layer; using the patterned hard mask layer as a mask, etching the stacked layers to form capacitor holes and exposing the contact structure.

8. The method as described in claim 7, characterized in that, The method further includes: A lower electrode, a capacitor dielectric layer, and an upper electrode are formed within the capacitor hole.

9. The method as described in claim 1, characterized in that, The semiconductor substrate includes a buried channel transistor, one of the source and drain regions of the transistor being in contact with a bit line, and the other source and drain region being electrically connected to the contact structure.

10. A semiconductor device, characterized in that, The semiconductor device includes: Semiconductor substrate; Contact structures located on the semiconductor substrate; A capacitor electrically connected to the contact structure, the capacitor comprising a lower electrode, a dielectric layer, and an upper electrode; The lower electrode includes a support structure, which is subjected to ion implantation and annealing in sequence. The implanted ions include at least one of Ar, H, He, N, O, C, Si and B ions. The support structure includes at least one support layer. Ion collisions are used in the support layer to cut the Si-O network and release the stress between the Si-O bonds.

11. The semiconductor device as claimed in claim 10, characterized in that, The material of the support layer is SiN, SiBN, SiCN or SiON.

12. The semiconductor device as claimed in claim 10, characterized in that, The support structure also includes at least one or more combinations of Ar, H, and He ions.

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