Capacitor structure for integrated circuit and related method

Abstract

The present invention relates to a capacitor structure for an integrated circuit and a related method. Embodiments of the present disclosure provide a capacitor for an integrated circuit (IC). The capacitor may include a first vertical electrode located on an upper surface of a first conductor within a first wiring layer. The capacitor dielectric may be located on an upper surface of the first vertical electrode. A second vertical electrode may be located on an upper surface of the capacitor dielectric. The second vertical electrode is located vertically between the capacitor dielectric and the second conductor. An inter-level dielectric (ILD) layer is adjacent to each of the first vertical electrode, the capacitor dielectric, and the second vertical electrode. The ILD layer is located vertically between the first conductor and the second conductor.

Description

Technical Field

[0001] The present disclosure relates to integrated circuit (IC) structure formation, and more particularly to capacitor structures for ICs and related methods of forming the capacitor structures. Background Art

[0002] The capacitor structure in an IC typically includes two metal plates with an insulator between them. In such a configuration, the plates occupy at least the minimum surface area to achieve the desired capacitance. A conventional method for integrating capacitors into integrated circuits is to form transverse metal lines or "fingers" that extend outward from a larger wiring that intersects similar metal lines in nearby wiring. However, as device sizes continue to decrease, this configuration may limit manufacturability and capacitance range. This limitation in capacitor size is particularly concerning when product specifications require ultra-low capacitors, i.e., capacitors not exceeding approximately 0.5 femtofarads (fF). Conventional methods for providing ultra-low capacitance include, for example, increasing the spacing between alternating horizontal electrodes to reduce the capacitance density in the capacitor structure. Alternative methods include connecting larger capacitors in series to reduce the effective capacitance between two nodes. However, these and other methods produce significant uncertainty and error in the actual capacitance of the device. Summary of the Invention

[0003] Some aspects of the present disclosure provide a capacitor for an integrated circuit (IC), the capacitor comprising: a first vertical electrode located on an upper surface of a first conductor within a first wiring layer; a capacitor dielectric located on an upper surface of the first vertical electrode; a second vertical electrode located on an upper surface of the capacitor dielectric, wherein the second vertical electrode is vertically located between the capacitor dielectric and the second conductor; and an inter-level dielectric (ILD) layer adjacent to each of the first vertical electrode, the capacitor dielectric, and the second vertical electrode, wherein the ILD layer is vertically located between the first conductor and the second conductor.

[0004] Other aspects of the present disclosure provide a wiring layer stack for an integrated circuit (IC), the wiring layer stack comprising: a first wiring layer comprising a first plurality of conductors; an inter-level dielectric (ILD) layer located on an upper surface of the first wiring layer; a second wiring layer located on an upper surface of the ILD layer, the second wiring layer comprising a second plurality of conductors; at least one capacitor located within the ILD layer, the at least one capacitor comprising: a first vertical electrode located on an upper surface of one of the first plurality of conductors, a capacitor dielectric located on an upper surface of the first vertical electrode, and a second vertical electrode located on an upper surface of the capacitor dielectric, wherein the second vertical electrode is vertically located between one of the second plurality of conductors and the capacitor dielectric; and at least one via located within the ILD layer, coupling one of the first plurality of conductors to one of the second plurality of conductors, wherein a portion of the ILD layer separates the via from the at least one capacitor in a horizontal direction.

[0005] Some other aspects of the present disclosure provide a method of forming a capacitor for an integrated circuit (IC), the method comprising: forming a first opening in a first portion of an inter-level dielectric (ILD) layer to expose a first conductor below the first portion of the ILD layer; forming a first vertical electrode on an upper surface of the first conductor and within the first portion of the ILD layer to fill the first opening; forming a capacitor dielectric on an upper surface of the first vertical electrode; forming a second vertical electrode on an upper surface of the capacitor dielectric; and forming a second portion of the ILD layer on an upper surface of the first portion of the ILD layer, the second portion of the ILD layer being adjacent to the capacitor dielectric and the second vertical electrode.

[0006] The foregoing and other features of the present disclosure will be apparent from the following more particular description of embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments of the present disclosure will be described in detail with reference to the following drawings, wherein like reference numerals represent like elements, and wherein:

[0008] Figure 1 A cross-sectional view of a preliminary structure to be processed according to an embodiment of the present disclosure is shown.

[0009] Figure 2 A cross-sectional view illustrating forming a first opening in a first portion of an inter-level dielectric (ILD) layer according to an embodiment of the present disclosure is shown.

[0010] Figure 3 A cross-sectional view illustrating forming a first vertical electrode in a first opening according to an embodiment of the present disclosure is shown.

[0011] Figure 4 A cross-sectional view of forming capacitor dielectric material and electrode material according to an embodiment of the present disclosure is shown.

[0012] Figure 5 A cross-sectional view illustrating forming a capacitor dielectric and a second vertical electrode according to an embodiment of the present disclosure is shown.

[0013] Figure 6 A cross-sectional view illustrating forming a second portion of an ILD layer according to an embodiment of the present disclosure is shown.

[0014] Figure 7 A cross-sectional view illustrating forming a second opening in a second portion of the ILD layer according to an embodiment of the present disclosure is shown.

[0015] Figure 8 A cross-sectional view illustrating forming a second wiring layer according to an embodiment of the present disclosure is shown.

[0016] Figure 9 An enlarged cross-sectional view of a capacitor and wiring layers according to an embodiment of the present disclosure is shown.

[0017] It should be noted that the drawings of the present disclosure are not necessarily drawn to scale. The drawings are intended only to depict typical aspects of the present disclosure and therefore should not be considered to limit the scope of the present disclosure. In the drawings, like reference numerals represent like elements between the drawings. DETAILED DESCRIPTION

[0018] In the following description, reference is made to the accompanying drawings which form a part of the present invention and which illustrate specific exemplary embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it is understood that other embodiments may be used and changes may be made without departing from the scope of the present teachings. Therefore, the following description is illustrative only.

[0019] Embodiments of the present disclosure provide a capacitor structure for an IC and a related method for forming the capacitor structure. An embodiment of the capacitor structure may, for example, include a first vertical electrode located on the upper surface of a first conductor within a first wiring layer. The capacitor dielectric may be located on the upper surface of the first vertical electrode. The second vertical electrode may be located on the upper surface of the capacitor dielectric, thereby positioning the second vertical electrode between the capacitor dielectric and the second conductor in the vertical direction. An inter-level dielectric (ILD) layer may be adjacent to the first vertical electrode, the capacitor dielectric, and the second vertical electrode. The ILD layer may also be located between the first conductor and the second conductor in the vertical direction. The method according to an embodiment of the present disclosure is operable to form the capacitor structure, and other parts of the IC, such as wiring layers located above and below the capacitor structure, may be optionally formed.

[0020] Figure 1 A cross-sectional view in plane XZ of a preliminary structure 100 to be processed according to an embodiment of the present disclosure is shown. Figure 1 The illustrated preliminary structure 100 provides a starting set of materials intended for embodiments of the present disclosure, but it should be understood that embodiments of the present disclosure may be implemented in different designs without significantly altering the various example techniques discussed herein.

[0021] The preliminary structure 100 may include a first region 102 and a second region 104 located at two different positions within a plane XZ. As an example, the first region 102 is shown as being separated from the second region 104 in the horizontal direction by an indeterminate distance indicated by a dashed line. In various other embodiments, each region 102, 104 may be directly adjacent to each other, separated along different directions (e.g., within a plane YZ), and / or adopt any other spatial arrangement. The various portions of the preliminary structure 100 may be formed on a first wiring layer 110 comprising various insulating and / or conductive materials. The first wiring layer 110 may be located (i.e., directly or indirectly located) on or otherwise above a device layer comprising electronic devices such as transistors, diodes, resistors, capacitors, inductors, etc., for providing operating characteristics of the device. The composition and function of the device layer are well known in the art and are not shown in the drawings or discussed in further detail herein.

[0022] The wiring layer 110 may be formed of an insulating material, such as one or more oxide-based dielectric materials suitable for physically and electrically separating various regions of conductive material in the wiring layer 110. The oxide-based dielectric materials may also be suitable for distinguishing from other dielectric materials discussed elsewhere herein. The dielectric materials may include, but are not limited to: carbon-doped silicon dioxide materials; fluorinated silicate glass (FSG); organic polymer thermoset materials; silicon oxycarbide; SiCOH dielectrics; fluorine-doped silicon oxide; spin-on glass; silsesquioxanes, including hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), and mixtures or copolymers of HSQ and MSQ; benzocyclobutene (BCB)-based polymer dielectrics, and any silicon-containing low-k dielectric. Examples of spin-on low-k films having SiCOH-type compositions using silsesquioxane chemistry include HOSP TM (available from Honeywell), JSR 5109 and 5108 (available from Japan Synthetic Rubber), Zirkon TM(available from Shipley Microelectronics, a Rohm and Haas division), and porous low-k (ELk) materials (available from Applied Materials). Examples of carbon-doped silica materials or organosilanes include Black Diamond TM (available from Applied Materials) and Coral TM (Available from Lam Research). An example of a HSQ material is FOx TM (Available from Dow Corning).

[0023] Portions of wiring layer 110 may include first conductors 120 (e.g., one or more metal lines) for electrically coupling portions of the device layer to other wiring layers and / or other portions of the device layer. First conductor 120 may include any currently known or later developed conductive material capable of forming a conductive path between multiple electrically active elements. By way of example, first conductor 120 may include any and / or all conductive materials, such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), titanium (Ti), and the like. Although not shown in the figures, a barrier liner may also be deposited on the sidewalls of the insulating material adjacent to first conductor 120, prior to formation of first conductor 120. The deposited barrier liner may include any currently known or later developed barrier liner material (e.g., a refractory metal liner), including, but not limited to, tantalum nitride (TaN) and tantalum; tantalum nitride, tantalum, and cobalt; and magnesium (Mn), or combinations thereof. First conductor 120 may be formed, for example, by depositing conductive material within trenches in wiring layer 110 and / or by patterning wiring layer 110 and / or first conductor 120 material. By way of example, three first conductors 120 are shown in the first region 102 of the insulating structure, and one first conductor 120 is shown in the second region 104 of the preliminary structure 100, although this is not necessarily the case in all embodiments. Forming a material by "deposition" or "deposition" may generally include any now known or later developed technique suitable for the material to be deposited, including, but not limited to, for example: chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), sub-atmospheric pressure CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction process CVD (LRPCVD), metal organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin coating, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.

[0024] The preliminary structure 100 may, for example, include a barrier film 130 located above the wiring layer 110 and the first conductor 120 therein to isolate the overlying material from the wiring layer 110 below it in the vertical direction. The barrier film 130 may include one or more electrically insulating materials with particularly high etching resistance. More specifically, the barrier film 130 may be formed as an "etch stop layer" that is configured to prevent the underlying device components from being removed or modified in subsequent processing. Therefore, the barrier film 130 may include, for example, an oxygen-doped silicon carbide (SiC:O) layer, a nitrogen-doped silicon carbide (SiC:N) layer, or other materials with similar properties. The preliminary structure 100 may also include a first portion of an ILD layer 140 located on the barrier film 130 (hereinafter referred to as the "first portion"). The first portion 140 may include one or more insulating materials contained in the wiring layer 110, and / or may include any other currently known or later developed insulating material.

[0025] Steering Figure 2Embodiments of the present disclosure may include forming one or more first openings 150 within the first portion 140 and within the first region 102, without forming first openings 150 within the second region 104. Reactive ion etching (RIE) using a mask 152 positioned appropriately over the first portion 140 is a suitable technique for forming the first openings 150. Etching generally refers to the removal of material from a substrate (or a structure formed on the substrate) and is typically performed using a mask positioned appropriately to selectively remove material from specific areas of the substrate while leaving material in other areas of the substrate unaffected. There are generally two types of etching: (i) wet etching and (ii) dry etching. Wet etching is performed using a solvent (e.g., an acid) that is selected for its ability to selectively dissolve a given material (e.g., an oxide) while leaving another material (e.g., polysilicon) relatively intact. This ability to selectively etch a given material is fundamental to many semiconductor manufacturing processes. Wet etching typically etches homogeneous materials (e.g., oxides) isotropically, but wet etching can also anisotropically etch single-crystalline materials (e.g., silicon wafers). Dry etching can also be performed using plasma. The plasma system can operate in several modes by adjusting the plasma parameters. Ordinary plasma etching produces neutrally charged high-energy radicals that react on the surface of the wafer. Since the neutral particles attack the wafer from all angles, the process is isotropic. Ion milling or sputter etching bombards the wafer with high-energy ions of a rare gas, which approach the wafer from roughly one direction, so the process is highly anisotropic. Reactive ion etching (RIE) operates under conditions between sputtering and plasma etching and can be used to produce deep and narrow features suitable for creating similar elements, such as the vertical electrodes discussed in this article. The formation of the first opening 150 can also remove the underlying portion of the barrier film 130 to expose the upper surface J of the first conductor 120.

[0026] refer to Figure 3 , the embodiment of the present disclosure includes a first conductor 120 on the upper surface J ( Figure 2 ) is formed on the first vertical electrode 160. The first vertical electrode 160 may include any currently known or later developed material suitable for use as a capacitor electrode, for example, aluminum (Al), tantalum (Ta), silver (Ag), one or more metals described herein with respect to the first conductor 120, and / or other conductive materials. The first vertical electrode 160 may be formed by deposition to partially or completely fill the first opening 150 ( Figure 2). In the case where the plurality of first openings 150 have been formed, the first vertical electrode 160 can be formed by deposition and subsequent etching, planarization, etc., so that the upper surface of the first portion 140 is coplanar with the upper surface L of the first vertical electrode 160. Before, during, or after forming the first vertical electrode 160, the mask 152 ( Figure 2 ).

[0027] Continue to Figure 4 Embodiments of the present disclosure may include forming other materials for capacitor structures within the ILD material of the IC (e.g., above the first portion 140). Formation of these materials may also include, for example, forming a capacitor dielectric layer 162 and an electrode layer 164 on the upper surface L of the first vertical electrode 160, in addition to the exposed portion of the first portion 140. When deposited, the capacitor dielectric layer 162 may be non-selectively formed on the first region 102 and the second region 104. In this case, the electrode layer 164 may also cover the entire capacitor dielectric layer 162 in the first region 102 and the second region 104. The capacitor dielectric layer 162 may have a different material composition than the first portion 140 and may be selected to have a higher dielectric constant than the insulating material of the first portion 140. According to one example, the capacitor dielectric layer 162 may include one or more oxide-based dielectric materials (e.g., HfO2) and / or nitride-based dielectric materials, such as silicon nitride (SiN), while the first portion 140 may include one or more oxide dielectric materials, such as silicon dioxide (SiO2). In further embodiments, the capacitor dielectric layer 162 may include any dielectric material having a higher dielectric constant than the first portion 140. According to example embodiments, the capacitor dielectric layer 162 may be formed to a vertical thickness T between about 5 nanometers (nm) and about 15 nm over the first vertical electrode 160. The electrode layer 164 may have the same composition or a similar composition as the first vertical electrode 160 and may be formed to any desired vertical thickness on the capacitor dielectric layer 162.

[0028] Continue to Figure 5 , subsequent processing may include using capacitor dielectric layer 162 ( Figure 4 ) and electrode layer 164 ( Figure 4 ) to form the remaining components of the capacitor at desired locations in the first region 102. For example, the mask 165 may be formed on the electrode layer 164 ( Figure 4). With mask 165 in place, exposed portions of the dielectric layer and electrode layer 164 in first region 102 and second region 104 may be removed (e.g., by etching). The remaining portions of the material may form a set of capacitor dielectrics 166, each of which is located below the upper surface L ( Figure 3 ). Similarly, the remaining portion of electrode layer 164 can define a set of second vertical electrodes 168, each of which is located on the upper surface of capacitor dielectric 166 below it. The height of second vertical electrodes 168 above capacitor dielectric 166 can be different from the height of first vertical electrode 160 above first conductor 120. In some cases, first vertical electrode 160 can be significantly taller than second vertical electrode 166 along the Z-axis, but this is not necessarily the case in all embodiments.

[0029] For example, capacitor dielectric 166 can be formed by depositing capacitor dielectric layer 162 before etching the deposited material from non-capacitor regions of the device, which can allow for greater control over the dimensions of capacitor dielectric 166. However, this approach is not required in all embodiments. Capacitor dielectric 166 and second vertical electrode 168 can be formed by any process that selectively forms these materials on first vertical electrode 160, such as forming the material, forming an opening above first vertical electrode 160, and forming capacitor dielectric 166 and second vertical electrode 168 in the opening. In this case, the dimensions of capacitor dielectric 166 can be controlled by etching rather than deposition. Additional variations can allow the dimensions of capacitor dielectric 166 to be determined by other processes. Regardless of the process used to form capacitor dielectric and / or vertical electrode 168, capacitor dielectric 166 can maintain a thickness T between approximately 5 nm and approximately 15 nm, as discussed elsewhere herein. Mask 165 can be removed, where applicable, such as by stripping and / or any other process suitable for removing masking material from a structure.

[0030] Steering Figure 6 , embodiments of the present disclosure may include forming the remainder of the ILD material for the various wiring layers of the IC without significant differences from conventional processing. For example, Figure 6The ILD layer 170 is shown formed by forming a second portion (hereinafter referred to as "second portion") 172 of ILD material on the first portion 140 in the capacitor region 104 and the second region 104. The second portion 172 may also be formed on and adjacent to the capacitor dielectric 166 and the second vertical electrode 168 in the first region 102. The second portion 172 may include the same material as the first portion 140 or a similar material. In the case where the second portion 172 has the same composition as the first portion 140, there may be no visible interface between the first portion 140 and the second portion 172 of the ILD layer 170. The vertical interface between the portions 140, 172 is shown in dashed lines to indicate that each portion 140, 172 is part of one ILD layer 170.

[0031] Steering Figure 7 Subsequent processing may include forming a routing mask 173 over portions of the ILD layer 170 to align portions of the first region 102 and the second region 104 for subsequent metal deposition. With the mask 173 in place over selected portions of the ILD layer 170, the disclosed method may include forming a set of second openings 174 within the second portion 172. The second openings 174 may be formed to expose the upper surface M of the second vertical electrode 168 in the first region 102. The second openings 174 in the routing region 104 may similarly extend only partially into the ILD layer 170. The second openings 174 in the second region 104 may be used to form metal lines, some of which may extend laterally (i.e., into or out of the plane of the page) and / or laterally at other locations relative to other conductive elements (e.g., horizontally along the X or Y axis). In some cases, third openings 176 may be formed in the routing region 104 by removing portions of the ILD layer 170 to expose the first conductor 120 thereunder. The third opening 176 can be formed to create a via structure for vertically coupling the first conductor 120 to an overlying conductive material, as discussed elsewhere herein. The third opening 176 can be deeper than the second opening 176, for example, by forming it with the aid of an additional mask (not shown) before or after forming the second opening 174. After the second opening 174 and the third opening 176 have been formed, the mask 173 can be removed by stripping and / or any other process for removing mask material from the structure.

[0032] refer to Figure 8 , the subsequent processing may include forming a conductive material for an overlying wiring layer above the wiring layer 110. Forming such a material may include, for example, forming a conductive material in the second opening 174 ( Figure 7) is deposited within the second region 104. The second conductor 180 may include any currently known or later developed conductive material, such as any of those discussed herein with respect to the first conductor 120. In addition to forming the second conductor 180, portions of the conductive material may at least partially fill the third opening 176 ( Figure 7 ) to form, for example, a via 182 on the first conductor 120 and a metal line 184 on the via 182. The second conductor 180, via 182, and / or metal line 184 may be formed, for example, by depositing a conductive material and subsequently planarizing it. Where the third opening 176 is previously formed in the ILD layer 170, the metal line 184 may have a greater width than the via 182 due to the shape of the third opening 176. Although not shown in the figures, a barrier liner may also be deposited on the sidewalls of the openings 174, 176 in the ILD layer 170, and may be deposited before the second conductor 180, via 182, and / or metal line 184 are formed (e.g., as described elsewhere herein). In some cases, the second conductor 180, via 182, and / or metal line 184 may be formed by a damascene process. Damascene is a process in which an interconnect pattern is first photolithographically defined in a dielectric layer, metal is then deposited to fill the resulting line slot openings or via openings, and excess metal is then removed by chemical mechanical polishing (planarization). Dual damascene is a similar process in which the interconnect pattern defines line slot openings as well as via openings (e.g., as may be the case in third opening 176) prior to metal deposition. The conductive materials may also be planarized (e.g., by chemical mechanical planarization (CMP) or a similar process) so that they are coplanar with the top surface of ILD layer 170.

[0033] Also refer to Figure 8 and Figure 9 ,in Figure 9An enlarged view of elements in the first region 102 is provided, and embodiments of the present disclosure provide a capacitor 190 and / or wiring layer stack 200 for an IC structure. After forming the second conductor 180, the first vertical electrode 160, the capacitor dielectric 166, and the second vertical electrode 168 form an electrical path in the form of the capacitor 190. The capacitor 190 couples the first conductor 120 to the second conductor 180 in a vertical direction. In such a configuration, for example, as a result of the etching process and / or other techniques used to form the first vertical electrode 160, the capacitor dielectric 166, and / or the second vertical electrode 168, the capacitor dielectric 166 can be substantially vertically aligned with the first vertical electrode 160 and the second vertical electrode 168. The term "substantially vertically aligned" can be defined as the capacitor dielectric 166 having a vertical centerline axis that is substantially the same as the centerline axis of the vertical electrodes 160, 168. Thus, the capacitor dielectric 166 may have a different size, width, etc. than the vertical electrodes 160, 168, but may still maintain a substantially vertical alignment with the vertical electrodes 160, 168. The ILD layer 170 may connect the capacitor 190 in the first region 102 to the via 182 in the second region 104. Figure 8 The horizontal distance between capacitor 190 and via 182 may be, for example, at least about 50 micrometers (μm).

[0034] During operation, when a potential is applied across them, for example due to the presence of capacitor dielectric 166, vertical electrodes 160, 168 may become oppositely charged. This structure will cause capacitor 190 to store charge during operation, similar to a conventional parallel plate arrangement. However, capacitor 190 according to the present disclosure can provide a low-capacitance capacitor embedded within ILD layer 170 and located above wiring layer 110. To provide these operational features, additional wiring layer 192 and metal line 194 can be formed above ILD layer 170, where metal line 194 is electrically coupled to second conductor 180. A voltage source 196 (e.g., any conceivable power source, such as a battery) can be coupled to second vertical electrode 168 of capacitor 190 via metal line 194 and second conductor 180. First vertical electrode 160 can similarly be electrically coupled to ground GND (or another node having a voltage different from that of voltage source 196) via first conductor 120. The voltage source 196 and the ground GND are shown using schematic icons to indicate that they can be coupled to the capacitor 190 of the wiring layer stack 200 through multiple intermediate conductors, layers, electrical structures, etc. These elements can be coupled through portions of the first conductor 120, the second conductor 180, the metal line 194, etc. that extend into or out of the plane of the page. In other embodiments, the wiring layer 110 and / or the additional wiring layer 192 can include additional vias for coupling the first conductor 120 and / or the metal line 194 to other wiring layers in the wiring layer stack 200.

[0035] Embodiments of the present disclosure provide various technical and commercial advantages, some of which are described herein as examples. Capacitor 190 and wiring layer stack 200 may be characterized in that capacitor dielectric 166 has a vertical thickness determined by deposition characteristics (e.g., deposition time) rather than etching characteristics. Deposition is easier to control than etching, and therefore, in contrast to capacitors formed by conventional techniques, the size of capacitor dielectric 166 hardly changes. These attributes can then allow for more consistent implementation of extremely low capacitance (e.g., approximately 0.5 fF) than other types of capacitors in IC. The resulting capacitance variation relative to design specifications may be, for example, an error of approximately ten percent relative to the desired capacitance in capacitor 190. The method of the present disclosure may also be integrated into conventional processes to form the metal wiring layers of an IC without fundamentally changing the method of operation and / or adding a large number of additional steps.

[0036] The above-described method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single-chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0037] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of the features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or the groups they constitute. "Optional" or "optionally" means that the event or situation described subsequently may or may not occur, and that the description includes situations where the event occurs and situations where the event does not occur.

[0038] Approximate language, as used throughout the specification and claims, may be used to modify any quantitative representation that is permissible to vary without resulting in a change in the basic function to which it relates. Accordingly, a value modified by one or more terms such as "about," "approximately," and "substantially" is not limited to the precise value specified. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. Herein and throughout the specification and claims, range limitations may be combined and / or interchanged, such ranges are identified and include all subranges contained therein unless the context or language indicates otherwise. "Approximately" applied to a particular value of a range applies to both values ​​and may indicate + / - 10% of the stated value unless otherwise dependent upon the precision of the instrument used to measure the value.

[0039] The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been given for purposes of illustration and description, but is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles and practical application of the disclosure and to enable others skilled in the art to understand the various embodiments of the disclosure with various modifications suitable for the particular use contemplated.

Claims

1. A capacitor for an integrated circuit (IC), comprising: a first vertical electrode on an upper surface of a first conductor within the first wiring layer, wherein the first vertical electrode includes a sidewall; a capacitor dielectric on an upper surface of the first vertical electrode, wherein the capacitor dielectric includes sidewalls vertically aligned with the sidewalls of the first vertical electrode; a second vertical electrode positioned on an upper surface of the capacitor dielectric, wherein the second vertical electrode is vertically positioned between the capacitor dielectric and a second conductor, wherein the second vertical electrode and the second conductor include sidewalls vertically aligned with the sidewalls of the first vertical electrode; as well as an inter-level dielectric (ILD) layer adjacent to each of the first vertical electrode, the capacitor dielectric, and the second vertical electrode, and wherein the second conductor comprises a metal line within a second wiring layer located on an upper surface of the ILD layer, wherein the ILD layer is located vertically between the first conductor and the metal line. 2 . The capacitor of claim 1 , wherein a vertical thickness of the capacitor dielectric between the first vertical electrode and the second vertical electrode is between 5 nm and 15 nm. 3 . The capacitor of claim 1 , wherein the ILD layer comprises an oxide dielectric material, and wherein the capacitor dielectric comprises a nitride dielectric material. 4 . The capacitor of claim 1 , wherein a portion of the ILD layer horizontally separates the first vertical electrode, the capacitor dielectric, and the second vertical electrode from a via within the ILD layer. 5 . The capacitor of claim 4 , wherein a combined height of the first vertical electrode, the capacitor dielectric, and the second vertical electrode above the first wiring layer is equal to a height of the via above the first wiring layer. 6 . The capacitor of claim 1 , further comprising a barrier film adjacent to the first vertical electrode and below the ILD layer.

7. A wiring layer stack for an integrated circuit (IC), the wiring layer stack comprising: a first wiring layer comprising a first plurality of conductors; an inter-level dielectric (ILD) layer located on an upper surface of the first wiring layer; a second wiring layer on an upper surface of the ILD layer, the second wiring layer comprising a second plurality of conductors; at least one capacitor located within the ILD layer, the at least one capacitor comprising: a first vertical electrode positioned on an upper surface of one of the first plurality of conductors, wherein the first vertical electrode comprises a sidewall, a capacitor dielectric on an upper surface of the first vertical electrode, wherein the capacitor dielectric includes sidewalls vertically aligned with the sidewalls of the first vertical electrode, and a second vertical electrode positioned on an upper surface of the capacitor dielectric, wherein the second vertical electrode is vertically positioned between one of the second plurality of conductors and the capacitor dielectric, wherein the second vertical electrode and the one of the second plurality of conductors include sidewalls vertically aligned with the sidewalls of the first vertical electrode, and wherein the one of the second plurality of conductors comprises a metal line within the second wiring layer; as well as At least one via is located within the ILD layer and couples one of the first plurality of conductors to one of the second plurality of conductors, wherein a portion of the ILD layer horizontally separates the via from the at least one capacitor. 8 . The wiring layer stack of claim 7 , wherein a vertical thickness of the capacitor dielectric between the first vertical electrode and the second vertical electrode is between 5 nanometers and 15 nm. 9 . The wiring layer stack of claim 7 , wherein the ILD layer comprises an oxide dielectric material, and wherein the capacitor dielectric comprises a nitride dielectric material. 10 . The wiring layer stack of claim 7 , wherein a height of the at least one capacitor is equal to a height of the at least one via. 11 . The wiring layer stack of claim 7 , further comprising a barrier film adjacent to the first vertical electrode of the at least one capacitor and located between the first wiring layer and the ILD layer in a vertical direction.

12. A method of forming a capacitor for an integrated circuit (IC), the method comprising: forming a first opening in a first portion of an inter-level dielectric (ILD) layer to expose a first conductor beneath the first portion of the ILD layer; forming a first vertical electrode on an upper surface of the first conductor and within the first portion of the ILD layer to fill the first opening, wherein the first vertical electrode includes a sidewall; forming a capacitor dielectric on an upper surface of the first vertical electrode, wherein the capacitor dielectric includes sidewalls vertically aligned with the sidewalls of the first vertical electrode; forming a second vertical electrode on an upper surface of the capacitor dielectric, wherein the second vertical electrode includes sidewalls vertically aligned with the sidewalls of the first vertical electrode; forming a second portion of the ILD layer on an upper surface of the first portion of the ILD layer, the second portion of the ILD layer being adjacent to the capacitor dielectric and the second vertical electrode; as well as A second conductor is formed on an upper surface of the second vertical electrode and over the second portion of the ILD layer, wherein the second conductor includes a sidewall vertically aligned with the sidewall of the first vertical electrode, wherein the second conductor includes a metal line within a second wiring layer located on the upper surface of the second portion of the ILD layer. 13 . The method of claim 12 , wherein the second portion of the ILD layer is formed such that a top surface of the ILD layer is coplanar with a top surface of a portion of the second conductor within the ILD layer.

14. The method of claim 12, wherein forming the capacitor dielectric comprises forming a nitride dielectric material on the upper surface of the first vertical electrode to a thickness between 5 nanometers and 15 nanometers.

15. The method according to claim 12, wherein: The first conductor is coupled to the second conductor through a capacitor including the first vertical electrode, the capacitor dielectric, and the second vertical electrode.

16. The method according to claim 12, further comprising: forming a barrier film on an upper surface of a wiring layer, the wiring layer including the first conductor; as well as forming the first portion of the ILD layer on an upper surface of the barrier film, Wherein forming the first opening in the first portion of the ILD layer further comprises forming the first opening through the barrier film.

17. The method of claim 12, further comprising forming vias in the first portion of the ILD layer and the second portion of the ILD layer, wherein the ILD layer is horizontally located between each of the first vertical electrode, the capacitor dielectric, and the second vertical electrode and the vias.

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