A multi-port electrostatic protection MOS structure

Abstract

The application discloses a multi-port electrostatic protection MOS structure, and belongs to the field of semiconductor devices and manufacturing. In the multi-port electrostatic protection MOS structure, a NPN current channel and a PN Diode current channel formed by a power supply anode, a power supply cathode and an I / O port are used to realize all-round protection between the power supply anode, the power supply cathode and the I / O port. In addition, compared with a plurality of ESD devices corresponding to an I / O port to a power supply cathode, an I / O port to a power supply anode and a power supply anode to a power supply cathode in the prior art, the application can realize the above multi-port electrostatic protection requirement through a single electrostatic protection MOS structure, thereby reducing the number of ESD devices and further saving the chip area.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices and manufacturing, in particular to a multi-port electrostatic protection MOS structure. BACKGROUND

[0002] With the feature size of semiconductor integrated circuit manufacturing process becoming smaller and smaller, the size of chip unit also becomes smaller and smaller, and the anti-static ability of chip becomes more and more important. Electrostatic discharge can cause permanent damage to semiconductor components and computer systems, thereby affecting the circuit function of integrated circuit and making the electronic product work abnormally, so some protection measures or functions must be designed to protect the chip from the damage of electrostatic discharge phenomenon.

[0003] In the design of multi-port electrostatic protection MOS structure, the related art adopts the design method of setting electrostatic protection structure between each port, but causes the problems of too many ESD devices and too much chip area occupation. SUMMARY

[0004] The present application provides a multi-port electrostatic protection MOS structure, which can solve the problem of too much chip area occupation in the design of multi-port electrostatic protection structure in the related art.

[0005] The present application provides a multi-port electrostatic protection MOS structure, which comprises:

[0006] a substrate 1, an electrical isolation layer 2, a P-type well 3, a first N-type well 4.1, a second N-type well 4.2, a gate 5, a source 6, a drain 7, a first body region 8, a second body region 9, a first N-type heavily doped region 10, a second heavily doped region 11, a third heavily doped region 12, a fourth N-type heavily doped region 13, a first P-type heavily doped region 14 and a second P-type heavily doped region 15;

[0007] The electrical isolation layer 2 is formed on the substrate 1, and the P-type well 3, the first N-type well 4.1 and the second N-type well 4.2 are located on the electrical isolation layer 2.

[0008] The gate 5 is formed above the P-type well 3, the source 6 and the drain 7 are symmetrically arranged on both sides of the upper surface of the P-type well 3, and the first body region 8 and the second body region 9 are symmetrically arranged on both sides of the upper surface of the P-type well 3.

[0009] The upper surface of the first N-type well 4.1 is formed with the first N-type heavily doped region 10 and the first P-type heavily doped region 14; the upper surface of the second N-type well 4.2 is formed with the fourth N-type heavily doped region 13 and the second P-type heavily doped region 15; the second heavily doped region 11 is arranged between the first N-type well 4.1 and the P-type well 3, and the third heavily doped region 12 is arranged between the P-type well 3 and the second N-type well 4.2.

[0010] The first N-type heavily doped region 10 and the fourth N-type heavily doped region 13 are connected to the anode of a power supply; the gate 5 is connected to the cathode of the power supply; the drain 7 is connected to an I / O port; the first P-type heavily doped region 14 and the second P-type heavily doped region 15 are respectively short-circuited with the I / O port.

[0011] Optionally, in the first N-type well 4.1, the first N-type heavily doped region 10 and the first P-type heavily doped region 14 have a certain interval.

[0012] Optionally, in the second N-type well 4.2, the fourth N-type heavily doped region 13 and the second P-type heavily doped region 15 have a certain interval.

[0013] Optionally, in the P-type well 3, the source 6 and the first body region 8 have a certain interval, and the drain 7 and the second body region 9 have a certain interval.

[0014] Optionally, the conductivity type of the substrate 1 is P-type.

[0015] Optionally, the second heavily doped region 11 and the third heavily doped region 12 are N-type heavily doped regions or P-type heavily doped regions.

[0016] Optionally, the electrically isolated layer 2 is an N-type deep well or an N-type buried layer.

[0017] Optionally, the source 6 and the drain 7 are N-type heavily doped regions.

[0018] Optionally, the first body region 8 and the second body region 9 are N-type heavily doped regions.

[0019] In summary, the application provides a multi-port electrostatic protection MOS structure, P-type heavily doped regions are introduced into the first N-type well and the second N-type well and shorted with the I / O port, N-type heavily doped regions are introduced into the adjacent N-type well and P-type well and left floating, the I / O port exists NPN current channel formed by the drain, the P-type well and the source with respect to the power cathode (GND terminal), the power cathode exists PN Diode current channel formed by the body region, the P-type well and the drain with respect to the I / O port, the I / O port exists PN Diode current channel formed by the first N-type heavily doped region, the N-type well and the first P-type heavily doped region with respect to the power anode (VDD), the power anode exists NPN current channel formed by the first N-type heavily doped region, the second heavily doped region, the N-type well, the P-type well and the drain with respect to the I / O port, the power anode exists NPN current channel formed by the first N-type heavily doped region, the N-type well, the second heavily doped region and the P-type well with respect to the power cathode, the power cathode exists PN Diode current channel formed by the body region, the P-type well, the second heavily doped region, the N-type well and the first N-type heavily doped region with respect to the power anode, realizing all-around protection between the power anode, the power cathode and the I / O port, in addition, compared with the related art which sets multiple ESD devices corresponding to the I / O port to the power cathode, the I / O port to the power anode and the power anode to the power cathode, the application can meet the above multi-port electrostatic protection requirement through one electrostatic protection MOS structure, reducing the number of ESD devices and saving the chip area. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the specific embodiments or the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the application, and those skilled in the art can also obtain other drawings according to these drawings without any creative effort.

[0021] Figure 1 A cross-sectional view of a multi-port electrostatic protection MOS structure is shown;

[0022] Figure 2 A top view of the structure is shown; Figure 1

[0023] Figure 3 A position diagram without forming metal silicide is shown. DETAILED DESCRIPTION

[0024] ​With reference to the drawings, the technical solutions in the present application will be clearly and completely described below. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of the present application.

[0025] In the description of the present application, it should be noted that the orientations or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0026] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or the internal communication of two elements, it can be wireless connection, or wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0027] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as there is no conflict between them.

[0028] In the related art, if full protection is not formed among IO, GND and VDD, the unprotected port is easy to be damaged by ESD, resulting in the loss of functionality of the chip, and thus in the multi-port scenario, it is necessary to set up an electrostatic protection structure among the ports, such as IO to GND, IO to VDD, and VDD to GND, which need to be protected by ESD devices, that is, at least 3 devices are needed. The device structure of the present application can meet the above electrostatic protection requirements by using a single kind of MOS structure suitable for multi-port electrostatic protection, reducing the number of ESD devices and saving chip area. The MOS structure suitable for multi-port electrostatic protection will be described in the following embodiments.

[0029] Please refer to Figure 1 and Figure 2 , Figure 1 shows a cross-sectional view of a MOS structure suitable for multi-port electrostatic protection provided by an embodiment of the present application, Figure 2 showsFigure 1 A top view of the corresponding structure.

[0030] As shown in FIG. 1 and FIG. 2, the structure comprises at least a substrate 1, an electrical isolation layer 2, a P-type well 3, a first N-type well 4.1, a second N-type well 4.2, a gate 5, a source 6, a drain 7, a first bulk 8, a second bulk 9, a first N-type heavily doped region 10, a second heavily doped region 11, a third heavily doped region 12, a fourth N-type heavily doped region 13, a first P-type heavily doped region 14 and a second P-type heavily doped region 15. Figure 1 Figure 2 As shown in FIG. 1 and FIG. 2, the structure comprises at least a substrate 1, an electrical isolation layer 2, a P-type well 3, a first N-type well 4.1, a second N-type well 4.2, a gate 5, a source 6, a drain 7, a first bulk 8, a second bulk 9, a first N-type heavily doped region 10, a second heavily doped region 11, a third heavily doped region 12, a fourth N-type heavily doped region 13, a first P-type heavily doped region 14 and a second P-type heavily doped region 15.

[0031] The electrical isolation layer 2 is formed on the substrate 1, and the P-type well 3, the first N-type well 4.1 and the second N-type well 4.2 are all located on the electrical isolation layer 2.

[0032] The gate 5 is formed above the P-type well 3, and the source 6 and the drain 7 are symmetrically arranged on both sides of the upper surface of the P-type well 3. The first bulk 8 and the second bulk 9 are symmetrically arranged on both sides of the upper surface of the P-type well 3.

[0033] The upper surface of the first N-type well 4.1 is formed with the first N-type heavily doped region 10 and the first P-type heavily doped region 14; the upper surface of the second N-type well 4.2 is formed with the fourth N-type heavily doped region 13 and the second P-type heavily doped region 15; the second heavily doped region 11 is arranged between the first N-type well 4.1 and the P-type well 3, and the third heavily doped region 12 is arranged between the P-type well 3 and the second N-type well 4.2.

[0034] The first N-type heavily doped region 10 and the fourth N-type heavily doped region 13 are both connected to the anode of the power supply; the gate 5 is connected to the cathode of the power supply; the drain 7 is connected to the I / O port; the first P-type heavily doped region 14 and the second P-type heavily doped region 15 are respectively short-circuited with the I / O port.

[0035] Optionally, in the first N-type well 4.1, the first N-type heavily doped region 10 and the first P-type heavily doped region 14 have a certain interval.

[0036] Optionally, in the second N-type well 4.2, the fourth N-type heavily doped region 13 and the second P-type heavily doped region 15 have a certain interval.

[0037] Optionally, in the P-type well 3, the source 6 and the first bulk 8 have a certain interval, and the drain 7 and the second bulk 9 have a certain interval.

[0038] Optionally, the conductivity type of the substrate 1 is P-type.

[0039] Optionally, the second heavily doped region 11 and the third heavily doped region 12 are N-type heavily doped regions or P-type heavily doped regions. ​

[0040] Optionally, the electrical isolation layer 2 is an N-type deep well or an N-type buried layer.

[0041] Optionally, the source 6 and the drain 7 are N-type heavily doped regions.

[0042] Optionally, the first body region 8 and the second body region 9 are N-type heavily doped regions.

[0043] In summary, the application provides a multi-port electrostatic protection MOS structure, P-type heavily doped regions are introduced into the first N-type well and the second N-type well and are short-circuited with I / O ports, N-type heavily doped regions are introduced into the adjacent N-type well and P-type well and are floating, there is an NPN current channel formed by the drain, the P-type well and the source for the I / O port to the power cathode (GND terminal), there is a PN Diode current channel formed by the body region, the P-type well and the drain for the power cathode to the I / O port, there is a PN Diode current channel formed by the first N-type heavily doped region, the N-type well and the first P-type heavily doped region for the I / O port to the power anode (VDD), there is an NPN current channel formed by the first N-type heavily doped region, the N-type well, the P-type well and the drain for the power anode to the I / O port, there is an NPN current channel formed by the first N-type heavily doped region, the N-type well, the second heavily doped region, the P-type well and the source for the power anode to the power cathode, there is a PN Diode current channel formed by the body region, the P-type well, the second heavily doped region, the N-type well and the first N-type heavily doped region for the power cathode to the power anode, realizing all-around protection among the power anode, the power cathode and the I / O port; in addition, compared with the related art which sets multiple ESD devices corresponding to the I / O port to the power cathode, the I / O port to the power anode and the power anode to the power cathode, the application can meet the above multi-port electrostatic protection requirement through one electrostatic protection MOS structure, reducing the number of ESD devices and saving the chip area.

[0044] In addition, in advanced processes, metal silicide process is often used, the metal silicide process involves that there is a metal surface layer between the Drain and the Gate, under the process, the metal surface layer forms metal silicide (such as Figure 3 as shown in the position 301 not forming metal silicide), the formed metal silicide can cause the following problems.

[0045] The surface resistance is reduced, the melting point is lowered, and under the ESD condition, the current is prone to go to the position 301, causing the region to heat and burn out, and the failure voltage can be less than the trigger voltage, causing the multi-finger device composed of the structure to open unevenly, and the like, reducing the ESD protection performance. Therefore, it needs to be explained that in the embodiment of the application, the metal between the Drain and the Gate is removed to improve the electrostatic protection capability, prevent the formation of metal silicide, and avoid the above problems.

[0046] Obviously, the above-mentioned embodiments are only examples for clearly illustrating the present application, but not limitation to the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, it is not necessary and also impossible to enumerate all the embodiments. The changes or variations derived from the above are still within the protection scope of the present application.

Claims

1. A MOS structure suitable for multi-port electrostatic protection, characterized in that, The application relates to a substrate, an electrical isolation layer, a P-type well, a first N-type well, a second N-type well, a gate, a source, a drain, a first body region, a second body region, a first N-type heavily doped region, a second heavily doped region, a third heavily doped region, a fourth N-type heavily doped region, a first P-type heavily doped region and a second P-type heavily doped region. The electrical isolation layer is formed on the substrate, and the P-type well, the first N-type well and the second N-type well are located on the electrical isolation layer. The gate is formed above the P-type well, the source and the drain are symmetrically arranged on the upper surface of the P-type well, and the first body region and the second body region are symmetrically arranged on the upper surface of the P-type well. The upper surface of the first N-type well is formed with the first N-type heavily doped region and the first P-type heavily doped region, the upper surface of the second N-type well is formed with the fourth N-type heavily doped region and the second P-type heavily doped region, the second heavily doped region is arranged between the first N-type well and the P-type well, and the third heavily doped region is arranged between the P-type well and the second N-type well. The first body region is arranged outside the source away from the gate, the second body region is arranged outside the drain away from the gate, the first P-type heavily doped region is arranged outside the first N-type heavily doped region, and the second P-type heavily doped region is arranged outside the fourth N-type heavily doped region. The first N-type heavily doped region and the fourth N-type heavily doped region are connected to the anode of a power supply, the gate is connected to the cathode of the power supply, the drain is connected to an I / O port, and the first P-type heavily doped region and the second P-type heavily doped region are respectively short-circuited with the I / O port. In the first N-type well, the first N-type heavily doped region and the first P-type heavily doped region have a certain interval.

2. The multi-port electrostatically protected MOS structure of claim 1, wherein, In the second N-type well, the fourth N-type heavily doped region and the second P-type heavily doped region have a certain interval.

3. The multi-port electrostatically protected MOS structure of claim 1, wherein, In the P-type well, the source and the first body region have a certain interval, and the drain and the second body region have a certain interval.

4. The multi-port electrostatically protected MOS structure of claim 1, wherein, The conductivity type of the substrate is P-type.

5. The multi-port electrostatically protected MOS structure of claim 1, wherein, The second heavily doped region and the third heavily doped region are N-type heavily doped regions or P-type heavily doped regions.

6. The multi-port electrostatically protected MOS structure according to any one of claims 1 to 5, wherein, The electrical isolation layer is an N-type deep well or an N-type buried layer.

7. The multi-port electrostatically protected MOS structure according to any one of claims 1 to 5, wherein, The source and the drain are N-type heavily doped regions.

8. The multi-port electrostatically protected MOS structure according to any one of claims 1 to 5, wherein, The first body region and the second body region are N-type heavily doped regions.

9. The multi-port electrostatically protected MOS structure according to any one of claims 1 to 5, wherein, ​

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