A gate device, a memory device and a method for preparing the same

Abstract

An embodiment of the present invention discloses a selector, and the selector includes: a selection layer, the material of the selection layer includes a two-dimensional Bi2O2X material, where X is selected from at least one of S, Se, and Te. By using the two-dimensional Bi2O2X material as the selection layer, the present invention utilizes its out-of-plane unipolar resistive switching behavior to realize the function of the selection layer, and can achieve good bidirectional conduction characteristics. Due to the characteristics of two-dimensional materials, the aspect ratio of the device can be well reduced, which is beneficial to the high density of the device. In addition, the two-dimensional Bi2O2X material itself has insulating properties and has a low leakage current in the off state. At the same time, the device performance can be controlled by adjusting the oxygen vacancies and X vacancies in the material, and the selection layer has better control freedom.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a gate, a memory and a preparation method thereof. Background Art

[0002] The gate is an important digital circuit structure and an important component of many devices such as field programmable gate arrays (FPGAs) and memories. It directly affects the speed, power consumption and other performance of the devices. The three-dimensional (3D) memory using gates is a memory device used to store information in modern information technology and has great prospects in terms of ultra-high integration density. However, the leakage path in the 3D memory reduces its performance, increases the overall power consumption, and limits the scale of the 3D memory. As the storage density gradually increases, how to optimize and improve the gate and the performance of the 3D memory using gates have become important research directions in this field. Summary of the invention

[0003] In view of this, an embodiment of the present invention provides a gate, a memory and a method for manufacturing the same to solve at least one problem in the background technology.

[0004] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0005] An embodiment of the present invention provides a gate, which includes: a gate layer, wherein a material of the gate layer includes a two-dimensional Bi2O2X material, wherein X is selected from at least one of S, Se, and Te.

[0006] In the above solution, the material of the gating layer includes two-dimensional Bi2O2Se material.

[0007] In the above solution, the threshold voltage of the gating layer is less than 4V.

[0008] In the above solution, the thickness of the gating layer is less than 10 nm.

[0009] An embodiment of the present invention further provides a memory, which includes the gate described in the above solution.

[0010] In the above solution, the memory includes:

[0011] A first conductive line extending along a first direction;

[0012] a gating layer stacked on the first conductive line and extending along a first direction, wherein the gating layer is a layered gating device;

[0013] a second conductive line extending along a second direction, wherein the first direction intersects the second direction;

[0014] A storage unit is located between the selection layer and the second conductive line and extends along a third direction, wherein the third direction is perpendicular to the first direction and the second direction.

[0015] The embodiment of the present invention further provides a method for preparing a gate, comprising:

[0016] A gating layer is formed, wherein the gating layer includes a two-dimensional Bi2O2X material, wherein X is selected from at least one of S, Se, and Te.

[0017] In the above solution, the material of the gating layer includes two-dimensional Bi2O2Se material.

[0018] In the above solution, the threshold voltage of the gating layer is less than 4V.

[0019] In the above solution, the thickness of the gating layer is less than 10 nm.

[0020] An embodiment of the present invention further provides a method for preparing a memory, comprising:

[0021] forming a first conductive line material layer, wherein the first conductive line material layer is used to form a first conductive line extending along a first direction;

[0022] Forming a gate material layer and a memory cell material layer stacked along a third direction on the first conductive line material layer, wherein the gate material layer comprises a two-dimensional Bi2O2X material, wherein X is selected from at least one of S, Se, and Te, and the gate material layer and the memory cell material layer are used to form a gate layer and a memory cell;

[0023] A second conductive line extending along a second direction is formed on the storage unit; wherein,

[0024] The first direction intersects with the second direction, and the third direction is perpendicular to the first direction and the second direction.

[0025] In the above solution, the gating material layer and the memory cell material layer are used to form the gating layer and the memory cell, including:

[0026] The gating material layer and the memory cell material layer are used to form a gating layer and a plurality of memory cells, and the plurality of memory cells are located on the same gating layer.

[0027] The embodiment of the present invention uses a two-dimensional Bi2O2X material as a gating layer, and uses its unipolar resistive switching behavior in the out-of-plane direction to realize the function of the gating layer, which can achieve good bidirectional conduction characteristics. Due to the characteristics of the two-dimensional material, the aspect ratio of the device can be well reduced, which is conducive to the high density of the device. In addition, the two-dimensional Bi2O2X material itself has insulating properties and has a lower leakage current in the off state. At the same time, the device performance can be controlled by adjusting the oxygen vacancies and X vacancies in the material, and the gating layer has better control freedom.

[0028] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a structural schematic diagram of a memory in the related art;

[0030] Figure 2 A schematic diagram of the structure of a memory provided by an embodiment of the present invention;

[0031] Figure 3 Schematic diagram of the conduction principle of two-dimensional Bi2O2X material;

[0032] Figure 4 A schematic diagram of the structure of a memory provided by another embodiment of the present invention;

[0033] Figure 5 A schematic diagram of a process for preparing a memory provided by an embodiment of the present invention;

[0034] Figures 6a to 6f A schematic diagram of the structure of a memory during the preparation process provided by an embodiment of the present invention.

[0035] Reference numerals:

[0036] 110 - bit line; 111 - word line; 112 - selection layer; 113 - storage unit;

[0037] 210-first conductive line; 210'-first conductive line material layer; 211-second conductive line; 211'-second conductive line material layer; 212-selection layer; 212'-selection material layer; 213-storage unit; 213'-storage unit material layer; 213"-storage unit structure; 221-first electrode layer; 221'-first electrode material layer; 222-storage layer; 222'-storage material layer; 223-second electrode layer; 223'-second electrode material layer;

[0038] Substrate-310; two-dimensional Bi2O2X material-311; hill-like structure-312. DETAILED DESCRIPTION

[0039] The exemplary embodiments disclosed in the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0040] In the following description, a large number of specific details are given to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0041] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0042] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present invention necessarily has the first element, component, region, layer or part.

[0043] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0044] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0045] As used in the description below, the term "three-dimensional memory" refers to a semiconductor device having memory cells arranged vertically on a laterally oriented substrate so that the number of memory cells increases in the vertical direction relative to the substrate. As used herein, the term "vertical / vertically" means nominally perpendicular to the lateral surface of the substrate.

[0046] like Figure 1As shown, in the related art, the three-dimensional memory is mainly a three-dimensional cross-point architecture, in which the gating layer 112 and the storage unit 113 are located at the intersection of the bit line (BL) 110 and the word line (WL) 111 that intersect each other vertically. For phase change memory, resistive random access memory, and magnetic random access memory based on the cross-point structure, the leakage current problem in the cross array is the main obstacle to achieving high-density integration. The development of a universal gating layer with high fatigue characteristics and high uniformity is of great significance for realizing the high-density three-dimensional cross array integration of the above-mentioned memory. For advanced gating layer materials, it is not only required to have a good switching ratio, that is, a large on-state resistance to meet the requirements of large operating current, and a low off-state resistance to meet the requirements of small leakage, but also the gating layer material is required to have good fatigue characteristics, that is, the number of repeated switches must match the fatigue characteristics of the storage material, otherwise the stored information will be lost and the device will fail. In addition, for the continuous evolution of advanced process nodes, our gating layer is also required to be as thin and small as possible. In addition, the requirement for the gating layer is that its switching speed should be as fast as possible, otherwise it will affect the operating speed of the device.

[0047] Current 1S1R (one-select-one-resistance) phase change memory or resistive memory all use an ovonic threshold switching (OTS) as a gating layer unit, but the OTS gating layer unit has disadvantages such as high thickness, large leakage current, and high threshold voltage.

[0048] Based on this, an embodiment of the present invention provides a gate, such as Figure 2 As shown, the gate includes: a gate layer 212, the material of the gate layer 212 includes a two-dimensional Bi2O2X material, wherein X is selected from at least one of S, Se, and Te.

[0049] The embodiment of the present invention further provides a memory, comprising the gate described in the above solution, such as Figure 2 As shown, the memory includes: a first conductive line 210 extending along a first direction; a selection layer 212 stacked on the first conductive line 210 and extending along the first direction, the selection layer 212 is a layered selection device; a second conductive line 211 extending along a second direction, the first direction intersecting with the second direction; a storage unit 213 located between the selection layer 212 and the second conductive line 211 and extending along a third direction, the third direction being perpendicular to the first direction and the second direction.

[0050] In actual operation, the first conductive line 210 and the second conductive line 211 can be used as a word line and a bit line, respectively. For example, when the first conductive line 210 is a word line, the second conductive line 211 is a bit line, and when the first conductive line 210 is a bit line, the second conductive line 211 is a word line. The first conductive line 210 and the second conductive line 211 can be composed of 20nm / 20nm equal width (line / space, L / S) conductive lines formed after a patterning process. The material of the first conductive line and the second conductive line may include a conductive material, and the conductive material includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide or any combination thereof. In some specific embodiments, the material of the first conductive line and the second conductive line is tungsten.

[0051] In some embodiments, the first direction and the second direction may be perpendicular to each other.

[0052] The embodiment of the present invention uses a two-dimensional Bi2O2X material as a gating layer, and uses its unipolar resistive switching behavior in the out-of-plane direction to realize the function of the gating layer, which can achieve good bidirectional conduction characteristics. Due to the characteristics of the two-dimensional material, the aspect ratio of the device can be well reduced, which is conducive to the high density of the device. In addition, the two-dimensional Bi2O2X material itself has insulating properties and has a lower leakage current in the off state. At the same time, the device performance can be controlled by adjusting the oxygen vacancies and X vacancies in the material, and the gating layer has better control freedom.

[0053] In some embodiments, the material of the gating layer includes a two-dimensional Bi2O2Se material.

[0054] Attached Figure 3 Schematic diagram of the conduction principle of two-dimensional Bi2O2X materials, as shown in the attached figure. Figure 3As shown, a two-dimensional Bi2O2X material 311 is deposited on the surface of a substrate 310, and the material of the substrate can be, for example, SiO2 / Si, and an electric field in a vertical direction is formed in a local area of ​​the two-dimensional Bi2O2X material 311. The two-dimensional Bi2O2X material 311 has unique electrical properties in the out-of-plane direction at the nanoscale, that is, under the action of an electric field in the vertical direction, a nanoscale hill-like structure 312 along the direction of the electric field will be formed on the surface of the two-dimensional Bi2O2X material 311. These unique changes in the nanoscale atomic structure will cause a huge bend in the energy band structure of the electrons in the region, thereby realizing a nano-conductive channel, so that the originally insulating two-dimensional Bi2O2X material 311 is turned on in a local area along the direction of the electric field outside the plane, thereby realizing a good resistive switching behavior. As the electric field is removed, these formed hill-like structures 312 will recover quickly, thereby returning to the initial state. This conduction behavior of the two-dimensional Bi2O2X material 311 is independent of the direction of the electric field, similar to an OTS device, and can achieve good bidirectional conduction characteristics. And compared to OTS, due to the characteristics of the two-dimensional material itself, it can be several atomic layers thick, so for the device, the aspect ratio can be well reduced, which is conducive to the high density of the device. In addition, the two-dimensional Bi2O2X material 311 material itself has insulating properties. When the electric field strength is higher than a certain threshold, that is, when a hill-like atomic structure is formed, a conduction path will be formed. Therefore, in the off state, the gating layer of this material will have a lower leakage current. Effective regulation of device performance can be achieved only through regulation at the atomic layer level. In addition to the participation of electrons in conduction, the dynamic balance between the movement of oxygen vacancies and X (S, Se or Te) vacancies under the action of the electric field and the generation of Joule heat jointly contributes to the conduction process of the gating layer in the on state, so this gating layer has better control freedom.

[0055] In some embodiments, the threshold voltage of the gating layer is less than 4V, for example, 3.5V, 2.5V, and 1.5V. The current OTS gating layer realizes the on-state current based on the transition of electrons between charge traps, but due to the single carrier and the limitation of trap density, the general on-state current is too low, making it difficult to increase the higher drive current. The threshold voltage of the current OTS gating layer is relatively high, usually higher than 4V, which brings great trouble to the selection and design of peripheral circuits. In addition, the high turn-on voltage also brings huge surge current impact, making our operation of the device uncontrollable. This solution uses a two-dimensional Bi2O2X material as the gating layer, which can achieve stable on / off performance at a lower threshold voltage, increasing the design freedom of the device.

[0056] In some embodiments, the thickness of the gating layer is less than 10nm, for example, 7nm, 4nm, 2nm. The conventional OTS gating layer needs to ensure a certain thickness to meet the low leakage requirement, otherwise the leakage of the device will increase, which will not only cause the problem of misoperation, but also greatly increase the power consumption of the device. At the same time, due to the limitation of the aspect ratio, it will be difficult to continue to reduce the size of the 1S1R memory based on the OTS gating layer, otherwise it will bring huge challenges to the process. This solution uses a two-dimensional Bi2O2X material as the gating layer. Due to the characteristics of the two-dimensional material itself, it can be as thick as several atomic layers. Therefore, for the device, its aspect ratio can be well reduced, which is conducive to the high density of the device. At the same time, effective regulation of device performance can be achieved only through regulation at the atomic layer level.

[0057] In some embodiments, the Bi2O2X material includes oxygen vacancies and X (X is selected from at least one of S, Se, and Te) vacancies. Exemplarily, the concentration of the oxygen vacancies is greater than 0.02 and less than 0.2, and the concentration of the X vacancies is greater than 0.01 and less than 0.1. The concentration of oxygen vacancies and X vacancies is too high, and excessive defects will cause the performance of the two-dimensional Bi2O2X material to decrease. The concentration of oxygen vacancies and X vacancies is too low, which is not conducive to improving the electrical properties of the two-dimensional Bi2O2X material in the out-of-plane direction. The originally insulating two-dimensional Bi2O2X material is turned on in a local area along the electric field direction outside the plane. In addition to the participation of electrons in conduction, the dynamic balance between the movement of oxygen vacancies and Se vacancies under the action of the electric field and the generation of Joule heat contributes to the conduction process of the gate layer in the open state. Therefore, this gate layer has better control freedom. In actual operation, oxygen vacancies and X vacancies can be used to adjust the parameters such as the gate layer threshold voltage, switching ratio, and conductivity.

[0058] In some embodiments, as shown in the attached Figure 2As shown, the storage unit 213 includes a first electrode 221, a storage layer 222, and a second electrode 223 stacked and distributed in sequence along a third direction, wherein the storage layer 222 includes a phase change storage material or a resistive storage material. The materials of the first electrode 221 and the second electrode include a metal material or a carbon-containing material, wherein the metal material includes but is not limited to tungsten or titanium, and the carbon-containing material includes but is not limited to amorphous carbon, carbon nanotubes, or graphene. In some embodiments, the thickness of the first electrode 221 and the second electrode may be 10-50nm, and illustratively, for example, 12nm, 18nm, etc. The first electrode 221 and the second electrode 223 are respectively connected to the gating layer 212 and the second conductive line 211, and the gating layer 212 drives the storage layer to complete data storage or erasure according to the voltage signal on the first conductive line 210 and the second conductive line 211. The phase change storage material includes an alloy based on chalcogenide (chalcogenide glass), such as GST (Ge-Sb-Te) alloy, or includes any other appropriate phase change material. The resistive memory material includes but is not limited to HfOx, AlOx, TaOx, etc., or includes any other appropriate resistive memory material.

[0059] In some embodiments, as shown in the attached Figure 4 As shown, the memory includes: a plurality of storage units 213, and the plurality of storage units 213 are located on the same gating layer 212. The traditional OTS gating layer corresponds to the storage unit one by one, and each gating layer drives the data storage or erasure of a storage unit. When preparing the OTS gating layer, it is necessary to first form an OTS gating material layer, and then form a single OTS gating layer through an additional etching process. On the one hand, the etching process increases the cost and causes pollution or other damage to the device. On the other hand, the adjacent OTS gating layers are too close to each other, which will cause unnecessary crosstalk. The disclosed embodiment uses a two-dimensional Bi2O2X material as a gating layer, and uses its unipolar resistive switching behavior in the out-of-plane direction to realize the function of the gating layer. The gating layer can be formed in one step without the need for an additional etching process; and it has unique out-of-plane electrical properties, which can realize conduction in the area where a vertical electric field exists locally, and other areas still remain in an insulating state. A two-dimensional Bi2O2X gating layer plane can drive multiple storage units in the vertical direction, increasing the integration of the device.

[0060] In some embodiments, the memory further includes: an isolation structure (not shown in the figure), the isolation structure is located between adjacent memory cells and is used to electrically isolate the adjacent memory cells. The isolation structure includes but is not limited to silicon oxide, silicon oxynitride, silicon nitride or a combination thereof.

[0061] The disclosed embodiment also provides a method for preparing a gate, the method comprising: forming a gate layer, the gate layer comprising a two-dimensional Bi2O2X material, wherein X is selected from at least one of S, Se, and Te. The method for forming the gate layer includes but is not limited to a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) process, or a combination thereof.

[0062] The present disclosure also provides a method for preparing a memory. Figure 5 A schematic diagram of a process for preparing a memory device according to an embodiment of the present invention. Figure 5 As shown, the method includes:

[0063] Step 501: forming a first conductive line material layer, wherein the first conductive line material layer is used to form a first conductive line extending along a first direction;

[0064] Step 502: forming a gate material layer and a memory cell material layer stacked along a third direction on the first conductive line material layer, wherein the gate material layer comprises a two-dimensional Bi2O2X material, wherein X is selected from at least one of S, Se, and Te, and the gate material layer and the memory cell material layer are used to form a gate layer and a memory cell;

[0065] Step 503: Form a second conductive line on the storage unit and extending along a second direction; wherein the first direction intersects with the second direction, and the third direction is perpendicular to the first direction and the second direction.

[0066] In some embodiments, the gating layer includes a two-dimensional Bi2O2Se material.

[0067] Next, combine Figures 6a to 6f The memory and the preparation method thereof provided in the embodiment of the present invention are further described in detail.

[0068] The method starts at step 501, such as Figure 6a As shown, a first conductive line material layer 210 ′ is formed, and the first conductive line material layer 210 ′ is used to form a first conductive line 210 extending along a first direction.

[0069] In actual operation, a substrate 310 may be provided first, and the substrate is located below the process execution surface, so as to provide support for the process. Here, the substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

[0070] Then, a first conductive line material layer 210' is formed on the substrate 310. The material of the first conductive line may include a conductive material, and the conductive material includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide or any combination thereof.

[0071] Next, execute step 502. Figure 6b-6d A gating material layer 212' and a memory cell material layer 213' are formed on the first conductive line material layer 210' and stacked along a third direction. The gating material layer 212' includes a two-dimensional Bi2O2X material, and the X is selected from at least one of S, Se, and Te, for example, including but not limited to a two-dimensional Bi2O2Se material. The gating material layer 212' and the memory cell material layer 213' are used to form the gating layer 212 and the memory cell 213.

[0072] For details, first, see the attached Figure 6b , a gating material layer 212' is formed on the first conductive line material layer 210'. In actual operation, the formation process of the gating material layer 212' includes but is not limited to a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) process or a combination thereof.

[0073] In some embodiments, after forming the gating material layer, it also includes: annealing the gating material layer in a vacuum or a reducing atmosphere. The reducing atmosphere may be, for example, H2. By annealing in a vacuum or a reducing atmosphere, the oxygen vacancies and X (X is selected from at least one of S, Se, and Te) vacancies concentrations of the two-dimensional Bi2O2X material are increased. The originally insulating two-dimensional Bi2O2X material is turned on in a local area along the electric field direction outside the plane. In addition to the participation of electrons in conduction, the dynamic balance between the movement of oxygen vacancies and X vacancies under the action of the electric field and the generation of Joule heat contributes to the conduction process of the gating layer in the open state. Therefore, this gating layer has better control freedom. In actual operation, the gating layer threshold voltage, switching ratio, conductivity and other parameters can be adjusted by oxygen vacancies and X vacancies. Specifically, the concentration of the oxygen vacancies is greater than 0.02 and less than 0.2, and the concentration of the X vacancies is greater than 0.01 and less than 0.1. If the concentration of oxygen vacancies and X vacancies is too high, the defects will lead to the performance degradation of the two-dimensional Bi2O2X material. If the concentration of oxygen vacancies and X vacancies is too low, it will not be conducive to improving the electrical properties of the two-dimensional Bi2O2X material in the out-of-plane direction.

[0074] Next, see Appendix Figure 6c, forming a memory cell material layer 213' on the gating material layer 212'. In some embodiments, the memory cell material layer 213' includes a first electrode material layer 221', a memory material layer 222', and a second electrode material layer 223' stacked and distributed in sequence along a third direction, wherein the memory material layer 222' includes a phase change memory material or a resistive memory material. The first electrode material layer 221', the memory material layer 222', and the second electrode material layer 223' are used to form the first electrode layer 221, the memory layer 222, and the second electrode layer 223, respectively.

[0075] The materials of the first electrode material layer 221' and the second electrode material layer 223' include metal materials or carbon-containing materials, wherein the metal materials include but are not limited to tungsten or titanium, and the carbon-containing materials include but are not limited to amorphous carbon, carbon nanotubes or graphene, etc. In some embodiments, the thickness of the first electrode material layer 221' and the second electrode material layer 223' may be 10-50nm, for example, 12nm, 18nm, etc.

[0076] The phase change memory material includes a chalcogenide-based alloy (chalcogenide glass), such as a GST (Ge-Sb-Te) alloy, or includes any other suitable phase change material. The resistive memory material includes but is not limited to HfOx, AlOx, and TaOx, or includes any other suitable resistive material.

[0077] The first electrode 221 and the second electrode 223 are connected to the gating layer 212 and the second conductive line 211 respectively. The gating layer drives the storage layer to complete data storage or erasure according to the voltage signals on the first conductive line 210 and the second conductive line 211.

[0078] Next, as attached Figure 6d As shown, the memory cell material layer 213', the gating material layer 212' and the first electrode material layer 210' are etched along the first direction, the first electrode material layer 210' becomes a first conductive line 211 extending along the first direction, the gating material layer 212' becomes a gating layer 212, and the memory cell material layer 213' becomes a memory cell structure 213".

[0079] Finally, execute step 503, as shown in the attached Figure 6e and attached Figure 6f As shown, a second conductive line 211 extending along a second direction is formed on the storage unit 213; wherein the first direction intersects with the second direction, and the third direction is perpendicular to the first direction and the second direction.

[0080] Specifically, first of all, as attached Figure 6eAs shown, a second conductive line material layer 211 ′ extending along a second direction is formed on the memory cell structure 213 ″.

[0081] The material of the second conductive line material layer 211 ′ may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.

[0082] Next, the second conductive line material layer 211' and the memory cell structure 213" are etched along the second direction, the second conductive line material layer 211' becomes a second conductive line 211 extending along the second direction, and the memory cell structure 213" becomes a memory cell 213. Specifically, the first electrode material layer 221', the memory material layer 222' and the second electrode material layer 223' become the first electrode layer 221, the memory layer 222 and the second electrode layer 223, respectively.

[0083] In actual operation, before forming the second conductive line material layer 211 ′, a filling material may be used to fill the gaps between the memory cell structures 213 ″.

[0084] In some embodiments, as shown in the attached Figure 6f As shown, the gate material layer 212' and the memory cell material layer 213' are used to form the gate layer 212 and the memory cell 213, including: the gate material layer 212' and the memory cell material layer 213' are used to form the gate layer 212 and a plurality of memory cells 213, and the plurality of memory cells 213 are located on the same gate layer 212. In actual operation, as shown in the attached Figure 6e and 6fAs shown, a second conductive line material layer 211' extending along the second direction is formed on the memory cell structure 213", and the second conductive line material layer 211' and the memory cell structure 213" are etched along the second direction. At this time, the etching process does not need to penetrate the selection layer 212. For example, the surface of the selection layer 212 can be used as an etching stop layer or an etching barrier layer. Traditional OTS selection layers correspond one to one with memory cells, and each selection layer drives the data storage or erasure of a memory cell. When preparing the OTS selection layer, it is necessary to first form an OTS selection material layer, and then form a single OTS selection layer through an additional etching process. On the one hand, the etching process increases the cost and may cause pollution or other damage to the device. On the other hand, the adjacent OTS selection layers are too close to each other, which may cause unnecessary crosstalk. By using two-dimensional Bi2O2Se material as the gating layer and utilizing its unipolar resistive switching behavior in the out-of-plane direction to realize the function of the gating layer, the gating layer can be formed in one step without the need for additional etching processes. It also has unique out-of-plane electrical properties, which can achieve conduction in areas where a vertical electric field exists locally, while other areas remain in an insulating state. A two-dimensional Bi2O2Se gating layer plane can drive multiple storage units in the vertical direction, increasing the integration of the device.

[0085] In some embodiments, the method further includes: forming an isolation structure (not shown in the figure), the isolation structure is located between adjacent memory cells 213, and is used to electrically isolate adjacent memory cells 213. The isolation structure includes but is not limited to one of silicon oxide, silicon oxynitride, and silicon nitride, or a combination thereof.

[0086] In some embodiments, the threshold voltage of the gating layer is less than 4V, for example, 3.5V, 2.5V, and 1.5V. The current OTS gating layer realizes the on-state current based on the transition of electrons between charge traps, but due to the single carrier and the limitation of trap density, the general on-state current is too low, making it difficult to increase the higher drive current. The threshold voltage of the current OTS gating layer is relatively high, usually higher than 4V, which brings great trouble to the selection and design of peripheral circuits. In addition, the high turn-on voltage also brings huge surge current impact, making our operation of the device uncontrollable. This solution uses a two-dimensional Bi2O2X material as the gating layer, which can achieve stable on / off performance at a lower threshold voltage, increasing the design freedom of the device.

[0087] In some embodiments, the thickness of the gating layer is less than 10nm, for example, 7nm, 4nm, 2nm. The conventional OTS gating layer needs to ensure a certain thickness to meet the low leakage requirement, otherwise the leakage of the device will increase, which will not only cause the problem of misoperation, but also greatly increase the power consumption of the device. At the same time, due to the limitation of the aspect ratio, it will be difficult to continue to reduce the size of the 1S1R memory based on the OTS gating layer, otherwise it will bring huge challenges to the process. This solution uses a two-dimensional Bi2O2X material as the gating layer. Due to the characteristics of the two-dimensional material itself, it can be as thick as several atomic layers. Therefore, for the device, its aspect ratio can be well reduced, which is conducive to the high density of the device. At the same time, effective regulation of device performance can be achieved only through regulation at the atomic layer level.

[0088] In summary, the embodiment of the present invention uses a two-dimensional Bi2O2X material as a gating layer, and uses its unipolar resistive switching behavior in the out-of-plane direction to realize the function of the gating layer, which can achieve good bidirectional conduction characteristics. Due to the characteristics of the two-dimensional material, the aspect ratio of the device can be well reduced, which is conducive to the high density of the device. In addition, the two-dimensional Bi2O2X material itself has insulating properties and has a lower leakage current in the off state. At the same time, the device performance can be controlled by adjusting the oxygen vacancies and X vacancies in the material, and the gating layer has better control freedom.

[0089] It should be noted that the gate, the method for preparing the gate, the memory using the gate, and the method for preparing the memory provided by the present invention belong to the same concept; the gate and the method for preparing the gate, and the memory and the method for preparing the memory provided in the embodiments of the present disclosure can be applied to any integrated circuit including the structure. The various technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict. Those skilled in the art can change the order of the steps of the above-mentioned formation method without leaving the protection scope of the present disclosure. The various steps in the embodiments of the present disclosure can be executed simultaneously or in a sequential order without conflict.

[0090] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A gate, characterized in that: include: A gating layer, wherein the material of the gating layer comprises a two-dimensional Bi2O2X material, wherein X is selected from at least one of S and Te, and the thickness of the gating layer is less than or equal to 7 nm; The Bi2O2X material includes oxygen vacancies and X vacancies, the concentration of the oxygen vacancies is greater than 0.02 and less than 0.2, and the concentration of the X vacancies is greater than 0.01 and less than 0.

1.

2. The gate according to claim 1, characterized in that: The threshold voltage of the gating layer is less than 4V.

3. A memory, characterized in that: The memory comprises the gate according to any one of claims 1-2.

4. The memory according to claim 3, characterized in that: include: A first conductive line extending along a first direction; a gating layer stacked on the first conductive line and extending along a first direction, wherein the gating layer is a layered gating device; a second conductive line extending along a second direction, wherein the first direction intersects the second direction; A storage unit is located between the selection layer and the second conductive line and extends along a third direction, wherein the third direction is perpendicular to the first direction and the second direction.

5. A method for preparing a gate, characterized in that: include: Forming a gating layer, wherein the gating layer comprises a two-dimensional Bi2O2X material, wherein X is selected from at least one of S and Te, and the thickness of the gating layer is less than or equal to 7 nm; The Bi2O2X material includes oxygen vacancies and X vacancies, the concentration of the oxygen vacancies is greater than 0.02 and less than 0.2, and the concentration of the X vacancies is greater than 0.01 and less than 0.

1.

6. The preparation method according to claim 5, characterized in that: The threshold voltage of the gating layer is less than 4V.

7. A method for preparing a memory, characterized in that: include: forming a first conductive line material layer, wherein the first conductive line material layer is used to form a first conductive line extending along a first direction; A gate material layer and a memory cell material layer stacked along a third direction are formed on the first conductive line material layer, wherein the gate material layer comprises a two-dimensional Bi2O2X material, wherein X is selected from at least one of S and Te, and the Bi2O2X material comprises oxygen vacancies and X vacancies, wherein the concentration of the oxygen vacancies is greater than 0.02 and less than 0.2, and the concentration of the X vacancies is greater than 0.01 and less than 0.1, and the gate material layer and the memory cell material layer are used to form a gate layer and a memory cell, and the thickness of the gate layer is less than or equal to 7 nm; A second conductive line extending along a second direction is formed on the storage unit; wherein, The first direction intersects with the second direction, and the third direction is perpendicular to the first direction and the second direction.

8. The preparation method according to claim 7, characterized in that: The gating material layer and the memory cell material layer are used to form a gating layer and a memory cell, and include: The gating material layer and the memory cell material layer are used to form a gating layer and a plurality of memory cells, and the plurality of memory cells are located on the same gating layer.

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