Semiconductor devices

Abstract

The purpose is to provide a technology capable of reducing the on-voltage. A semiconductor device comprises: a carrier storage layer; an upper active portion as an upper polysilicon layer, which is arranged on a first insulating film along the inner wall of the upper portion of a trench penetrating the carrier storage layer and is connected to a gate electrode; and a lower polysilicon layer, which is arranged on a second insulating film along the inner wall of the lower portion of the trench, and a third insulating film is arranged between the lower polysilicon layer and the upper active portion. The lower end of the upper active portion is located below the lower end of the carrier storage layer.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] Various technologies have been proposed for semiconductor devices such as insulated gate bipolar transistors (hereinafter sometimes referred to as "IGBTs"). For example, Patent Document 1 proposes an IGBT in which a two-layer gate is used as a gate of the IGBT, and the two-layer gate includes an upper active portion connected to a gate electrode and a lower dummy portion connected to an emitter electrode and insulated from the upper active portion in a trench.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2017-147431

[0004] The above-mentioned IGBT with two gate layers has the following advantages, that is, even if the hot carriers of dynamic avalanche (DA) generated by the electric field near the bottom of the trench are injected into the gate oxide film of the lower dummy portion at the time of cutoff, the gate characteristics will not be degraded. However, such an IGBT has the problem of high on-voltage. Summary of the invention

[0005] Therefore, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a technology capable of reducing the on-voltage.

[0006] The semiconductor device of the present invention comprises: a semiconductor substrate provided with an emitter electrode and a gate electrode; a first conductive type carrier storage layer arranged on the upper surface side of the semiconductor substrate; a second conductive type base layer arranged on the upper surface side of the carrier storage layer; a first conductive type source layer arranged on the upper surface side of the base layer; an upper active portion as an upper polysilicon layer, arranged on a first insulating film along the inner wall of the upper portion of a trench and connected to the gate electrode, The groove penetrates the source layer, the base layer and the carrier accumulation layer; and a lower layer of polysilicon is arranged on a second insulating film along the inner wall of the lower portion of the groove, and a third insulating film is arranged between the lower layer of polysilicon and the upper layer active portion. The lower layer of polysilicon is any one of a lower layer dummy portion connected to the emitter electrode, a lower layer active portion connected to the gate electrode, and an electrically floating lower layer floating portion, and the lower end of the upper layer active portion is located below the lower end of the carrier accumulation layer.

[0007] Effects of the Invention

[0008] According to the present invention, the lower end of the upper active portion is located below the lower end of the carrier storage layer, so that the on-voltage can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0010] Figure 2 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0011] Figure 3 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0012] Figure 4 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0013] Figure 5 This is a diagram for explaining conduction loss.

[0014] Figure 6 This is a diagram for explaining conduction loss.

[0015] Figure 7 This is a diagram for explaining conduction loss.

[0016] Figure 8 It is a cross-sectional view showing a first related method of manufacturing a semiconductor device.

[0017] Fig. 9 It is a cross-sectional view showing a second related method of manufacturing a semiconductor device.

[0018] Fig.10 It is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment.

[0019] Fig.11 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0020] Fig.12 It is a cross-sectional view showing the structure of a semiconductor device according to Modification 1.

[0021] Fig.13 It is a cross-sectional view showing the structure of a semiconductor device according to Modification 1.

[0022] Fig.14 It is a cross-sectional view showing the structure of a semiconductor device according to Modification Example 2.

[0023] Fig.15 It is a cross-sectional view showing the structure of a semiconductor device according to Modification 3.

[0024] Fig.16 It is a cross-sectional view showing the structure of a semiconductor device according to the third embodiment.

[0025] Fig.17 It is a cross-sectional view showing the structure of a semiconductor device according to a fourth embodiment.

[0026] Fig.18 It is a cross-sectional view showing the structure of a semiconductor device according to Modification 1.

[0027] Fig.19 It is a cross-sectional view showing the structure of a semiconductor device according to Modification 1.

[0028] Fig. 20 It is a cross-sectional view showing the structure of a semiconductor device according to Modification 1 of Embodiments 1 to 4. DETAILED DESCRIPTION

[0029] Hereinafter, the embodiments will be described with reference to the accompanying drawings. The features described in the following embodiments are illustrative, and not all features are necessary. In addition, in the description shown below, the same structural elements are marked with the same or similar reference numerals in multiple embodiments, and mainly different structural elements are described. In addition, in the description recorded below, specific positions and directions such as "upper", "lower", "left", "right", "table" or "back" are not necessarily consistent with the directions during actual implementation.

[0030] In addition, the fact that a certain part has a higher concentration than other parts means, for example, that the average value of the concentration of the certain part is higher than the average value of the concentration of other parts. Conversely, the fact that a certain part has a lower concentration than other parts means, for example, that the average value of the concentration of the certain part is lower than the average value of the concentration of other parts. In addition, the following description assumes that the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. In addition, n - Indicates that the impurity concentration is lower than n, n + indicates that the impurity concentration is higher than n. Similarly, p - Indicates that the impurity concentration is lower than p, p + Indicates that the impurity concentration is higher than p.

[0031] <Implementation method 1>

[0032] <Structure>

[0033] Figure 1 1 is a cross-sectional view showing the structure of the semiconductor device according to the present embodiment 1. Hereinafter, the structure of the semiconductor device including the semiconductor element 100 which is an IGBT will be mainly described.

[0034] The semiconductor element 100 has a semiconductor substrate. The semiconductor substrate may be formed of a common semiconductor wafer or an epitaxial growth layer. An emitter electrode 1 and a gate electrode 15 are provided on the semiconductor substrate. In the first embodiment, the emitter electrode 1 and the gate electrode 15 are arranged on or above the semiconductor substrate.

[0035] The semiconductor substrate comprises p + Type contact layer 3, n + type source layer 4, p-type base layer 5, n-type carrier storage layer 6, n - The semiconductor substrate has an n-type drift layer 9, an n-type buffer layer 10 and a p-type collector layer 11. Figure 1 In the + Type source layer 4 and p + The range from the p-type contact layer 3 to the p-type collector layer 11 .

[0036] exist Figure 1 In, n + Type source layer 4 and p + The upper end of the p-type contact layer 3 in the paper is the upper surface of the semiconductor substrate as the first main surface, and the lower end of the p-type collector layer 11 in the paper is the lower surface of the semiconductor substrate as the second main surface. The upper surface of the semiconductor substrate is the main surface on the front side of the semiconductor element 100, and the lower surface of the semiconductor substrate is the main surface on the back side of the semiconductor element 100. The semiconductor element 100 has an n-type contact layer 3 between the upper surface and the lower surface opposite to the upper surface. - Type drift layer 9.

[0037] As described in detail later, a trench 7 is arranged on the upper surface side of the semiconductor substrate, an upper active portion 13 as upper polysilicon is arranged in the upper portion of the trench 7, and a lower dummy portion 14 as lower polysilicon is arranged in the lower portion of the trench 7. In the following description, the portion of the trench 7 on the upper active portion 13 side is sometimes referred to as an active trench.

[0038] like Figure 1 As shown, on the upper surface side of the semiconductor substrate, specifically, on n - The n-type drift layer 9 is provided with n-type impurities having a concentration ratio n - The n-type drift layer 9 is high in the n-type carrier storage layer 6. - The n-type drift layer 9 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity. - The concentration of the n-type impurity in the drift layer 9 is, for example, 1.0E+12 / cm 3 ~1.0E+15 / cm 3 The n-type carrier storage layer 6 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity. The concentration of the n-type impurity in the n-type carrier storage layer 6 is, for example, 1.0E+13 / cm3 ~1.0E+17 / cm 3 It is preferred that the concentration of the n-type impurity in the n-type carrier storage layer 6 is lower than n - The concentration of n-type impurities in the drift layer 9 is, for example, about 1 to 2 orders of magnitude higher. By configuring the n-type carrier storage layer 6, the conduction loss when the current flows can be reduced. - The type drift layer 9 is collectively referred to as the drift layer.

[0039] The n-type carrier storage layer 6 is formed, for example, by introducing n-type impurities into the n-type carrier storage layer. - Ion implantation is performed on the semiconductor substrate of the n-type drift layer 9, and then annealing is performed to make the implanted n-type impurities - The type drift layer 9 is diffused into the semiconductor substrate.

[0040] The p-type base layer 5 is disposed on the upper surface side of the n-type carrier storage layer 6. The p-type base layer 5 is in contact with the gate oxide film 8 of the active trench.

[0041] An n-type base layer is disposed on the upper surface of the p-type base layer 5 so as to be in contact with the gate oxide film 8 of the active trench. + type source layer 4, and p + Type contact layer 3. + Type source layer 4 and p + The n type contact layer 3 constitutes the upper surface of the semiconductor substrate. + The type source layer 4 is arranged on both sides of the trench 7 in the width direction so as to be in contact with the gate oxide film 8. + The type contact layer 3 is arranged between adjacent trenches 7. + Type source layer 4 and p + The contact layer 3 can also be formed along the extension direction of the groove 7 ( Figure 1 The depth direction) is alternately arranged.

[0042] In addition, p + The p-type contact layer 3 is a region where the concentration of p-type impurities is higher than that of the p-type base layer 5. + When distinguishing between the p-type contact layer 3 and the p-type base layer 5, they can be referred to separately or the p-type base layer 5 can be referred to as the p-type contact layer 3 and the p-type base layer 5. + The p-type contact layer 3 and the p-type base layer 5 are collectively referred to as a p-type base layer.

[0043] In addition, the semiconductor device 100 is - The n-type drift layer 9 is provided with an n-type impurity having a concentration ratio n -The n-type buffer layer 10 is formed to prevent the depletion layer extending from the p-type base layer 5 to the lower surface from punching through when the semiconductor element 100 is in the off state. The n-type buffer layer 10 can be formed by, for example, phosphorus (P) or protons (H + ) can be formed by the injection of phosphorus (P) and protons (H + ) are formed by the injection of both. In addition, the semiconductor element 100 may be formed without configuring the n-type buffer layer 10. Figure 1 The region of the n-type buffer layer 10 shown is also provided with n - The structure of the n-type drift layer 9 can also be formed by forming the n-type buffer layer 10 and the n-type - The type drift layer 9 is collectively referred to as the drift layer.

[0044] The semiconductor element 100 includes a p-type collector layer 11 disposed on the lower surface side of the n-type buffer layer 10. - A p-type collector layer 11 is arranged between the p-type drift layer 9 and the lower surface of the semiconductor substrate.

[0045] like Figure 1 As shown, the semiconductor element 100 is configured to penetrate the p-type base layer 5 from the upper surface of the semiconductor substrate to reach the n-type base layer 5. - The trench 7 of the n type drift layer 9. Specifically, the trench 7 is n + The p-type source layer 4, the p-type base layer 5, and the n-type carrier storage layer 6 penetrate each other.

[0046] The upper active portion 13 as the upper polysilicon is arranged on the first insulating film along the inner wall of the upper portion of the trench 7. The lower dummy portion 14 as the lower polysilicon is arranged on the second insulating film along the inner wall of the lower portion of the trench 7, and a third insulating film is arranged between the lower dummy portion 14 and the upper active portion 13. That is, the upper active portion 13 and the lower dummy portion 14 are electrically insulated by the third insulating film.

[0047] The upper active portion 13 is connected to the gate electrode 15 , and the first insulating film and the third insulating film are each included in the gate oxide film 8 .

[0048] The lower dummy portion 14 is connected to the emitter electrode 1. As in the first embodiment, when the lower polysilicon is the lower dummy portion 14, the second insulating film between the inner wall of the lower portion of the trench 7 and the lower dummy portion 14 does not have the function of a normal gate oxide film. However, in the modified example described later, since the lower polysilicon is sometimes not the lower dummy portion 14 but the lower active portion, the following description is made assuming that the second insulating film is also included in the gate oxide film 8 for convenience.

[0049] As described above, the semiconductor device according to the first embodiment has a two-layer gate A / D composed of an upper active portion 13 and a lower dummy portion 14 that are electrically separated. Furthermore, the lower end of the upper active portion 13 is located below the lower end of the n-type carrier storage layer 6. In addition, in the first embodiment, the depth La of the upper active portion 13 is greater than or equal to 1.5 times the depth Lb of the p-type base layer 5, but is not limited thereto. In addition, the depth corresponds to the size from the upper surface of the semiconductor substrate to the lower end of the structural element.

[0050] The upper portion of the upper active portion 13 faces the p-type base layer 5 via the first insulating film of the gate oxide film 8. When a gate drive voltage is applied to the upper active portion 13, a channel is formed in the p-type base layer 5 in contact with the gate oxide film 8 in the active trench.

[0051] like Figure 1 As shown, the interlayer insulating film 2 is disposed on the upper active portion 13. The emitter electrode 1 is disposed on a region of the upper surface of the semiconductor substrate where the interlayer insulating film 2 is not disposed and on the interlayer insulating film 2.

[0052] like Figure 1 As shown, the emitter electrode 1 and n + Type source layer 4, p + The type contact layer 3 and the lower dummy portion 14 are in ohmic contact with n + Type source layer 4, p + The emitter electrode 1 is electrically connected to the lower dummy portion 14 in the other cross sections.

[0053] The emitter electrode 1 may be made of, for example, an aluminum alloy such as an aluminum silicon alloy (Al-Si alloy), or may be made of a multilayer metal film formed by chemical plating or electrolytic plating on an electrode formed of an aluminum alloy. The plating formed by chemical plating or electrolytic plating may be, for example, a nickel (Ni) plating film. In addition, when there is a tiny area such as between adjacent interlayer insulating films 2 that cannot be well buried by the emitter electrode 1, a tungsten film with better burying properties than the emitter electrode 1 may be arranged in the tiny area, and the emitter electrode 1 is set on the tungsten film.

[0054] In addition, a barrier metal may be provided between the interlayer insulating film 2 and the emitter electrode 1. The barrier metal may be, for example, a conductor containing titanium (Ti) such as titanium nitride, or TiSi which is an alloy of titanium and silicon (Si). + A barrier metal is provided on the n-type semiconductor layer such as the n-type source layer 4. The barrier metal and the emitter electrode 1 may be collectively referred to as an emitter electrode.

[0055] A collector electrode 12 is provided on the lower surface side of the p-type collector layer 11. The collector electrode 12 may be made of an aluminum alloy, an aluminum alloy and a plated film, as with the emitter electrode 1, or may have a structure different from that of the emitter electrode 1. The collector electrode 12 is in ohmic contact with the p-type collector layer 11 and is electrically connected to the p-type collector layer 11.

[0056] <Manufacturing method>

[0057] Next, an example of a method for manufacturing a semiconductor device according to the first embodiment is described. First, a semiconductor device having n is prepared. - The semiconductor substrate may be a semiconductor substrate of an n-type drift layer 9. The semiconductor substrate may be an n-type wafer containing n-type impurities, such as an FZ wafer produced by an FZ (Floating Zone) method or an MCZ wafer produced by an MCZ (Magnetic applied CZochralki) method.

[0058] The concentration of n-type impurities contained in the semiconductor substrate is appropriately selected according to the withstand voltage of the semiconductor device to be manufactured. For example, for a semiconductor device with a withstand voltage of 1200V, the concentration of n-type impurities in the semiconductor substrate is appropriately selected according to the withstand voltage of the semiconductor device to be manufactured. - The concentration of the n-type impurity is adjusted so that the resistivity of the n-type drift layer 9 is about 40 to 120 Ω·cm. In the process of preparing the semiconductor substrate, the entire semiconductor substrate becomes n-type. - The semiconductor element 100 is manufactured by injecting p-type or n-type impurity ions described below from the upper surface side or the lower surface side of such a semiconductor substrate, and then diffusing the impurity ions in the semiconductor substrate by heat treatment or the like, thereby forming a p-type or n-type semiconductor layer on the semiconductor substrate.

[0059] In addition, a region serving as a terminal region is arranged around the cell region in which the semiconductor element 100 is arranged. Below, the manufacturing method of the structure of the cell region of the semiconductor element 100 is mainly described, but the terminal region of the semiconductor element 100 can be manufactured by a known manufacturing method. For example, an FLR (Field Limmiting Ring) having a p-type terminal well layer can also be formed in the terminal region as a withstand voltage retention structure. In this case, the FLR can be formed by injecting p-type impurity ions into the terminal region before processing the cell region of the semiconductor element 100, or by injecting p-type impurity ions into the terminal region simultaneously with the ion implantation of p-type impurities into the cell region of the semiconductor element 100 to form the FLR.

[0060] Next, n-type impurities such as phosphorus (P) are injected from the upper surface side of the semiconductor substrate to form an n-type carrier accumulation layer 6. In addition, p-type impurities such as boron (b) are injected from the upper surface side of the semiconductor substrate to form a p-type base layer 5. The n-type carrier accumulation layer 6 and the p-type base layer 5 are formed in the following manner, that is, after impurity ions are injected into the semiconductor substrate, the impurity ions are diffused by heat treatment. The n-type impurities and the p-type impurities are ion-implanted after masking is performed on the upper surface of the semiconductor substrate, so that the n-type carrier accumulation layer 6 and the p-type base layer 5 are selectively formed on the upper surface side of the semiconductor substrate. Specifically, the n-type carrier accumulation layer 6 and the p-type base layer 5 are formed in the cell area and connected to the p-type terminal well layer in the terminal area. In addition, mask processing is a process in which a resist layer is applied onto a semiconductor substrate and an opening is formed in a specified area of ​​the resist layer using photolithography technology, thereby forming a mask on the semiconductor substrate for performing ion implantation or etching on a specified area of ​​the semiconductor substrate through the opening.

[0061] Next, if Figure 2 As shown in FIG. 2( a ), n-type impurities are selectively implanted into the upper surface side of the p-type base layer 5 in the cell region by mask processing to form an n-type base layer. + The n-type source layer 4. The implanted n-type impurities may be, for example, arsenic (As) or phosphorus (P).

[0062] Then, if Figure 2 As shown in (b), n is formed from the upper surface side of the semiconductor substrate. + The p-type source layer 4, the p-type base layer 5, and the n-type carrier storage layer 6 penetrate to reach the n-type - The trench 7 of the type drift layer 9. In the cell area, the n + The sidewall of the trench 7 through which the type source layer 4 passes constitutes an n + The groove 7 may also be formed by stacking an oxide film such as SiO2, which will serve as a mask, on a semiconductor substrate, forming an opening in the oxide film at a portion where the groove 7 is to be formed by masking, and etching the semiconductor substrate using the oxide film with the opening as a mask.

[0063] Then, the semiconductor substrate is heated in an atmosphere containing oxygen to form a gate oxide film 8 on the inner wall of the trench 7 and the upper surface of the semiconductor substrate. The gate oxide film 8 formed on the upper surface of the semiconductor substrate is removed in a subsequent step.

[0064] Next, if Figure 2 As shown in (c), polysilicon 14a doped with n-type or p-type impurities is deposited by CVD (chemical vapor deposition) or the like in the trench 7 where the gate oxide film 8 is formed.

[0065] Next, if Figure 3 As shown in FIG. 1A , the upper portion of the polysilicon 14a is etched to form the lower dummy portion 14. At this time, the gate oxide film 8 formed on the upper surface of the semiconductor substrate serves as a mask to suppress the upper surface of the semiconductor substrate and the n + Etching of type source layer 4.

[0066] Then, if Figure 3 As shown in (b), the exposed gate oxide film 8 is removed by wet etching or the like. That is, the gate oxide film 8 on the inner wall of the upper portion of the trench 7, on the lower dummy portion 14, and on the upper surface of the semiconductor substrate is removed.

[0067] Next, if Figure 3 As shown in (c), the semiconductor substrate is heated in an atmosphere containing oxygen to form a gate oxide film 8 on the upper portion of the lower dummy portion 14 and the exposed inner wall of the trench 7 .

[0068] Then, if Figure 4 As shown in (a), polysilicon doped with n-type or p-type impurities is deposited by CVD or the like in the trench 7 where the gate oxide film 8 is formed, thereby forming the upper active portion 13.

[0069] Next, form p + Then, after the interlayer insulating film 2 is formed on the upper active portion 13, that is, on the two-layer gate A / D, the gate oxide film 8 formed on the upper surface of the semiconductor substrate is removed. The interlayer insulating film 2 may be, for example, SiO2. Furthermore, a contact hole is formed in the interlayer insulating film 2 stacked by masking. The contact hole is formed at n + On the source layer 4, p + type contact layer 3.

[0070] Then, if Figure 4 As shown in (b), an emitter electrode 1 is formed on the upper surface of the semiconductor substrate and on the interlayer insulating film 2. The emitter electrode 1 can be formed by, for example, stacking an aluminum silicon alloy (Al-Si alloy) by PVD (physical vapor deposition) such as sputtering or evaporation. In addition, a nickel alloy (Ni alloy) can be further formed on the formed aluminum silicon alloy by chemical plating or electrolytic plating to form the emitter electrode 1. If the emitter electrode 1 is formed by plating, a thick metal film can be easily formed as the emitter electrode 1, so that the heat resistance can be improved by increasing the heat capacity of the emitter electrode 1. In addition, when the emitter electrode 1 composed of an aluminum silicon alloy is formed by PVD and then a nickel alloy is further formed by plating, the plating treatment for forming the nickel alloy can also be implemented after the processing of the lower surface side of the semiconductor substrate is performed.

[0071] Next, the lower surface of the semiconductor substrate is ground to thin the semiconductor substrate to a predetermined designed thickness. The thickness of the ground semiconductor substrate can be, for example, 80 μm to 200 μm.

[0072] Then, n-type impurities are implanted from the lower surface side of the semiconductor substrate to form an n-type buffer layer 10. Then, p-type impurities are implanted from the lower surface side of the semiconductor substrate to form a p-type collector layer 11.

[0073] The n-type buffer layer 10 may be formed by, for example, implanting phosphorus (P) ions or implanting protons (H + ), or it can be formed by injecting both protons and phosphorus. Protons can be injected into a deep position from the lower surface of the semiconductor substrate with a relatively low acceleration energy. In addition, the injection depth of protons can be easily changed by changing the acceleration energy. Therefore, when the n-type buffer layer 10 is formed by protons, as long as multiple injections are performed while changing the acceleration energy, a thicker n-type buffer layer 10 can be formed in the thickness direction of the semiconductor substrate than when it is formed by phosphorus.

[0074] In addition, phosphorus can increase the activation rate as an n-type impurity compared to protons. Therefore, even if the semiconductor substrate is thinned, as long as the n-type buffer layer 10 is formed by phosphorus, the punch-through of the depletion layer can be suppressed. In order to further thin the semiconductor substrate, it is preferred to form the n-type buffer layer 10 by injecting both protons and phosphorus in such a way that the protons are injected deeper than the phosphorus from the lower surface.

[0075] The p-type collector layer 11 can be formed, for example, by implanting boron (b). After boron is ion implanted from the lower surface side of the semiconductor substrate, laser annealing is performed by irradiating the lower surface with laser, thereby activating the implanted boron to form the p-type collector layer 11. At this time, phosphorus of the n-type buffer layer 10 implanted to a shallow position from the lower surface of the semiconductor substrate is also activated at the same time.

[0076] In addition, since the protons in the n-type buffer layer 10 are activated at a relatively low annealing temperature of 380° C. to 420° C., after proton implantation, in addition to the process for proton activation, it is necessary to pay attention to the fact that the temperature of the entire semiconductor substrate does not reach a temperature higher than 380° C. to 420° C. The above-mentioned laser annealing can only make the lower surface of the semiconductor substrate reach a high temperature, and therefore can be used to activate n-type impurities and p-type impurities after proton implantation.

[0077] Next, a collector electrode 12 is formed on the lower surface of the semiconductor substrate. The collector electrode 12 can be formed by stacking aluminum silicon alloy (Ai-Si alloy), titanium (Ti), etc. through PVD stacking such as sputtering or evaporation, or can be formed by stacking multiple metals such as aluminum silicon alloy, titanium, nickel or gold. In addition, the collector electrode 12 can also be formed by further forming a metal film by chemical plating or electrolytic plating on the metal film formed by PVD.

[0078] Through the above-described steps, a plurality of semiconductor elements 100 are produced in a matrix on one n-type wafer. The semiconductor elements 100 are completed by cutting them into individual pieces by laser cutting or blade cutting.

[0079] <Conduction loss and on-state voltage>

[0080] Next, before describing the conduction loss and the on-voltage of the semiconductor element 100 according to the first embodiment, the related contents will be described.

[0081] Figure 5 is the conduction loss (E ON dI / dt is determined by the gate resistance (hereinafter sometimes referred to as “R G ”) and the gate-emitter capacitance (hereinafter sometimes referred to as “C GE ”) is determined by the current I C Increases to voltage V GE The first period until the current becomes constant temporarily becomes shorter as dI / dt increases, and is related to R G and C GE Roughly proportional.

[0082] dV / dt is determined by the gate resistance (R G ) and the gate-collector capacitance (hereinafter sometimes referred to as “C GC ”) determines the voltage V GE The second period of temporary maintenance becomes shorter as the absolute value of dV / dt increases, and is related to R G and C GC Roughly proportional.

[0083] The smaller the on-off time corresponding to the sum of the first and second periods, the smaller the conduction loss (E ON ) is smaller. Therefore, as long as the gate capacitance (C GE , C GC ), the absolute values ​​of dI / dt and dV / dt become larger, which can reduce the conduction loss (E ON ).

[0084] However, if the absolute values ​​of dI / dt and dV / dt become too large, radiation noise may occur. Therefore, R G Adjustment is performed so that dI / dt or dV / dt becomes a predetermined value. Whether dI / dt or dV / dt is set to a predetermined value depends on the application, but in the first embodiment, dV / dt is described as a predetermined value.

[0085] Figure 6 This means that C GC from Figure 5 The conduction loss (E ON ). If we increase C GC , the absolute value of dV / dt becomes smaller and the second period becomes longer.

[0086] Figure 7 It is to explain relative to Figure 5 The state of C GC Increase, and reduce R so that dV / dt becomes a specified value G The conduction loss (E ON ). By reducing R G , so that dV / dt becomes a specified value, and the second period becomes Figure 5 On the other hand, by reducing R G , so that dI / dt becomes larger, and R G and C GE Proportional to the first period ratio Figure 5 The first period is short. Therefore, when dV / dt is a specified value, Figure 7 On-off time ratio Figure 5 The on-off time is short, and Figure 5 The conduction loss (E ON )compared to, Figure 7 The conduction loss (E ON ) is lowered.

[0087] As mentioned above, in order to reduce the conduction loss, increase C GC C GC / C GE It is effective that this ratio becomes larger.

[0088] Figure 8 1 is a cross-sectional view showing the structure of a first related semiconductor device related to the semiconductor device according to the first embodiment. The first related semiconductor device has an IGBT structure having two gate A / D layers as in the first embodiment, but the depth of the upper active portion 13 is the same as the depth of the p-type base layer 5 .

[0089] Here, for a typical 1-layer gate, C GE The C GC In the upper active portion 13 and n - The N-type drift layer 9 and the N-type carrier accumulation layer 6 are generated in the portion between them.

[0090] At once Figure 8 As for the IGBT structure, the upper active portion 13 is basically not connected to the n - The n-type drift layer 9 and the n-type carrier accumulation layer 6 face each other, so Figure 8 The IGBT structure of C GC Compared with the conventional single-layer gate IGBT structure C GC Small. And, Figure 8 For the IGBT structure, C GE It is also generated between the upper active part 13 and the lower dummy part 14, so Figure 8 The 2-layer gate A / D IGBT structure of C GE Compared with the conventional single-layer gate IGBT structure C GE As a result, Figure 8 For the IGBT structure, C GC Small, C GC / C GE Therefore, when dV / dt is set to a predetermined value, there is a problem that the conduction loss cannot be reduced.

[0091] As for the first related semiconductor as described above, it is not considered that C GC / C GE Instead of increasing the conduction loss, the opposite is true. GC / C GE That is, in the first related semiconductor, the depth of the upper active portion 13 is the same as the depth of the p-type base layer 5 so as not to increase C GC .

[0092] However, when the depth of the upper active portion 13 is smaller than the depth of the p-type base layer 5, the channel cannot be turned on. Therefore, the depth of the upper active portion 13 is slightly greater than the depth of the p-type base layer 5 so that the channel is turned on even if there is manufacturing fluctuation in the depth of the upper active portion 13. Specifically, in the first related semiconductor, the depth of the upper active portion 13 is designed to be about 1.1 times the depth of the p-type base layer 5.

[0093] Fig. 9 It is a cross-sectional view showing the structure of a second related semiconductor device related to the semiconductor device according to the first embodiment. Fig. 9A second related semiconductor device is conceived as Figure 8 According to the first related semiconductor device, there is a fluctuation of about 0 to 30% in the diffusion process and the like, and the depth of the upper active portion 13 is about 1.4 times the depth of the p-type base layer 5 .

[0094] At once Fig. 9 In terms of IGBT structure, Figure 8 Compared with the IGBT structure of FIG. 1 , the portion of the upper active portion 13 facing the n-type carrier storage layer 6 is increased, so C GC / C GE But Fig. 9 In the IGBT structure, the lower end of the upper active portion 13 is located above the lower end of the n-type carrier accumulation layer 6, so the upper active portion 13 is not opposite to the lower portion of the n-type carrier accumulation layer 6. GC / C GE In addition, since the storage layer cannot be formed in the portion of the lower portion of the n-type carrier storage layer 6 that contacts the side surface of the trench 7, the carrier storage effect when the gate voltage is applied is low and the on-voltage becomes high.

[0095] <Summary of Implementation Method 1>

[0096] In the first embodiment, the lower end of the upper active portion 13 is located below the lower end of the n-type carrier storage layer 6. With such a structure, the upper active portion 13 and the lower portion of the n-type carrier storage layer 6 are opposed to each other, so that the C GC / C GE Furthermore, since the storage layer is formed in the portion of the lower portion of the n-type carrier storage layer 6 that contacts the side surface of the trench 7, the carrier storage effect can be enhanced and the on-voltage can be reduced.

[0097] In addition, in this embodiment 1, if Figure 1 As shown in FIG. 1 , the depth La of the upper active portion 13 is greater than or equal to 1.5 times the depth Lb of the p-type base layer 5. According to such a structure, the upper active portion 13 and the n-type base layer 5 can be connected. - The relative portion between the C type drift layers 9 increases. GC / C GE becomes larger, thus reducing the conduction loss.

[0098] <Variation 1>

[0099] In the first embodiment, the depth La of the upper active portion 13 in the two-layer gate A / D is greater than or equal to 1.5 times the depth Lb of the p-type base layer 5, but the present invention is not limited thereto. For example, the depth La of the upper active portion 13 may be greater than or equal to 2 times the depth Lb of the p-type base layer 5.

[0100] According to such a structure, the upper active part 13 and n - The relative portion between the C type drift layers 9 is further increased so that GC / C GE Furthermore, as a unique effect of this modification example 1, even when the depth Lb of the p-type base layer 5 is deeper than expected due to process fluctuations such as thermal diffusion, a large C can be maintained. GC / C GE .

[0101] <Implementation method 2>

[0102] <Structure>

[0103] Fig.10 is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment. Fig.10 In the cross-sectional views thereafter, illustration of the gate electrode 15 and its wiring etc. may be omitted as appropriate.

[0104] In the first embodiment, the thickness of the gate oxide film 8 is not particularly specified. In contrast, in the second embodiment, the thickness of the second insulating film between the lower dummy portion 14 and the inner wall of the trench 7 in the gate oxide film 8 is thicker than the thickness of the first insulating film between the upper active portion 13 and the inner wall of the trench 7.

[0105] <Manufacturing method>

[0106] First, the method described in Implementation 1 is performed. Figure 2 (a). Next, Fig.11 As shown in (a), after the trench 7 is formed, the semiconductor substrate is heated in an atmosphere containing oxygen to form a thick gate oxide film 8 on the inner wall of the trench 7 and the upper surface of the semiconductor substrate.

[0107] Then, polysilicon doped with n-type or p-type impurities is stacked by CVD or the like in the trench 7 where the gate oxide film 8 is formed.

[0108] Next, if Fig.11 As shown in (b), the upper part of the polysilicon is etched to form a lower dummy portion 14. At this time, the thick gate oxide film 8 formed on the upper surface of the semiconductor substrate serves as a mask to suppress the upper surface of the semiconductor substrate and the n + Etching of type source layer 4.

[0109] Then, if Fig.11As shown in (c), the exposed gate oxide film 8 is removed by wet etching or the like. That is, the gate oxide film 8 formed on the inner wall of the upper portion of the trench 7, on the lower dummy portion 14, and on the upper surface of the semiconductor substrate is removed.

[0110] Next, the semiconductor substrate is heated in an atmosphere containing oxygen to form a relatively thin gate oxide film 8 on the upper portion of the lower dummy portion 14 and the exposed inner wall of the trench 7. In addition, the thin gate oxide film 8 formed on the upper surface of the semiconductor substrate is removed in a subsequent process as in Embodiment 1. Then, polysilicon doped with n-type or p-type impurities is stacked in the trench 7 where the gate oxide film 8 is formed by CVD or the like to form the upper active portion 13.

[0111] <Summary of Implementation Method 2>

[0112] In a structure where the upper active portion 13 is disposed deeply as in the first embodiment, it is necessary to perform etching of polysilicon for a long time when forming the lower dummy portion 14. Figure 2 (c) and Figure 3 As shown in (a), if the gate oxide film 8 is thin when etching the polysilicon 14a, the gate oxide film 8 on the upper surface of the semiconductor substrate may disappear due to etching. + In contrast, in the second embodiment, as Fig.11 As shown in (b), when etching polysilicon, the gate oxide film 8 is thick, so that the upper surface of the semiconductor substrate and the n + Etching of type source layer 4.

[0113] <Variation 1>

[0114] In the description so far, only two layers of gate electrodes A / D are arranged in the trench, but the present invention is not limited to this.

[0115] As the first example, Fig.12 As shown, a single-layer gate A may be disposed in a trench 21 similar to the trench 7. That is, an active portion 23 of polysilicon connected to the gate electrode 15 may be disposed on the inner wall of the trench 21 from the upper portion to the lower portion via a fourth insulating film 22 similar to the gate oxide film 8. In addition, in this structure, the thickness of the fourth insulating film 22 between the active portion 23 of the single-layer gate A and the inner wall of the trench 21 may be thicker than the thickness of the first insulating film between the upper active portion 13 of the double-layer gate A / D and the inner wall of the trench 7.

[0116] As a second example, Fig.13As shown, a dummy D layer may be disposed in the trench 21 similar to the trench 7. That is, a dummy portion 24 of polysilicon connected to the emitter electrode 1 and disposed via a fourth insulating film 22 similar to the gate oxide film 8 may be disposed on the inner wall of the trench 21 from the upper part to the lower part. In addition, in this structure, the thickness of the fourth insulating film 22 between the dummy portion 24 of the dummy D layer and the inner wall of the trench 21 may be thicker than the thickness of the first insulating film between the upper active portion 13 of the two-layer gate A / D and the inner wall of the trench 7.

[0117] Next, the manufacturing method of the structure of this modification example 1 is described. Here, the manufacturing method of the structure having two gate A / D layers and one gate A layer is described, but the manufacturing method of the structure having two gate A / D layers and one dummy D layer is the same as below.

[0118] First, the method described in Implementation 1 is performed. Figure 2 (a)~ Figure 2 (c) Step. Thus, polysilicon is formed on the inner wall of the trench 7 via the gate oxide film 8, and is formed on the inner wall of the trench 21 via the fourth insulating film 22. Furthermore, the polysilicon in the trench 7 of the two-layer gate A / D is exposed by masking, and a mask is formed on the polysilicon in the trench 21 of the single-layer gate A.

[0119] Next, instead of etching the polysilicon in the trench 21 of the single-layer gate A, the upper portion of the polysilicon in the trench 7 of the double-layer gate A / D is etched to form the lower dummy portion 14 of the double-layer gate A / D. Then, the gate oxide film 8 formed on the inner wall of the upper portion of the trench 7, on the lower dummy portion 14, and on the upper surface of the semiconductor substrate is removed by wet etching or the like.

[0120] Next, the semiconductor substrate is heated in an atmosphere containing oxygen to form a gate oxide film 8 on the upper portion of the lower dummy portion 14 of the two-layer gate A / D and the exposed inner wall of the trench 7. Then, polysilicon doped with n-type or p-type impurities is stacked by CVD or the like in the trench 7 where the gate oxide film 8 is formed, forming an upper active portion 13. In addition, portions other than the upper active portion 13 in the polysilicon are removed by etching. Thus, the two-layer gate A / D and the one-layer gate A are formed.

[0121] <Summary of Modification 1>

[0122] In the structure in which one layer of gate A is inserted as described above, C GC / C GEIn addition, the thick fourth insulating film 22 of the single-layer gate A can suppress the injection of hot carriers generated by dynamic avalanche, thereby suppressing the degradation of gate characteristics.

[0123] On the other hand, in the above structure in which a dummy D layer without gate capacitance is inserted, it is possible to maintain C GC / C GE At the same time, it reduces the gate charge (Qg) of the semiconductor device.

[0124] <Variation 2>

[0125] Fig.14 It is a cross-sectional view showing the structure of a semiconductor device according to the second modification.

[0126] The semiconductor device according to the first embodiment has two layers of gate A / D, but is not limited thereto. Fig.14 As shown in FIG. 1 , the lower polysilicon layer may be the lower active portion 14b connected to the gate electrode 15 instead of the lower dummy portion 14 connected to the emitter electrode 1. That is, the semiconductor device may also have a two-layer gate A / A composed of the upper active portion 13 and the lower active portion 14b. In addition, in this structure, the thickness of the second insulating film between the lower active portion 14b and the inner wall of the trench 7 may be thicker than the thickness of the first insulating film between the upper active portion 13 and the inner wall of the trench 7.

[0127] In the two-layer gate A / A of the second modification example configured as described above, the active portion and the n - The relative portion of the C type drift layer 9 is increased. GC / C GE In addition, the thick second insulating film can suppress the injection of hot carriers generated by dynamic avalanche, thereby suppressing the degradation of gate characteristics.

[0128] <Variation 3>

[0129] Fig.15 It is a cross-sectional view showing the structure of the semiconductor device according to the third modification.

[0130] The semiconductor device may also include an electrically floating p-type semiconductor layer 25. In addition, the semiconductor layer 25 is arranged on the upper surface side of the n-type carrier accumulation layer 6 in the same manner as the p-type base layer 5. In addition, the semiconductor device may also include an active portion 28 of polysilicon that is arranged on the inner wall from the upper part to the lower part of the groove 26 that penetrates the semiconductor layer 25 and the n-type carrier accumulation layer 6 through the fourth insulating film 27 and is connected to the gate electrode 15. That is, it may be arranged so that the active portion 28 is sandwiched by the floating semiconductor layer 25. In addition, the semiconductor device may also include a dummy portion 31 of polysilicon that is arranged on the inner wall from the upper part to the lower part of the groove 29 provided adjacent to the groove 26 through the fifth insulating film 30 and is connected to the emitter electrode 1.

[0131] According to the third modification example configured as described above, C is generated between the floating semiconductor layer 25 and the active portion 28. GC Without producing C GE Therefore, it is possible to further make C GC / C GE becomes larger, thus the conduction loss can be further reduced.

[0132] <Implementation method 3>

[0133] Fig.16 It is a cross-sectional view showing the structure of a semiconductor device according to the third embodiment.

[0134] The semiconductor device according to the first embodiment has two layers of gate A / D, but is not limited thereto. Fig.16 As shown, the lower polysilicon may be an electrically floating lower floating portion 14c instead of the lower dummy portion 14 connected to the emitter electrode 1. That is, the semiconductor device may have a two-layer gate A / F composed of the electrically separated upper active portion 13 and the lower floating portion 14c.

[0135] According to the third embodiment configured as described above, no C is generated between the upper active portion 13 and the lower floating portion 14c. GE Therefore, it is possible to reduce C GE , which can further enable C GC / C GE becomes larger, thus the conduction loss can be further reduced.

[0136] <Implementation method 4>

[0137] Fig.17 It is a cross-sectional view showing the structure of a semiconductor device according to the fourth embodiment.

[0138] The semiconductor device according to the fourth embodiment includes a p-type bottom layer 32 disposed at the bottom of the trench 7 in the semiconductor substrate. According to the fourth embodiment, the electric field at the bottom of the trench 7 can be reduced by the p-type bottom layer 32. Therefore, the generation of dynamic avalanche can be suppressed, and the degradation of gate characteristics can be suppressed.

[0139] <Variation 1>

[0140] In the fourth embodiment, the thickness and width of the p-type bottom layer 32 are relatively small, but the present invention is not limited thereto. Fig.18 As shown, the thickness and width of the p-type bottom layer 32 may be increased to the extent that adjacent p-type bottom layers 32 are connected to each other. According to such a structure, the voltage can be maintained in a wider range by the p-type bottom layer 32, so the electric field can be further reduced. Therefore, the generation of dynamic avalanche can be further suppressed, and the degradation of gate characteristics can be suppressed.

[0141] In general, holes cause the potential of the p-type bottom layer 32 to change during conduction, thereby generating displacement current. Fig.18 As shown, if the floating p-type bottom layer 32 is arranged to face the upper active portion 13 , the displacement current flows into the upper active portion 13 facing the p-type bottom layer 32 , causing the gate potential to fluctuate and deteriorating the controllability of dV / dt.

[0142] Therefore, if Fig.19 As shown in FIG. 1 , the p-type bottom layer 32 may be configured so as to be in contact with the second insulating film between the lower dummy portion 14 and the inner wall of the trench 7 but not in contact with the first insulating film between the upper active portion 13 and the inner wall of the trench 7. That is, the p-type bottom layer 32 may be configured so as not to be opposed to the upper active portion 13. With such a structure, the change in gate potential caused by displacement current can be suppressed.

[0143] <Variation 1 of Embodiments 1 to 4>

[0144] The upper active portion 13 of the first to fourth embodiments may also be used as a gate of an RC-IGBT. That is, the semiconductor element 100 of the first to fourth embodiments may also be an RC-IGBT. The structure of the RC-IGBT will be briefly described below.

[0145] Fig. 20 2 is a cross-sectional view showing the structure of the RC-IGBT. The RC-IGBT includes an IGBT region 35 where the IGBT is arranged and a diode region 36 where the diode is arranged. The IGBT region 35 uses the same structure as in the first to fourth embodiments. The diode region 36 uses, for example, Fig.13 However, an n-type cathode layer 37 is arranged in the diode region 36 instead of the p-type collector layer 11 .

[0146] <Variation 2 of Embodiments 1 to 4>

[0147] The upper active portion 13 of the first to fourth embodiments may also be used as a gate of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). That is, the semiconductor element 100 of the first to fourth embodiments may also be a MOSFET.

[0148] <Variation 3 of Embodiments 1 to 4>

[0149] In Embodiments 1 to 4, the semiconductor used for the semiconductor substrate and the like is not described, but the semiconductor may be silicon or a wide bandgap semiconductor. The wide bandgap semiconductor includes, for example, silicon carbide, gallium nitride-based materials, gallium oxide, or diamond. With such a structure, the withstand voltage of the semiconductor device can be improved.

[0150] In addition, the embodiments and the modifications can be freely combined, or the embodiments and the modifications can be appropriately modified or omitted.

[0151] Description of the label

[0152] 1 emitter electrode, 4n + Type source layer, 5p type base layer, 6n - Carrier accumulation layer, 7, 21, 26 grooves, 8 gate oxide film, 13 upper active part, 14 lower dummy part, 14b lower active part, 15 gate electrode, 22, 27 fourth insulating film, 23 active part, 24 dummy part, 25 semiconductor layer, 32 bottom layer.

Claims

1. A semiconductor device comprising: A semiconductor substrate provided with an emitter electrode and a gate electrode; a first conductivity type carrier storage layer disposed on the upper surface side of the semiconductor substrate; A second conductive type base layer disposed on the upper surface side of the carrier storage layer; A first conductive type source layer disposed on the upper surface side of the base layer; An upper active portion as an upper polysilicon layer, which is arranged on a first insulating film along an inner wall of an upper portion of a trench and connected to the gate electrode, the trench penetrating the source layer, the base layer, and the carrier storage layer; as well as a lower layer of polysilicon disposed on a second insulating film along an inner wall of a lower portion of the trench, wherein a third insulating film is disposed between the lower layer of polysilicon and the upper layer active portion, The lower layer polysilicon is any one of a lower layer dummy portion connected to the emitter electrode, a lower layer active portion connected to the gate electrode, and a lower layer floating portion that is electrically floating. A lower end of the upper active portion is located below a lower end of the carrier storage layer.

2. The semiconductor device according to claim 1, wherein The depth of the upper active portion is greater than or equal to 1.5 times the depth of the base layer.

3. The semiconductor device according to claim 2, wherein: The depth of the upper active portion is greater than or equal to twice the depth of the base layer.

4. The semiconductor device according to claim 1, wherein The second insulating film is thicker than the first insulating film.

5. The semiconductor device according to claim 2, wherein: The second insulating film is thicker than the first insulating film.

6. The semiconductor device according to claim 3, wherein: The second insulating film is thicker than the first insulating film.

7. The semiconductor device according to any one of claims 1 to 6, wherein: The present invention also comprises: an active portion as polysilicon connected to the gate electrode or a dummy portion as polysilicon connected to the emitter electrode, which is arranged on a fourth insulating film along the inner wall from the upper part to the lower part of the groove penetrating the source layer, the base layer and the carrier storage layer, The fourth insulating film is thicker than the first insulating film.

8. The semiconductor device according to any one of claims 1 to 6, wherein: The semiconductor device also has: an electrically floating semiconductor layer of a second conductivity type, arranged on the upper surface side of the carrier storage layer; and The active portion, which is polysilicon, is disposed on a fourth insulating film along an inner wall from the upper portion to the lower portion of a trench penetrating the semiconductor layer and the carrier storage layer, and is connected to the gate electrode.

9. The semiconductor device according to any one of claims 1 to 6, wherein: A second conductive type bottom layer is further provided, and the second conductive type bottom layer is arranged at the bottom of the trench in the semiconductor substrate.

10. The semiconductor device according to claim 9, wherein The base layer is in contact with the second insulating film but is not in contact with the first insulating film.

11. The semiconductor device according to any one of claims 1 to 6, wherein: The upper active portion is used as a gate of the RC-IGBT.

12. The semiconductor device according to any one of claims 1 to 6, wherein: The upper active portion is used for the gate of the MOSFET.

13. The semiconductor device according to any one of claims 1 to 6, wherein: The semiconductor substrate includes a wide bandgap semiconductor.

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