Superjunction trench gate MOSFET and method for manufacturing the same

Abstract

The present invention provides a super junction trench gate MOSFET and a preparation method thereof, wherein the method comprises: using a structure of a hard mask plus a photoresist mask as a mask to form a high energy injection region, and then using a mask structure of a remaining thickness and a third silicon oxide layer as a mask to form a low energy injection region, and the high energy injection region and the low energy injection region are formed by injection self-alignment, wherein the distance between each of the low energy injection regions and the gate dielectric layer is greater than the distance between each of the high energy injection regions and the gate dielectric layer. The present application forms a low energy injection region by using a mask structure of a remaining thickness and a third silicon oxide layer as a mask to inject and form the low energy injection region, so that the injection opening of the low energy injection region is reduced, and the low energy injection region is further away from the gate dielectric layer than the high energy injection region, so that the on resistance of the accumulation region (the overlap of the trench gate and the epitaxial layer) can be improved, thereby reducing the on resistance of the device and improving the reliability and safety of the device.

Description

Technical Field

[0001] The present application relates to the technical field of manufacturing MOSFET devices, and in particular to a super junction trench gate MOSFET and a preparation method thereof. Background Art

[0002] Trench gate MOSFET devices are widely used in power conversion circuits and are often used in power switching devices. The on-resistance (Rsp) and breakdown voltage (BV) of the trench gate are one of its important parameter indicators. Obtaining a higher breakdown voltage and lower Rsp can improve the competitiveness of the product. In order to improve the on-resistance of the medium and high voltage (50V~200V) trench gate, the concept of super junction-trench gate MOSFET was proposed.

[0003] Taking an N-channel trench gate as an example, an epitaxial layer is formed on a highly doped substrate, a trench gate is formed in the epitaxial layer, a gate dielectric layer is formed between the trench gate and the epitaxial layer, and a P-type ion implantation region (P-pillar) with auxiliary drift region depletion is formed on both sides of the trench gate. In order to improve the characteristics of the super junction-trench gate MOSFET device, the bottom end of the P-pillar is currently placed as close to the highly doped substrate as possible, so that the concentration of the entire epitaxial layer can be increased.

[0004] However, the P-pillar formed by the ion implantation process requires a very thick photoresist / hard mask (3000KeV P-type ions require 5um) for high-energy P-type ion implantation. Therefore, for small-sized cells, high-energy implantation will be limited by the aspect ratio. At the same time, it also makes the P-pillar too close to the gate dielectric layer, which significantly increases the resistance of the device's accumulation region, resulting in an increase in the device's on-resistance. Summary of the invention

[0005] The present application provides a super junction trench gate MOSFET and a preparation method thereof, which can solve the problem in a trench gate MOSFET device that the P-pillar is too close to the gate dielectric layer, resulting in an increase in the on-resistance of the device.

[0006] In one aspect, the present invention provides a method for preparing a super junction trench gate MOSFET, comprising:

[0007] A substrate is provided, wherein an epitaxial layer is formed on the front side of the substrate, a trench is formed in the epitaxial layer, a gate dielectric layer and a trench gate are formed in the trench, the gate dielectric layer covers the bottom wall and the side wall of the trench, the trench gate covers the gate dielectric layer and fills the trench, a body region is further formed in the epitaxial layer, and the upper surface of the body region is flush with the upper surface of the epitaxial layer;

[0008] forming a first silicon oxide layer and a silicon nitride layer in sequence, wherein the first silicon oxide layer covers the body region, the gate dielectric layer and the trench gate, and the silicon nitride layer covers the first silicon oxide layer;

[0009] forming a mask structure, wherein the mask structure is located on the silicon nitride layer above the trench gate;

[0010] Using an ion implantation process to form two high-energy implantation regions in the epitaxial layer on both sides of the mask structure, wherein the high-energy implantation regions are close to the lower surface of the epitaxial layer;

[0011] Removing a portion of the thickness of the mask structure and forming a third silicon oxide layer, wherein the third silicon oxide layer covers the remaining thickness of the mask structure and the silicon nitride layer;

[0012] Using an ion implantation process, two low-energy implantation regions are formed in the epitaxial layer and the body region on both sides of the mask structure of the remaining thickness, wherein the low-energy implantation regions are located on the high-energy implantation regions;

[0013] removing the third silicon oxide layer, the remaining thickness of the mask structure and the silicon nitride layer;

[0014] forming a heavily doped region in the body region by using an ion implantation process;

[0015] forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers a portion of the surface of the gate dielectric layer, the trench gate and the heavily doped region; and,

[0016] Forming a source metal layer and a drain metal layer, wherein the source metal layer covers the interlayer dielectric layer and the remaining surface of the heavily doped region, and the drain metal layer covers the back side of the substrate;

[0017] Wherein, the distance between each of the low-energy injection regions and the gate dielectric layer is greater than the distance between each of the high-energy injection regions and the gate dielectric layer.

[0018] Optionally, in the method for preparing the super junction trench gate MOSFET, the thickness of the third silicon oxide layer is

[0019] Optionally, in the method for preparing the super junction trench gate MOSFET, the ion implantation opening of the low energy implantation area is formed by self-alignment based on the thickness of the third silicon oxide layer and the ion implantation opening of the high energy implantation area.

[0020] Optionally, in the method for preparing the super junction trench gate MOSFET, the difference between the distance between each low energy injection region and the gate dielectric layer and the distance between each high energy injection region and the gate dielectric layer is equal to the thickness of the third silicon oxide layer.

[0021] Optionally, in the method for preparing the super junction trench gate MOSFET, a p-type impurity implantation process is used to form two symmetrical high energy implantation regions in the epitaxial layer on the trench side, wherein the ion implantation concentration of the high energy implantation region is 2E12atoms / cm 2 ~2E13atoms / cm 2 , the injection energy is greater than or equal to 1000KeV~3000KeV.

[0022] Optionally, in the method for preparing the super junction trench gate MOSFET, a p-type impurity implantation process is used to form two symmetrical low energy implantation regions in the epitaxial layer and the body region on the trench side, wherein the ion implantation concentration of the low energy implantation region is 2E12atoms / cm 2 ~2E13atoms / cm 2 , the injection energy is less than or equal to 200KeV~2500KeV.

[0023] Optionally, in the method for preparing the super junction trench gate MOSFET, the step of forming a mask structure, wherein the mask structure is located on the silicon nitride layer above the trench gate, comprises:

[0024] forming a second silicon oxide layer, wherein the second silicon oxide layer covers the silicon nitride layer;

[0025] forming a photoresist layer, wherein the photoresist layer covers the second silicon oxide layer; and

[0026] The photoresist layer and the second silicon oxide layer above the body region are removed by photolithography and etching processes to obtain the mask structure.

[0027] Optionally, in the method for preparing the super junction trench gate MOSFET, the thickness of the second silicon oxide layer is 2 μm to 5 μm, and the thickness of the photoresist layer is 0.5 μm to 3 μm.

[0028] Optionally, in the method for preparing the super junction trench gate MOSFET, after forming the heavily doped region in the body region by an ion implantation process and before forming the interlayer dielectric layer, the method for preparing the super junction trench gate MOSFET further includes:

[0029] Etching the heavily doped region and a portion of the body region using a patterned photoresist layer to obtain a contact hole;

[0030] Using the patterned photoresist layer as a mask, an ion implantation process is used to form a diffusion region in the body region, wherein the diffusion region is located at the bottom end of the contact hole;

[0031] performing a thermal annealing process on the diffusion region, the high energy implantation region, and the low energy implantation region to activate the diffusion region, the high energy implantation region, and the low energy implantation region; and

[0032] The contact hole is filled with metal to obtain a metal plug.

[0033] Optionally, in the method for preparing the super junction trench gate MOSFET, the thickness of the first silicon oxide layer is The thickness of the silicon nitride layer is

[0034] Optionally, in the method for preparing the super junction trench gate MOSFET, the conductivity type of the doped ions of the substrate is N-type.

[0035] On the other hand, the present invention also provides a super junction trench gate MOSFET, comprising:

[0036] A substrate, wherein an epitaxial layer is formed on the front side of the substrate, a trench is formed in the epitaxial layer, a gate dielectric layer and a trench gate are formed in the trench, the gate dielectric layer covers the bottom wall and side walls of the trench, the trench gate covers the gate dielectric layer and fills the trench, a body region is further formed in the epitaxial layer, and an upper surface of the body region is flush with an upper surface of the epitaxial layer;

[0037] Two high energy implantation regions, the high energy implantation regions are respectively located in the epitaxial layer at two sides of the trench and close to the lower surface of the epitaxial layer;

[0038] Two low energy implantation regions, the low energy implantation regions are respectively located in the epitaxial layer and the body region at both sides of the trench and are located on the high energy implantation region;

[0039] a heavily doped region, the heavily doped region being located in the body region;

[0040] an interlayer dielectric layer, the interlayer dielectric layer covering a portion of the surface of the gate dielectric layer, the trench gate and the heavily doped region; and,

[0041] A source metal layer and a drain metal layer, wherein the source metal layer covers the interlayer dielectric layer and the remaining surface of the heavily doped region, and the drain metal layer covers the back side of the substrate;

[0042] Wherein, the distance between each of the low-energy injection regions and the gate dielectric layer is greater than the distance between each of the high-energy injection regions and the gate dielectric layer.

[0043] The technical solution of this application has at least the following advantages:

[0044] The present invention provides a super junction trench gate MOSFET and a preparation method thereof, wherein the method comprises: using a hard mask plus a photoresist mask structure as a mask to form a high energy injection region, and using a hard mask structure of a remaining thickness and a third silicon oxide layer as a mask to form a low energy injection region, and the high energy injection region and the low energy injection region are formed by injection self-alignment, wherein the distance between each low energy injection region and the gate dielectric layer is greater than the distance between each high energy injection region and the gate dielectric layer. The present application forms a low energy injection region by using a mask structure of a remaining thickness and a third silicon oxide layer as a mask to inject after the high energy injection region is injected, so that the injection opening of the low energy injection region is reduced, so that the low energy injection region is further away from the gate dielectric layer than the high energy injection region, so that the on-resistance of the accumulation region (the overlap of the epitaxial layer below the trench gate and the body region) can be improved, thereby reducing the on-resistance of the device and improving the reliability and safety of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] Figure 1 is a flow chart of a method for preparing a super junction trench gate MOSFET according to an embodiment of the present invention;

[0047] Figure 2-Figure 11 It is a schematic diagram of the semiconductor structure in each process step of preparing a super junction trench gate MOSFET according to an embodiment of the present invention;

[0048] The reference numerals are described as follows:

[0049] 101-substrate, 102-epitaxial layer, 103-1-high energy implantation region, 103-2-low energy implantation region, 104-gate dielectric layer, 105-trench gate, 106-body region, 108-heavily doped region, 107-diffusion region, 109-contact hole, 110-interlayer dielectric layer, 111-source metal layer, 112-drain metal layer;

[0050] 201 - a first silicon oxide layer, 202 - a silicon nitride layer, 203 - a second silicon oxide layer, 204 - a photoresist layer, 205 - a third silicon oxide layer. DETAILED DESCRIPTION

[0051] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0052] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0053] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0054] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0055] The present invention provides a method for preparing a super junction trench gate MOSFET. Figure 1 , Figure 1 1 is a flow chart of a method for preparing a super junction trench gate MOSFET according to an embodiment of the present invention, wherein the method for preparing a super junction trench gate MOSFET comprises:

[0056] S10: providing a substrate, wherein an epitaxial layer is formed on the front side of the substrate, a trench is formed in the epitaxial layer, a gate dielectric layer and a trench gate are formed in the trench, the gate dielectric layer covers the bottom wall and the side wall of the trench, the trench gate covers the gate dielectric layer and fills the trench, a body region is further formed in the epitaxial layer, and an upper surface of the body region is flush with an upper surface of the epitaxial layer;

[0057] S20: forming a first silicon oxide layer and a silicon nitride layer in sequence, wherein the first silicon oxide layer covers the body region, the gate dielectric layer and the trench gate, and the silicon nitride layer covers the first silicon oxide layer;

[0058] S30: forming a mask structure, wherein the mask structure is located on the silicon nitride layer above the trench gate;

[0059] S40: using an ion implantation process to form two high-energy implantation regions in the epitaxial layer on both sides of the mask structure, wherein the high-energy implantation regions are close to a lower surface of the epitaxial layer;

[0060] S50: removing a portion of the thickness of the mask structure and forming a third silicon oxide layer, wherein the third silicon oxide layer covers the remaining thickness of the mask structure and the silicon nitride layer;

[0061] S60: using an ion implantation process to form two low-energy implantation regions in the epitaxial layer and the body region at both sides of the mask structure of the remaining thickness, wherein the low-energy implantation regions are located on the high-energy implantation regions;

[0062] S70: removing the third silicon oxide layer, the remaining thickness of the mask structure and the silicon nitride layer;

[0063] S80: forming a heavily doped region in the body region by an ion implantation process;

[0064] S90: forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers a portion of the surface of the gate dielectric layer, the trench gate, and the heavily doped region; and,

[0065] S100: forming a source metal layer and a drain metal layer, wherein the source metal layer covers the interlayer dielectric layer and the remaining surface of the heavily doped region, and the drain metal layer covers the back side of the substrate;

[0066] Wherein, the distance between each of the low-energy injection regions and the gate dielectric layer is greater than the distance between each of the high-energy injection regions and the gate dielectric layer.

[0067] For details, please refer to Figure 2-Figure 11 , Figure 2-Figure 11 Schematic diagram of semiconductor structure in each process step of preparing super junction trench gate MOSFET according to an embodiment of the present invention. This embodiment takes N-type channel SJ-TGMOSFET as an example to elaborate on the preparation method of super junction trench gate MOSFET.

[0068] First, if Figure 2As shown, a substrate 101 is provided, an epitaxial layer 102 is formed on the front side of the substrate 101, a trench is formed in the epitaxial layer 102, a gate dielectric layer 104 and a trench gate 105 are formed in the trench, the gate dielectric layer 104 covers the bottom wall and side wall of the trench, the trench gate 105 covers the gate dielectric layer 104 and fills the trench, and a body region 106 is also formed in the epitaxial layer 102, and the upper surface of the body region 106 is flush with the upper surface of the epitaxial layer 102. Specifically, the conductivity type of the doped ions of the substrate is N-type, preferably, the substrate 101 is a highly doped N-type substrate, the epitaxial layer 102 can be an N-type epitaxial layer, which can also be called an N-type drift region, wherein the doping concentration of the N-type impurities can be 5E15atoms / cm 3 ~1E17 atoms / cm 3 .

[0069] Then, if Figure 3 As shown, a first silicon oxide layer 201 and a silicon nitride layer 202 are formed in sequence, wherein the first silicon oxide layer 201 covers the body region 106, the gate dielectric layer 104 and the trench gate 105, and the silicon nitride layer 202 covers the first silicon oxide layer 201. Specifically, the thickness of the first silicon oxide layer 201 is The thickness of the silicon nitride layer 202 is

[0070] Then, if Figure 4 As shown, a mask structure is formed, and the mask structure is located on the silicon nitride layer 202 above the trench gate 105. Specifically, the step of forming a mask structure, and the mask structure is located on the silicon nitride layer 202 above the trench gate 105 includes:

[0071] Step 1: forming a second silicon oxide layer 203, wherein the second silicon oxide layer 203 covers the silicon nitride layer 202. Specifically, the thickness of the second silicon oxide layer 203 may be 2 μm to 5 μm.

[0072] Step 2: forming a photoresist layer 204, wherein the photoresist layer 204 covers the second silicon oxide layer 203. Specifically, the thickness of the photoresist layer 204 may be 0.5 μm to 3 μm.

[0073] Step three: remove the photoresist layer 204 and the second silicon oxide layer 203 above the body region 106 by photolithography and etching processes, and retain the remaining photoresist layer 204 and the second silicon oxide layer 203 on the silicon nitride layer 202 above the trench gate 105 to obtain the mask structure.

[0074] Further, such as Figure 5As shown, an ion implantation process is used to form two high-energy implantation regions 103-1 in the epitaxial layer 201 on both sides of the mask structure (the remaining photoresist layer 204 and the second silicon oxide layer 203), and the high-energy implantation region 103-1 is close to the lower surface of the epitaxial layer 102. Specifically, a p-type impurity (e.g., boron ion) implantation process is used to form two symmetrical high-energy implantation regions 103-1 in the epitaxial layer 102 on the trench side, wherein the ion implantation concentration of the high-energy implantation region 103-1 may be 2E12atoms / cm 2 ~2E13atoms / cm 2 , the injection energy is greater than or equal to 1000KeV~3000KeV.

[0075] Then, if Figure 6 As shown, a portion of the mask structure is removed and a third silicon oxide layer 205 is formed, and the third silicon oxide layer 205 covers the remaining mask structure and the silicon nitride layer 202. Specifically, the photoresist layer 204 is removed, and the third silicon oxide layer 205 is deposited on the surface of the silicon nitride layer 202 and the surface of the second silicon oxide layer 203. The thickness of the third silicon oxide layer 205 is

[0076] Further, such as Figure 7 As shown, an ion implantation process is used to form two low-energy implantation regions 103-2 in the epitaxial layer 102 and the body region 106 on both sides of the remaining thickness of the mask structure, and the low-energy implantation region 103-2 is located on the high-energy implantation region 103-1. Specifically, the distance between each of the low-energy implantation regions 103-2 and the gate dielectric layer 104 is greater than the distance between each of the high-energy implantation regions 103-1 and the gate dielectric layer 104. A p-type impurity (e.g., boron ion) implantation process is used to form two symmetrical low-energy implantation regions in the epitaxial layer and the body region on the trench side, wherein the ion implantation concentration of the low-energy implantation region is 2E12atoms / cm 2 ~2E13atoms / cm 2 , the injection energy is less than or equal to 200KeV~2500KeV.

[0077] In this embodiment, based on the thickness of the third silicon oxide layer 205 and the ion implantation opening of the high energy implantation area 103-1, the ion implantation opening of the low energy implantation area 103-2 is self-aligned. It can be seen that the difference between the distance between each low energy implantation area 103-2 and the gate dielectric layer 104 and the distance between each high energy implantation area 103-1 and the gate dielectric layer 104 is equal to the thickness of the third silicon oxide layer 205.

[0078] Then, if Figure 8 As shown, the third silicon oxide layer 205, the remaining thickness of the mask structure (the second silicon oxide layer 203), and the silicon nitride layer 202 are removed. Specifically, first, the silicon nitride layer 202 is used as an etching barrier layer to etch away the third silicon oxide layer 205 and the remaining thickness of the mask structure (the second silicon oxide layer 203), and then the silicon nitride layer 202 is etched away.

[0079] Further, such as Figure 8 As shown, an N-type heavily doped region 108 is formed in the body region 106 by an ion implantation process. Fig. 9 As shown, after the heavily doped region 108 is formed in the body region 106 by an ion implantation process, the method for preparing the super junction trench gate MOSFET may further include:

[0080] Step (1): using a patterned photoresist layer (not shown) to etch the heavily doped region 108 and a portion of the body region 106 to obtain a contact hole 109;

[0081] Step (2): using the patterned photoresist layer as a mask, an ion implantation process is performed to form a diffusion region 107 in the body region 106, wherein the diffusion region 107 is located at the bottom end of the contact hole 109;

[0082] Step (3): performing a thermal annealing process on the diffusion region 107, the high energy injection region 103-1 and the low energy injection region 103-2 to activate the diffusion region 107, the high energy injection region 103-1 and the low energy injection region 103-2;

[0083] Step (4): Filling the contact hole 109 with metal to obtain a metal plug, which can lead out the heavily doped region 108 and the diffusion region 107.

[0084] Then, if Fig.10 As shown, an interlayer dielectric layer 110 is formed, and the interlayer dielectric layer 110 covers a portion of the surface of the gate dielectric layer 104 , the trench gate 105 , and the heavily doped region 108 .

[0085] Finally, if Fig.11 As shown, a source metal layer 111 and a drain metal layer 112 are formed, wherein the source metal layer 111 covers the remaining surface of the interlayer dielectric layer 110 and the heavily doped region 108 and the surface of the metal plug (contact hole 109 ), and the drain metal layer 112 covers the back side of the substrate 101 .

[0086] In the present application, after the high-energy injection region 103-1 is injected, the remaining thickness of the mask structure (the second silicon oxide layer 203) and the third silicon oxide layer 205 are used as masks for injection to form a low-energy injection region 103-2, so that the injection opening of the low-energy injection region 103-2 is reduced, and the low-energy injection region 103-2 is further away from the gate dielectric layer 104 than the high-energy injection region 103-1. In this way, the on-resistance of the accumulation region (the overlap of the trench gate and the epitaxial layer, which can be understood as the lower half structure of the trench gate 105) can be improved, thereby reducing the on-resistance of the device and improving the reliability and safety of the device.

[0087] Based on the same inventive concept, this embodiment also provides a super junction trench gate MOSFET, such as Fig.11 As shown, the super junction trench gate MOSFET includes:

[0088] A substrate 101, wherein an epitaxial layer 102 is formed on the front side of the substrate 101, a trench is formed in the epitaxial layer 102, a gate dielectric layer 104 and a trench gate 105 are formed in the trench, the gate dielectric layer 104 covers the bottom wall and the side wall of the trench, the trench gate 105 covers the gate dielectric layer 104 and fills the trench, and a body region 106 is further formed in the epitaxial layer 102, and the upper surface of the body region 106 is flush with the upper surface of the epitaxial layer 102;

[0089] Two high-energy implantation regions 103 - 1 , wherein the high-energy implantation regions 103 - 1 are respectively located in the epitaxial layer 102 at both sides of the trench and close to the lower surface of the epitaxial layer 102 ;

[0090] Two low-energy implantation regions 103 - 2 , the low-energy implantation regions 103 - 2 are respectively located in the epitaxial layer 102 and the body region 106 at both sides of the trench and are located on the high-energy implantation region 103 - 1 ;

[0091] A heavily doped region 108 , wherein the heavily doped region 108 is located in the body region 106 ;

[0092] an interlayer dielectric layer 110, wherein the interlayer dielectric layer 110 covers a portion of the surface of the gate dielectric layer 104, the trench gate 105 and the heavily doped region 108; and,

[0093] A source metal layer 111 and a drain metal layer 112, wherein the source metal layer 111 covers the interlayer dielectric layer 110 and the remaining surface of the heavily doped region 108, and the drain metal layer 112 covers the back side of the substrate 101;

[0094] The distance between each of the low-energy injection regions 103 - 2 and the gate dielectric layer 104 is greater than the distance between each of the high-energy injection regions 103 - 1 and the gate dielectric layer 104 .

[0095] Preferably, the super junction trench gate MOSFET may further include: a contact hole 109 and a diffusion region 107, wherein the contact hole 109 is located in the heavily doped region 108 and the partially thick body region 106, and the diffusion region 107 is located at the bottom of the contact hole 109. Further, the contact hole 109 needs to be filled with metal to obtain a metal plug that leads the heavily doped region 108 and the diffusion region 107 out.

[0096] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for preparing a super junction trench gate MOSFET, characterized in that: include: A substrate is provided, wherein an epitaxial layer is formed on the front side of the substrate, a trench is formed in the epitaxial layer, a gate dielectric layer and a trench gate are formed in the trench, the gate dielectric layer covers the bottom wall and the side wall of the trench, the trench gate covers the gate dielectric layer and fills the trench, a body region is further formed in the epitaxial layer, and the upper surface of the body region is flush with the upper surface of the epitaxial layer; forming a first silicon oxide layer and a silicon nitride layer in sequence, wherein the first silicon oxide layer covers the body region, the gate dielectric layer and the trench gate, and the silicon nitride layer covers the first silicon oxide layer; forming a mask structure, wherein the mask structure is located on the silicon nitride layer above the trench gate; Using an ion implantation process to form two high-energy implantation regions in the epitaxial layer on both sides of the mask structure, wherein the high-energy implantation regions are close to the lower surface of the epitaxial layer; Removing a portion of the thickness of the mask structure and forming a third silicon oxide layer, wherein the third silicon oxide layer covers the remaining thickness of the mask structure and the silicon nitride layer; Using an ion implantation process, two low-energy implantation regions are formed in the epitaxial layer and the body region on both sides of the mask structure of the remaining thickness, wherein the low-energy implantation regions are located on the high-energy implantation regions; removing the third silicon oxide layer, the remaining thickness of the mask structure and the silicon nitride layer; forming a heavily doped region in the body region by using an ion implantation process; forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers a portion of the surface of the gate dielectric layer, the trench gate and the heavily doped region; as well as, Forming a source metal layer and a drain metal layer, wherein the source metal layer covers the interlayer dielectric layer and the remaining surface of the heavily doped region, and the drain metal layer covers the back side of the substrate; Wherein, the distance between each of the low-energy injection regions and the gate dielectric layer is greater than the distance between each of the high-energy injection regions and the gate dielectric layer.

2. The method for preparing a super junction trench gate MOSFET according to claim 1, characterized in that: The thickness of the third silicon oxide layer is 200Å~3000Å.

3. The method for preparing a super junction trench gate MOSFET according to claim 2, characterized in that: The ion implantation opening of the low energy implantation area is formed by self-alignment based on the thickness of the third silicon oxide layer and the ion implantation opening of the high energy implantation area.

4. The method for preparing a super junction trench gate MOSFET according to claim 1, characterized in that: The difference between the distance between each of the low-energy implantation regions and the gate dielectric layer and the distance between each of the high-energy implantation regions and the gate dielectric layer is equal to the thickness of the third silicon oxide layer.

5. The method for preparing a super junction trench gate MOSFET according to claim 1, characterized in that: A p-type impurity implantation process is used to form two symmetrical high-energy implantation regions in the epitaxial layer on the side of the trench, wherein the ion implantation concentration of the high-energy implantation region is 2E12atoms / cm 2 ~2E13atoms / cm 2 , the injection energy is greater than or equal to 1000KeV~3000KeV.

6. The method for preparing a super junction trench gate MOSFET according to claim 1, characterized in that: A p-type impurity implantation process is used to form two symmetrical low-energy implantation regions in the epitaxial layer and the body region on the side of the trench, wherein the ion implantation concentration of the low-energy implantation region is 2E12atoms / cm 2 ~ 2E13atoms / cm 2 , the injection energy is less than or equal to 200 KeV ~2500 KeV.

7. The method for preparing a super junction trench gate MOSFET according to claim 1, characterized in that: The step of forming a mask structure, wherein the mask structure is located on the silicon nitride layer above the trench gate, comprises: forming a second silicon oxide layer, wherein the second silicon oxide layer covers the silicon nitride layer; forming a photoresist layer, wherein the photoresist layer covers the second silicon oxide layer; and The photoresist layer and the second silicon oxide layer above the body region are removed by photolithography and etching processes to obtain the mask structure.

8. The method for preparing a super junction trench gate MOSFET according to claim 7, characterized in that: The thickness of the second silicon oxide layer is 2 μm to 5 μm, and the thickness of the photoresist layer is 0.5 μm to 3 μm.

9. The method for preparing a super junction trench gate MOSFET according to claim 1, characterized in that: After forming the heavily doped region in the body region by an ion implantation process and before forming the interlayer dielectric layer, the method for preparing the super junction trench gate MOSFET further includes: Etching the heavily doped region and a portion of the body region using a patterned photoresist layer to obtain a contact hole; Using the patterned photoresist layer as a mask, an ion implantation process is used to form a diffusion region in the body region, wherein the diffusion region is located at the bottom end of the contact hole; performing a thermal annealing process on the diffusion region, the high energy implantation region, and the low energy implantation region to activate the diffusion region, the high energy implantation region, and the low energy implantation region; and The contact hole is filled with metal to obtain a metal plug.

10. The method for preparing a super junction trench gate MOSFET according to claim 1, characterized in that: The thickness of the first silicon oxide layer is 50Å~200Å; the thickness of the silicon nitride layer is 200Å-10000Å.

11. The method for preparing a super junction trench gate MOSFET according to claim 1, characterized in that: The conductivity type of the doped ions of the substrate is N type.

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