Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate, forming a channel fin on the substrate, and further forming a gate structure across the channel fin on the substrate. The gate structure covers a portion of the top and a portion of the sidewalls of the channel fin, and a sidewall layer is formed on the sidewall of the gate structure, the sidewall layer having an outer sidewall facing away from the gate structure; using the sidewall layer as an etching mask, forming source / drain recesses in the channel fins on both sides of the gate structure, the sidewalls of the source / drain recesses being recessed relative to the outer sidewall in a direction toward the gate structure; and forming a source / drain doped layer in the source / drain recess. This embodiment of the invention expands the space of the source / drain recesses, correspondingly providing more space for forming the source / drain doped layer, thus forming a larger source / drain doped region, thereby introducing greater stress into the channel and improving the performance of the semiconductor structure, for example, improving channel effect and anti-channel effect.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, the size of MOSFET devices is constantly shrinking, and the gate length of transistors is also constantly shrinking. Short-channel effect (SCE) and reverse short-channel effect (RSCE) have become key limiting factors for improving the performance of MOSFET devices.

[0003] Therefore, in order to reduce the impact of short-channel effects, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. Compared with planar MOSFETs, FinFET structures have stronger channel control capabilities, but still require increased channel stress to better suppress short-channel effects. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which enhances channel stress and improves the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; a channel fin located on the substrate; a gate structure spanning the channel fin and covering a portion of the top and a portion of the sidewalls of the channel fin; a sidewall layer located on the sidewalls of the gate structure, the sidewall layer having an outer sidewall facing away from the gate structure; source / drain recesses located in the channel fins on both sides of the gate structure, the sidewalls of the source / drain recesses being recessed relative to the outer sidewalls in a direction toward the gate structure; and a source / drain doped layer located in the source / drain recesses.

[0006] Optionally, a portion of the sidewall of the source / drain recess is recessed relative to the outer sidewall in a direction toward the gate structure.

[0007] Optionally, the normal direction of the substrate surface is longitudinal, and the channel fin includes a first fin layer and a second fin layer stacked alternately along the longitudinal direction, the first fin layer and the second fin layer being made of different materials; the sidewall of the source / drain groove includes the end face of the first fin layer and the end face of the second fin layer, and in the source / drain groove, the end face of the first fin layer or the end face of the second fin layer is recessed relative to the outer sidewall in the direction toward the gate structure.

[0008] Optionally, the electron mobility of the second fin layer is greater than that of the first fin layer; the end face of the first fin layer is recessed relative to the outer wall in the direction toward the gate structure.

[0009] Optionally, in the longitudinal direction, the second fin layer is located between adjacent first fin layers.

[0010] Optionally, in the channel fin, the number of layers of the first fin layer in the longitudinal direction is two to four.

[0011] Optionally, the material of the first fin layer includes silicon, and the material of the second fin layer includes silicon germanide.

[0012] Optionally, in the longitudinally staggered first fin layer and the second fin layer, the thickness of the first fin layer is 15 nm to 30 nm, and the thickness of the second fin layer is 15 nm to 30 nm.

[0013] Optionally, the sidewall of the source / drain groove is recessed by a distance relative to the outer sidewall that is at least equal to the thickness of the sidewall.

[0014] Optionally, the sidewalls of the source / drain recesses are recessed by up to 2 nm to 3 nm relative to the sidewalls of the gate structure.

[0015] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a channel fin is formed on the substrate, and a gate structure is further formed on the substrate spanning the channel fin, the gate structure covering a portion of the top and a portion of the sidewalls of the channel fin, a sidewall layer being formed on the sidewalls of the gate structure, the sidewall layer having an outer sidewall facing away from the gate structure; using the sidewall layer as an etching mask, forming source / drain recesses in the channel fins on both sides of the gate structure, the sidewalls of the source / drain recesses being recessed relative to the outer sidewalls in a direction toward the gate structure; and forming a source / drain doped layer in the source / drain recesses.

[0016] Optionally, in the step of forming the source-drain recess, a portion of the sidewall of the source-drain recess is recessed relative to the outer sidewall in a direction toward the gate structure.

[0017] Optionally, in the step of providing the substrate, the normal direction of the substrate surface is longitudinal, and the channel fin includes a first fin layer and a second fin layer stacked alternately along the longitudinal direction, wherein the first fin layer and the second fin layer are made of different materials; in the step of forming the source / drain groove, the sidewall of the source / drain groove includes the end face of the first fin layer and the end face of the second fin layer, and in the source / drain groove, the end face of the first fin layer or the end face of the second fin layer is recessed relative to the outer sidewall in the direction toward the gate structure.

[0018] Optionally, the electron mobility of the second fin layer is greater than that of the first fin layer; in the step of forming the source-drain groove, the end face of the first fin layer is recessed relative to the outer wall in the direction toward the gate structure.

[0019] Optionally, in the longitudinal direction, the second fin layer is located between adjacent first fin layers.

[0020] Optionally, in the fin structure, the number of layers of the first fin layer in the longitudinal direction is two to four.

[0021] Optionally, the method for forming the source / drain groove includes: using the sidewall layer as an etching mask, etching the first fin layer and the second fin layer on both sides of the gate structure to form a first groove in the channel fin; performing lateral etching on the first fin layer or the second fin layer exposed on the sidewall of the first groove along a direction perpendicular to the sidewall of the gate structure to form a second groove communicating with the first groove in the channel fin below the gate structure, wherein the second groove and the first groove constitute the source / drain groove.

[0022] Optionally, the lateral etching process includes a wet etching process.

[0023] Optionally, a dry etching process is used to etch the first fin layer and the second fin layer on both sides of the gate structure to form the first groove.

[0024] Optionally, the material of the first fin includes silicon, and the material of the second fin layer includes silicon germanide.

[0025] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0026] In the semiconductor structure provided by the embodiments of the present invention, source and drain grooves are provided in the channel fins on both sides of the gate structure. The sidewalls of the source and drain grooves are recessed relative to the outer sidewalls in the direction toward the gate structure. Compared with the scheme where the sidewalls of the source and drain grooves are flush with the outer sidewalls, the embodiments of the present invention expand the space of the source and drain grooves, and correspondingly provide a larger space for forming the source and drain doped layer. Therefore, a larger source and drain doped layer is formed, which brings greater stress to the channel and thus improves the performance of the semiconductor structure. For example, it increases the saturation current (Idsat) and operating current (Ieff) of the semiconductor structure and improves the channel effect (SCE) and reverse channel effect (RSCE).

[0027] In this embodiment of the invention, the sidewall layer is used as an etching mask to form source / drain grooves in the channel fins on both sides of the gate structure. The sidewalls of the source / drain grooves are recessed relative to the outer sidewalls in the direction toward the gate structure. Compared with the scheme where the sidewalls and outer sidewalls of the source / drain grooves are flush, this embodiment of the invention expands the space of the source / drain grooves, thus providing more space for forming the source / drain doped layer. Therefore, a larger source / drain doped layer is formed, which brings greater stress to the channel and improves the performance of the semiconductor structure. For example, it increases the saturation current (Idsat) and operating current (Ieff) of the semiconductor structure and improves the channel effect (SCE) and reverse channel effect (RSCE). Attached Figure Description

[0028] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0029] Figure 4 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0030] Figures 5 to 8 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0031] The performance of semiconductor structures still needs improvement. This paper analyzes the reasons why the performance of a semiconductor structure still needs improvement, using a specific semiconductor structure formation method as an example.

[0032] refer to Figures 1 to 3 The diagram shows a schematic representation of each step in a method for forming a semiconductor structure.

[0033] refer to Figure 1 A substrate 10 is provided, on which a channel fin 20 is formed, and a gate structure 30 is also formed on the substrate 10 across the channel fin 20. The gate structure 30 covers a portion of the top and a portion of the sidewalls of the channel fin 20. A sidewall layer 31 is formed on the sidewall of the gate structure 30, and the sidewall layer 31 has an outer sidewall 32 facing away from the gate structure.

[0034] refer to Figure 2 Using the sidewall layer 31 as an etching mask, a dry etching process is used to form source / drain grooves 40 in the channel fins 20 on both sides of the gate structure 30. The sidewalls of the source / drain grooves 40 are flush with the outer sidewall 32.

[0035] refer to Figure 3 A source / drain doped layer 50 is formed in the source / drain groove 40.

[0036] As the feature size of the device decreases, the space of the source / drain groove 40 also decreases, resulting in a smaller volume of the source / drain doped layer 50. In this case, the source / drain doped layer 50 cannot provide sufficient stress to the channel, thereby affecting the performance of the semiconductor structure.

[0037] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a channel fin is formed on the substrate, and a gate structure is further formed on the substrate spanning the channel fin, the gate structure covering a portion of the top and a portion of the sidewalls of the channel fin, a sidewall layer being formed on the sidewalls of the gate structure, the sidewall layer having an outer sidewall facing away from the gate structure; using the sidewall layer as an etching mask, forming source / drain recesses in the channel fins on both sides of the gate structure, the sidewalls of the source / drain recesses being recessed relative to the outer sidewalls in a direction toward the gate structure; and forming a source / drain doped layer in the source / drain recesses.

[0038] In this embodiment of the invention, the sidewall layer is used as an etching mask to form source / drain grooves in the channel fins on both sides of the gate structure. The sidewalls of the source / drain grooves are recessed relative to the outer sidewalls in the direction toward the gate structure. Compared with the scheme where the sidewalls and outer sidewalls of the source / drain grooves are flush, this embodiment of the invention expands the space of the source / drain grooves, thus providing more space for forming the source / drain doped layer. Therefore, a larger source / drain doped layer is formed, which brings greater stress to the channel and improves the performance of the semiconductor structure. For example, it increases the saturation current (Idsat) and operating current (Ieff) of the semiconductor structure and improves the channel effect (SCE) and reverse channel effect (RSCE).

[0039] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0040] refer to Figure 4 The diagram shows a schematic representation of an embodiment of the semiconductor structure of the present invention.

[0041] The semiconductor structure includes: a substrate 101; a channel fin 201 located on the substrate 101; a gate structure 301 spanning the channel fin 201 and covering a portion of the top and a portion of the sidewalls of the channel fin 201; a sidewall layer 311 located on the sidewalls of the gate structure 301, the sidewall layer 311 having an outer sidewall 321 facing away from the gate structure 301; source / drain recesses (not shown) located in the channel fins 201 on both sides of the gate structure 301, the sidewalls of the source / drain recesses being recessed relative to the outer sidewall 321 in a direction toward the gate structure 301; and a source / drain doped layer 501 located in the source / drain recesses.

[0042] In the semiconductor structure provided by this embodiment of the invention, the channel fins 201 on both sides of the gate structure 301 have source / drain grooves. The sidewalls of the source / drain grooves are recessed relative to the outer sidewalls 321 in the direction toward the gate structure 301. Compared with the scheme where the sidewalls of the source / drain grooves and the outer sidewalls 321 are flush, this embodiment of the invention expands the space of the source / drain grooves, and correspondingly provides a larger space for forming the source / drain doped layer 501. Therefore, a larger source / drain doped layer 501 is formed, which brings greater stress to the channel and thus improves the performance of the semiconductor structure. For example, it increases the saturation current (Idsat) and operating current (Ieff) of the semiconductor structure and improves the channel effect (SCE) and reverse channel effect (RSCE).

[0043] The substrate 101 provides the basis for the process operation of forming the semiconductor structure.

[0044] In this embodiment, the substrate 101 is made of silicon. In other embodiments, the substrate 101 may also be made of one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium bismuth. The substrate 101 may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The material of the substrate 101 may be a material suitable for process requirements or easy to integrate.

[0045] The channel fin 201 is located on the substrate 101 and is used to provide a channel for the fin field-effect transistor.

[0046] In this embodiment, the normal direction of the surface of the substrate 101 is longitudinal, and the channel fin 201 includes a first fin layer 211 and a second fin layer 221 that are stacked alternately along the longitudinal direction. The first fin layer 211 and the second fin layer 221 are made of different materials.

[0047] By employing a first fin layer 211 and a second fin layer 221 made of different materials and stacked longitudinally in an alternating manner, during the formation of the semiconductor structure, the etching selectivity ratio between the first fin layer 211 and the second fin layer 221 facilitates the recessing of a portion of the sidewall of the channel fin 201 relative to the outer wall 321 in the direction toward the gate structure 301, thereby expanding the space of the source / drain recess. Compared to a single-layer channel fin, this embodiment, by recessing a portion of the sidewall of the channel fin 201 relative to the outer wall 321 in the direction toward the gate structure 301, can simultaneously ensure that excessive channel fins 201 are not removed and that the space of the source / drain recess is expanded, thus meeting process requirements while ensuring structural stability.

[0048] The first fin layer 211 and the second fin layer 221 are made of different materials, which facilitates selective etching of the fin layers that need to be recessed during the formation of the semiconductor structure.

[0049] In this embodiment, the electron mobility of the second fin layer 221 is greater than that of the first fin layer 211.

[0050] The majority carriers migrate faster within the second fin layer 221, resulting in a larger current flowing through it. This leads to a higher operating current and lower power consumption in the final field-effect transistor. Therefore, the higher electron mobility of the second fin layer 221 compared to the first fin layer 211 is beneficial for obtaining a field-effect transistor with high operating current and low power consumption.

[0051] In this embodiment, the first fin layer 211 is made of silicon, and the second fin layer 221 is made of silicon germanide. The stress generated in the second fin layer 221 is greater than the stress generated in the first fin layer 211.

[0052] The material of the second fin layer 221 is silicon germanide, and the material of the first fin layer 211 is silicon. Silicon germanide has a larger electron mobility than silicon, which can generate a larger operating current. Furthermore, a larger etching selectivity can be formed between silicon germanide and silicon. Therefore, when etching the first fin layer 211, it is easy to retain the second fin layer 221 to form the source-drain groove.

[0053] The source / drain groove is used to provide growth space for the source / drain doped layer 501.

[0054] The sidewall of the source / drain recess is recessed relative to the outer sidewall 321 in the direction toward the gate structure 301, thereby expanding the space of the source / drain recess.

[0055] In this embodiment, a portion of the sidewall of the source / drain groove is recessed relative to the outer sidewall 321 in the direction toward the gate structure 301.

[0056] Compared to a scheme where all sidewalls of the source / drain groove are recessed relative to the outer sidewall in the direction toward the gate structure, in this embodiment, a portion of the sidewalls of the source / drain groove are recessed relative to the outer sidewall 321 in the direction toward the gate structure 301, so that the remaining channel fin 201 is not too small, thereby reducing the probability of adversely affecting the performance of the semiconductor structure.

[0057] Specifically, the sidewall of the source / drain groove includes the end face of the first fin layer 211 and the end face of the second fin layer 221, that is, the end face of the first fin layer 211 and the end face of the second fin layer 221 constitute the sidewall of the source / drain groove, and in the source / drain groove, the end face of the first fin layer 211 or the end face of the second fin layer 221 is recessed relative to the outer sidewall 321 in the direction toward the gate structure 301.

[0058] Specifically, based on the device performance requirements, one end face is selected from the end face of the first fin layer 211 and the end face of the second fin layer 221, and the selected end face is recessed relative to the outer sidewall 321 in the direction toward the gate structure 301.

[0059] In this embodiment, the electron mobility of the second fin layer 221 is greater than that of the first fin layer 211. The end face of the first fin layer 211 is recessed relative to the outer wall in the direction toward the gate structure 301, thereby causing a portion of the sidewall of the source / drain groove to be recessed relative to the outer wall 321 in the direction toward the gate structure 301.

[0060] The source / drain groove is formed by the concave and expanding end face of the first fin layer 211 relative to the outer wall 321 in the direction toward the gate structure 301. Thus, the end face of the first fin layer 211 is concave relative to the end face of the second fin layer 221. This increases the space of the source / drain groove while retaining the second fin layer 221, which has a higher electron mobility, thus facilitating a larger operating current. Furthermore, since the electron mobility of the first fin layer 211 is lower than that of the second fin layer 221, concave end face of the first fin layer 211 relative to the end face of the second fin layer 221 increases the stress exerted by the source / drain doped layer 501 on the first fin layer 211. In this embodiment, the concave distance of the sidewall of the source / drain groove relative to the outer wall 321 is at least equal to the thickness of the sidewall layer 311.

[0061] If the recessed distance between the sidewall of the source / drain groove and the outer sidewall 321 is too small, the source / drain groove will not form a sufficiently large space, resulting in an insufficient volume of the source / drain doped layer 501 to provide adequate stress for the channel. Therefore, the recessed distance between the sidewall of the source / drain groove and the outer sidewall 321 is at least equal to the thickness of the sidewall layer 311, thereby effectively expanding the space of the source / drain groove and enabling the source / drain doped layer 501 to provide sufficient stress for the channel.

[0062] Specifically, the sidewalls of the source / drain recesses are recessed by at most 2nm to 3nm relative to the sidewalls of the gate structure 301. For example, the sidewalls of the source / drain recesses are recessed by at most 2.5nm relative to the sidewalls of the gate structure 301.

[0063] If the sidewall of the source / drain groove is recessed too far relative to the outer sidewall, it will increase the difficulty of the process and cause the remaining length of the first fin 211 below the gate structure 301 to be too small, resulting in a short channel length and thus affecting the performance of the semiconductor structure.

[0064] In this embodiment, the second fin layer 221 is located between adjacent first fin layers 211.

[0065] Because the doping of the second fin layer 221 material is difficult to control, and the stress generated by the second fin layer 221 is relatively large, if the second fin layer 221 is too close to the gate structure 301 in the vertical direction, too many first fins 211 below the second fin layer 221 will be affected by the stress generated by the second fin layer 221, thereby increasing the probability of damage to the first fins 211 and also leading to a decrease in the reliability of the semiconductor structure. If the second fin layer 221 is too close to the substrate 101 in the vertical direction, the gate structure 301 will find it difficult to control the leakage current of the second fin layer 221, thereby easily causing excessive leakage current. Therefore, in this embodiment, when using the second fin layer 221 with greater stress, the second fin layer 221 is located between adjacent first fin layers 211.

[0066] In this embodiment, in the channel fin 201, the first fin layer 211 has at least two layers in the longitudinal direction.

[0067] However, the number of layers in the first fin layer 211 cannot be too large. If the number of layers is too large, the thickness of each first fin layer 211 will be relatively small, which will easily increase the difficulty and complexity of the process. Moreover, the material of the source / drain doped layer 501 will be difficult to fill the space enclosed by the recess of the first fin layer 211, which is not conducive to the stability of the semiconductor structure. Therefore, in this embodiment, the number of layers in the first fin layer 211 is two to four.

[0068] In this embodiment, the channel fin 201 includes two first fin layers 211, which reduces the complexity of the process while allowing for a larger space in the source / drain groove.

[0069] The end faces of the two first fin layers 211 are recessed relative to the outer wall 321 toward the gate structure 301, leaving the end face of the second fin layer 221 unrecessed. This ensures the stability of the semiconductor structure and allows the space for the source-drain grooves to expand to meet process requirements.

[0070] In this embodiment, in the longitudinally staggered first fin layer 211 and second fin layer 221, the thickness of the first fin layer 211 is 15 nm to 30 nm, and the thickness of the second fin layer is 15 nm to 30 nm. For example, the thickness of the first fin layer 211 is 20 nm, and the thickness of the second fin layer 221 is 20 nm.

[0071] The thickness of the first fin layer 211 should not be too small or too large. If the thickness of the first fin layer 211 is too small, it will increase the difficulty of the process of recessing the end face of the first fin layer 211 relative to the outer wall 321 in the direction toward the gate structure 301, and the source / drain groove space will not be large enough, and the source / drain doped layer 501 will not provide sufficient stress. If the thickness of the first fin layer 211 is too large, it will lead to the second fin layer 221 being too thin, and the structure of the second fin layer 221 will be unstable, affecting the overall stability of the semiconductor structure.

[0072] The thickness of the second fin layer 221 should not be too small or too large. If the thickness of the second fin layer 221 is too small, it will lead to instability of the structure of the second fin layer 221, affecting the overall stability of the semiconductor structure. If the thickness of the second fin layer 221 is too large, it will lead to the thickness of the first fin layer 211 being too small, which will increase the difficulty of the process of recessing the end face of the first fin layer 211 relative to the outer wall 321 in the direction toward the gate structure 301. The source / drain groove space will also be insufficient, and the source / drain doping layer will not provide sufficient stress.

[0073] It should be noted that the semiconductor structure further includes: a bottom fin (not shown), located between the bottom of the channel fin 201 and the substrate 101; and an isolation layer (not shown), located on the substrate 101 exposed by the bottom fin, with the top of the isolation layer flush with the top of the bottom fin.

[0074] The bottom fin and the bottommost fin layer are an integral structure.

[0075] In this embodiment, the bottommost fin layer is the first fin layer 211. Therefore, the bottom fin and the bottommost first fin layer 211 are an integral structure.

[0076] The isolation layer serves as a shallow trench isolation (STI) structure to isolate adjacent transistors. The isolation layer can be made of silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the isolation layer is made of silicon oxide.

[0077] In this embodiment, the gate structure 301 is a metal gate structure.

[0078] In this embodiment, the gate structure 301 includes a high-k gate dielectric layer (not shown), a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer.

[0079] The high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high-k gate dielectric layer is HfO2.

[0080] The work function layer is used to adjust the threshold voltage of the formed transistor. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.

[0081] The gate electrode layer is used to bring out the electrical properties of the gate structure 301. In this embodiment, the material of the gate electrode layer is Al, Cu, Ag, Au, Pt, Ni, Ti, or W.

[0082] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0083] In other embodiments, the gate structure may also be a pseudo-gate structure, which occupies space for the subsequent formation of a metal gate structure. The pseudo-gate structure may be a single-layer structure or a multi-layer structure, and the material of the pseudo-gate structure may include one or both of amorphous silicon and polycrystalline silicon. Alternatively, the material of the pseudo-gate structure may also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon nitride, silicon carbonitride, or amorphous carbon.

[0084] It should be noted that, depending on process requirements, a gate oxide layer (not shown) may also be formed between the gate structure 301 and the channel fin 201. The material of the gate oxide layer may be silicon oxide.

[0085] The sidewall layer 311 serves as an etching mask for forming the source / drain grooves and also protects the sidewalls of the gate structure 301.

[0086] The sidewall layer 311 can be a single-layer structure or a multi-layer structure, and the material of the sidewall layer 311 can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall layer 311 is a single-layer structure, and the material of the sidewall layer 311 is silicon nitride.

[0087] In this embodiment, the sidewall layer 311 has an outer sidewall 321 facing away from the gate structure 301.

[0088] The source / drain doped layer 501 is used to provide stress to the channel region of the transistor.

[0089] In this embodiment, the material of the source / drain doped layer 501 includes one or more of silicon germanide, silicon, and silicon carbide.

[0090] In this embodiment, the semiconductor structure is used to form a PMOS transistor. The source / drain doped layer 501 includes an epitaxial layer doped with P-type ions. The material of the epitaxial layer can be silicon or silicon germanide, thereby providing compressive stress to the channel region of the PMOS transistor, which is beneficial to improving the carrier mobility of the PMOS transistor. The P-type ions are B ions, Ga ions, or In ions. In other embodiments, when the semiconductor structure is used to form an NMOS transistor, the source / drain doped layer includes an epitaxial layer doped with N-type ions. The material of the epitaxial layer can be silicon or silicon carbide, thereby providing tensile stress to the channel region of the NMOS transistor, which is beneficial to improving the carrier mobility of the NMOS transistor. The N-type ions are P ions, As ions, or Sb ions.

[0091] Figures 5 to 8 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0092] refer to Figure 5 A substrate 100 is provided, on which a channel fin 200 is formed, and a gate structure 300 is also formed on the substrate 100 across the channel fin 200. The gate structure 300 covers a portion of the top and a portion of the sidewalls of the channel fin 200. A sidewall layer 310 is formed on the sidewall of the gate structure 300, and the sidewall layer 310 has an outer sidewall 320 facing away from the gate structure 300.

[0093] The substrate 100 provides the basis for subsequent process operations.

[0094] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate 100 may also be made of one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium bismuth. The substrate 100 may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The material of the substrate 100 may be a material suitable for process requirements or easy to integrate.

[0095] The channel fin 200 is located on the substrate 100 and is used to provide a channel for the fin field-effect transistor.

[0096] In this embodiment, in the step of providing the substrate 100, the normal direction of the surface of the substrate 100 is longitudinal, and the channel fin 200 includes a first fin layer 210 and a second fin layer 220 that are stacked alternately along the longitudinal direction, and the first fin layer 210 and the second fin layer are made of different materials 220.

[0097] Subsequent processes include: using the sidewall layer 310 as an etching mask, forming source / drain recesses in the channel fins 200 on both sides of the gate structure 300, wherein the sidewalls of the source / drain recesses are recessed relative to the outer sidewall 320 in the direction toward the gate structure 300. By employing a first fin layer 210 and a second fin layer 220 of different materials stacked longitudinally in an alternating manner, and utilizing the etching selectivity ratio between the first fin layer 210 and the second fin layer 220, it is easy to make the end face of the first fin layer or the end face of the second fin layer recessed relative to the outer sidewall in the direction toward the gate structure, thereby causing a portion of the sidewalls of the source / drain recesses to be recessed relative to the outer sidewall in the direction toward the gate structure.

[0098] In this embodiment, the electron mobility of the second fin layer 220 is greater than that of the first fin layer 210.

[0099] The majority carriers migrate faster within the second fin layer 220, resulting in a larger current flowing through it. This leads to a higher operating current and lower power consumption in the final field-effect transistor. Therefore, the higher electron mobility of the second fin layer 220 compared to the first fin layer 210 is beneficial for obtaining a field-effect transistor with high operating current and low power consumption.

[0100] In this embodiment, the first fin layer 210 is made of silicon, and the second fin layer 220 is made of silicon germanide. The stress generated in the second fin layer 221 is greater than the stress generated in the first fin layer 211.

[0101] The material of the second fin layer 220 is silicon germanide, and the material of the first fin layer 210 is silicon. Silicon germanide has a larger electron mobility than silicon, which can generate a larger operating current. Furthermore, a larger etching selectivity ratio can be formed between silicon germanide and silicon, which is beneficial to retain the second fin layer 220 when etching the first fin layer 210, thus forming the source / drain groove 420.

[0102] In this embodiment, in the longitudinal direction, the second fin layer 220 is located between adjacent first fin layers 210.

[0103] Because the doping of the second fin layer 220 material is difficult to control, and the stress generated by the second fin layer 220 is relatively large, if the second fin layer 220 is too close to the gate structure 300 in the vertical direction, too many first fins 210 below the second fin layer 220 will be affected by the stress generated by the second fin layer 220, thereby increasing the probability of damage to the first fins 210 and also leading to a decrease in the reliability of the semiconductor structure. If the second fin layer 210 is too close to the substrate 100 in the vertical direction, the gate structure 300 will find it difficult to control the leakage current of the second fin layer 220, thereby easily causing excessive leakage current. Therefore, in this embodiment, when using the second fin layer 220 with greater stress, the second fin layer 220 is located between adjacent first fin layers 210.

[0104] In this embodiment, in the channel fin portion 200, the first fin layer 210 has at least two layers in the longitudinal direction.

[0105] However, the number of layers in the first fin layer 210 cannot be too large. If the number of layers is too large, the thickness of each first fin layer 210 will be relatively small, which will easily increase the difficulty and complexity of the process. Moreover, the material of the source / drain doped layer 500 will be difficult to fill the space enclosed by the recess of the first fin layer 210, which is not conducive to the stability of the semiconductor structure. Therefore, in this embodiment, the number of layers in the first fin layer 210 is two to four.

[0106] In this embodiment, the channel fin 200 includes two first fin layers 210, which reduces the complexity of the process while allowing for a larger space in the source / drain groove.

[0107] In this embodiment, in the longitudinally staggered first fin layer 210 and second fin layer 220, the thickness of the first fin layer 210 is 15 nm to 30 nm, and the thickness of the second fin layer is 15 nm to 30 nm. For example, the thickness of the first fin layer 210 is 20 nm, and the thickness of the second fin layer 220 is 20 nm.

[0108] The thickness of the first fin layer 210 should not be too small or too large. If the thickness of the first fin layer 210 is too small, it will increase the difficulty of the process of recessing the end face of the first fin layer 210 relative to the outer wall 320 in the direction toward the gate structure 300, and the space of the source / drain groove 420 formed will not be large enough, and the source / drain doped layer formed will not provide sufficient stress. If the thickness of the first fin layer 210 is too large, it will lead to the second fin layer 220 being too thin, and the structure of the second fin layer 220 will be unstable, affecting the overall stability of the semiconductor structure.

[0109] The thickness of the second fin layer 220 should not be too small or too large. If the thickness of the second fin layer 220 is too small, it will cause the structure of the second fin layer 220 to be unstable, affecting the overall stability of the semiconductor structure. If the thickness of the second fin layer 220 is too large, it will cause the thickness of the first fin layer 210 to be too small, which will increase the difficulty of the process of recessing the end face of the first fin layer 210 relative to the outer wall 320 in the direction toward the gate structure 300. The space of the source / drain groove 420 formed will also be insufficient, and the source / drain doped layer formed will not provide sufficient stress.

[0110] It should be noted that a bottom fin (not shown) is also formed between the bottom of the channel fin 201 and the base 101, and an isolation layer (not shown) is also formed on the exposed base 101 of the bottom fin, with the top of the isolation layer being flush with the top of the bottom fin.

[0111] The bottom fin and the bottommost fin layer are an integral structure.

[0112] In this embodiment, the bottommost fin layer is the first fin layer 210. Therefore, the bottom fin and the bottommost first fin layer 210 are an integral structure.

[0113] The isolation layer serves as a shallow trench isolation (STI) structure to isolate adjacent transistors. The isolation layer can be made of silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the isolation layer is made of silicon oxide.

[0114] In this embodiment, the gate structure 300 is a dummy gate structure. The dummy gate structure occupies space for the subsequent formation of the metal gate structure. The dummy gate structure can be a single-layer structure or a multilayer structure. The material of the dummy gate structure includes one or both of amorphous silicon and polycrystalline silicon. Alternatively, the material of the dummy gate structure can also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon nitride, silicon carbonitride, or amorphous carbon.

[0115] It should be noted that, depending on process requirements, a gate oxide layer (not shown) may also be formed between the gate structure 300 and the channel fin 200. The material of the gate oxide layer may be silicon oxide.

[0116] The sidewall layer 310 serves as an etching mask for forming the source / drain grooves and also protects the sidewalls of the gate structure 300.

[0117] The sidewall layer 310 can be a single-layer structure or a multilayer structure, and the material of the sidewall layer 310 can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall layer 310 is a single-layer structure, and the material of the sidewall layer 310 is silicon nitride.

[0118] In this embodiment, the sidewall layer 310 has an outer sidewall 320 facing away from the gate structure 300.

[0119] Reference Figure 6 and Figure 7 Using the sidewall layer 310 as an etching mask, source / drain grooves 420 are formed in the channel fins 200 on both sides of the gate structure 300. The sidewalls of the source / drain grooves 420 are recessed relative to the outer sidewall 320 in the direction toward the gate structure 300.

[0120] The source / drain groove 420 is used to provide growth space for subsequent source / drain doped layers.

[0121] The sidewalls of the source / drain recess are recessed relative to the outer sidewall in the direction toward the gate structure. Compared with the scheme where the sidewalls of the source / drain recess and the outer sidewall are flush, the embodiment of the present invention expands the space of the source / drain recess, thereby providing more space for forming the source / drain doped layer. As a result, a larger source / drain doped layer is formed, which brings greater stress to the channel and thus improves the performance of the semiconductor structure. For example, it increases the saturation current (Idsat) and operating current (Ieff) of the semiconductor structure and improves the channel effect (SCE) and reverse channel effect (RSCE).

[0122] In this embodiment, during the step of forming the source / drain recess 420, a portion of the sidewall of the source / drain recess 420 is recessed relative to the outer sidewall 320 in a direction toward the gate structure 300 (e.g., Figure 7 (As shown).

[0123] Compared to a scheme where all sidewalls of the source / drain recess are recessed relative to the outer sidewall in the direction toward the gate structure, a portion of the sidewalls of the source / drain recess 420 are recessed relative to the outer sidewall 321 in the direction toward the gate structure 301, so that the remaining channel fin 201 is not too small, thereby reducing the probability of adversely affecting the performance of the semiconductor structure.

[0124] Specifically, the sidewall of the source / drain recess includes the end face of the first fin layer 210 and the end face of the second fin layer 220. That is, the end face of the first fin layer 210 and the end face of the second fin layer 220 constitute the sidewall of the source / drain recess 420. Therefore, after the source / drain recess 420 is formed, the end face of the first fin layer 210 or the end face of the second fin layer 220 is recessed relative to the outer sidewall 320 in the direction toward the gate structure 300.

[0125] Specifically, the fin layer that needs to be recessed is determined based on the performance requirements of the device.

[0126] In this embodiment, the electron mobility of the second fin layer 220 is greater than that of the first fin layer 210. Therefore, the end face of the first fin layer 210 is recessed relative to the outer wall 320 in the direction toward the gate structure 300.

[0127] The source / drain groove 420 is formed by the concave and enlarged end face of the first fin layer 210 relative to the outer wall 320 in the direction toward the gate structure 300. Thus, the end face of the first fin layer 210 is concave relative to the end face of the second fin layer 220, thereby increasing the space of the source / drain groove while retaining the second fin layer 220 with a higher electron mobility, which is beneficial to obtaining a larger operating current.

[0128] Specifically, refer to Figure 6 The method for forming the source / drain recess 420 includes: using the sidewall layer 310 as an etching mask, etching the first fin layer 210 and the second fin layer 220 on both sides of the gate structure 300, and forming the first recess 400 in the channel fin 200.

[0129] The formation of the first groove 400 provides a process basis for the subsequent formation of the source-drain groove 420.

[0130] In this embodiment, a dry etching process (e.g., anisotropic dry etching process) is used to etch the first fin layer 210 and the second fin layer 220 on both sides of the gate structure 200 to form the first groove 400.

[0131] The dry etching process has the characteristics of anisotropic etching. Therefore, by selecting the dry etching process, it is beneficial to reduce the damage to the substrate 100. At the same time, the dry etching is more directional, which is beneficial to directionally etching the first fin layer 210 and the second fin layer 220 on both sides of the gate structure 200, and is beneficial to improving the morphological quality and dimensional accuracy of the first groove 400.

[0132] refer to Figure 7 Along a direction perpendicular to the sidewall of the gate structure 300, the first fin layer 210 exposed on the sidewall of the first groove 400 is etched laterally, and a second groove 410 communicating with the first groove 400 is formed in the channel fin 200 below the gate structure 300. The second groove 410 and the first groove 400 constitute a source-drain groove 420.

[0133] In this embodiment, the lateral etching process includes a wet etching process.

[0134] The wet etching process has the characteristics of isotropic etching, thereby achieving the effect of lateral etching. It also helps to completely remove the parts that need to be removed from the first fin layer 210, thus providing a good interface foundation for the subsequent process to form the source / drain doped layer 500, thereby improving the formation quality of the source / drain doped layer 500.

[0135] Meanwhile, the wet etching process can achieve a high etching selectivity and is easy to achieve, thereby reducing the loss of other film layers (e.g., the second fin layer 220 and the sidewall layer 310).

[0136] Furthermore, by employing a wet etching process, it is beneficial to avoid the problem of plasma damage.

[0137] In this embodiment, in the step of forming the source / drain groove 420, the sidewall of the source / drain groove 420 is recessed by a distance relative to the outer sidewall at least equal to the thickness of the sidewall 310.

[0138] If the recessed distance between the sidewall of the source / drain groove 420 and the outer sidewall 320 is too small, the source / drain groove 420 will not form a sufficiently large space, resulting in an insufficient volume of the formed source / drain doped layer to provide adequate stress for the channel. Therefore, the recessed distance between the sidewall of the source / drain groove 420 and the outer sidewall 320 must be at least equal to the thickness of the sidewall layer 310, thereby effectively expanding the space of the source / drain groove 420 and enabling the source / drain doped layer 500 to provide sufficient stress for the channel.

[0139] In this embodiment, the sidewalls of the source / drain recess 420 are recessed by at most 2nm to 3nm relative to the sidewalls of the gate structure 300. For example, the sidewalls of the source / drain recess 420 are recessed by at most 2.5nm relative to the sidewalls of the gate structure 300.

[0140] If the sidewall of the source / drain recess 420 is recessed too far relative to the outer sidewall 320, it will increase the difficulty of the process and cause the remaining length of the first fin 210 below the gate structure 300 to be too small, resulting in a short channel length and thus affecting the performance of the semiconductor structure.

[0141] It should be noted that, in this embodiment, the distance by which the sidewall of the source / drain groove 420 is recessed relative to the outer wall 320 refers to the distance by which the sidewall of the second groove 410 is recessed relative to the outer wall 320.

[0142] It should also be noted that, in other embodiments, depending on process requirements, the second fin layer exposed on the sidewall of the first groove can also be etched laterally along a direction perpendicular to the sidewall of the gate structure.

[0143] refer to Figure 8 In the source drain groove 420 (e.g. Figure 7 A source / drain doped layer 500 is formed in the (shown) layer.

[0144] The source / drain doped layer 500 is used to provide stress to the channel region of the transistor.

[0145] In this embodiment, an epitaxial growth process is used to form an epitaxial layer (not shown) in the source / drain groove 420, and during the formation of the epitaxial layer, in-situ self-doped ions form the source / drain doped layer 500.

[0146] Epitaxial growth is a commonly used process in the semiconductor field for forming source and drain doped layers, and it has high process compatibility.

[0147] The source / drain doped layer 500 is made of one or more of silicon germanide, silicon, and silicon carbide.

[0148] In this embodiment, the semiconductor structure is used to form a PMOS transistor. The source / drain doped layer 500 includes an epitaxial layer doped with P-type ions. The material of the epitaxial layer can be silicon or silicon germanide, thereby providing compressive stress to the channel region of the PMOS transistor, which is beneficial to improving the carrier mobility of the PMOS transistor. The P-type ions are B ions, Ga ions, or In ions. In other embodiments, when the semiconductor structure is used to form an NMOS transistor, the source / drain doped layer includes an epitaxial layer doped with N-type ions. The material of the epitaxial layer can be silicon or silicon carbide, thereby providing tensile stress to the channel region of the NMOS transistor, which is beneficial to improving the carrier mobility of the NMOS transistor. The N-type ions are P ions, As ions, or Sb ions.

[0149] The semiconductor structure described in this embodiment can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0150] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, Comprising: a substrate; a channel fin on the substrate; a gate structure across the channel fin and covering part of the top and part of the sidewall of the channel fin; a sidewall layer on the sidewall of the gate structure, the sidewall layer having an outer sidewall facing away from the gate structure; a source-drain recess in the channel fin on both sides of the gate structure, part of the sidewall of the source-drain recess being recessed relative to the outer sidewall in a direction towards the gate structure and the rest of the sidewall not being recessed relative to the outer sidewall in a direction towards the gate structure; a source-drain doped layer in the source-drain recess.

2. The semiconductor structure of claim 1, wherein, The normal direction of the surface of the substrate is longitudinal, the channel fin comprises first fin layers and second fin layers staggered along the longitudinal direction, the materials of the first fin layers and the second fin layers are different; The sidewall of the source-drain recess comprises end faces of the first fin layers and end faces of the second fin layers, and in the source-drain recess, the end faces of the first fin layers or the end faces of the second fin layers are recessed relative to the outer sidewall in a direction towards the gate structure.

3. The semiconductor structure of claim 2, wherein, The electron mobility of the second fin layers is greater than the electron mobility of the first fin layers; The end faces of the first fin layers are recessed relative to the outer sidewall in a direction towards the gate structure.

4. The semiconductor structure of claim 3, wherein, In the longitudinal direction, the second fin layers are located between adjacent first fin layers.

5. The semiconductor structure of claim 3, wherein, In the channel fin, in the longitudinal direction, the number of layers of the first fin layers is two to four.

6. The semiconductor structure of claim 2 or 3, wherein, The material of the first fin layers comprises silicon, and the material of the second fin layers comprises silicon germanium.

7. The semiconductor structure of any one of claims 2-5, wherein the semiconductor structure is a vertical semiconductor structure. In the first fin layers and the second fin layers staggered along the longitudinal direction, the thickness of the first fin layers is 15nm to 30nm, and the thickness of the second fin layers is 15nm to 30nm.

8. The semiconductor structure of any one of claims 1-3, wherein, The distance by which the sidewall of the source-drain recess is recessed relative to the outer sidewall is at least equal to the thickness value of the sidewall.

9. The semiconductor structure of claim 8, wherein, The sidewall of the source-drain recess is recessed relative to the sidewall of the gate structure by at most 2nm to 3nm.

10. A method of forming a semiconductor structure, comprising: Comprising: providing a substrate, a channel fin being formed on the substrate, a gate structure being formed on the substrate and across the channel fin, the gate structure covering part of the top and part of the sidewall of the channel fin, a sidewall layer being formed on the sidewall of the gate structure, the sidewall layer having an outer sidewall facing away from the gate structure; forming a source-drain recess in the channel fin on both sides of the gate structure with the sidewall layer as an etching mask, part of the sidewall of the source-drain recess being recessed relative to the outer sidewall in a direction towards the gate structure and the rest of the sidewall not being recessed relative to the outer sidewall in a direction towards the gate structure; forming a source-drain doped layer in the source-drain recess.

11. The method of forming a semiconductor structure of claim 10, wherein, In the step of providing the substrate, the normal direction of the surface of the substrate is longitudinal, the channel fin comprises first fin layers and second fin layers staggered along the longitudinal direction, the materials of the first fin layers and the second fin layers are different; In the step of forming the source-drain recess, the sidewall of the source-drain recess comprises an end surface of the first fin layer and an end surface of the second fin layer, and in the source-drain recess, the end surface of the first fin layer or the end surface of the second fin layer is recessed in a direction towards the gate structure relative to the outer sidewall.

12. The method of forming a semiconductor structure of claim 11, wherein, The electron mobility of the second fin layer is greater than the electron mobility of the first fin layer. In the step of forming the source-drain recess, the end surface of the first fin layer is recessed in a direction towards the gate structure relative to the outer sidewall.

13. The method of forming a semiconductor structure of claim 12, wherein, In the longitudinal direction, the second fin layer is located between adjacent first fin layers.

14. The method of forming a semiconductor structure of claim 12, wherein, In the fin structure, in the longitudinal direction, the number of layers of the first fin layer is two to four.

15. The method of forming a semiconductor structure of claim 11, wherein, The method for forming the source-drain recess comprises: taking the sidewall layer as an etching mask, etching the first fin layer and the second fin layer on both sides of the gate structure, and forming a first recess in the channel fin; In a direction perpendicular to the sidewall of the gate structure, the first fin layer or the second fin layer exposed by the sidewall of the first recess is subjected to a lateral etching treatment, and a second recess is formed in the channel fin below the gate structure and is in communication with the first recess, and the second recess and the first recess constitute a source-drain recess.

16. The method of forming a semiconductor structure of claim 15, wherein, The lateral etching treatment process comprises a wet etching process.

17. The method of forming a semiconductor structure of claim 15, wherein, A dry etching process is adopted to etch the first fin layer and the second fin layer on both sides of the gate structure, and the first recess is formed.

18. The method of forming a semiconductor structure of claim 11 or 12, wherein, The material of the first fin layer comprises silicon, and the material of the second fin layer comprises silicon germanium.

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