Power supply unit

Abstract

A power supply device includes a power supply chip and a power supply control circuit. The power supply chip is configured to convert an input voltage into a first voltage and generate an indication signal and a sensing voltage, wherein the indication signal indicates the connection status and power supply status of a power receiving device of the power supply device. The power supply control circuit includes: a current limiting circuit configured to generate a first reset signal in response to a comparison result between the sensing voltage and a threshold voltage; a logic circuit configured to generate a control signal based on the indication signal and the input voltage; and a switching circuit configured to determine whether to supply the first voltage to the current limiting circuit based on the control signal. In response to the first reset signal being in a first logic state, the power supply chip shuts off power to the power receiving device.

Description

Technical Field

[0001] Embodiments of the present invention relate to power control, and more particularly, to a power supply device. Background Art

[0002] For network equipment with power supplying equipment (PSE) functions, since input power is limited, it is necessary to control the output power to the connected powered device.

[0003] However, when a powered device is connected to a conventional network device, the conventional network device is easily affected by the surge current generated during the connection, causing the power supply function to malfunction. Summary of the Invention

[0004] In view of this, the present invention provides a power supply device to solve the above problem.

[0005] The present invention provides a power supply device, comprising a power supply chip and a power supply control circuit. The power supply chip is configured to convert an input voltage into a first voltage and generate an indication signal and a sensing voltage, wherein the indication signal indicates the connection status of a power receiving device of the power supply device. The power supply control circuit includes: a current limiting circuit configured to generate a first reset signal in response to a comparison result between the sensing voltage and a threshold voltage; a logic circuit configured to generate a control signal based on the indication signal and the input voltage; and a switching circuit configured to determine whether to supply the first voltage to the current limiting circuit based on the control signal. In response to the first reset signal being in a first logic state, the power supply chip shuts off power to the power receiving device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A schematic diagram showing a power supply device according to an embodiment of the present invention is shown.

[0007] Figure 2 FIG. 1 is a schematic diagram of input signals and output signals of a power supply chip according to an embodiment of the present invention.

[0008] Figures 3A to 3D is a circuit diagram of a power supply control circuit according to different embodiments of the present invention. DETAILED DESCRIPTION

[0009] The following description is a preferred embodiment of the present invention, and is intended to describe the basic spirit of the present invention, but is not intended to limit the present invention. The actual content of the present invention must be referred to the scope of the following claims.

[0010] It must be understood that the words "comprise", "include", etc. used in this specification are used to indicate the existence of specific technical features, values, method steps, operation processes, elements and / or components, but do not exclude the addition of more technical features, values, method steps, operation processes, elements, components, or any combination of the above.

[0011] The words "first," "second," and "third" used in the claims are used to modify elements in the claims and are not used to indicate a priority order, a precedence relationship, or that one element precedes another, or a temporal sequence in performing method steps. They are only used to distinguish elements with the same name.

[0012] Figure 1 A schematic diagram showing a power supply device according to an embodiment of the present invention is shown.

[0013] The power supply device 10 is, for example, a wireless access point (AP) device and a Power over Ethernet (PoE) device. The power supply device 10 includes a processor 110 , a power supply chip 120 , a power control circuit 130 , a power input terminal 150 , and a power output terminal 160 .

[0014] The power input terminal 150 is used to receive a DC voltage (e.g., 48 volts) from a power source or a DC voltage from a power supply (not shown) via Power over Ethernet (PoE). The power output terminal 160 is used to connect a powered device (PD) 20 to the power supply device 10. The power chip 120 in the power supply device 10 is used to convert the DC voltage from the power input terminal 150 into an output voltage, which is then supplied to the powered device 20 via a cable 161 (e.g., an RJ45 cable) over Ethernet. The processor 110 is used to control the operation of the communication device 10 and can control the power chip 120 to provide or disable the output voltage to the power output terminal 160.

[0015] The power supply control circuit 130 is used to control the output power of the power supply chip 120 and prevent the power supply chip 120 from shutting down due to the inrush current generated when the powered device 20 is first connected to the power supply device 10. In addition, the reset signal RESET (e.g., a first reset signal) generated by the power supply control circuit 130 and the reset signal CPU_RST generated by the processor 110 do not interfere with each other. The reset signal CPU_RST generated by the processor 110 can be generated by the optical coupler 112 to generate the reset signal RESET (e.g., a second reset signal). Either the first reset signal or the second reset signal can cause the power supply chip 120 to shut down the power provided to the powered device 20. In some embodiments, the first reset signal and the second reset signal are input to a logic OR gate to generate the reset signal RESET. Optocouplers 111 and 112 are disposed between the processor 110 and the power supply chip 120 to isolate electromagnetic interference and voltage transients.

[0016] The power control circuit 130 includes a logic circuit 131, a switch circuit 132, and a current limiting circuit 133. The logic circuit 131 is used to control the switch circuit 132, and the switch circuit 132 determines whether to supply power to the current limiting circuit 133 based on a control signal from the logic circuit 131. The current limiting circuit 133 compares the sense voltage VSENSE from the power chip 120 with the threshold voltage VSET and determines the logic level of the reset signal RESET based on the comparison result. The power chip 120 then determines whether to shut down the power supply to the powered device 20 based on the reset signal RESET.

[0017] Figure 2 This is a schematic diagram of the input and output signals of the power supply chip according to an embodiment of the present invention. Figure 1 and Figure 2 .

[0018] like Figure 2As shown, the input signals of the power supply chip 120 include an input voltage Vin and a reset signal RESET. The input voltage Vin is transmitted from the power receiving terminal 150 to the V_MAIN pin of the power supply chip 120. The reset signal RESET can be a first reset signal from the power control circuit 130 or a second reset signal generated by the CPU reset signal CPU_RST output by the processor 110 via the optocoupler 112. For ease of explanation, the input voltage Vin can also be referred to as the voltage V_MAIN. Furthermore, the power supply chip 120 includes a voltage conversion circuit (not shown) for converting the input voltage Vin into a voltage VAUX3P3 and a sense voltage VSENSE. Furthermore, the power supply chip 120 can generate an indicator signal LED0 based on the connection status and power supply status of the powered device 20. The power supply chip 120 also generates a corresponding sense voltage VSENSE based on the load of the powered device 20 (for example, one or more powered devices 20 may be connected in series). The higher the load on the powered device 20, the higher the sense voltage VSENSE. The lower the load of the powered device 20, the lower the sense voltage VSENSE. The power supply chip 120 must prioritize providing power to the internal components of the power supply device 10. When the load is too high, the reset signal RESET must be used to shut down the power to the powered device 20.

[0019] For example, voltage VAUX3P3 (e.g., 3.3 volts) is provided to power control circuit 130, and operating current ICC of power chip 120 is limited to less than 1 mA. Furthermore, the operating current of optocouplers 111 and 112 is approximately 5 mA. Therefore, voltage VAUX3P3 generated by power chip 120 is insufficient to drive optocoupler 111, and may cause optocoupler 111 to malfunction. In this embodiment, optocoupler 111 is driven by voltage V_MAIN, and optocoupler 112 is driven by reset signal CPU_RST generated by processor 110. For example, processor 110 determines whether powered device 20 is connected to power supply device 10 and is receiving power properly based on power supply determination signal PSE_DET. When the power supply determination signal PSE_DET is in a low logic state, it indicates that the powered device 20 is connected to the power supply device 10 and is normally powered. In this case, the processor 110 can output a reset signal CPU_RST according to software settings to control whether the power supply chip 120 supplies power to the powered device 20. The anode and cathode of the diode of the optocoupler 112 are connected to the processor 110 and ground, respectively. The emitter of the phototransistor of the optocoupler 112 is connected to the voltage source VSS (e.g., ground = 0V), and the collector of the phototransistor of the optocoupler 112 outputs a second reset signal to the power supply chip 120.

[0020] In one embodiment, when the power supply device 10 is activated, the power supply chip 120 detects the connection status of the voltage output terminal 160, for example, whether the powered device 20 is connected to the voltage output terminal 160. When the power supply chip 120 determines that the powered device 20 is not connected to the power supply device 10, or when the power supply chip 120 determines that the powered device 20 is connected to the power supply device 10 and the power supply chip 120 has passed the detection but has not yet supplied power to the powered device 20, the power supply chip 120 generates an indication signal LED0 at a high voltage level (or a high logic state). When the power supply chip 120 determines that the powered device 20 is connected to the power supply device 10 and is supplying power to the powered device 20 normally, the power supply chip 120 generates an indication signal LED0 at a low voltage level (or a low logic state).

[0021] The indicator signal LED0 then passes through the optocoupler 111 to output a power supply determination signal PSE_DET. When the power supply determination signal PSE_DET is at a high voltage level, the processor 110 determines that the powered device 20 is not connected or is connected but not powered. When the power supply determination signal PSE_DET is at a low voltage level, the processor 110 determines that the powered device 20 is connected and is receiving power.

[0022] Figures 3A to 3D is a circuit diagram of a power supply control circuit according to different embodiments of the present invention. Figure 1 and Figures 3A to 3D .

[0023] like Figure 3A As shown, logic circuit 131 includes transistors Q2 and Q3, where transistor Q2 is an NPN bipolar junction transistor (BJT) and transistor Q3 is a PNP bipolar junction transistor. The emitter of transistor Q3 is connected to node N5, and the voltage V_MAIN output by the power supply chip 120 is provided to node N5. The base of transistor Q3 is connected to node N6 via resistor R7, and the indicator signal LED0 output by the power supply chip 120 is provided to node N6. The collector of transistor Q3 is connected to node N4 via resistor R6, where node N4 is connected to the base of transistor Q2, and node N4 is connected to voltage source VSS (e.g., ground = 0V) via resistor R5. The emitter of the transistor Q2 is connected to the voltage source VSS, and the collector of the transistor Q2 is connected to the gate of the transistor Q1 and to the node N2 via the resistor R4. The voltage VAUX3P3 generated by the power supply chip 120 is provided to the node N2.

[0024] Switch circuit 132 can be implemented, for example, using transistor Q1, which is a P-type field-effect transistor. The source of transistor Q1 is connected to node N2, and voltage VAUX3P3 generated by power supply chip 120 is provided to node N2. The drain of transistor Q1 is connected to node N1, which serves as the voltage input terminal V+ for comparator circuit 134. Current limiting circuit 133 includes comparator circuit 134 and resistors R1-R3. Resistors R1 and R2 form a voltage divider circuit to generate threshold voltage VSET.

[0025] In the first scenario, if the power chip 120 employs a low active reset design, the threshold voltage VSET is connected to the positive input terminal +IN of the comparator circuit 134, and the sense voltage VSENSE generated by the power chip 120 is connected to the negative input terminal -IN of the comparator circuit 134. When the output current provided by the power chip 120 to the powered device 20 does not exceed a predetermined value, the sense voltage VSENSE < the voltage VSET. Therefore, the reset signal RESET output by the comparator circuit 134 is at a high voltage level. In this case, the power chip 120 does not shut down the powered device 20 and continues to supply power to the powered device. When the output current provided by the power chip 120 to the powered device 20 is greater than or equal to the predetermined value, the sense voltage VSENSE >= the voltage VSET. Therefore, the reset signal RESET output by the comparator circuit 134 is at a low voltage level. In this case, the power chip 120 shuts down the powered device 20.

[0026] In the second scenario, if the power chip 120 is designed with an active high reset, the threshold voltage VSET is connected to the negative input terminal -IN of the comparator circuit 134, and the sense voltage VSENSE generated by the power chip 120 is connected to the positive input terminal +IN of the comparator circuit 134. When the output current provided by the power chip 120 to the powered device 20 does not exceed the predetermined value, the sense voltage VSENSE < the voltage VSET. Therefore, the reset signal RESET output by the comparator circuit 134 is at a low voltage level. In this case, the power chip 120 does not shut down the powered device 20 and continues to supply power to the powered device. When the output current provided by the power chip 120 to the powered device 20 is greater than or equal to the predetermined value, the sense voltage VSENSE >= the voltage VSET. Therefore, the reset signal RESET output by the comparator circuit 134 is at a high voltage level. In this case, the power chip 120 shuts down the powered device 20.

[0027] In some embodiments, the connection method of the components in current limiting circuit 130 in the second scenario is similar to that in the first scenario, but an inverter can be provided at the output of current limiting circuit 130 to change the logic state of reset signal RESET. For ease of explanation, the following embodiments use the first scenario as an example. Furthermore, the voltage of indicator signal LED0 when at a high voltage level is equal to voltage V_MAIN.

[0028] like Figure 3A As shown, when the power supply chip 120 determines that the power receiving device 20 is not connected to the power supply device 10, or determines that the power receiving device 20 is connected to the power supply device 10 and the power supply chip 120 has passed the detection but has not yet supplied power to the power receiving device 20, the indication signal LED0 generated by the power supply chip 120 is at a high voltage level. At this time, because the emitter and base of transistor Q3 are both at a high voltage level, transistor Q3 is not conducting. Therefore, the base and emitter of transistor Q2 are both at a low voltage level, which is the voltage source VSS (for example, ground = 0V), so transistor Q2 is not conducting. In addition, the gate and source of transistor Q1 are at a high voltage level, so transistor Q1 is not conducting. At this time, the voltage input terminal V+ of the comparator circuit 134 is grounded, so the comparator circuit 134 does not operate. Because the emitter and base of the transistor Q3 are both at high voltage levels, the diode of the optocoupler 111 is not conducting. At this time, the power supply determination signal PSE_DET is pulled high to a high voltage level. Therefore, the processor 110 can know that the powered device 20 is not connected or is connected but not powered.

[0029] When the power supply chip 120 determines that the powered device 20 is connected to the power supply device 10 and is properly supplying power to the powered device 20, the indication signal LED0 generated by the power supply chip 120 is at a low voltage level. At this point, because the emitter of transistor Q3 is at a high voltage level and its base is at a low voltage level, transistor Q3 is turned on. Consequently, the base voltage of transistor Q2 is at a high voltage level and its emitter voltage is at a low voltage level, turning on transistor Q2. Furthermore, the gate of transistor Q1 is at a low voltage level and its source voltage is at a high voltage level, turning on transistor Q1. At this point, voltage VAUX3P3 is provided to the voltage input terminal V+ of the comparator circuit 134, allowing the comparator circuit 134 to function normally. Because voltage V_MAIN is at a high voltage level and indication signal LED0 is at a low voltage level, the diode of the optocoupler 111 is turned on. At this point, the power supply determination signal PSE_DET is at a low voltage level, allowing the processor 110 to determine that the powered device 20 is connected and properly supplying power.

[0030] Please refer to Figure 3B , Figure 3B The current limiting circuit 130 is similar to Figure 3A ,but Figure 3B Transistors Q2 and Q3 of logic circuit 131 are implemented using an N-type field-effect transistor and a P-type field-effect transistor, respectively. The source of transistor Q3 is connected to node N5, and the voltage V_MAIN output by the power supply chip 120 is provided to node N5. The gate of transistor Q3 is connected to node N6 through resistor R7, and the indication signal LED0 output by the power supply chip 120 is provided to node N6. The drain of transistor Q3 is connected to node N4 through resistor R6, where node N4 is connected to the gate of transistor Q2, and node N4 is connected to voltage source VSS (e.g., ground = 0V) through resistor R5. The drain of transistor Q2 is connected to the gate of transistor Q1 and to node N2 through resistor R4, where voltage VAUX3P3 generated by the power supply chip 120 is provided to node N2.

[0031] like Figure 3B As shown, when the power supply chip 120 determines that the power receiving device 20 is not connected to the power supply device 10, or determines that the power receiving device 20 is connected to the power supply device 10 and the power supply chip 120 has passed the detection but has not yet supplied power to the power receiving device 20, the indication signal LED0 generated by the power supply chip 120 is at a high voltage level. At this time, because the gate and source of transistor Q3 are both at a high voltage level, transistor Q3 is not conducting. Therefore, the gate and source of transistor Q2 are both at a low voltage level, which is the voltage source VSS (e.g., ground = 0V), so transistor Q2 is not conducting. In addition, the gate and source of transistor Q1 are at a high voltage level, so transistor Q1 is not conducting. At this time, the voltage input terminal V+ of the comparator circuit 134 is grounded, so the comparator circuit 134 does not operate. Because the gate and drain of the transistor Q3 are both at high voltage levels, the diode of the optocoupler 111 is not conducting, and the phototransistor of the optocoupler 111 is not conducting. Therefore, the power supply determination signal PSE_DET is pulled high to a high voltage level. Therefore, the processor 110 can know that the powered device 20 is not connected or is connected but not powered.

[0032] When the power supply chip 120 determines that the powered device 20 is connected to the power supply device 10 and is properly supplying power to the powered device 20, the indication signal LED0 generated by the power supply chip 120 is at a low voltage level. At this point, because the source of transistor Q3 is at a high voltage level and its gate is at a low voltage level, transistor Q3 is turned on. Consequently, the gate of transistor Q2 is at a high voltage level and its source voltage is at a low voltage level, turning on transistor Q2. Furthermore, because the gate of transistor Q1 is at a low voltage level and its source voltage is at a high voltage level, transistor Q1 is turned on. At this point, the voltage input terminal V+ of the comparator circuit 134 is connected to the voltage VAUX3P3, allowing the comparator circuit 134 to operate normally. Because the voltage V_MAIN is at a high voltage level and the indication signal LED0 is at a low voltage level, the diode of the optocoupler 111 is turned on. At this point, the phototransistor of the optocoupler 111 is turned on, causing the power supply determination signal PSE_DET to be grounded and at a low voltage level. Therefore, the processor 110 can determine that the powered device 20 is connected and properly supplying power.

[0033] Please refer to Figure 3C , Figure 3C The current limiting circuit 130 is similar to Figure 3A ,but Figure 3C Transistors Q2 and Q3 of logic circuit 131 are replaced by optocoupler 135. The anode and cathode of diode 1351 of optocoupler 135 are connected to nodes N5 and N6, respectively. Voltage V_MAIN and indicator signal LED0 output by power supply chip 120 are provided to nodes N5 and N6, respectively. The collector and emitter of phototransistor 1352 of optocoupler 135 are connected to node N3 and voltage source VSS, respectively. Node N3 is connected to the gate of transistor Q1 and, through resistor R4, to node N2. Voltage VAUX3P3 generated by power supply chip 120 is provided to node N2.

[0034] like Figure 3CAs shown, when the power supply chip 120 determines that the powered device 20 is not connected to the power supply device 10, or determines that the powered device 20 is connected to the power supply device 10 and the power supply chip 120 has passed the detection but has not yet supplied power to the powered device 20, the indication signal LED0 generated by the power supply chip 120 is at a high voltage level. At this time, because the anode and cathode of the diode 1351 of the optocoupler 135 are both at high voltage levels, the diode 1351 of the optocoupler 135 is not conducting, and the phototransistor 1352 of the optocoupler 135 is also not conducting. Therefore, the node N3 is pulled up to the high voltage level of the voltage VAUX3P3. In addition, the gate and source of the transistor Q1 are at high voltage levels, so the transistor Q1 is not conducting. At this time, the voltage input terminal V+ of the comparator circuit 134 is grounded, and the comparator circuit 134 is not operating. Because nodes N5 and N6 are both at a high voltage level, the diode of the optocoupler 111 is not conducting, and the phototransistor of the optocoupler 111 is also not conducting. Therefore, the power supply determination signal PSE_DET is pulled high by the subsequent circuit (processor 110) to a high voltage level. Therefore, the processor 110 can know whether the powered device 20 is not connected or is connected but not powered.

[0035] When the power supply chip 120 determines that the powered device 20 is connected to the power supply device 10 and is properly supplying power to the powered device 20, the indicator signal LED0 generated by the power supply chip 120 is at a low voltage level. At this point, because the anode and cathode of the diode 1351 of the optocoupler 135 are at high and low voltage levels, respectively, the diode 1351 of the optocoupler 135 is turned on, and the phototransistor 1352 of the optocoupler 135 is also turned on. Consequently, node N3 (i.e., the gate of transistor Q1) is also pulled down to the low voltage level of the voltage source VSS. Because the gate of transistor Q1 is at a low voltage level and its source voltage is at a high voltage level, transistor Q1 is turned on. At this point, the voltage input terminal V+ of the comparator circuit 134 is connected to the voltage VAUX3P3, and the comparator circuit 134 operates normally. Because the voltage V_MAIN is at a high voltage level and the indicator signal LED0 is at a low voltage level, the diode of the optocoupler 111 is turned on. At this time, the phototransistor of the optocoupler 111 is turned on, causing the power supply determination signal PSE_DET to be grounded and at a low voltage level. Therefore, the processor 110 can know that the powered device 20 is connected and is powered normally.

[0036] Please refer to Figure 3D , Figure 3D The current limiting circuit 130 is similar to Figure 3A ,but Figure 3DTransistors Q2 and Q3 of the logic circuit 131 are replaced by a voltage level conversion chip 136, wherein the left side and right side of the voltage level conversion chip 136 are respectively low logic level input terminals (e.g., low voltage input terminal (VCC[A] pin) and low voltage data terminal (A pin)) and high logic level input terminals (high voltage input terminal (VCC[B] pin) and high voltage data terminal (B pin)). For example, the low voltage input terminal (VCC[A] pin) and high voltage input terminal (VCC[B] pin) of the voltage level conversion chip 136 are connected to voltage VAUX3P3 (node ​​N2) and voltage V_MAIN (node ​​N5), respectively, wherein voltage V_MAIN (e.g., 48V, 12V, or 5V) is higher than voltage VAUX3P3 (3.3V). The low-voltage data terminal (pin A) of the voltage level conversion chip 136 is connected to the gate of transistor Q1 and, via resistor R4, to node N2. The voltage VAUX3P3 generated by the power supply chip 120 is provided to node N2. The high-voltage data terminal (pin B) of the voltage level conversion chip 136 is connected to the indicator signal LED0 (node ​​N6). Furthermore, the GND pin of the voltage level conversion chip 136 is connected to the voltage source VSS, and the DIR pin is grounded via resistor R7. This can be used, for example, to control the direction of voltage conversion from pin B to pin A.

[0037] like Figure 3D As shown, when the power supply chip 120 determines that the powered device 20 is not connected to the power supply device 10, or determines that the powered device 20 is connected to the power supply device 10 and the power supply chip 120 has passed the detection but has not yet supplied power to the powered device 20, the indicator signal LED0 generated by the power supply chip 120 is at a high voltage level. At this time, the voltage level conversion chip 136 converts the first high voltage level (voltage V_MAIN) at the high voltage data terminal (pin B) to a second high voltage level (e.g., voltage VAUX3P3) output at the low voltage data terminal (pin A). Therefore, the gate and source of transistor Q1 are at a high voltage level, so transistor Q1 is not conducting. At this time, the voltage input terminal V+ of the comparator circuit 134 is grounded, and the comparator circuit 134 is not operational. Because nodes N5 and N6 are both at a high voltage level, the diode of the optocoupler 111 is not conducting, and the phototransistor of the optocoupler 111 is also not conducting. Therefore, the power supply determination signal PSE_DET is pulled high by the subsequent circuit (processor 110) to a high voltage level. Therefore, the processor 110 can know whether the powered device 20 is not connected or is connected but not powered.

[0038] When the power supply chip 120 determines that the powered device 20 is connected to the power supply device 10 and is properly supplying power to the powered device 20, the indication signal LED0 generated by the power supply chip 120 is at a low voltage level. At this point, the voltage level conversion chip 136 converts the first low voltage level at the high voltage data terminal (pin B) to a second low voltage level output at the low voltage data terminal (pin A). Because the gate of transistor Q1 is at a low voltage level and its source voltage is at a high voltage level, transistor Q1 is turned on. At this time, the voltage input terminal V+ of the comparator circuit 134 is connected to the voltage VAUX3P3, and the comparator circuit 134 operates normally. Because the voltage V_MAIN is at a high voltage level and the indication signal LED0 is at a low voltage level, the diode of the optocoupler 111 is turned on. At this point, the phototransistor of the optocoupler 111 is turned on, causing the power supply determination signal PSE_DET to be grounded and at a low voltage level. Therefore, the processor 110 can determine that the powered device 20 is connected and properly supplying power.

[0039] In summary, the present invention provides a power supply device that, when connected to a powered device, controls its output power to a predetermined level, preventing malfunction of the power supply chip caused by the transient surge current generated when the powered device is first connected to the power supply device. Furthermore, the power supply device includes logic circuitry to enable external power supply, preventing malfunction of the optocoupler due to insufficient internal power.

[0040] Although the present invention is disclosed above with reference to preferred embodiments, they are not intended to limit the scope of the invention. Anyone with ordinary knowledge in the art may make slight changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0041]

Explanation of symbols

[0042] 10: Power supply device

[0043] 20: Power receiving device

[0044] 110: Processor

[0045] 111, 112: Optocoupler

[0046] 120: Power supply chip

[0047] 130: Power supply control circuit

[0048] 131: Logic Circuits

[0049] 132: Switching Circuit

[0050] 133: Current limiting circuit

[0051] 135: Optocoupler

[0052] 1351: diode

[0053] 1352: Phototransistor

[0054] 136: Voltage level conversion chip

[0055] 150: Power input terminal

[0056] 160: Power output terminal

[0057] 161: Cable

[0058] Q1-Q3: Transistors

[0059] R1-R9: resistors

[0060] Vin: input voltage

[0061] VSET: threshold voltage

[0062] VSENSE: sense voltage

[0063] CPU_RST: reset signal

[0064] RESET: reset signal

[0065] V_MAIN: voltage

[0066] VAUX3P3: voltage

[0067] VSS: voltage source

[0068] LED0: indicator signal

[0069] PSE_DET: power supply judgment signal

[0070] N1-N6: nodes

[0071] V+, V-: voltage input terminals

[0072] +IN: positive input

[0073] -IN: negative input terminal

[0074] OUT: output pin

Claims

1. A power supply device, comprising: a power supply chip for converting an input voltage into a first voltage and generating an indication signal and a sensing voltage, wherein the indication signal indicates a connection status and a power supply status of a power receiving device of the power supply device; as well as The power supply control circuit includes: a current limiting circuit for generating a first reset signal in response to a comparison result between the sensing voltage and a threshold voltage; a logic circuit for generating a control signal according to the indication signal and the input voltage; and a switch circuit for determining whether to provide the first voltage to the current limiting circuit according to the control signal; In response to the first reset signal being in a first logic state, the power supply chip turns off the power provided to the powered device.

2. The power supply device according to claim 1, wherein: When the power supply chip determines that the powered device is not connected to the power supply device, or determines that the powered device is connected to the power supply device and the power supply chip passes the detection but power has not yet been supplied to the powered device, the indication signal generated by the power supply chip is at a high voltage level. When the power supply chip determines that the powered device has been connected to the power supply device and that power has been supplied to the powered device normally, the indication signal generated by the power supply chip is at a low voltage level.

3. The power supply device according to claim 2, wherein the switch circuit comprises a first P-type transistor, wherein a gate, a source and a drain of the first P-type transistor are respectively connected to the control signal, the first voltage and the voltage input terminal of the current limiting circuit.

4. The power supply device according to claim 3 , wherein in response to the indication signal being at a high voltage level, the control signal generated by the logic circuit is at a high voltage level, In response to the indication signal being at a low voltage level, the control signal generated by the logic circuit is at a low voltage level.

5. The power supply device according to claim 4 , wherein the current limiting circuit comprises: A voltage divider circuit, configured to divide the first voltage to generate the threshold voltage; as well as A comparison circuit for comparing the threshold voltage and the sensing voltage. When the sensing voltage is greater than or equal to the threshold voltage, the first reset signal output by the comparison circuit is in the first logic state. When the sensing voltage is less than the threshold voltage, the first reset signal output by the comparison circuit is in a second logic state relative to the first logic state.

6. The power supply device according to claim 4, wherein the logic circuit comprises: a first PNP bipolar junction transistor, wherein a base of the first PNP bipolar junction transistor is connected to the indication signal via a first resistor, and an emitter of the first PNP bipolar junction transistor is connected to the input voltage; and a first NPN bipolar junction transistor, wherein the base of the first NPN bipolar junction transistor is connected to the collector of the first PNP bipolar junction transistor through a second resistor, the emitter of the first NPN bipolar junction transistor is grounded, and the collector of the first NPN bipolar junction transistor is connected to the gate of the first P-type transistor and is connected to the first voltage through a third resistor.

7. The power supply device according to claim 4, wherein the logic circuit comprises: a second P-type transistor, wherein a gate of the second P-type transistor is connected to the indication signal via a fourth resistor, and a source of the second P-type transistor is connected to the input voltage; as well as a first N-type transistor, wherein the gate of the first N-type transistor is connected to the drain of the second P-type transistor through a fifth resistor and is grounded through a sixth resistor, the source of the first N-type transistor is grounded, and the drain of the first N-type transistor is connected to the gate of the first P-type transistor and is connected to the first voltage through a seventh resistor.

8. The power supply device according to claim 4, wherein the logic circuit comprises a first optical coupler, the first optical coupler comprising a first diode and a first phototransistor, in, The anode and cathode of the first diode are connected to the input voltage and the indication signal respectively, the emitter of the phototransistor is grounded, and the collector of the phototransistor is connected to the gate of the first P-type transistor and to the first voltage through an eighth resistor.

9. A power supply device according to claim 4, wherein the logic circuit includes a voltage level conversion chip, wherein the high voltage input terminal and the high voltage data terminal of the voltage level conversion chip are connected to the input voltage and the indication signal, the low voltage input terminal of the voltage level conversion chip is connected to the first voltage and is connected to the gate of the first P-type transistor through a ninth resistor, the low voltage data terminal of the voltage level conversion chip is connected to the gate of the first P-type transistor, the ground terminal of the voltage level conversion chip is grounded, and the direction terminal of the voltage level conversion chip is grounded through a tenth resistor.

10. The power supply device according to claim 1, further comprising: processor; a second optical coupler comprising a second diode and a second phototransistor, wherein an anode of the second diode is connected to the input voltage via an eleventh resistor, a cathode of the second diode is connected to the indication signal, an emitter of the second phototransistor is grounded, and a collector of the second phototransistor outputs a power supply determination signal to the processor; as well as The third optical coupler includes a third diode and a third phototransistor, wherein the anode and cathode of the third diode are connected to the processor and ground respectively, the emitter of the third phototransistor is grounded, and the collector of the third phototransistor outputs a second reset signal to the power supply chip. In response to the first reset signal or the second reset signal being in the first logic state, the power supply chip turns off the power provided to the powered device.

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