Integrated circuit, power supply circuit

Abstract

An integrated circuit appropriately changes input current for charging an input capacitor to improve a power factor. The integrated circuit includes a first capacitor and an inductor to which a voltage corresponding to an alternating voltage is applied, and a transistor to control an inductor current in the inductor. The transistor of a power supply circuit which generates an output voltage based on the alternating voltage is switched, including an oscillation circuit to output an oscillation voltage which rises at a prescribed slope from a first voltage when the inductor current is less than a first prescribed value, an error voltage output circuit to output an error voltage corresponding to a difference between a feedback voltage corresponding to the output voltage and a reference voltage, and a drive circuit to turn on the transistor when the inductor current is less than the first prescribed value and to turn off the transistor when the oscillation voltage is a second voltage based on the error voltage. An output circuit changes at least either one of the first voltage and the second voltage based on a rectified voltage obtained by full-wave rectifying the alternating voltage and outputs the same so that the on time of the transistor becomes shorter when the level of the rectified voltage becomes higher.

Description

Technical Field

[0001] This invention relates to integrated circuits and power supply circuits. Background Technology

[0002] Typically, there are integrated circuits that form the waveforms of AC voltage and input current into similar shapes to improve the power factor (e.g., Patent Documents 1-9).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: US Patent No. 7,538,525

[0006] Patent Document 2: U.S. Patent Application Publication No. 2019 / 0305664

[0007] Patent Document 3: International Publication No. 2018 / 087960

[0008] Patent Document 4: US Patent No. 6946819

[0009] Patent Document 5: US Patent No. 6,984,963

[0010] Patent Document 6: US Patent No. 5,689,176

[0011] Patent Document 7: U.S. Patent No. 5,592,128

[0012] Patent Document 8: Japanese Patent Application Publication No. 2015-039261

[0013] Patent Document 9: Japanese Patent Application Publication No. 2006-094697 Summary of the Invention

[0014] The technical problem that the invention aims to solve

[0015] When an AC voltage is applied to the input capacitor of an AC-DC converter, distortion may occur in the input current, thus degrading the power factor.

[0016] The present invention was made in view of the aforementioned existing problems, and its object is to provide an integrated circuit that can appropriately change the input current to improve the power factor.

[0017] Technical means for solving technical problems

[0018] The first aspect of the integrated circuit according to the present invention, which solves the above problems, includes: a first capacitor and an inductor, the first capacitor and the inductor being applied with a voltage corresponding to an AC voltage; and a transistor that controls an inductor current flowing through the inductor, the integrated circuit switching the transistor of a power supply circuit that generates an output voltage based on the AC voltage, the integrated circuit including: an oscillation circuit that outputs an oscillation voltage that rises from the first voltage at a predetermined slope when the inductor current becomes less than a first predetermined value; an error voltage output circuit that outputs an error voltage corresponding to the difference between a feedback voltage and a reference voltage corresponding to the output voltage; a drive circuit that turns on the transistor when the inductor current becomes less than the first predetermined value and turns off the transistor when the oscillation voltage becomes a second voltage based on the error voltage; and an output circuit that, in order to shorten the on-time of the transistor when the level of the rectified voltage obtained by full-wave rectification of the AC voltage becomes higher, varies at least one of the first voltage and the second voltage based on the rectified voltage and outputs an output.

[0019] A second aspect of the integrated circuit according to the present invention, which solves the above-mentioned problems, includes: a first capacitor and an inductor, the first capacitor and the inductor being applied with a voltage corresponding to an AC voltage; and a transistor that controls the inductor current flowing through the inductor, the integrated circuit switching the transistor of a power supply circuit that generates an output voltage according to the AC voltage, the integrated circuit including: an oscillation circuit that outputs a rising oscillation voltage when the inductor current becomes less than a predetermined value; an error voltage output circuit that outputs an error voltage corresponding to the difference between a feedback voltage corresponding to the output voltage and a reference voltage; a drive circuit that turns on the transistor when the inductor current becomes less than the predetermined value and turns off the transistor when the oscillation voltage becomes the error voltage; and an output circuit that changes the slope of the oscillation voltage and outputs it in order to shorten the on-time of the transistor when the level of the rectified voltage obtained by full-wave rectification of the AC voltage becomes high and lengthen the on-time of the transistor when the output voltage decreases.

[0020] The power supply circuit of the present invention, which solves the above problems, is a power supply circuit that generates an output voltage based on an AC voltage, comprising: a first capacitor and an inductor, wherein the first capacitor and the inductor are subjected to a voltage corresponding to the AC voltage; a transistor that controls the inductor current flowing through the inductor; and an integrated circuit that switches the transistor, the integrated circuit comprising: an oscillation circuit that outputs an oscillation voltage that rises from the first voltage at a predetermined slope when the inductor current becomes less than a predetermined value; an error voltage output circuit that outputs an error voltage corresponding to the difference between a feedback voltage corresponding to the output voltage and a reference voltage; a drive circuit that turns on the transistor when the inductor current becomes less than the predetermined value and turns off the transistor when the oscillation voltage becomes a second voltage based on the error voltage; and an output circuit that, in order to shorten the on-time of the transistor when the level of the rectified voltage obtained by full-wave rectification of the AC voltage becomes higher, changes at least one of the first voltage and the second voltage based on the rectified voltage and outputs the output.

[0021] Invention Effects

[0022] According to the present invention, an integrated circuit can be provided that appropriately changes the input current to improve the power factor. Attached Figure Description

[0023] Figure 1 This is a diagram illustrating an example of an AC-DC converter 10a.

[0024] Figure 2 This is a diagram illustrating an example of the power factor improvement IC26a.

[0025] Figure 3 This is a graph showing the relationship between AC voltage Vac, rectified voltage Vh, and voltage divider voltage Vhdiv.

[0026] Figure 4 This is a diagram showing an example of an oscillator circuit 40 and an output circuit 60.

[0027] Figure 5 This is a diagram illustrating the operation of the power factor improvement IC26a.

[0028] Figure 6 This is a diagram showing an example of an oscillator circuit 40 and an output circuit 61.

[0029] Figure 7 This is a graph showing the relationship between the voltage divider Vhdiv and the gain G of the output circuit 61.

[0030] Figure 8This is a diagram showing the operation of the power factor improvement IC26a when load 11 is under heavy load.

[0031] Figure 9 This is a diagram illustrating an example of the power factor improvement IC26c.

[0032] Figure 10 This is a diagram showing an example of the output circuit 62.

[0033] Figure 11 This is a diagram showing the operation of the power factor improvement IC26a when load 11 is under heavy load.

[0034] Figure 12 This is a diagram illustrating an example of an AC-DC converter 10b.

[0035] Figure 13 This is a diagram illustrating an example of the power factor improvement IC26d.

[0036] Figure 14 This is a graph showing the relationship between the peak voltage Vpeak and the detection voltage Vload.

[0037] Figure 15 This is a diagram showing an example of the output circuit 63.

[0038] Figure 16 This is a diagram showing the operation of the power factor improvement IC26d when load 11 is under heavy load.

[0039] Figure 17 This is a diagram illustrating an example of the power factor improvement IC26e.

[0040] Figure 18 This is a diagram showing an example of the output circuit 64.

[0041] Figure 19 This is a diagram illustrating the operation of the power factor improvement IC26e.

[0042] Figure 20 This is a diagram illustrating an example of the power factor improvement IC26f.

[0043] Figure 21 This is a diagram showing an example of an oscillating circuit 41.

[0044] Figure 22 This is a diagram illustrating an example of the operation of the power factor improvement IC26f when load 11 is under heavy load.

[0045] Figure 23 This is a diagram illustrating an example of the power factor improvement IC26g.

[0046] Figure 24This is a diagram showing an example of an oscillating circuit 42.

[0047] Figure 25 This is a diagram illustrating an example of the operation of the power factor improvement IC26g when load 11 is under heavy load.

[0048] Figure 26 This is a diagram illustrating an example of the power factor improvement IC26h.

[0049] Figure 27 This is a diagram showing an example of an AC component detection circuit 200.

[0050] Figure 28 This is a graph showing the variation of the drive signal Vp1 based on the voltage Vcomp and the oscillation voltage Vr, which have noise components. Detailed Implementation

[0051] Based on the description in this specification and the accompanying drawings, at least the following matters are clearly defined.

[0052] ======This implementation method======

[0053] Figure 1 This is a diagram illustrating an example of the structure of an AC-DC converter 10a as one embodiment of the present invention. The AC-DC converter 10a is a boost chopper power supply circuit that uses the AC voltage Vac of a commercial power supply to generate a target level output voltage Vout.

[0054] Load 11 is, for example, a DC-DC converter or an electronic device that operates under DC voltage.

[0055] <<<Overview of AC-DC Converter 10a>>>

[0056] The AC-DC converter 10a is configured to include an input line filter 20, a full-wave rectifier circuit 21, capacitors 22, 25, 33, and 34, a transformer 23, diodes 24, 28, and 29, a power factor improvement IC 26, an NMOS transistor 27, and resistors 30 to 32.

[0057] An input line filter 20 is disposed between nodes N1 and N2, where an AC voltage Vac is applied, and the full-wave rectifier circuit 21 (described later). This circuit is used to remove noise from the commercial power supply to the AC-DC converter 10a. Furthermore, in this embodiment, the current in nodes N1 and N2, where the AC voltage Vac is applied, is set as the input current Iin. Here, the AC voltage Vac is, for example, a voltage of 100–240V with a frequency of 50–60Hz.

[0058] The full-wave rectifier circuit 21 performs full-wave rectification on the noise-removed specified AC voltage Vac, and applies it as the rectified voltage Vrec to the capacitor 22 and the main coil L1 of the transformer 23.

[0059] Alternatively, the rectified voltage Vrec is applied directly to the main coil L1, but it can also be applied to the main coil L1 via a component such as a resistor (not shown). Furthermore, in this embodiment, "applying" includes not only directly supplying voltage to a specified node, but also indirectly supplying voltage via a component such as a resistor (not shown), and supplying a voltage after voltage division.

[0060] Capacitor 22 is a component used to filter the rectified voltage Vrec, and transformer 23 has a main coil L1 and an auxiliary coil L2 magnetically coupled to the main coil L1. Here, in this embodiment, the auxiliary coil L2 is wound such that the polarity of the voltage generated in the auxiliary coil L2 is opposite to the polarity of the voltage generated in the main coil L1. Furthermore, the voltage Vzcd generated in the auxiliary coil L2 is applied to terminal ZCD of the power factor improvement IC 26 (described later).

[0061] Furthermore, the main coil L1, together with diode 24, capacitor 25, and NMOS transistor 27, constitutes a boost chopper circuit. Therefore, the charging voltage of capacitor 25 is the DC output voltage Vout. Additionally, the output voltage Vout is, for example, 400V.

[0062] The power factor improvement IC26 is an integrated circuit that controls the switching of the NMOS transistor 27 to improve the power factor of the AC-DC converter 10a and make the output voltage Vout level a target level (e.g., 400V). Specifically, the power factor improvement IC26 drives the NMOS transistor 27 based on the inductor current IL flowing through the main coil L1 and the output voltage Vout.

[0063] The following section details the power factor correction IC26, which has terminals FB, ZCD, COMP, OUT, and VH. Additionally, the power factor correction IC26 has terminals other than the aforementioned five (FB, ZCD, COMP, OUT, and VH), but these are omitted here for simplicity.

[0064] NMOS transistor 27 is a transistor used to control the power supplied by AC-DC converter 10a to load 11. In this embodiment, NMOS transistor 27 is a MOS (Metal Oxide Semiconductor) transistor, but it is not limited to this. NMOS transistor 27 can be any transistor capable of power control, for example, it could be a bipolar transistor. Furthermore, the gate electrode of NMOS transistor 27 is connected to be driven by a signal from terminal OUT.

[0065] Resistors 30 and 31 form a voltage divider circuit for dividing the output voltage Vout and generate a feedback voltage Vfb used when switching the NMOS transistor 27. Additionally, the feedback voltage Vfb generated at the node connected to resistors 30 and 31 is applied to terminal FB.

[0066] Resistor 32 and capacitors 33 and 34 are phase compensation components for the power factor improvement IC26, which is controlled by feedback. Resistor 32 and capacitor 33 are connected in series between terminal COMP and ground, and capacitor 34 is connected in parallel with resistor 33 and capacitor 33.

[0067] Diodes 28 and 29 form a full-wave rectifier circuit, connected to the front stage of the full-wave rectifier circuit 21, and apply a voltage Vh corresponding to the AC voltage Vac to the terminal VH of the power factor improvement IC 26. The AC voltage Vac obtained from the node of the front stage of the full-wave rectifier circuit 21 is rectified to obtain the voltage Vh. This allows for more accurate detection of the phase angle of voltage Vh, unaffected by capacitor 22. Specifically, the anode of diode 28 is connected to the non-grounded line of the front stage of the full-wave rectifier circuit 21. On the other hand, the anode of diode 29 is connected to the grounded line of the front stage of the full-wave rectifier circuit 21. The cathodes of diodes 28 and 29 are connected together and connected to the terminal VH of the power factor improvement IC 26. Furthermore, a voltage divider obtained by dividing the voltages of the cathodes of diodes 28 and 29 can also be applied to the terminal VH of the power factor improvement IC 26.

[0068] <<<Operation of AC-DC Converter 10a>>>

[0069] The operation of AC-DC converter 10a will be explained below in conjunction with the operation of power factor improvement IC26, and how general power factor improvement IC26 improves the power factor of AC-DC converter 10a.

[0070] First, when the AC voltage Vac is applied to nodes N1 and N2, it is applied to the full-wave rectifier circuit 21 via the input line filter 20. The full-wave rectifier circuit 21 performs full-wave rectification on the AC voltage Vac and outputs a rectified voltage Vrec. The capacitor 22 filters the rectified voltage Vrec, and the filtered rectified voltage Vrec is applied to the main coil L1.

[0071] Next, if the inductor current IL flowing through the main coil L1 becomes approximately zero, the power factor improvement IC26 turns on the NMOS transistor 27. At this time, the capacitor current IL flows to ground via the NMOS transistor 27.

[0072] Then, if the period corresponding to the feedback voltage Vfb has elapsed, the power factor improvement IC26 turns off the NMOS transistor 27. At this time, the main coil L1 stores energy so that the inductor current IL that flowed when the NMOS transistor was turned on continues to flow.

[0073] If the voltage at the anode of diode 24 becomes higher than the forward voltage Vf generated in capacitor 25 due to this energy, a current corresponding to the inductor current IL flows through the main coil L1 via diode 24, charging capacitor 25. The voltage generated in capacitor 25 then becomes the output voltage Vout.

[0074] Additionally, if the main coil L1 releases energy and the inductor current IL becomes almost zero, the power factor correction IC 26 turns on the NMOS transistor 27 again. Thus, if the inductor current IL becomes almost zero, the power factor correction IC 26 turns on the NMOS transistor 27; if a period corresponding to the feedback voltage Vfb has elapsed, the power factor correction IC 26 turns off the NMOS transistor 27. Afterward, the power factor correction IC 26 continues to turn the NMOS transistor 27 on and off.

[0075] By doing so, the power factor improvement IC26 sets the waveform of the average value of the inductor current IL (i.e., the input current Iin) to be similar in shape to the waveform of the AC voltage Vac, thereby improving the power factor of the AC-DC converter 10a.

[0076] However, when the difference between the absolute value of the AC voltage Vac and the voltage value of the capacitor 22 is less than the forward voltage Vf of the diode (not shown) that constitutes the diode bridge of the full-wave rectifier circuit 21, the current does not flow through the diode (not shown).

[0077] That is, near the area where the absolute value of the AC voltage Vac is small, no current flows to charge capacitor 22, resulting in no input current Iin flowing (hereinafter, this phenomenon is referred to as a "dead zone"). In this case, the waveform of the input current Iin is not similar to the waveform of the AC voltage Vac, becoming a cause of power factor and total high-frequency distortion (hereinafter referred to as "THD"). Furthermore, "a small absolute value of the AC voltage Vac" means that when the level of the AC voltage Vac is positive, the level of the AC voltage Vac is low.

[0078] Therefore, near the point where the absolute value of the AC voltage Vac is relatively small, capacitor 22 is discharged, causing the voltage value of capacitor 22 to decrease, thus requiring the inductor current IL to flow. Furthermore, the power factor improvement IC 26, described later, eliminates dead zones by allowing a large amount of inductor current IL to flow near the point where the absolute value of the AC voltage Vac is relatively small, thereby improving the power factor of AC-DC converters such as 10a. Additionally, capacitor 22 is equivalent to a "first capacitor," and the main coil L1 is equivalent to an "inductor." Moreover, the current flowing through the main coil L1 is the "inductor current IL."

[0079] === ...

[0080] Figure 2 This diagram illustrates an example of a power factor improvement IC26a, which is a first embodiment of the power factor improvement IC26. The power factor improvement IC26a is configured to include an oscillation circuit 40, a drive circuit 50, an output circuit 60, a voltage divider circuit 70, and an error voltage output circuit 71. Furthermore, in Figure 2 In the text, for convenience, the terminals are depicted on the same side as... Figure 1 In different locations, however, the wiring, components, etc., connected to each terminal are... Figure 1 and Figure 2 The same applies to both.

[0081] The oscillation circuit 40 generates the oscillation voltage Vr required when the NMOS transistor 27 is turned on and off. Specifically, if the inductor current IL is almost zero and there is an input "H" level drive signal Vp1, the oscillation circuit 40 outputs an oscillation voltage Vr, the amplitude of which gradually increases from the bias voltage Vrampl (described later) output by the output circuit 60 (described later) with a prescribed slope. Details of the oscillation circuit 40 will be described later.

[0082] The driving circuit 50 is a circuit that outputs a driving signal Vdr and drives the NMOS transistor 27. Specifically, if the inductor current IL becomes almost zero, the driving circuit 50 turns on the NMOS transistor 27, and if the oscillation voltage Vr becomes a voltage corresponding to the feedback voltage Vfb, the driving circuit 50 turns off the NMOS transistor 27. Moreover, the driving circuit 50 is configured to include a zero-current detection circuit 80, a delay circuit 81, an OR gate circuit 82, an SR flip-flop 83, a turn-on timer circuit 84, a comparator 85, and a buffer 86.

[0083] The zero-current detection circuit 80 detects whether the current value of the inductor current IL is a "current value Ia" (hereinafter referred to as zero for convenience) that represents almost zero, based on the voltage Vzcd at terminal ZCD. Furthermore, when the zero-current detection circuit 80 detects that the current value of the inductor current IL is "zero" ("current value Ia"), it outputs a high-level (hereinafter referred to as "H" level) signal Vz. The zero-current detection circuit 80 is configured to include a comparator (not shown) that compares a predetermined voltage of the auxiliary coil L2 when the inductor current IL changes to "current value Ia" with the voltage Vzcd.

[0084] If the zero current detection circuit 80 outputs a signal Vz at the "H" level, the delay circuit 81 will delay for a specified time before outputting the pulse signal Vp2.

[0085] The OR gate circuit 82 performs a logical OR operation on the pulse signals Vp2 and Vp3. Specifically, if the delay circuit 81 outputs a "H" level pulse signal Vp2 or the turn-on timer circuit 84 (described later) outputs a "H" level pulse signal Vp3, then the OR gate circuit 82 outputs a "H" level set signal Ss. Therefore, in this embodiment, the pulse signal Vp2 or pulse signal Vp3 output from the OR gate circuit 82 is used as the set signal Vp3.

[0086] If the OR gate outputs a "H" level set signal Ss, then the SR flip-flop 83 outputs a "H" level drive signal Vp1. On the other hand, if the comparator 85 (described later) outputs a "H" level reset signal Sr, then the SR flip-flop 83 outputs a low level (hereinafter referred to as "L" level) drive signal Vp1.

[0087] When the power factor improvement IC26a starts up, or when no AC voltage Vac is provided and no pulse signal Vp2 is output, the turn-on timer circuit 84 outputs a pulse signal Vp3 to turn on the NMOS transistor 26. Specifically, when no pulse signal Vp2 is output for a specified period, a "H" level pulse signal Vp3 is output every specified period.

[0088] Comparator 85 is a circuit that compares the voltage Vcomp, output from the error voltage output circuit 71 (described later) based on the feedback voltage Vfb, with the oscillation signal Vr. Specifically, voltage Vcomp is applied to the inverting input terminal of comparator 85, and the oscillation voltage Vr is applied to the non-inverting input terminal of comparator 85. Therefore, when the level of oscillation voltage Vr is lower than the level of voltage Vcomp, comparator 85 outputs a reset signal Sr of level "L", and when the level of oscillation voltage Vr is higher than the level of voltage Vcomp, comparator 85 outputs a reset signal Sr of level "H".

[0089] Buffer 86 is a circuit that drives NMOS transistor 27 based on drive signal Vp1. Specifically, buffer 86 uses a signal Vdr with the same logic level as the input signal to drive NMOS transistor 27, which has a relatively large gate capacitance. Furthermore, buffer 86 turns on NMOS transistor 27 based on the "H" level drive signal Vp1 and turns off NMOS transistor 27 based on the "L" level drive signal Vp1.

[0090] Output circuit 60 is a circuit that outputs the bias voltage Vramp1 to oscillation circuit 40. Specifically, output circuit 60 is a circuit that outputs the bias voltage Vramp1 based on the voltage divider voltage Vhdiv output by voltage divider circuit 70 (described later), so that when the level of voltage divider voltage Vhdiv becomes high, the conduction time of NMOS transistor 27 becomes shorter.

[0091] The voltage divider circuit 70 is a circuit that generates a voltage Vhdiv by dividing the voltage Vh obtained by full-wave rectification of the AC voltage Vac. The following will refer to... Figure 3 To explain. Here, Figure 3 This is a graph showing the relationship between AC voltage Vac, voltage Vh obtained by full-wave rectification of AC voltage Vac, and voltage divider voltage Vhdiv generated by voltage divider circuit 70.

[0092] Voltage divider circuit 70 includes resistors 87 and 88. Specifically, one end of resistor 87 is connected to terminal VH, and the other end is connected in series to one end of resistor 88. Furthermore, the other end of resistor 88 is grounded. As a result, a voltage Vhdiv is generated at the node where resistors 87 and 88 are connected.

[0093] Furthermore, the voltage level of the AC voltage Vac changes periodically according to the phase angle. Similarly, the voltage levels of voltage Vh and the voltage divider voltage Vhdiv also change periodically according to the phase angle. Specifically, when the phase angle changes from 0 degrees to 90 degrees, the level of AC voltage Vac increases; when the phase angle changes from 90 degrees to 270 degrees, the level of AC voltage Vac decreases. Moreover, when the phase angle changes from 270 degrees to 360 degrees, the level of AC voltage Vac increases. On the other hand, when the phase angle changes from 0 degrees to 90 degrees, the level of voltage Vh increases; when the phase angle changes from 90 degrees to 180 degrees, the level of voltage Vh decreases. Similarly, when the phase angle changes from 180 degrees to 360 degrees, the level of voltage Vh changes. The voltage divider voltage Vhdiv is obtained by dividing voltage Vh; therefore, the voltage divider voltage Vhdiv, like voltage Vh, changes periodically according to the phase angle.

[0094] Furthermore, although an example of providing a voltage divider circuit 70 within the power factor improvement IC26a has been described, a voltage divider circuit may also exist externally to the power factor improvement IC26a, and the AC voltage Vac may be rectified by diodes 28 and 29, with the voltage divided by the voltage divider circuit applied to terminal VH. Additionally, the resistors within the voltage divider circuit 70 are described as resistors 87 and 88, but this is not a limitation; any combination of resistors may be used.

[0095] return Figure 2 The following describes the error voltage output circuit 71. The error voltage output circuit 71 is a transconductance amplifier 89. Furthermore, the transconductance amplifier 89 generates an error current Ie based on the error between the reference voltage VREF1 corresponding to the target level output voltage Vout and the feedback voltage Vfb. This error current Ie charges capacitors 33 and 34 via terminal COMP, generating a voltage Vcomp. The error voltage output circuit 71 then outputs the voltage Vcomp. The voltage Vcomp corresponds to the "error voltage," and the "current value Ia" corresponds to the "first specified value."

[0096] <<<An Example of Oscillator Circuit 40 and Output Circuit 60>>>

[0097] Figure 4 This is a diagram illustrating an example of an oscillation circuit 40 and an output circuit 60. The output circuit 60 is a buffer circuit 100 that outputs the divided voltage Vhdiv as a bias voltage Vrampl to the oscillation circuit 40.

[0098] The oscillation circuit 40 is a circuit that outputs an oscillation voltage Vr, and includes capacitors 110 and 111 and a charging / discharging circuit 90. In addition, the charging / discharging circuit 90 is a circuit that charges and discharges capacitor 110 to generate an oscillation voltage Vr with a specified slope, and includes a constant current source 112 that outputs a constant current Iramp0, an inverter 113, and an NMOS transistor 114.

[0099] When the inductor current IL is nearly zero and a "H" level drive signal Vp1 is input, the NMOS transistor 114 is turned off, and the capacitor 110 is charged by a constant current Iramp0 from the constant current source 112. Additionally, the capacitor 111 is charged to maintain the bias voltage Vrampl from the output circuit 60.

[0100] Therefore, the oscillation voltage Vr is obtained by adding the voltage of capacitor 110 to the voltage of capacitor 111 (i.e., the bias voltage Vrampl). Furthermore, when a drive signal Vp1 of level "H" is input, the oscillation voltage Vr gradually increases from the bias voltage Vrampl at a predetermined slope because the voltage of capacitor 110 gradually increases at a predetermined slope.

[0101] On the other hand, when a "L" level drive signal Vp1 is input to capacitor 110, NMOS transistor 114 is turned on and discharged. At this time, the charge stored in capacitor 110 is drawn to ground through the transistor (not shown) of the output stage of buffer circuit 100 and NMOS transistor 114. As capacitor 110 is discharged, the oscillation voltage Vr becomes the bias voltage Vrampl. Furthermore, capacitor 110 acts as a "second capacitor".

[0102] <<<Operation of Power Factor Improvement IC26a>>>

[0103] Figure 5 This diagram illustrates the operation of the power factor improvement IC26a. At time t0, the phase angle of the voltage Vh obtained by full-wave rectification of the AC voltage Vac is 0 degrees, and the level of the voltage divider voltage Vhdiv obtained by dividing Vh is at its lowest. Then, the output circuit 60 outputs the voltage divider voltage Vhdiv as the bias voltage Vrampl. Therefore, the bias voltage Vrampl begins to rise as the voltage divider voltage Vhdiv increases.

[0104] At time t1, when the inductor current IL becomes approximately less than zero, the delay circuit 81 outputs a "H" level pulse signal Vp2. Then, the SR flip-flop 83 outputs a "H" level drive signal Vp1, resulting in the power factor improvement IC26a turning on the NMOS transistor 27. At this time, the bias voltage Vrampl is higher than the bias voltage Vrampl at time t0.

[0105] When NMOS transistor 27 is turned on, charging / discharging circuit 90 begins to charge capacitor 110 with a constant current Iramp0. Furthermore, the oscillation voltage Vr is obtained by adding the bias voltage Vrampl output from output circuit 60 to the voltage of capacitor 110. At this time, capacitor 110 is charged by the constant current Iramp0, and therefore, the oscillation voltage Vr gradually increases with a predetermined slope.

[0106] At time t2, when the oscillation voltage Vr changes to voltage Vcomp, comparator 85 outputs a reset signal Sr at the "H" level. Consequently, SR flip-flop 83 outputs a drive signal Vp1 at the "L" level, and as a result, power factor improvement IC26a turns off NMOS transistor 27.

[0107] When NMOS transistor 27 is turned off, the charging / discharging circuit 90 discharges capacitor 110, and the oscillation voltage Vr becomes the bias voltage Vrampl. Then, from time t2 to time t3, the power factor improvement IC 26a similarly repeats the driving of the NMOS transistor. Furthermore, from time t2 to time t3, the bias voltage Vrampl increases according to the rise of the voltage divider voltage Vhdiv. Therefore, the on-time of NMOS transistor 27 gradually shortens.

[0108] At time t3, the power factor improvement IC26a turns on NMOS transistor 27, and at time t4, the power factor improvement IC26a turns off NMOS transistor 27. Furthermore, the on-time of NMOS transistor 27 from time t3 to time t4 is shorter than the on-time of NMOS transistor 27 from time t1 to time t2. This is because during the period from time t3 to time t4, the bias voltage Vrampl (i.e., the voltage divider voltage Vhdiv), which varies according to the level of voltage Vh, is higher than during the period from time t1 to time t2.

[0109] Therefore, the power factor improvement IC26a can shorten the on-time of the NMOS transistor 27 when the voltage Vh level becomes high. From time t4 to time t5, the power factor improvement IC26a similarly repeats the driving of the NMOS transistor. Furthermore, from time t4 to time t5, the bias voltage Vrampl decreases as the voltage divider voltage Vhdiv decreases. Therefore, after time t4, the on-time of the NMOS transistor 27 gradually increases.

[0110] At time t5, the phase angle of the voltage Vh obtained by full-wave rectification of the AC voltage Vac is 180 degrees, and the level of the voltage divider voltage Vhdiv obtained by dividing the voltage Vh is the lowest. In addition, the bias voltage Vrampl is equivalent to the "first voltage", and the voltage Vcomp is equivalent to the "second voltage".

[0111] Based on the above operations, the on-time of the NMOS transistor 27 in the power factor improvement IC26a increases near the low level of voltage Vh, i.e., near the low absolute value of AC voltage Vac. Therefore, the power factor improvement IC26a can allow a large amount of inductor current IL to flow near the low absolute value of AC voltage Vac, i.e., in the low phase angle region, thereby reducing dead zones. As a result, the power factor improvement IC26a can improve power factor and THD. Furthermore, by changing the bias voltage Vrampl through the output circuit 60, the on-time of NMOS transistor 27 can be varied, regardless of the influence of noise components in voltage Vcomp caused by switching noise of NMOS transistor 27.

[0112] In addition, Figure 5 In the diagram, only a few pulses are depicted for the drive signal Vp1 to aid understanding. Figure 2 The power factor improvement IC26a operates in this implementation. However, the switching frequency of the NMOS transistor 27, for example, is several kHz, which is sufficiently high than the frequency of the AC voltage Vac, i.e., 50-60 Hz. Therefore, in practice, a very large amount of drive signal Vp1 is contained within one cycle of the AC voltage Vac.

[0113] === ...

[0114] The power factor improvement IC26b, a second embodiment of the power factor improvement IC26, differs from the power factor improvement IC26a in that it uses output circuit 61 as the output circuit. Additionally, objects labeled with the same reference numerals are... Figure 2 The power factor improvement is the same as that of IC26a.

[0115] <<<Structure of Output Circuit 61>>>

[0116] Figure 6 This is a diagram illustrating an example of the oscillation circuit 40 and the output circuit 61. The output circuit 61 is an amplifier circuit that amplifies the divided voltage Vhdiv with a gain G corresponding to the level of the divided voltage Vhdiv and outputs it as a bias voltage Vrampl. Specifically, as... Figure 7 As shown, when the voltage divider voltage Vhdiv rises, the output circuit 61 reduces the gain G and decreases the rise of the bias voltage Vrampl.

[0117] The output circuit 61 is configured to include an operational amplifier 120, a resistor 121, and a variable resistor 122. The voltage divider voltage Vhdiv and the bias voltage Vrampl have the relationship shown in the following equation.

[0118] Vrammpl=(R1+R2) / R1×Vhdiv···(1)

[0119] =G×Vhdiv···(2)

[0120] Here, the resistance value R1 is the resistance value of resistor 121, and the resistance value R2 is the resistance value of variable resistor 122. Moreover, the output circuit 61 is configured such that when the level of the voltage divider Vhidv rises, the resistance value R2 decreases, and the gain G of the output circuit 61 decreases.

[0121] Therefore, the power factor improvement IC26b can allow a large amount of inductor current IL to flow near the area where the absolute value of the AC voltage Vac is small, i.e., in the low phase angle region, thereby reducing dead zones. As a result, the power factor improvement IC26b can improve both power factor and THD.

[0122] <<<Operation of IC26a for Power Factor Improvement under Heavy Load>>>

[0123] Figure 8 This diagram illustrates the operation of the power factor improvement IC26a when load 11 is under heavy load. Here, "heavy load" means that, compared to "light load," the power consumption of load 11 increases, and the input current Iin of AC-DC converter 10a increases. Furthermore, in this embodiment, "heavy load" means, for example, that the current flowing through load 11 is a predetermined current value (e.g., 5A) or more, while "light load" means that the current flowing through load 11 is less than a predetermined current value.

[0124] exist Figure 8 In the middle, the power factor improvement IC26a is used to... Figure 5 The NMOS transistor 27 is driven in the same way as the case, and Figure 8 The time interval from t10 to t15 corresponds to Figure 5 From time t0 to time t5. However, since load 11 becomes a "heavy load", the input current Iin is higher than that. Figure 5 In cases where the AC voltage Vac is relatively low, the inductor current IL flows more freely. Then, the power factor improvement IC26a can extend the on-time of the NMOS transistor 27 near a small absolute value of the AC voltage Vac, thus allowing a large amount of inductor current IL to flow. On the other hand, the power factor improvement IC26a can shorten the on-time of the NMOS transistor 27 near a large absolute value of the AC voltage Vac. Therefore, the power factor improvement IC26a can prevent the inductor current IL from flowing insufficiently near a large absolute value of the AC voltage Vac under "heavy load" conditions. As a result, the power factor improvement IC26a cannot make the waveform of the average value of the inductor current IL (i.e., the input current Iin) similar to the waveform of the AC voltage Vac.

[0125] Therefore, the following describes an implementation of power factor improvement ICs 26c and 26d, which can set the waveform of the average value of the inductor current IL (i.e., the input current Iin) to be similar to the waveform of the AC voltage Vac, even when the load 11 is a "heavy load".

[0126] === ...

[0127] Figure 9 This diagram illustrates an example of a power factor improvement IC 26c. The power factor improvement IC 26c, as a third embodiment of the power factor improvement IC 26, differs from the power factor improvement IC 26a in that it uses output circuit 62 as the output circuit. Additionally, objects with the same reference numerals are... Figure 2 The power factor improvement is the same as that of IC26a.

[0128] <<<Structure of Output Circuit 62>>>

[0129] Figure 10This diagram illustrates an example of the output circuit 62. The output circuit 62 outputs a bias voltage Vrampl to the oscillation circuit 40, corresponding to the difference between the divided voltage Vhdiv and the voltage Vcomp. Specifically, the output circuit 62 changes the bias voltage Vrampl based on the divided voltage Vhdiv and the voltage Vcomp, causing the on-time of the NMOS transistor 27 to shorten when the level of the divided voltage Vhdiv increases. Furthermore, the output circuit 62 changes the bias voltage Vrampl based on the divided voltage Vhdiv and the voltage Vcomp, causing the on-time of the NMOS transistor 27 to increase when the feedback voltage Vfb decreases. Additionally, the output circuit 62 is configured to include a current generation circuit 130 and a voltage generation circuit 150.

[0130] The current generation circuit 130 is a circuit that generates current I1 based on the difference between the voltage divider voltage Vhdiv and the voltage Vcomp. The current generation circuit 130 is configured to include operational amplifiers 140, 141, 144, and 145, resistors 142, 143, and 147, NMOS transistor 146, and PMOS transistors 148 and 149.

[0131] Operational amplifier 140 forms a buffer circuit for the output voltage Vcomp, and operational amplifier 144 forms a buffer circuit for the output voltage divider Vhdiv.

[0132] Operational amplifier 141 and resistors 142 and 143 constitute a differential amplifier circuit for amplifying the difference between the voltage divider voltage Vhdiv and the voltage Vcomp. If the output voltage of operational amplifier 141 is set as voltage Vx, then voltage Vx is expressed by the following formula.

[0133] Vx=(R3+R4) / R3×(Vhdiv-R4 / (R3+R4)×Vcomp)···(3)

[0134] Here, the resistance value R3 is the resistance value of resistor 142, and the resistance value R4 is the resistance value of resistor 143.

[0135] Operational amplifier 145 is a circuit used to control the current I0 flowing through NMOS transistor 146, such that the voltage generated in resistor 147 by the flow of current I0, plus the voltage divider voltage Vhdiv, becomes voltage Vx. Therefore, current I0 is expressed by the following formula.

[0136] I0=(Vx-Vhdiv) / R5···(4)

[0137] Here, the resistance value R5 is the resistance value of resistor 147.

[0138] Then, if the voltage Vx in equation (3) is substituted into equation (4), the current I0 is expressed by the following equation.

[0139] I0=(Vhdiv-Vcomp)×R4 / R3 / R5···(5)

[0140] PMOS transistors 148 and 149 form a current mirror circuit and output a current I1 corresponding to the current I0. The ratio K0 between currents I0 and I1 is determined by the ratio between the dimensions of PMOS transistors 148 and 149. Furthermore, using current I0, current I1 is expressed by the following formula.

[0141] I1 = K0 × I0

[0142] =K0×(Vhdiv-Vcomp)×R4 / R3 / R5···(6)

[0143] The voltage generation circuit 150 is a buffer circuit that outputs a voltage Vrampl generated by allowing current I1 to flow through resistor 151 as a bias voltage. The voltage generation circuit 150 is configured to include resistor 151 and operational amplifier 152.

[0144] If the current I1 from the current generation circuit 130 flows through the resistor 151, a voltage Vy is generated. The voltage Vy is expressed by the following formula using formula (6).

[0145] Vy = R6 × I1

[0146] =K0×(Vhdiv-Vcomp)×R4 / R3 / R5×R6···(7)

[0147] Here, the resistance value R6 is the resistance value of resistor 151.

[0148] Operational amplifier 152 forms a buffer circuit that outputs the voltage Vy input to the non-inverting input terminal as a bias voltage Vrampl. Therefore, voltage Vrampl is equal to voltage Vy, and voltage Vrampl is expressed by the following formula.

[0149] Vrampl=Vy

[0150] =K0×(Vhdiv-Vcomp)×R4 / R3 / R5×R6···(8)

[0151] <<<Power Factor Improvement IC26c Operation>>>

[0152] Figure 11This diagram illustrates the operation of the power factor improvement IC26c when load 11 is under heavy load. At time t20, the phase angle of the voltage Vh obtained by full-wave rectification of the AC voltage Vac is 0 degrees, and the level of the voltage divider voltage Vhdiv obtained by dividing the voltage Vh is the lowest. Moreover, the output circuit 62 outputs the bias voltage Vrampl, which is expressed by equation (8).

[0153] In this embodiment, when the phase angle of the voltage divider Vhdiv is low, the resistance values ​​of resistors 87 and 88 in the voltage divider circuit 70 are set so that the voltage divider Vhdiv becomes less than the voltage Vcomp. Therefore, at time t20, the voltage divider Vhdiv is less than the voltage Vcomp, and thus, the bias voltage Vrampl becomes, for example, approximately the voltage level of ground.

[0154] At time t21, if the inductor current IL becomes almost zero, the power factor improvement circuit 26c turns on the NMOS transistor 27. Then, the oscillation voltage Vr gradually rises with a prescribed slope. Furthermore, at time t21, the bias voltage Vrampl is still approximately at ground level.

[0155] At time t22, if the oscillation voltage Vr becomes greater than the voltage Vcomp, the power factor improvement IC26c turns off the NMOS transistor 27. Furthermore, from time t20 to time t22, no current I1 flows through the current generation circuit 130, thus the bias voltage Vrampl remains approximately constant. Moreover, from time t22 to time t23, the power factor improvement IC26c similarly repeats the driving of the NMOS transistor.

[0156] At time t23, the power factor improvement IC26c turns on NMOS transistor 27, and at time t24, the power factor improvement IC26c turns off NMOS transistor 27. Furthermore, the on-time of NMOS transistor 27 from time t23 to time t24 is shorter than the on-time of NMOS transistor 27 from time t21 to time t22. This is because from time t23 to time t24, the voltage divider voltage Vhdiv becomes greater than the voltage Vcomp, and the bias voltage Vrampl becomes higher than approximately the ground voltage level. Additionally, from time t20 to time t23, the voltage divider voltage Vhdiv increases, thus gradually shortening the on-time of NMOS transistor 27.

[0157] However, compared to the power factor improvement IC26a, the bias voltage Vrampl decreases when load 11 becomes a "heavy load". Therefore, compared to the power factor improvement IC26a, more input current Iin flows from time t20 to time t25. Furthermore, from time t24 to time t25, the power factor improvement IC26c similarly repeats the driving of the NMOS transistor. Moreover, from time t24 to time t25, the bias voltage Vrampl decreases as the voltage divider voltage Vhdiv decreases, then becomes approximately ground level. Therefore, after time t24, the on-time of the NMOS transistor 27 gradually increases.

[0158] At time t25, the phase angle of the voltage Vh obtained by full-wave rectification of the AC voltage Vac is 180 degrees, and the level of the voltage Vhdiv obtained by voltage division of Vh is the lowest.

[0159] Based on the above actions, for the power factor improvement IC26a, near the higher level of voltage Vh, i.e., near the area where the absolute value of AC voltage Vac is larger, the bias voltage Vrampl of the power factor improvement IC26c is lower than that of the power factor improvement IC26a. Therefore, the on-time of NMOS transistor 27 is longer compared to the power factor improvement IC26a. Consequently, the power factor improvement IC26c can flow a large amount of inductor current IL near the area where the absolute value of AC voltage Vac is larger, i.e., in the high phase angle region. Therefore, even if load 11 becomes a "heavy load," the power factor improvement IC26c can set the waveform of the input current Iin to be similar in shape to the waveform of AC voltage Vac. As a result, the power factor improvement IC26c can improve both power factor and THD.

[0160] In addition, Figure 11 In the diagram, only a few pulses are depicted for the drive signal Vp1 to aid understanding. Figure 9 The power factor improvement IC26c operates in this implementation. However, the switching frequency of the NMOS transistor 27, for example, is several kHz, which is sufficiently high than the frequency of the AC voltage Vac, i.e., 50-60 Hz. Therefore, in practice, a very large amount of drive signal Vp1 is contained within one cycle of the AC voltage Vac.

[0161] exist Figure 9In the implementation of the power factor improvement IC26c, a large inductor current IL flows near the region of high phase angle, i.e., near the absolute value of the AC voltage Vac, based on the voltage Vcomp. However, by estimating the state of the load 11 based on the measured value of the inductor current IL when the NMOS transistor 27 is turned on and controlling the AC-DC converter 10b, the degradation of the power factor when the load 11 becomes a "heavy load" can be reduced. Therefore, the power factor improvement IC26d used in the AC-DC converter 10b, and which will be described next, can, through this method, set the waveform of the average value of the inductor current IL (i.e., the input current Iin) to be similar in shape to the waveform of the AC voltage Vac, even when the load 11 is a "heavy load".

[0162] <<<Structure of AC-DC Converter 10b>>>

[0163] Figure 12 This is a diagram illustrating an example of AC-DC converter 10b. The difference between AC-DC converter 10b and AC-DC converter 10a is that AC-DC converter 10b has a resistor 35 for measuring the inductor current IL when NMOS transistor 27 is turned on.

[0164] === ...

[0165] Figure 13 This is a diagram illustrating an example of a power factor improvement IC 26d. As a fourth embodiment of the power factor improvement IC 26, the power factor improvement IC 26d has a terminal A, to which a voltage generated in resistor 35 due to the inductor current IL flowing when the NMOS transistor 27 is turned on is applied. Furthermore, the power factor improvement IC 26d differs from the power factor improvement IC 26a in that it has an output circuit 63 as an output circuit and also includes a load detection circuit 72 for detecting the state of the load 11 based on the voltage at terminal A. Additionally, objects with the same reference numerals are... Figure 2 The power factor improvement is the same as that of IC26a.

[0166] The load detection circuit 72 is a circuit that detects the state of the load 11. Specifically, the load detection circuit 72 outputs a detection voltage Vload corresponding to the load current Iload flowing through the load 11, based on the voltage at terminal A.

[0167] Figure 14 This is a graph showing the relationship between the peak voltage Vpeak and the detection voltage Vload. Here, the peak voltage Vpeak represents the peak voltage of the voltage applied to terminal A when the inductor current IL flows through the resistor 35 when the NMOS transistor 27 is turned on.

[0168] Moreover, such as Figure 14 As shown, if the peak voltage Vpeak exceeds the voltage value Vpeak0, the load detection circuit 72 outputs a detection voltage Vload that is proportional to the voltage value obtained by subtracting the voltage value Vpeak0 from the peak voltage Vpeak. On the other hand, if the peak voltage Vpeak does not exceed the voltage value Vpeak0, the detection voltage Vload becomes zero. In addition, the voltage value Vpeak0 is equivalent to a "second specified value".

[0169] <<<Structure of Output Circuit 63>>>

[0170] Figure 15 This diagram illustrates an example of output circuit 63. Instead of the voltage Vcomp in the case of output circuit 62, output circuit 63 is a circuit that outputs the voltage corresponding to the difference between the divided voltage Vhdiv and the detection voltage Vload as a bias voltage Vrampl to oscillation circuit 40. Output circuit 63 is configured to include current generation circuit 130 and voltage generation circuit 150.

[0171] The current generation circuit 130 and the voltage generation circuit 150 are the same as those of the output circuit 62. Therefore, the output circuit 63 outputs a bias voltage Vrampl, which is expressed by the following formula.

[0172] Vrampl=K0×(Vhdiv-Vload)×R4 / R3 / R5×R6···(9)

[0173] <<<Operation of Power Factor Improvement IC26d>>>

[0174] Figure 16 This diagram illustrates the operation of the power factor correction IC26d when load 11 is under heavy load. The operation of the power factor correction IC26d is related to... Figure 11 The difference in the operation of the power factor improvement IC26c shown is that the bias voltage Vrampl is generated based on the voltage divider voltage Vhdiv and the detection voltage Vload. However, the relationship between the bias voltage Vrampl and the on-time of the NMOS transistor 27 is the same. Furthermore, the operation of the power factor improvement IC26d is the same as that of the power factor improvement IC26c, so its description is omitted. Additionally, Figure 16 The time intervals from t30 to t35 correspond to Figure 11 From time t20 to time t25.

[0175] Based on the above actions, near the higher voltage level Vh, i.e., near the greater absolute value of the AC voltage Vac, the on-time of the NMOS transistor 27 in the power factor improvement IC26d becomes longer than that in the power factor improvement IC26a. Therefore, similar to the power factor improvement IC26c, the power factor improvement IC26d can flow a large amount of inductor current IL near the greater absolute value of the AC voltage Vac, i.e., in the high phase angle region. Therefore, even if the load 11 becomes a "heavy load," the power factor improvement IC26d can set the waveform of the input current Iin to be similar in shape to the waveform of the AC voltage Vac. As a result, the power factor improvement IC26d can improve both the power factor and THD.

[0176] In addition, Figure 16 In the diagram, only a few pulses are depicted for the drive signal Vp1 to aid understanding. Figure 13 The power factor improvement IC26d operates in this implementation. However, the switching frequency of the NMOS transistor 27, for example, is several kHz, which is sufficiently high than the frequency of the AC voltage Vac, i.e., 50-60 Hz. Therefore, in practice, a very large amount of drive signal Vp1 is contained within one cycle of the AC voltage Vac.

[0177] === ...

[0178] Figure 17 This diagram illustrates an example of the power factor improvement IC26e. The power factor improvement IC26e, as a fifth embodiment of the power factor improvement IC26, differs from the power factor improvement IC26a in that the output circuit 64 is provided as the output circuit and the bias voltage Vrampl of the oscillation circuit 40 is a predetermined voltage. Additionally, objects with the same reference numerals are... Figure 2 The power factor improvement is the same as that of IC26a.

[0179] <<<Structure of Output Circuit 64>>>

[0180] Figure 18 This diagram illustrates an example of the output circuit 64. The output circuit 64 outputs a voltage Vcompx, corresponding to the difference between the divided voltage Vhdiv and the voltage Vcomp, to the comparator 85. Specifically, when the level of the divided voltage Vhdiv increases, the output circuit 64 outputs the voltage Vcompx obtained by decreasing the voltage Vcomp; when the level of the divided voltage Vhdiv decreases, it outputs the voltage Vcompx obtained by increasing the voltage Vcomp.

[0181] The output circuit 64 is configured to include a buffer circuit 160 and an inverting amplifier circuit 170. The buffer circuit 160 is configured to include an operational amplifier 161. Furthermore, the operational amplifier 161 is configured to output a voltage divider voltage Vhdiv applied to the non-inverting terminal.

[0182] The inverting amplifier circuit 170 is a circuit that inverts and amplifies the output voltage of the operational amplifier 161. The inverting amplifier circuit 170 is configured to include resistors 171 and 173 and an operational amplifier 172. The output voltage Vcompx of the inverting amplifier circuit 170 is expressed by the following formula.

[0183] Vcompx=-R8 / R7×(Vhdiv-Vcomp)+Vcomp···(10)

[0184] <<<Power Factor Improvement IC26e Operation>>>

[0185] Figure 19 This diagram illustrates the operation of the power factor improvement IC26e. At time t40, the phase angle of the voltage Vh obtained by full-wave rectification of the AC voltage Vac is 0 degrees, and the level of the voltage divider voltage Vhdiv obtained by dividing Vh is at its lowest. Then, the output circuit 64 outputs voltage Vcompx based on the voltage divider voltage Vhdiv and the voltage Vcomp. Then, the voltage Vcompx gradually decreases from time t40 to time t43. As a result, the on-time of the NMOS transistor 27 gradually shortens.

[0186] At time t41, if the inductor current IL is almost zero, the delay circuit 81 outputs a "H" level pulse signal Vp2. Then, the SR flip-flop 83 outputs a "H" level drive signal Vp1, resulting in the power factor improvement IC26e turning on the NMOS transistor 27.

[0187] When NMOS transistor 27 is turned on, charging / discharging circuit 90 begins to charge capacitor 110 with a constant current Iramp0. Furthermore, the oscillation voltage Vr is obtained by adding a predetermined voltage, i.e., the bias voltage Vrampl, to the voltage of capacitor 110. At this time, capacitor 110 is charged by the constant current Iramp0, and therefore, the oscillation voltage Vr gradually increases with a predetermined slope.

[0188] At time t42, when the oscillation voltage Vr changes to voltage Vcompx, comparator 85 outputs a "H" level reset signal Sr. Consequently, SR flip-flop 83 outputs a "L" level drive signal Vp1, and as a result, power factor improvement IC26e turns off NMOS transistor 27.

[0189] When NMOS transistor 27 is turned off, the charging / discharging circuit 90 discharges capacitor 110, and the oscillation voltage Vr becomes the specified voltage, i.e., the bias voltage Vrampl. Then, from time t42 to time t43, the power factor improvement IC26e repeats the driving of NMOS transistor 27 in the same way.

[0190] At time t43, the power factor improvement IC26e turns on NMOS transistor 27, and at time t44, it turns off. Furthermore, the on-time of NMOS transistor 27 from time t43 to time t44 is shorter than the on-time from time t41 to time t42. This is because the voltage level of Vcompx, which varies according to the voltage level Vh, is lower during the period from time t43 to time t44 than during the period from time t41 to time t42. Therefore, the power factor improvement IC26e can shorten the on-time of NMOS transistor 27 when the voltage level Vh increases. From time t44 to time t45, the power factor improvement IC26e repeats the same operation of NMOS transistor 27. Moreover, after time t44, the voltage divider Vhdiv decreases, and therefore, the voltage Vcompx gradually increases. Consequently, the on-time of NMOS transistor 27 gradually increases.

[0191] At time t45, the phase angle of the voltage Vh obtained by full-wave rectification of the AC voltage Vac is 180 degrees, and the level of the voltage divider voltage Vhdiv obtained by dividing the voltage Vh is the lowest. Furthermore, at... Figure 17 In the power factor improvement IC26e, the voltage Vcompx is equivalent to the "second voltage".

[0192] Based on the above operation, the on-time of the NMOS transistor 27 in the power factor improvement IC26e becomes longer near the low level of voltage Vh, i.e., near the small absolute value of the AC voltage Vac. Therefore, the power factor improvement IC26e can flow a large amount of inductor current IL near the small absolute value of the AC voltage Vac, i.e., in the low phase angle region, thereby reducing dead zones. As a result, the power factor improvement IC26e can improve both power factor and THD.

[0193] In addition, Figure 19 In the diagram, only a few pulses are depicted for the drive signal Vp1 to aid understanding. Figure 17The power factor improvement IC26e operates in this implementation. However, the switching frequency of the NMOS transistor 27, for example, is several kHz, which is sufficiently high than the frequency of the AC voltage Vac, i.e., 50-60 Hz. Therefore, in practice, a very large amount of drive signal Vp1 is contained within one cycle of the AC voltage Vac.

[0194] === ...

[0195] Figure 20 This diagram illustrates an example of a power factor improvement IC 26f. The power factor improvement IC 26f, a sixth embodiment of the power factor improvement IC 26, differs from the power factor improvement IC 26a in that it includes an oscillation circuit 41 but lacks an output circuit. Additionally, objects with the same reference numerals are... Figure 2 The power factor improvement is the same as that of IC26a.

[0196] <<<Structure of Oscillator Circuit 41>>>

[0197] Figure 21 This diagram illustrates an example of an oscillation circuit 41. The oscillation circuit 41 is a circuit that outputs an oscillation voltage Vr, and it is a circuit that changes the slope of the oscillation voltage Vr based on a voltage divider voltage Vhdiv and a voltage Vcomp. Specifically, the oscillation circuit 41 changes the slope of the oscillation voltage Vr and outputs it such that the on-time of the NMOS transistor 27 decreases when the level of the voltage divider voltage Vhdiv increases, and the on-time of the NMOS transistor 27 increases when the feedback voltage Vfb decreases.

[0198] The oscillation circuit 41 is configured to include a current generation circuit 131, a charging and discharging circuit 91, capacitors 110 and 111, a constant voltage source 190, and an operational amplifier 191. The current generation circuit 131 is largely the same as the current generation circuit 130, and the charging and discharging circuit 91 includes a PMOS transistor 180 to replace the PMOS transistor 149 of the current generation circuit 130.

[0199] Furthermore, the charging and discharging circuit 91 is a circuit that charges and discharges the capacitor 110 with current Iramp1 and generates an oscillating voltage Vr whose slope varies according to the current Iramp1, and is configured to include an inverter 113, an NMOS transistor 114, and a PMOS transistor 180.

[0200] When the inductor current IL becomes almost zero and a "H" level drive signal Vp1 is input, the NMOS transistor 114 is turned off, and the capacitor 110 is charged by the current Iramp1 from the PMOS transistor 180. Furthermore, the capacitor 111 is charged to maintain the bias voltage Vrampl from the operational amplifier 191. Here, the bias voltage Vrampl is the voltage output by a buffer circuit consisting of a constant voltage source 190 (output voltage Vrampl) and the operational amplifier 191.

[0201] Therefore, the oscillation voltage Vr is obtained by adding the voltage of capacitor 110 to the voltage of capacitor 111 (i.e., the bias voltage Vrampl). Furthermore, when a "H" level drive signal Vp1 is input, the voltage of capacitor 110, which is charged by current Iramp1, gradually increases, and the oscillation voltage Vr gradually increases from the bias voltage Vrampl with a slope corresponding to the current Iramp1.

[0202] On the other hand, when a "L" level drive signal Vp1 is input to capacitor 110, NMOS transistor 114 is turned on and discharged. At this time, the charge accumulated in capacitor 110 is drawn to ground through the transistor (not shown) of the output stage of operational amplifier 191 and NMOS transistor 114. As capacitor 110 is discharged, the oscillation voltage Vr becomes the bias voltage Vrampl.

[0203] Furthermore, if we consider... Figure 10 If we consider the current generation circuit 130 in the same way, the current Iramp1 is expressed by equation (6) as follows.

[0204] Iramp1=K1×(Vhdiv-Vcomp)×R4 / R3 / R5···(11)

[0205] Here, the ratio K1 is the ratio corresponding to the size ratio of PMOS transistors 148 and 180. In addition, the current Iramp1 is equivalent to "the charging current corresponding to the voltage corresponding to the rectified voltage and the error voltage".

[0206] <<<Operation of Power Factor Improvement IC26f>>>

[0207] Figure 22 This diagram illustrates an example of the operation of the power factor improvement IC26f when load 11 is under heavy load. At time t50, the phase angle of the voltage Vh obtained by full-wave rectification of the AC voltage Vac is 0 degrees, and the level of the voltage divider voltage Vhdiv obtained by dividing the voltage Vh is at its lowest. Furthermore, at time t50, the voltage divider voltage Vhdiv is smaller than the voltage Vcomp, therefore the current Iramp1 is a constant current value.

[0208] At time t51, if the inductor current IL becomes approximately less than zero, the delay circuit 81 outputs a "H" level pulse signal Vp2. Then, the SR flip-flop 83 outputs a "H" level drive signal Vp1, resulting in the power factor improvement IC26f turning on the NMOS transistor 27.

[0209] When NMOS transistor 27 is turned on, charging / discharging circuit 91 begins to charge capacitor 110 with current Iramp1. Furthermore, the oscillation voltage Vr becomes the voltage obtained by adding a predetermined voltage, i.e., the bias voltage Vrampl, to the voltage of capacitor 110. At this time, capacitor 110 is charged by current Iramp1, and therefore, the oscillation voltage Vr gradually increases with a slope corresponding to current Iramp1.

[0210] At time t52, when the oscillation voltage Vr changes to voltage Vcomp, comparator 85 outputs a reset signal Sr at the "H" level. Consequently, SR flip-flop 83 outputs a drive signal Vp1 at the "L" level, and as a result, power factor improvement IC26f turns off NMOS transistor 27.

[0211] When NMOS transistor 27 is turned off, the charging / discharging circuit 91 discharges capacitor 110, and the oscillation voltage Vr becomes the specified voltage, i.e., the bias voltage Vramp1. Then, from time t52 to time t53, the power factor improvement IC26f similarly repeats the driving of NMOS transistor 27. After time t52, since the voltage divider voltage Vhdiv is larger than the voltage Vcomp, the current Iramp1 increases with the rise of the voltage divider voltage Vhdiv. As a result, the on-time of NMOS transistor 27 gradually shortens.

[0212] At time t53, the power factor improvement IC26f turns on NMOS transistor 27, and at time t54, the power factor improvement IC26f turns off NMOS transistor 27. Furthermore, the on-time of NMOS transistor 27 from time t53 to time t54 is shorter than the on-time of NMOS transistor 27 from time t51 to time t52.

[0213] However, compared to the case where load 11 is under "light load", the voltage Vcomp increases and the current Iramp1 decreases. Therefore, during the period from time t50 to time t55, the on-time of NMOS transistor 27 is longer than when load 11 is under "light load". Consequently, when load 11 becomes under "heavy load", the power factor improvement IC 26f causes the input current Iin flowing through it to be greater than when load 11 is under "light load".

[0214] Therefore, even if load 11 becomes a "heavy load," the power factor improvement IC26f can set the waveform of the average value of the inductor current IL (i.e., the input current Iin) to be similar to the waveform of the AC voltage Vac. From time t54 to time t55, the power factor improvement IC26f similarly repeats the driving of the NMOS transistor 27. Furthermore, after time t54, the current Iramp1 decreases as the voltage divider voltage Vhdiv decreases. As a result, the on-time of the NMOS transistor 27 gradually increases.

[0215] At time t55, the phase angle of the voltage Vh obtained by full-wave rectification of the AC voltage Vac is 180 degrees, and the level of the voltage Vhdiv obtained by voltage division of Vh is the lowest.

[0216] Based on the above operations, the on-time of the NMOS transistor 27 in the power factor improvement IC26f increases near the lower voltage level of Vh, i.e., near the lower absolute value of the AC voltage Vac. Therefore, the power factor improvement IC26f can flow a large amount of inductor current IL near the lower absolute value of the AC voltage Vac, i.e., in the low phase angle region, thereby reducing dead zones. Furthermore, capacitor 111 maintains the bias voltage Vrampl, so the oscillation voltage Vr is less susceptible to noise generated by grounding.

[0217] Furthermore, when load 11 becomes a "heavy load," the on-time of the NMOS transistor 27 in the power factor improvement IC26f increases near the higher level of voltage Vh, i.e., near the area where the absolute value of the AC voltage Vac is larger. Therefore, the power factor improvement IC26f can flow a large amount of inductor current IL near the area where the absolute value of the AC voltage Vac is larger, i.e., in the high phase angle region. Thus, even when load 11 becomes a "heavy load," the power factor improvement IC26f can set the waveform of the input current Iin to a shape similar to the waveform of the AC voltage Vac. As a result, the power factor improvement IC26f can improve both the power factor and THD.

[0218] In addition, Figure 22 In the diagram, only a few pulses are depicted for the drive signal Vp1 to aid understanding. Figure 20 The power factor improvement IC26f operates in this implementation. However, the switching frequency of the NMOS transistor 27, for example, is several kHz, which is sufficiently high than the frequency of the AC voltage Vac (50-60 Hz). Therefore, in practice, a very large amount of drive signal Vp1 is contained within one cycle of the AC voltage Vac.

[0219] === ...

[0220] Figure 23 This is a diagram illustrating an example of a power factor improvement IC 26g. The power factor improvement IC 26g, as a seventh embodiment of the power factor improvement IC 26, differs from the power factor improvement IC 26d in that it includes an oscillation circuit 42 but lacks an output circuit. Additionally, objects with the same reference numerals are... Figure 2 The power factor improvement is the same as that of IC26a.

[0221] <<<Structure of Oscillator Circuit 42>>>

[0222] Figure 24 This is a diagram showing an example of an oscillation circuit 42. The oscillation circuit 42 is a circuit that charges capacitor 110 with the current Iramp2 corresponding to the difference between the voltage Vhdiv (the voltage Vcomp in the case of replacing the oscillation voltage 41) and the detection voltage Vload, and outputs an oscillation voltage Vr. The oscillation circuit 42 is constructed from the same circuitry as the oscillation circuit 41.

[0223] Therefore, if we take with Figure 21 If we consider the current generation circuit 131 in the same way, then the current Iramp2 is expressed by equation (11) as follows.

[0224] Iramp2=K1×(Vhdiv-Vload)×R4 / R3 / R5···(12)

[0225] In addition, the current Iramp2 is equivalent to "the charging current corresponding to the voltage corresponding to the rectified voltage and the detection voltage".

[0226] <<<Power Factor Improvement IC26g Operation>>>

[0227] Figure 25 This diagram illustrates an example of the operation of the power factor improvement IC26g when load 11 is under heavy load. The operation of the power factor improvement IC26g is compared with... Figure 20 The difference in the operation of the power factor improvement IC26f shown is that the current Iramp2 is generated based on the voltage divider voltage Vhdiv and the detection voltage Vload. However, the relationship between the current Iramp2 and the on-time of the NMOS transistor 27 is the same. Furthermore, since the operation of the power factor improvement IC26g is the same as that of the power factor improvement IC26f, its description is omitted. Figure 25 The time intervals t60 to t65 correspond to Figure 22 From time t50 to time t55.

[0228] Based on the above actions, the on-time of the NMOS transistor 27 in the power factor improvement IC26g becomes longer near the lower voltage level of Vh, i.e., near the lower absolute value of the AC voltage Vac. Therefore, the power factor improvement IC26g can flow a large amount of inductor current IL near the lower absolute value of the AC voltage Vac, i.e., in the low phase angle region, thereby reducing dead zones.

[0229] Furthermore, when load 11 becomes a "heavy load," the on-time of the NMOS transistor 27 in the power factor improvement IC26g increases near the higher level of voltage Vh, i.e., near the area where the absolute value of the AC voltage Vac is larger. Therefore, the power factor improvement IC26g can flow a large amount of inductor current IL near the area where the absolute value of the AC voltage Vac is larger, i.e., in the high phase angle region. Thus, even when load 11 becomes a "heavy load," the power factor improvement IC26f can set the waveform of the input current Iin to a shape similar to the waveform of the AC voltage Vac. As a result, the power factor improvement IC26f can improve both the power factor and THD.

[0230] In addition, Figure 25 In the diagram, only a few pulses are depicted for the drive signal Vp1 to aid understanding. Figure 23 The power factor improvement IC26g operates in this implementation. However, the switching frequency of the NMOS transistor 27, for example, is several kHz, which is sufficiently high than the frequency of the AC voltage Vac (50-60 Hz). Therefore, in practice, a very large amount of drive signal Vp1 is contained within one cycle of the AC voltage Vac.

[0231] ===Transformation Examples===

[0232] In this embodiment, an example of changing the bias voltage Vrampl according to the level of the voltage divider voltage Vhdiv in the power factor improvement IC26a is described. Furthermore, an example of changing the voltage Vcompx according to the level of the voltage divider voltage Vhdiv in the power factor improvement IC26e is described. However, as... Figure 26 As shown in the eighth embodiment of the power factor improvement IC26h, the output circuit 65 can also change the bias voltage Vrampl and the voltage Vcompx according to the level of the voltage divider voltage Vhdiv. Furthermore, the output circuit 65 is configured to include an oscillation circuit 40, an output circuit 60, a buffer circuit 160, and an inverting amplifier circuit 170.

[0233] Furthermore, in this embodiment, the voltage divider circuit 70 divides the voltage Vh obtained by full-wave rectification of the AC voltage Vac, thereby generating a divided voltage Vhdiv having an AC component of voltage Vh. However, Figure 27The AC component detection circuit 200 shown can generate a voltage Vh_compo with an AC component having a voltage Vh based on the voltage Vzcd from the auxiliary coil L2, and the power factor improvement IC 26 can also use the voltage Vh_compo instead of the voltage divider voltage Vhdiv.

[0234] Specifically, such as Figure 27 As shown, the AC component detection circuit 200 is configured to include an envelope detection circuit 201 and an inverting circuit 202. The envelope detection circuit 201 detects the peak value of a negative voltage Vzcd, whose polarity is opposite to the voltage generated in the main coil L1. Furthermore, the inverting circuit 202 inverts the detected peak value and outputs it as a voltage Vh_compo. Thus, the AC component detection circuit 200 outputs a voltage Vh_compo based on the voltage Vzcd, which has the same polarity as the voltage generated in the main coil L1.

[0235] ===Summary===

[0236] The AC-DC converters 10a and 10b of this embodiment have been described above. The oscillation circuit 40 outputs an oscillation voltage Vr that rises from the bias voltage Vrampl at a predetermined slope based on a constant current Iramp0. Thus, although details will be described later, for example, the power factor improvement IC 26a reduces the variation in the on-time of the NMOS transistor 27 in each switching cycle caused by the noise component of the voltage Vcomp. Furthermore, for example, the output circuit 60 changes the bias voltage Vrampl based on the divided voltage Vhdiv and outputs, such that when the level of the divided voltage Vhdiv increases, the on-time of the NMOS transistor 27 decreases. Additionally, for example, the output circuit 64 changes the voltage Vcompx based on the divided voltage Vhdiv and outputs, such that when the level of the divided voltage Vhdiv increases, the on-time of the NMOS transistor 27 decreases. Furthermore, the output circuit 65 changes the bias voltage Vrampl and voltage Vcompx based on the voltage divider voltage Vhdiv and outputs accordingly, causing the on-time of NMOS transistor 27 to shorten when the voltage divider voltage Vhdiv level is high. Consequently, near the lower level of the voltage divider voltage Vhdiv, the on-time of NMOS transistor 27 increases, resulting in a large inductor current IL flowing through it. Due to the large inductor current IL flowing through it, the voltage of capacitor 22 decreases, and the difference between the absolute value of the AC voltage Vac and the voltage value of capacitor 22 increases, causing current to flow through the diodes (not shown) constituting the diode bridge of the full-wave rectifier circuit 21. Therefore, the dead zone near the lower level of the voltage divider voltage Vhdiv is reduced. As a result, an integrated circuit can be provided that appropriately changes the input current to improve the power factor.

[0237] in addition, Figure 28 This is a graph illustrating the variation of the drive signal Vp1 based on the voltage Vcomp and the oscillation voltage Vr, which have noise components. At time t70, when the inductor current IL becomes approximately zero and the NMOS transistor 27 is turned on, the oscillation voltage Vr gradually increases with a first slope. Then, at time t71, if the oscillation voltage Vr becomes the noise level of the voltage Vcomp, the NMOS transistor 27 is turned off. However, if the voltage Vcomp has no noise, the NMOS transistor 27 is turned off at time t72. Furthermore, at time t73, when the inductor current IL becomes approximately zero and the NMOS transistor 27 is turned on, the oscillation voltage Vr gradually increases with a second slope that is larger than the first slope. Then, at time t74, if the oscillation voltage Vr becomes the noise level of the voltage Vcomp, the NMOS transistor 27 is turned off. However, if the voltage Vcomp has no noise, the NMOS transistor 27 is turned off at time t75. Here, comparing the period between times t71 and t72 with the period between times t74 and t75, it can be seen that the smaller the slope of the oscillation voltage Vr, the greater the variation in the on-time of the NMOS transistor 27 due to the noise of the voltage Vcomp. That is, when the slope of the oscillation voltage Vr changes, the variation in the on-time of the NMOS transistor in each switching cycle becomes larger. On the other hand, the oscillation circuit 40 uses a constant current Iramp0 to output an oscillation voltage Vr that gradually increases with a predetermined slope. Therefore, for example, the power factor improvement IC 26a can reduce the variation in the on-time of the NMOS transistor 27 in each switching cycle caused by the noise component of the voltage Vcomp.

[0238] Furthermore, for example, the output circuit 60 changes the bias voltage Vrampl based on the voltage divider voltage Vhdiv and outputs accordingly, such that when the level of the voltage divider voltage Vhdiv increases, the on-time of the NMOS transistor 27 decreases. This changes the bias voltage Vrampl, which has less noise, and reduces the influence of the noise component of the voltage Vcomp.

[0239] Furthermore, the oscillation circuit 40 includes a capacitor 110 connected to a capacitor 111 that maintains the bias voltage Vrampl and a charging / discharging circuit 90. Thus, assuming that the grounding varies due to switching noise without the capacitor 111, the oscillation voltage Vr would also vary. However, since a stable bias voltage Vrampl is applied to the capacitor 111, the influence of noise-driven grounding on the oscillation voltage Vr is reduced.

[0240] Furthermore, the output circuit 60 is a buffer circuit that uses the output divided voltage Vhdiv as the bias voltage Vrampl. Therefore, the power factor improvement IC 26a changes the on-time of the NMOS transistor 27 according to the divided voltage Vhdiv, thereby reducing dead zones.

[0241] Furthermore, the output circuit 61 is an amplifier circuit that amplifies the voltage divider voltage Vhdiv with a gain G corresponding to the level of the voltage divider voltage Vhdiv and outputs it as a bias voltage Vrampl. Thus, the power factor improvement IC26b can further extend the conduction time of the NMOS transistor 27 even when the voltage divider voltage Vhdiv is low, thereby reducing dead zones.

[0242] Furthermore, the output circuit 62 changes the bias voltage Vrampl based on the voltage divider voltage Vhdiv and the voltage Vcomp, thus shortening the on-time of the NMOS transistor 27 when the level of the voltage divider voltage Vhdiv increases. Conversely, the output circuit 62 changes the bias voltage Vrampl based on the voltage divider voltage Vhdiv and the voltage Vcomp, thus lengthening the on-time of the NMOS transistor 27 when the feedback voltage Vfb decreases. Therefore, when the load 11 becomes a "heavy load" and the feedback voltage Vfb decreases, the on-time of the NMOS transistor 27 increases, and thus, even when the load 11 becomes a "heavy load," the waveform of the AC voltage Vac becomes similar in shape to the waveform of the input current Iin.

[0243] Furthermore, the output circuit 62 includes a current generation circuit 130 and a voltage generation circuit 150. Therefore, the output circuit 62 can output a bias voltage Vrampl based on the voltage divider voltage Vhdiv and the voltage Vcomp using a simple circuit.

[0244] Furthermore, the output circuit 63 changes the bias voltage Vrampl based on the voltage divider voltage Vhdiv and the detection voltage Vload, and outputs accordingly. This causes the on-time of the NMOS transistor 27 to shorten when the level of the voltage divider voltage Vhdiv increases. Additionally, the output circuit 63 changes the bias voltage Vrampl based on the voltage divider voltage Vhdiv and the voltage Vload, and outputs accordingly. This causes the on-time of the NMOS transistor 27 to lengthen when the load current Iload increases. Therefore, even when the load 11 becomes a "heavy load" and the load current Iload increases, the on-time of the NMOS transistor 27 lengthens. Consequently, even when the load 11 becomes a "heavy load," the waveform of the AC voltage Vac changes to a shape similar to the waveform of the input current Iin.

[0245] Furthermore, the output circuit 63 includes a current generation circuit 130 and a voltage generation circuit 150. Thus, the output circuit 63 can output a bias voltage Vrampl based on the divided voltage Vhdiv and the sensed voltage Vload using a simple circuit.

[0246] Furthermore, the output circuit 64 changes the voltage Vcompx based on the voltage divider voltage Vhdiv and outputs accordingly, causing the on-time of NMOS transistor 27 to shorten when the voltage divider voltage Vhdiv level is high. Consequently, near the lower level of the voltage divider voltage Vhdiv, the on-time of NMOS transistor 27 increases, and the inductor current IL flows in large quantities. Due to the large flow of inductor current IL, the voltage of capacitor 22 decreases, and the difference between the absolute value of the AC voltage Vac and the voltage value of capacitor 22 increases, causing current to flow through the diodes (not shown) constituting the diode bridge of the full-wave rectifier circuit 21. Therefore, the dead zone near the lower level of the voltage divider voltage Vhdiv is reduced.

[0247] Furthermore, the oscillation circuit 40 includes a capacitor 110 connected to a capacitor 111 that maintains the bias voltage Vrampl and a charging / discharging circuit 90. Thus, assuming that the grounding is affected by switching noise in the absence of capacitor 111, the oscillation voltage Vr would also vary. However, since a stable bias voltage Vrampl is applied to capacitor 111, the influence of noise-driven grounding on the oscillation voltage Vr is reduced.

[0248] Furthermore, the output circuit 64 outputs the voltage Vcompx, corresponding to the difference between the divided voltage Vhdiv and the voltage Vcomp, to the comparator 85. Consequently, near the lower level of the divided voltage Vhdiv, the on-time of the NMOS transistor 27 increases, and the inductor current IL flows in large quantities. Due to the large flow of inductor current IL, the voltage of capacitor 22 decreases, and the difference between the absolute value of the AC voltage Vac and the voltage value of capacitor 22 increases, causing current to flow through the diodes (not shown) forming the diode bridge of the full-wave rectifier circuit 21. Therefore, the dead zone near the lower level of the divided voltage Vhdiv is reduced.

[0249] Furthermore, the output circuit 64 includes a buffer circuit 160 and an inverting amplifier circuit 170. Thus, the power factor improvement IC 26e can output the voltage Vcompx, corresponding to the difference between the divided voltage Vhdiv and the voltage Vcomp, to the comparator 85 through a simple circuit.

[0250] Furthermore, the oscillation circuit 41 changes the slope of the oscillation voltage Vr and outputs it, causing the on-time of NMOS transistor 27 to shorten when the level of the voltage divider Vhdiv increases and to lengthen when the feedback voltage Vfb decreases. Therefore, when the load 11 becomes a "heavy load" and the feedback voltage Vfb decreases, the on-time of NMOS transistor 27 increases. Thus, even when the load 11 becomes a "heavy load," the waveform of the AC voltage Vac changes to a shape similar to that of the input current Iin.

[0251] Furthermore, the oscillation circuit 41 uses the voltage divider Vhdiv and voltage Vcomp to change the slope of the oscillation voltage Vr. Thus, even if the load 11 becomes a "heavy load," the waveform of the AC voltage Vac changes to a shape similar to the waveform of the input current Iin.

[0252] Furthermore, the oscillation circuit 41 includes a capacitor 110 connected to a capacitor 111 that maintains a predetermined bias voltage Vrampl, and a charging / discharging circuit 91. Thus, the slope of the oscillation voltage Vr can be varied based on the voltage divider voltage Vhdiv and the voltage Vcomp using a simple circuit. Furthermore, assuming that the grounding is affected by switching noise without the capacitor 111, the oscillation voltage Vr would also vary. However, since a stable bias voltage Vrampl is applied to the capacitor 111, the influence of grounding with noise components on the oscillation voltage Vr is reduced.

[0253] Furthermore, the oscillation circuit 42 uses the voltage divider voltage Vhdiv and the detection voltage Vload to change the slope of the oscillation voltage Vr. As a result, when the load 11 becomes a "heavy load" and the detection voltage Vload rises, the on-time of the NMOS transistor 27 becomes longer. Therefore, even when the load 11 becomes a "heavy load", the waveform of the AC voltage Vac becomes similar to the waveform of the input current Iin.

[0254] Furthermore, the oscillation circuit 42 includes a capacitor 110 connected to a capacitor 111 that maintains a predetermined bias voltage Vrampl, and a charging / discharging circuit 91. Thus, the slope of the oscillation voltage Vr can be varied based on the voltage divider voltage Vhdiv and the detection voltage Vload using a simple circuit. Furthermore, assuming that the grounding is affected by switching noise without the capacitor 111, the oscillation voltage Vr would also vary. However, since a stable bias voltage Vrampl is applied to the capacitor 111, the influence of grounding with noise components on the oscillation voltage Vr is reduced.

[0255] The above embodiments are provided to facilitate understanding of the present invention, and are not intended to limit or restrict its interpretation. Furthermore, the present invention can be modified or improved without departing from its spirit, and the present invention naturally includes its equivalents.

[0256] Label Explanation

[0257] 10a, 10b AC-DC converters

[0258] 11 Load

[0259] 20-input line filter

[0260] 21 Full-wave rectifier circuit

[0261] Capacitors 22, 25, 33, 34, 110, 111

[0262] 23 Transformers

[0263] Diodes 24, 28, and 29

[0264] 27, 114, 146 NMOS transistors

[0265] Resistors 30, 31, 32, 35, 87, 88, 121, 142, 143, 147, 151, 171, 173

[0266] 40, 41, 42 Oscillating Circuits

[0267] 50 Drive Circuit

[0268] Output circuits 60, 61, 62, 63, 64, and 65

[0269] 70 Voltage Divider Circuit

[0270] 71 Error Voltage Output Circuit

[0271] 72 Load Detection Circuit

[0272] 80 Zero Current Detection Circuit

[0273] 81 Delay Circuit

[0274] 82 OR gate circuit

[0275] 83 SR trigger

[0276] 84 On-time timer circuit

[0277] 85 comparator

[0278] 86 Buffer

[0279] 89 Transconductance Amplifier

[0280] 90, 91 Charging and discharging circuits

[0281] 100, 160 buffer circuits

[0282] 112 Constant Current Source

[0283] 113 Inverter

[0284] Operational amplifiers 120, 140, 141, 144, 145, 152, 161, 172, 191

[0285] 122 Variable resistor

[0286] 130, 131 Current generation circuit

[0287] 148, 149, 180 PMOS transistors

[0288] 150V Voltage Generation Circuit

[0289] 170 Inverting Amplifier Circuit

[0290] 190 Constant voltage source

[0291] 200 AC component detection circuit

[0292] 201 Envelope Detection Circuit

[0293] 202 Inverting circuit.

Claims

1. An integrated circuit, comprising: A first capacitor and an inductor, wherein a voltage corresponding to an AC voltage is applied to the first capacitor and inductor; The integrated circuit includes a transistor that controls the inductor current flowing through the inductor, and the integrated circuit switches the transistor in a power supply circuit that generates an output voltage based on the AC voltage. The integrated circuit is characterized by comprising: An oscillating circuit that outputs an oscillating voltage that rises from a first voltage at a predetermined slope when the inductor current becomes less than a first predetermined value; An error voltage output circuit outputs an error voltage corresponding to the difference between a feedback voltage and a reference voltage. A driving circuit that turns on the transistor when the inductor current becomes less than a first predetermined value and turns off the transistor when the oscillation voltage becomes a second voltage based on the error voltage; and An output circuit that, in order to shorten the on-time of the transistor when the level of the rectified voltage obtained by full-wave rectification of the AC voltage becomes higher, modifies at least one of the first voltage and the second voltage based on the rectified voltage and outputs an output.

2. The integrated circuit as described in claim 1, characterized in that, The output circuit changes the first voltage (between the first voltage and the second voltage) based on the rectified voltage and then outputs the output.

3. The integrated circuit as described in claim 2, characterized in that, The oscillation circuit includes: A second capacitor, one end of which is subjected to the first voltage; and A charging and discharging circuit is connected to the other end of the second capacitor to charge and discharge the second capacitor and generate the oscillating voltage.

4. The integrated circuit as described in claim 3, characterized in that, The output circuit is a buffer circuit that outputs a voltage corresponding to the rectified voltage as the first voltage.

5. The integrated circuit as described in claim 3, characterized in that, The output circuit is an amplifier circuit that amplifies the voltage corresponding to the rectified voltage with a gain corresponding to the level of the rectified voltage and outputs it as the first voltage.

6. The integrated circuit according to any one of claims 1 to 3, characterized in that, The output circuit changes the first voltage and outputs based on the voltage corresponding to the rectified voltage and the second voltage, such that the conduction time of the transistor becomes shorter when the level of the rectified voltage increases and the conduction time of the transistor becomes longer when the output voltage decreases.

7. The integrated circuit as described in claim 6, characterized in that, The output circuit includes: A current generating circuit that generates a current corresponding to the difference between the voltage corresponding to the rectified voltage and the second voltage; and A voltage generation circuit that generates the first voltage based on the current.

8. The integrated circuit according to any one of claims 1 to 3, characterized in that, The power supply circuit further includes a load detection circuit that outputs a detection voltage corresponding to the load current flowing through the load in the power supply circuit. The output circuit changes the first voltage and outputs based on the voltage corresponding to the rectified voltage and the detected voltage, such that the conduction time of the transistor becomes shorter when the level of the rectified voltage increases and the conduction time of the transistor becomes longer when the load current increases.

9. The integrated circuit as described in claim 8, characterized in that, The output circuit includes: A current generating circuit generates a current corresponding to the difference between the rectified voltage and the detected voltage when the detected voltage becomes greater than a second predetermined value. as well as A voltage generation circuit that generates the first voltage based on the current.

10. The integrated circuit as claimed in claim 1, characterized in that, The output circuit changes the second voltage of the first voltage and the second voltage based on the rectified voltage and then outputs the output.

11. The integrated circuit as claimed in claim 10, characterized in that, The oscillation circuit includes: A second capacitor, one end of which is subjected to the first voltage; and A charging and discharging circuit is connected to the other end of the second capacitor to charge and discharge the second capacitor and generate the oscillating voltage.

12. The integrated circuit as claimed in claim 11, characterized in that, The output circuit outputs the voltage corresponding to the difference between the rectified voltage and the error voltage as the second voltage.

13. The integrated circuit as claimed in claim 12, characterized in that, The output circuit includes: A buffer circuit that outputs a voltage corresponding to the rectified voltage; and An inverting amplifier circuit that outputs a second voltage corresponding to the difference between the output from the buffer circuit and the error voltage.

14. An integrated circuit, comprising: A first capacitor and an inductor, wherein a voltage corresponding to an AC voltage is applied to the first capacitor and inductor; The integrated circuit includes a transistor that controls the inductor current flowing through the inductor, and the integrated circuit switches the transistor in a power supply circuit that generates an output voltage based on the AC voltage. The integrated circuit is characterized by comprising: An oscillating circuit that outputs a rising oscillating voltage when the inductor current becomes less than a specified value; An error voltage output circuit outputs an error voltage corresponding to the difference between a feedback voltage and a reference voltage; and A driving circuit that turns on the transistor when the inductor current becomes less than a predetermined value, and turns off the transistor when the oscillation voltage becomes the error voltage. In order to shorten the conduction time of the transistor when the level of the rectified voltage obtained by full-wave rectification of the AC voltage becomes higher, and to lengthen the conduction time of the transistor when the output voltage decreases, the oscillation circuit changes the slope of the oscillation voltage and outputs it.

15. The integrated circuit as claimed in claim 14, characterized in that, The oscillation circuit changes the slope of the oscillation voltage based on the voltage corresponding to the rectified voltage and the error voltage.

16. The integrated circuit as claimed in claim 15, characterized in that, The oscillation circuit includes: The second capacitor; and The charging and discharging circuit charges the second capacitor with a voltage corresponding to the rectified voltage and a charging current corresponding to the error voltage when the inductor current becomes less than a specified value. When the oscillation voltage becomes the error voltage, the charging and discharging circuit discharges the second capacitor and generates the oscillation voltage.

17. The integrated circuit as claimed in claim 14, characterized in that, The power supply circuit further includes a load detection circuit that outputs a detection voltage corresponding to the load current flowing through the load in the power supply circuit. The oscillation circuit changes the slope of the oscillation voltage based on the voltage corresponding to the rectified voltage and the detection voltage.

18. The integrated circuit as claimed in claim 17, characterized in that, The oscillation circuit includes: The second capacitor; and The charging and discharging circuit charges the second capacitor with a voltage corresponding to the rectified voltage and a charging current corresponding to the detected voltage when the inductor current becomes less than a specified value. When the oscillation voltage becomes the error voltage, the charging and discharging circuit discharges the second capacitor and generates the oscillation voltage.

19. A power supply circuit that generates an output voltage based on an AC voltage, characterized in that it comprises: A first capacitor and an inductor, wherein a voltage corresponding to the AC voltage is applied to the first capacitor and the inductor; A transistor that controls the inductor current flowing through the inductor; as well as An integrated circuit that switches the transistor on and off. The integrated circuit includes: An oscillating circuit that outputs an oscillating voltage that rises from a first voltage at a predetermined slope when the inductor current becomes less than a predetermined value; An error voltage output circuit outputs an error voltage corresponding to the difference between a feedback voltage and a reference voltage. A driving circuit that turns on the transistor when the inductor current becomes less than the predetermined value and turns off the transistor when the oscillation voltage becomes a second voltage based on the error voltage; and An output circuit that, in order to shorten the on-time of the transistor when the level of the rectified voltage obtained by full-wave rectification of the AC voltage becomes higher, alters at least one of the first voltage and the second voltage based on the rectified voltage and outputs an output.

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