Control Circuit and Control Method of Delay Locked Loop

Abstract

A control circuit and a control method for a delay locked loop are provided. The control circuit includes a power status detector, a voltage comparator, an enable signal generator, and a control signal generator. The power status detector detects the transition edge of a frequency enable signal to generate a trigger signal corresponding to a change in the operating power supply. The voltage comparator compares the operating power supply with a reference voltage and generates a comparison result. The enable signal generator makes the enable signal in an active state according to the trigger signal and makes the enable signal in a non-active state according to the comparison result. The control signal generator outputs a control frequency to generate a control signal when the enable signal is in an active state. The delay locked loop is applied to a memory to improve the reliability of data extraction.

Description

Technical Field

[0001] The present invention relates to a control circuit and a control method for a delay locked loop, and more particularly to a control circuit and a control method for a delay locked loop applied to a memory. Background Art

[0002] Please refer to Figure 1 , in the prior art, when the clock enable signal CKE in a dynamic random access memory is pulled up from a low logic value to a high logic value, the dynamic random access memory can be released from the power down mode, and the voltage value of the received operating voltage VINT will decrease. This decrease in the voltage value of the operating voltage VINT will cause the frequency period of the read data DQS provided by the dynamic random access memory to change, and cause the states of the clock signal CK and the read data DQS to be out of sync. In this way, if the read data DQS is captured at the time point TS, it may cause an error in data reading and reduce the reliability. Summary of the Invention

[0003] The present invention is directed to a control circuit for a delay locked loop and a control method thereof, which can improve the reliability of data reading in the application of a memory.

[0004] According to an embodiment of the present invention, the control circuit of the delay locked loop includes a power state detector, a voltage comparator, an enable signal generator, and a control signal generator. The power state detector receives the clock enable signal and generates a trigger signal corresponding to a change in the operating power supply according to the detected transition edge of the clock enable signal. The voltage comparator compares the operating power supply with a reference voltage and generates a comparison result. The enable signal generator is coupled to the power state detector and the voltage comparator, receives the trigger signal, and makes the enable signal in an active state according to the trigger signal, and makes the enable signal in a non-active state according to the comparison result. The control signal generator receives the enable signal and a control frequency, and outputs the control frequency to generate a control signal when the enable signal is in an active state.

[0005] According to an embodiment of the present invention, the control method of the delay locked loop includes: generating a trigger signal corresponding to a change in the operating power supply according to the detected transition edge of the clock enable signal; comparing the operating power supply with a reference voltage and generating a comparison result; making the enable signal in an active state according to the trigger signal and making the enable signal in a non-active state according to the comparison result; and outputting the control frequency to generate a control signal when the enable signal is in an active state, where the control signal is used to control the start or stop of the locking operation of the delay locked loop.

[0006] According to the above, the present invention stops the locking operation of the delay lock loop through the generated control signal in the time interval when the operating power supply is unstable, aiming at the changing state of the operating power supply, so as to maintain the reliability of data reading in the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The embodiments of the present invention are illustrated in the accompanying drawings and, together with the description, are used to explain the principles of the present invention.

[0008] Figure 1 is a waveform diagram of the operation of a memory that is common knowledge;

[0009] Figure 2 shows a schematic diagram of a control circuit of a delay lock loop (DLL) according to an embodiment of the present invention;

[0010] Figure 3 shows a circuit diagram of a control circuit of a delay lock loop according to an embodiment of the present invention;

[0011] Figure 4 shows the present invention Figure 3 a waveform diagram of the operation of a control circuit according to an embodiment;

[0012] Figure 5 shows a flowchart of a control method of a delay lock loop according to an embodiment of the present invention.

[0013] DESCRIPTION OF REFERENCE NUMERALS IN THE DRAWINGS

[0014] 200, 300: control circuit;

[0015] 210, 310: power supply state detector;

[0016] 220, 320: enable signal generator;

[0017] 230, 330: voltage comparator;

[0018] 240: control signal generator;

[0019] CKE_PD, CKE: frequency enable signal;

[0020] SRL: reset latch;

[0021] SB: set terminal;

[0022] RB: reset terminal;

[0023] OA: output terminal;

[0024] LOUT: latch signal;

[0025] DLL_LOCKED: Locking signal;

[0026] DCKEN: Reverse frequency enable delay signal;

[0027] VINT: Operating power supply;

[0028] TRIG: Trigger signal;

[0029] EN_CTRL: Enable signal;

[0030] OP1: Operational amplifier;

[0031] Cout: Comparison result;

[0032] VREF: Reference voltage;

[0033] AD1: AND gate;

[0034] PDCTRL: Control signal;

[0035] CLK_CTRL: Control frequency;

[0036] DQS: Read data;

[0037] CK, CK1: Frequency signals;

[0038] TS: Time point;

[0039] FF1: Flip-flop;

[0040] IV1: Inverter;

[0041] ND1~ND5: NAND gates;

[0042] CLK: Frequency terminal;

[0043] D: Data terminal;

[0044] Q: Output terminal;

[0045] TDIS: Time interval;

[0046] RESET: Reset signal;

[0047] S510~S540: Control steps of the delay locked loop. Detailed implementation manners

[0048] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0049] Please refer to Figure 2, the control circuit 200 includes a power state detector 210, an enable signal generator 220, a voltage comparator 230, and a control signal generator 240. The power state detector 210 receives the frequency enable signal CKE_PD. The power state detector 210 generates a trigger signal TRIG corresponding to the change of the operating power supply VINT according to the transition edge of the detected frequency enable signal CKE_PD. Here, in the application of the memory, after the frequency enable signal CKE_PD is pulled up from a low logic value to a high logic value, the voltage value of the operating power supply VINT will decrease. Therefore, in this embodiment, the power state detector 210 can generate the trigger signal TRIG by detecting the rising edge of the frequency enable signal CKE_PD, where the trigger signal TRIG is a pulse signal. In this embodiment, when the trigger signal TRIG generates a negative pulse, it means that the operating power supply VINT will have a decreasing change.

[0050] The enable signal generator 220 is coupled to the power state detector 210 and is used to receive the trigger signal TRIG. The enable signal generator 220 is used to generate an enable signal EN_CTRL. Among them, the enable signal generator 220 makes the enable signal EN_CTRL in an active state according to the trigger signal TRIG. And, the enable signal generator 220 further receives the comparison result Cout and makes the enable signal EN_CTRL in a non-active state according to the comparison result Cout. The above-mentioned active state and non-active state can be presented by different logic values. Among them, when the enable signal EN_CTRL is the first logic value, it is in the active state, and when the enable signal EN_CTRL is the second logic value, it is in the non-active state. The first logic value can be one of the high logic value and the low logic value, and the second logic value can be the other of the high logic value and the low logic value.

[0051] In addition, the voltage comparator 230 is coupled to the enable signal generator 220. The voltage comparator 230 receives the operating power supply VINT and the reference voltage VREF, and generates a comparison result Cout according to the comparison of the operating power supply VINT and the reference voltage VREF. Among them, the voltage comparator 230 can provide the comparison result Cout to make the enable signal generator 220 set the generated enable signal EN_CTRL to the non-active state when the voltage value of the operating power supply VINT is lower than the reference voltage VREF. And, when the voltage value of the operating power supply VINT returns to be greater than the reference voltage VREF, the voltage comparator 230 provides the comparison result Cout to make the enable signal generator 220 change the generated enable signal EN_CTRL to the active state.

[0052] The control signal generator 240 is coupled to the enable signal generator 220. The control signal generator 240 receives the enable signal EN_CTRL and the control frequency CLK_CTRL, and determines whether to output the control frequency CLK_CTRL to generate the control signal PDCTRL according to the enable signal EN_CTRL. When the enable signal EN_CTRL is in an active state, the control signal generator 240 provides the control frequency CLK_CTRL to generate the control signal PDCTRL. Conversely, when the enable signal EN_CTRL is in an inactive state, the control signal generator 240 makes the control signal PDCTRL a fixed logic value (e.g., a low logic value).

[0053] It can be known from the above description that in the embodiment of the present invention, the power state detector 210 detects the time point when the operating power VINT changes, and when the operating power VINT changes, the voltage comparator 230 compares the operating power VINT with the reference voltage VREF to obtain the recovery state of the operating power VINT after the decrease. In the time interval from the change of the operating power VINT to the stabilization of the operating power VINT to the normal state (greater than the reference voltage VREF), the control signal generator 240 can maintain the control signal PDCTRL at a fixed low logic value through the enable signal EN_CTRL in the inactive state, and stop the locking action of the delay lock loop. In addition, in the present embodiment, when the operating power VINT stabilizes to the normal state, the control signal generator 240 can generate the control signal PDCTRL equal to the control frequency CLK_CTRL through the enable signal EN_CTRL in the activated state, and restart the locking action of the delay lock loop. In this way, the delay lock loop can quickly complete the locking action and maintain the correctness of the memory read data.

[0054] Please refer to Figure 3, the control circuit 300 includes a power state detector 310, an enable signal generator 320, a voltage comparator 330, and a control signal generator 340. The power state detector 310 includes a flip-flop FF1 and a logic circuit composed of an inverter IV1 and a NAND gate ND1. The data terminal D of the flip-flop FF1 receives the frequency enable signal CKE_PD; the frequency terminal CLK of the flip-flop FF1 can receive the frequency signal CK1; the output terminal Q of the flip-flop FF1 is coupled to the input terminal of the inverter IV1 and provides a frequency enable delay signal DCKE; the flip-flop FF1 also receives a reset signal RESET to perform a reset operation. The inverter IV1 is used to invert the frequency enable delay signal DCKE to generate an inverted frequency enable delay signal DCKEN. The NAND gate ND1 receives the frequency enable signal CKE_PD, the inverted frequency enable delay signal DCKEN, and a lock signal DLL_LOCKED, and generates a negative pulse of a trigger signal TRIG based on the phase difference between the rising edge of the frequency enable signal CKE_PD and the falling edge of the inverted frequency enable delay signal DCKEN when the delay locked loop is locked. Among them, the length of the negative pulse of the trigger signal TRIG is equal to the time length between the rising edge of the frequency enable signal CKE_PD and the falling edge of the inverted frequency enable delay signal DCKEN.

[0055] The enable signal generator 320 includes a set-reset latch (SR Latch) SRL, NAND gates ND2 and ND5. The set-reset latch SRL includes NAND gates ND3 and ND4. The set terminal SB of the set-reset latch SRL receives the trigger signal TRIG, and the reset terminal RB of the set-reset latch SRL is coupled to the output terminal of the NAND gate ND2. The set-reset latch SRL is used to sense the negative pulse of the trigger signal TRIG and correspondingly generate a latch signal LOUT with a high logic value at the output terminal OA.

[0056] The NAND gate ND5 forms an output control circuit. The NAND gate ND5 receives the latch signal LOUT and a comparison result Cout generated by the voltage comparator 330, and generates an enable signal EN_CTRL based on the latch signal LOUT and the comparison result Cout. In this embodiment, the enable signal EN_CTRL has a high logic value in the active state and a low logic value in the non-active state.

[0057] The voltage comparator 330 receives an operating power supply VINT and a reference voltage VREF for comparison and generates a comparison result Cout. The voltage comparator 330 can be constructed by a hysteretic operational amplifier OP1. The positive input terminal of the operational amplifier OP1 receives the reference voltage VREF, and the negative input terminal of the operational amplifier OP1 receives the operating power supply VINT.

[0058] After the negative pulse of the trigger signal TRIG appears and the voltage value of the operating power supply VINT remains lower than the reference voltage VREF, the voltage comparator 330 generates a comparison result Cout with a high logic value. In cooperation with the latch signal LOUT, which is also of a high logic value, the NAND gate ND5 can generate a deactivated enable signal EN_CTRL. When the voltage value of the operating power supply VINT rises above the reference voltage VREF, the comparison result Cout generated by the voltage comparator 330 changes to a low logic value, causing the NAND gate ND5 to generate an activated enable signal EN_CTRL.

[0059] Meanwhile, based on the enable signal EN_CTRL being of a high logic value, the NAND gate ND2 can provide a low logic value signal to the reset terminal RB of the set-reset latch SRL according to the trigger signal TRIG, which is also of a high logic value, and the enable signal EN_CTRL, and reset the latch signal LOUT to a low logic value. Under the condition that the latch signal LOUT is of a low logic value, the enable signal EN_CTRL changes to an activated state (high logic value).

[0060] The control signal generator 340 can be constructed by the AND gate AD1. The AND gate AD1 receives the enable signal EN_CTRL and the control frequency CLK_CTRL, and determines whether to output the control frequency CLK_CTRL to generate the control signal PDCTRL according to whether the enable signal EN_CTRL is activated. When the enable signal EN_CTRL is of a high logic value, the control signal PDCTRL is the same as the control frequency CLK_CTRL. In contrast, when the enable signal EN_CTRL is of a low logic value, the control signal PDCTRL is of a low logic value.

[0061] Please refer to Figure 4 , where the negative pulse of the trigger signal TRIG can be generated according to the rising edge of the frequency enable signal CKE_PD. During the time interval TDIS when the enable signal EN_CTRL is deactivated, the locking operation of the delay locked loop can be stopped by maintaining the control signal PDCTRL at a low logic value. Also, after the voltage value of the operating power supply VINT recovers (after the time interval TDIS), the control signal PDCTRL returns to be equal to the control frequency CLK_CTRL, and the locking operation of the delay locked loop is restarted.

[0062] Please refer to Figure 5, in step S510, a trigger signal for causing a corresponding change in the operating power supply is generated according to the transition edge of the detection frequency enable signal; in step S520, the operating power supply is compared with a reference voltage to generate a comparison result; in step S530, the enable signal is made active according to the trigger signal, and the enable signal is made inactive according to the comparison result; and, in step S540, a control frequency is output when the enable signal is active to generate a control signal, where the control signal is used to control the start or stop of the locking operation of the delay locked loop.

[0063] Details of the implementation of the above steps are described in detail in the foregoing embodiments, and will not be elaborated herein.

[0064] According to the above, the present invention stops the locking operation of the frequency signal of the delay locked loop when the voltage value of the operating power supply drops by detecting the transition edge of the frequency enable signal. In the application of memory, the frequency information corresponding to the read data can be kept synchronized with the frequency signal to maintain the reliability of the read data.

[0065] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A control circuit for a delay locked loop, comprising: A power status detector that receives a frequency enable signal and generates a trigger signal for causing a corresponding change in the operating power supply according to the detected transition edge of the frequency enable signal; A voltage comparator that compares the operating power supply with a reference voltage and generates a comparison result; An enable signal generator coupled to the power status detector and the voltage comparator, receiving the trigger signal and, according to the trigger signal, when the operating power supply is greater than the reference voltage, making the enable signal in an active state, and according to the comparison result, when the operating power supply is less than the reference voltage, making the enable signal in a non-active state; And A control signal generator that receives the enable signal and a control frequency and outputs the control frequency to generate a control signal when the enable signal is in the active state, wherein the enable signal generator includes: A set-reset latch having a set terminal receiving the trigger signal, a reset terminal of the set-reset latch receiving an inverted signal of the enable signal, and an output terminal of the set-reset latch generating a latch signal; And An output control circuit coupled to the output terminal of the set-reset latch, receiving the comparison result and the latch signal, and generating the enable signal according to the comparison result and the latch signal.

2. The control circuit according to claim 1, wherein the transition edge is a rising edge, and the power status detector detects the rising edge of the frequency enable signal to generate the trigger signal as a pulse signal.

3. The control circuit according to claim 1, wherein the power status detector includes: A flip-flop having a data terminal receiving the frequency enable signal, a clock terminal of the flip-flop receiving a frequency signal, and an output terminal of the flip-flop generating a frequency enable delay signal; And A logic circuit that performs a logic operation on the frequency enable signal and the frequency enable delay signal and generates the trigger signal according to the time delay between the frequency enable signal and the frequency enable delay signal.

4. The control circuit according to claim 3, wherein the logic circuit includes: An inverter that receives the frequency enable delay signal and generates an inverted frequency enable delay signal; And An AND gate that performs an AND logic operation on the inverted frequency enable delay signal and the frequency enable signal to generate the trigger signal.

5. The control circuit according to claim 4, wherein the AND gate receives a lock signal and determines whether to generate the trigger signal according to the lock signal.

6. The control circuit according to claim 1, wherein the voltage comparator includes: An operational amplifier having a negative input terminal for receiving the operating power supply, a positive input terminal of the operational amplifier receiving the reference voltage, and an output terminal of the operational amplifier generating the comparison result.

7. The control circuit according to claim 1, wherein the voltage comparator is a hysteresis comparator.

8. The control circuit according to claim 1, wherein the enable signal generator further includes: A NAND gate has two input terminals for receiving the enable signal and the trigger signal respectively, and an output terminal of the NAND gate is coupled to a reset terminal of the set-reset latch.

9. The control circuit according to claim 1, wherein the control signal generator includes an AND gate, and the AND gate outputs the control frequency to generate the control signal when the enable signal is in the active state.

10. The control circuit according to claim 1, wherein the control signal is used to control the start or stop of the locking operation of the delay locked loop.

11. A control method for a delay locked loop, comprising: Generating a trigger signal corresponding to a change in an operating power supply according to a transition edge of a detection frequency enable signal; Comparing the operating power supply with a reference voltage and generating a comparison result; According to the trigger signal, when the operating power supply is greater than the reference voltage, making the enable signal in the active state, and according to the comparison result, when the operating power supply is less than the reference voltage, making the enable signal in the non-active state, wherein, providing a reset terminal of a set-reset latch to receive an inverted signal of the enable signal, providing an output terminal of the set-reset latch to generate a latch signal, providing an output control circuit to receive the comparison result and the latch signal, and generating the enable signal according to the comparison result and the latch signal; And Outputting a control frequency to generate a control signal when the enable signal is in the active state, wherein the control signal is used to control the start or stop of the locking operation of the delay locked loop.

12. The control method according to claim 11, wherein the transition edge is a rising edge.

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