Reverse Contacts and Silicide Processes for 3D Logic Devices

Abstract

A first source / drain (S / D) structure of a first transistor is formed on a substrate and is located at a first end of a first channel structure of the first transistor. A first replacement silicide layer is deposited on a surface of the first S / D structure and is made of a first dielectric. A second dielectric is formed to cover the first replacement silicide layer and the first S / D structure. Subsequently, a first interconnect opening is formed in the second dielectric to expose the first replacement silicide layer. The first interconnect opening is filled with a first replacement interconnect layer, wherein the first replacement interconnect layer is made of a third dielectric. Further, a heat treatment is performed on the substrate. The first replacement interconnect layer and the first replacement silicide layer are removed. A first silicide layer is formed on the surface of the first S / D structure.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit and priority of the filing dates of U.S. Provisional Patent Application No. 62 / 907,107, filed on September 27, 2019, and U.S. Non - Provisional Patent Application No. 17 / 010,491, filed on September 2, 2020, which are hereby incorporated by reference in their entirety. Field of the Invention

[0003] This disclosure relates to the fabrication of integrated circuits and microelectronic devices. Background of the Invention

[0004] In the fabrication of semiconductor devices, especially at the microscale, various fabrication processes are performed, such as film deposition, etch mask creation, patterning, photoresist development, material etching and removal, and doping processes. These processes are repeated to form desired semiconductor device elements on a substrate. Historically, microfabrication has been used to create transistors in a plane and form wiring / metallization layers on top, and thus, this has been characterized as two - dimensional (2D) circuits or 2D fabrication. Although scaling efforts have significantly increased the number of transistors per unit area in 2D circuits, as scaling enters the nanoscale semiconductor device fabrication nodes, scaling efforts will also face greater challenges. Semiconductor device fabricators have expressed a desire for three - dimensional (3D) semiconductor devices where transistors are stacked on top of each other. The fabrication of 3D semiconductor devices presents many new and unique challenges associated with scaling, post - fabrication processing, and other aspects of 3D fabrication processes. Summary of the Invention

[0005] Although critical dimension scaling inevitably reaches saturation, 3D integration is seen as a viable option for continued semiconductor scaling. Two - dimensional transistor density scaling stops when the contact gate pitch reaches its scaling limit due to manufacturing variability and electrostatic device limitations. Even experimental new transistor designs (such as vertical - channel surrounding - gate transistors) that may one day overcome these contact gate pitch scaling limitations do not guarantee getting semiconductor scaling back on track because resistance, capacitance, and reliability issues limit line pitch scaling, which in turn limits the density at which transistors can be routed into a circuit.

[0006] 3D integration (i.e., vertical stacking of multiple devices) aims to overcome these scaling limitations by increasing transistor density in volume rather than area. With the adoption of 3D NAND, the flash memory industry has successfully demonstrated and implemented this idea. Mainstream CMOS VLSI scaling, as used in products such as CPUs or GPUs, is exploring the use of 3D integration as a major means to drive the semiconductor roadmap forward and thus requires enabling technologies.

[0007] Replacement Metal Gate (RMG) module integration has been successfully used in semiconductor manufacturing. In the RMG process, polysilicon or amorphous silicon is first used to form the intended metal gate. Using these temporary materials enables high-temperature heat treatment on the source and drain sides of the device. If the metal gate has been formed using the desired or final work function metal (WFM), this heat treatment could typically damage the desired metal gate material. The damage may include causing a significant threshold voltage shift on the device. Therefore, the RMG process retains a "dummy" gate with sacrificial or temporary materials, such as a polysilicon or amorphous silicon structure. With the dummy gate in place, several high-temperature heat treatments can be performed. For example, source and drain epitaxial pre-clean and reactor heating are typically carried out in the range of 750 °C to 780 °C. Source and drain epitaxial growth is typically performed between 500 °C and 800 °C (depending on the Ge content and the in-situ nature of the dopant). Laser spike annealing (LSA) can be used to perform source and drain dopant activation, which is carried out in the temperature range of 800 °C to up to 1250 °C, with a duration in the range from sub-milliseconds to whole seconds.

[0008] In RMG process integration, for PMOS, the source and drain structures are typically composed of boron-doped SiGe, and for NMOS, typically of silicon doped with phosphorus and / or arsenic. These source and drain structures are then "capped" with a given dielectric etch stop layer (CESL) to protect the silicon epitaxial surface from oxidation when forming vias to the drain contacts through the pre-metal dielectric that contains the source and drain structures, and to provide an etch stop layer to prevent damage to the source and drain regions. In this integration flow, processes that are very sensitive to heat treatment can be performed last.

[0009] This FEOL (front-end-of-line) integration has several components or steps. Polysilicon or amorphous silicon is typically used to form dummy gates. Source-drains of NMOS and / or PMOS are grown epitaxially via in-situ dopant addition typically performed in a temperature range of 500°C to 800°C. Pre-cleaning of silicon fins or nanosheets can be carried out in the range of 750°C to 780°C to remove native oxide from the silicon surface. Optionally, additional dopants can be implanted through complementary block and implant processes. The contact structures are encapsulated and the source and drain are wrapped with a protective etch-stop dielectric layer such as SiN or SiCN. The contact regions are filled with a pre-metalization dielectric material such as silicon oxide. Then the dummy gate structure is opened or exposed, and then the polysilicon or amorphous silicon together with the thermal or chemical oxide liner protecting the channel material is removed. For nanosheet devices, this can include removing the silicon germanium layer separating the intended silicon channels. An interface layer such as thermal oxide or chemical oxide can be deposited or formed over the intended channel material(s). A high-k dielectric film (such as HfO or various HfO) coupled with a dipole-forming layer such as LaO and AlO is formed over the interface layer material to cover the channel material(s). The high-k dielectric can be covered with a conduction-blocking material such as TiN. A high-k reliability anneal or drive-in anneal is performed to reduce the formation of charge traps. This reliability anneal is typically performed in the range of 700°C to 750°C. Laser spike annealing (LSA) treatment activates the dopants within the source and drain regions. This activation anneal is carried out in the range of 800°C to 1250°C, with its duration in the range from sub-milliseconds to whole seconds. A replacement metal gate (RMG) process can then proceed, where the work function metals for NMOS and PMOS are deposited, etched and adjusted to set various threshold voltages and then filled with a highly conductive metal. Then, through the pre-metalization dielectric, vias to the drain contacts are opened from M0 (or metal zero level) down to the corresponding source and drain epitaxial structures. The CESL etch-stop and protective dielectric layers can be removed, and then the vias to the drain structures can be metalized after selective self-aligned salicidation of the source and drain.

[0010] Using this RMG method, the silicide is formed after all the individual process steps with high thermal requirements and is thus held at a temperature at which the silicide may undergo a phase change or agglomeration. Such a phase change or agglomeration can greatly alter the contact resistivity and have a negative impact on the power and performance of the device. It is known that such a phase change of common silicide materials can occur at temperatures as low as 700°C.

[0011] As device development moves towards higher performance and lower power, more attention has been focused on improving contact resistance. One possible way to improve it is to migrate to so-called wraparound contacts (WACs), where the silicide completely wraps, or at least as much as possible, the source and drain epitaxial surfaces.

[0012] The WAC (wraparound contact) integration process can be accomplished by several alternative methods. In one method, a guided source and drain epitaxial growth is performed that closely mimics the shape of the fin as much as possible. Thus, the opening and formation of silicide around the fin epitaxy can coexist with current integration methods that do not currently include means for forming source and drain structures that include fins. This process can be achieved by recessing the fin structure within the sidewall spacers and then subsequently using the sidewall spacers to guide continued epitaxial growth within the fin. The silicide process will still be performed after RMG and all high-temperature FEOL steps.

[0013] In another WAC method, after forming vias to the drain contacts, a spacer-assisted method is used to form conventional source and drain contacts, where a thin spacer with etch selectivity is deposited within the boundary of the via-to-drain structure. Next, an opening is anisotropically "punched" through at the bottom of the via-to-drain structure. Then, the pre-metal dielectric material surrounding the source and drain contacts can be isotropically etched to form a spherical opening that surrounds the entire surface or most of the surface of the source and drain epitaxial structures from which silicide can grow. The silicide process is still performed after RMG and all high-temperature FEOL steps.

[0014] In another WAC method, conventional source and drain contacts are formed and then self-aligned silicide is immediately formed around the contacts. In this way, a conventional via-to-drain structure can be used to contact the silicide without any further processing to ensure that the bottom of the via-to-drain structure fully wraps the entire contact structure. This process is completed prior to any RMG processing, where a higher thermal treatment is performed, so this requires that all processes in the RMG module, dopant activation, and reliability-driven annealing be performed at temperatures or conditions that do not cause a phase change in the silicide. However, one challenge with this WAC method is that reducing the thermal treatment temperatures for reliability-driven annealing, source and drain dopant activation annealing, and source and drain epitaxial growth will result in some cumulative degradation of both the power and performance of the device. For example, for in-situ doped films, transitioning to a lower epitaxial deposition temperature may result in a significant reduction in the solubility of phosphorus in the epitaxial silicon, and this lower dopant concentration will result in a higher contact resistance. For conditions where the in-situ dopant concentration can be supplemented by additional implantation of dopant species, this does not pose a problem. However, as devices are scaled down to smaller size scales, this becomes less feasible.

[0015] For 3D devices such as complementary FET devices (CFETs) where complementary devices are vertically placed on top of each other, since NMOS and PMOS will occupy the same space for implantation in the vertical orientation, incorporating any type of implantation process for stacked complementary devices is considered unfeasible. Similarly, reducing the reliability annealing temperature by taking a higher pressure reliability annealing has been shown to be less effective compared to high temperature annealing. Therefore, the issue with any type of silicide process before the RMG module is that there will be some trade - offs related to obtaining area benefits in complementary FET designs but at the cost of potentially degrading performance and / or increasing power. Figures 1A to 1C A comparison of a standard contact, a wrap - around contact formed using silicide before the RMG module, and a wrap - around contact based on a CFET design is shown.

[0016] Figure 1A is a cross - sectional view of a standard contact that can be used for a FINFET structure. As Figure 1A shown, a silicon fin 104 can protrude from a dielectric layer 102. A source / drain (S / D) structure 106 can be disposed on the silicon fin 104. In some embodiments, the S / D structure 106 can be made of phosphorous - doped silicon. A silicide layer 108 can be located on the top surface of the S / D structure 106. In some embodiments, the silicide layer 108 can be made of TiSi. Additionally, a dielectric capping layer 110 can be located above the silicide layer 108. In some embodiments, the dielectric capping layer 110 can be made of SiCN.

[0017] Figure 1B is a cross - sectional view of a wrap - around contact formed using silicide before the RMG module. As Figure 1B shown, a silicon fin (or fin structure) 114 can protrude from a dielectric layer 112. An S / D structure 116 can be located on the fin structure 114. In some embodiments, the S / D structure 116 can be made of phosphorous - doped silicon. A silicide layer 118 can be located above the S / D structure 116 and surround the top and side surfaces of the S / D structure 116. In some embodiments, the silicide layer 118 can be made of TiSi. A dielectric capping layer 120 can be located on the silicide layer 118 to cover the silicide layer 118. In some embodiments, the dielectric capping layer 120 can be made of SiCN.

[0018] In Figure 1C a cross - sectional view of a wrap - around contact based on a CFET design can be shown. The wrap - around contact can be formed based on a manufacturing process that can form silicide, barrier metal, and via to the drain high - conductivity metal before the RMG module. As Figure 1CAs shown, the power rail structure 122 can be located in the dielectric layer 134. The channel region 124 can be located above the power rail structure 122. The channel region 124 can be made of silicon. The S / D structure 126 can be formed to surround the channel region 124. The S / D structure 126 can be made of phosphorus-doped silicon. The silicide layer 128 can be arranged to wrap the S / D structure 126. The silicide layer 128 can be made of TiSi. The local interconnect structure 132 can be formed above the silicide layer 128. Additionally, a barrier layer 130 can be formed between the silicide layer 128 and the local interconnect structure 132, and the barrier layer further surrounds the local interconnect structure 132. In some embodiments, the local interconnect structure 132 can be made of ruthenium (Ru), and the barrier layer 130 can be made of TiN.

[0019] For complementary FET devices where NMOS and PMOS devices are vertically stacked on top of each other, the integration method for forming such devices typically consists of a process in which contacts and local interconnect structures are patterned and metallized before the RMG module. Thus, all heat treatments such as dopant activation and reliability annealing are performed after the source and drain have been grown, the silicide has been formed, and the silicide has been metallized with both a barrier metal fill and a highly conductive metal fill before the RMG module / process. Examples of CFET integration processes can include: (a) silicon pre-clean for epitaxial growth of the upper source and drain, (b) in-situ doped source and drain epitaxial growth, (c) reliability-driven annealing after high-k deposition, and (d) LSA dopant activation annealing.

[0020] In 3D monolithic stacked devices such as complementary FETs and vertically stacked transistors, the lower devices are formed and metallized before the upper devices, and the replacement metal gate module is performed with higher heat treatment. It is also necessary to prevent any diffusion of source and drain dopant species from the actual source and drain epitaxy through the silicide to the actual interconnect metal, which would significantly increase the contact resistance. In these cases, a barrier metal can be used to prevent such diffusion into the interconnect metal. However, this barrier metal has significantly lower conductivity compared to the interconnect metal itself. Thus, a large thickness of the barrier metal may also cause a net increase in the total resistance of the contacts and interconnect structures, as the volume of the barrier metal may occupy some volume portions that are typically occupied by the highly conductive fill metal.

[0021] Therefore, it is found herein that, in order to correct many heat treatment problems in 3D devices and conventional wrap-around contacts, many techniques for reducing the thermal annealing temperature will have some expected negative impacts on the performance or power of the device.

[0022] One embodiment includes using replacement silicide and replacement metal interconnect processes, where replacement materials are substituted into the integration flow and manufacturing process and then removed after completion of FEOL (front-end-of-line) annealing and replaced with final silicide and interconnect metal.

[0023] Of course, the order of the manufacturing steps disclosed herein is presented for clarity. Generally, these manufacturing steps can be performed in any suitable order. Additionally, although each of the different features, techniques, configurations, etc. in this disclosure may be discussed in different places in this disclosure, it should be noted that each concept can be performed independently of each other or in combination with each other. Accordingly, this disclosure can be implemented and viewed in many different ways.

[0024] It should be noted that the present invention content section does not specify every embodiment and / or incremental novel aspect of this disclosure or the claimed invention. Instead, the present invention content only provides a preliminary discussion of different embodiments and corresponding points of novelty compared to conventional techniques. For additional details and / or possible perspectives of the present invention and embodiments, the reader should refer to the detailed implementation section of this disclosure and the corresponding drawings as further discussed below.

[0025] According to one aspect of this disclosure, a method for forming a semiconductor device is provided. In the disclosed method, a first source / drain (S / D) structure of a first field-effect transistor is formed on a substrate. The first S / D structure may be located at a first end of a first channel structure of the first field-effect transistor. The first channel structure may be located above the substrate and extend along the top surface of the substrate. A first replacement silicide layer may be deposited on the surface of the first S / D structure, where the first replacement silicide layer may be made of a first dielectric. A second dielectric may be formed to cover the first replacement silicide layer and the first S / D structure of the first field-effect transistor. Subsequently, a first interconnect opening may be formed in the second dielectric to expose the first replacement silicide layer. The first interconnect opening may be filled with a first replacement interconnect layer, where the first replacement interconnect layer may be made of a third dielectric. Further, a heat treatment may be performed on the substrate. The first replacement interconnect layer in the first interconnect opening and the first replacement silicide layer may be removed. Then, a first silicide layer may be formed on the surface of the first S / D structure of the first field-effect transistor.

[0026] In some embodiments, before performing a heat treatment on a substrate, a first replacement interconnect layer in a first interconnect opening may be recessed. Subsequently, a first dielectric cap may be formed on the first replacement interconnect layer. Then, the first interconnect opening may be filled with a second dielectric. The second dielectric is further recessed to expose a second channel structure of a second field effect transistor. The second channel structure may be located above and spaced apart from the first channel structure. A second S / D structure of the second field effect transistor may be formed. The second S / D structure is located above and spaced apart from the first S / D structure. The second S / D structure may be located at a first end of the second channel structure. A second replacement silicide layer may be deposited on a surface of the second S / D structure, wherein the second replacement silicide layer may be made of a first dielectric. A second dielectric may be deposited to cover the second replacement silicide layer and the second S / D structure. A second interconnect opening may be formed in the second dielectric to expose the second replacement silicide layer. A second replacement interconnect layer may be formed in the second interconnect opening, wherein the second replacement interconnect layer may be made of a third dielectric.

[0027] In some embodiments, after forming the second replacement interconnect layer in the second interconnect opening, a portion of the second replacement interconnect layer may be removed, thereby forming a space above the second replacement interconnect layer. The space is further located in the second dielectric. A second dielectric cap may be formed on the second replacement interconnect layer. Then, the space may be filled with a second dielectric.

[0028] In some embodiments, after performing a heat treatment on the substrate, the second replacement interconnect layer and the second replacement silicide layer in the second interconnect opening may be removed. A second silicide layer may be deposited on a surface of the second S / D structure.

[0029] In some embodiments, to remove the second replacement interconnect layer and the second replacement silicide layer, an interlayer dielectric (ILD) may be formed above the second dielectric. Then, a patterned mask may be formed above the ILD. An etching process may be operated to form a first via opening and a second via opening based on the patterned mask. The first via opening and the second via opening extend into the second dielectric and the ILD to expose the first replacement interconnect layer and the second replacement interconnect layer, respectively. An etching process may be performed to further remove the first replacement interconnect layer, the first replacement silicide layer in the first interconnect opening, the second replacement interconnect layer in the second interconnect opening, and the second replacement silicide layer.

[0030] In some embodiments, after depositing the first silicide layer and the second silicide layer, first trench openings and second trench openings can be formed in the ILD based on a patterned mask, wherein the first trench opening is connected to a first via opening, and the second trench opening is connected to a second via opening. Conductive material can be deposited in the first trench opening, the second trench opening, the first via opening, the second via opening, the first interconnect opening, and the second interconnect opening to form a first metal line in the first trench opening, a second metal line in the second trench opening, a first via in the first via opening, a second via in the second via opening, a first interconnect structure in the first interconnect opening, and a second interconnect structure in the second interconnect opening. Thus, the first metal line, the first via, and the first interconnect structure are connected together. The second metal line, the second via, and the second interconnect structure are connected together.

[0031] In the disclosed method, a portion of the first metal line and a portion of the first via can be removed to form a first gap above the first via to separate the first interconnect structure from the first metal line. The first gap is disposed in the ILD and further extends into the second dielectric. A portion of the second metal line and a portion of the second via can be removed to form a second gap above the second via to separate the second interconnect structure from the second metal line. The second gap can be disposed in the ILD and further extends into the second dielectric. A first insulating layer can be deposited in the first gap, and a second insulating layer can be deposited in the second gap. A portion of the first insulating layer and a portion of the second insulating layer in the ILD can be further removed to form a first recessed space above the first insulating layer, and the first recessed space is located in the ILD, and a second recessed space is formed above the second insulating layer, and the second recessed space is located in the ILD. Then, conductive material can be deposited in the first recessed space and the second recessed space to refill the first metal line and the second metal line, respectively. Thus, the first insulating layer is located between the first metal line and the first interconnect structure, and the second insulating layer is located between the second metal line and the second interconnect structure.

[0032] In some embodiments, before performing a heat treatment on the substrate, a first gate structure is formed to surround the top surface of the first channel structure, and a second gate structure is formed to surround the top surface of the second channel structure. The first gate structure includes a first interface layer surrounding the top surface of the first channel structure, a first high-k dielectric film surrounding the first interface layer, and a first conductive barrier layer surrounding the first high-k dielectric film. The second gate structure includes a second interface layer surrounding the top surface of the second channel structure, a second high-k dielectric film surrounding the second interface layer, and a second conductive barrier layer surrounding the second high-k dielectric film.

[0033] In some embodiments, after performing a heat treatment on the substrate, a first work function metal may be formed over the first conduction barrier layer, and a second work function metal may be formed over the second conduction barrier layer.

[0034] In some embodiments, the heat treatment of the substrate may include heating the substrate to a temperature above 500 degrees Celsius. The heat treatment may be an annealing process configured to anneal at least one of the first S / D structure, the second S / D structure, the first gate structure, or the second gate structure.

[0035] In some embodiments, the first dielectric, the second dielectric, and the third dielectric may have different etch resistances relative to each other, such that an etch process removes one of the first dielectric, the second dielectric, and the third dielectric without removing the other two of the first dielectric, the second dielectric, and the third dielectric.

[0036] In some embodiments, the first channel structure may include one or more first nanosheets / first nanowires stacked over the substrate and extending along the top surface of the substrate. The first nanosheets / first nanowires are further spaced apart from each other. The second channel structure may include one or more second nanosheets / second nanowires stacked over the substrate and extending along the top surface of the substrate. The second nanosheets / second nanowires are further spaced apart from each other.

[0037] In another aspect of the present disclosure, a method for forming a semiconductor device is provided. In the disclosed method, a pair of channel structures may be formed over a substrate. The pair of channel structures may include a first channel structure of a first field effect transistor over the substrate and a second channel structure of a second field effect transistor stacked over the first channel structure. The first channel structure and the second channel structure may further extend along the top surface of the substrate. A first source / drain (S / D) structure may be formed at a first end of the first channel structure, a first replacement silicide layer may be formed on the surface of the first S / D structure, and a first replacement interconnect structure may be formed over the first replacement silicide layer. Additionally, a second S / D structure may be formed at a first end of the second channel structure, a second replacement silicide layer may be formed on the surface of the second S / D structure, and a second replacement interconnect structure may be formed over the second replacement silicide layer. Further, a heat treatment may be performed on the substrate. Subsequently, the first replacement silicide layer, the first replacement interconnect structure, the second replacement silicide layer, and the second replacement interconnect structure may be removed. A first silicide layer may be formed on the first S / D structure, and a second silicide layer may be formed on the second S / D structure.

[0038] To form a first replacement silicide layer on the surface of the first S / D structure and a first replacement interconnect structure above the first replacement silicide layer, a first dielectric can be deposited on the surface of the first S / D structure to form the first replacement silicide layer. A second dielectric can be deposited to cover the first replacement silicide and the first S / D structure. Then a first interconnect opening can be formed in the second dielectric, where the first interconnect opening exposes the first replacement silicide layer. The first interconnect opening can be filled with a first replacement interconnect structure, where the first replacement interconnect structure can be made of a third dielectric.

[0039] In some embodiments, before forming the second S / D structure at the first end of the second channel structure, the first replacement interconnect structure in the first interconnect opening can be recessed. Then a first dielectric cap can be formed on the first replacement interconnect structure. The first interconnect opening can be filled with a second dielectric. The second dielectric can be recessed to expose the second channel structure of the second field effect transistor, so that the second S / D structure can be formed at the first end of the second channel structure.

[0040] To form a second replacement silicide layer on the surface of the second S / D structure and a second replacement interconnect structure above the second replacement silicide layer, a first dielectric can be deposited on the surface of the second S / D structure to form the second replacement silicide layer. A second dielectric can be deposited to cover the second replacement silicide layer and the second S / D structure of the second field effect transistor. Then a second interconnect opening can be formed in the second dielectric, where the second interconnect opening exposes the second replacement silicide layer. Then, the second interconnect opening can be filled with a second replacement interconnect structure, where the second replacement interconnect structure can be made of a third dielectric.

[0041] In some embodiments, after forming the second replacement interconnect structure above the second replacement silicide layer, a portion of the second replacement interconnect structure can be removed, thereby forming a space above the second replacement interconnect structure, and the space is further located in the second dielectric. A second dielectric cap can be formed on the second replacement interconnect structure, and the space can be refilled with a second dielectric.

[0042] In some embodiments, to remove the first replacement silicide layer, the first replacement interconnect structure, the second replacement silicide layer, and the second replacement interconnect structure, an interlayer dielectric (ILD) may be formed over the second dielectric. A patterned mask may be formed over the ILD. An etching process may be performed to form a first via opening and a second via opening based on the patterned mask. The first via opening and the second via opening extend into the second dielectric and the ILD to expose the first replacement interconnect structure and the second replacement interconnect structure, respectively. Then, an etching process may be performed to remove the first replacement interconnect structure in the first interconnect opening, the first replacement silicide layer, the second replacement interconnect structure in the second interconnect opening, and the second replacement silicide layer.

[0043] In some embodiments, after forming a first silicide layer on the first S / D structure and a second silicide layer on the second S / D structure, a first trench opening and a second trench opening may be formed in the ILD based on a patterned mask. The first trench opening may be connected to the first via opening, and the second trench opening may be connected to the second via opening. Conductive material may be deposited in the first trench opening, the second trench opening, the first via opening, the second via opening, the first interconnect opening, and the second interconnect opening to form a first metal line in the first metal opening, a second metal line in the second metal opening, a first via in the first via opening, a second via in the second via opening, a first interconnect structure in the first interconnect opening, and a second interconnect structure in the second interconnect opening, respectively. Thus, the first metal line, the first via, and the first interconnect structure are connected together. The second metal line, the second via, and the second interconnect structure are connected together. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0045] Figure 1A is a cross-sectional view of a standard contact according to some embodiments.

[0046] Figure 1B is a cross-sectional view of a first wrap-around contact according to some embodiments.

[0047] Figure 1C is a cross-sectional view of a second wrap-around contact according to some embodiments.

[0048] Figure 2 is a perspective view of an exemplary complementary field-effect transistor (CFET) according to some embodiments.

[0049] Figures 3 to 45 is a perspective view of various exemplary intermediate steps in fabricating an exemplary CFET according to some embodiments. DETAILED DESCRIPTION

[0050] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Numerous specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. Additionally, the present disclosure may reuse reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and in itself does not indicate a relationship between the various embodiments and / or configurations being discussed.

[0051] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to one or more other elements or features as illustrated in the figures. In addition to the orientation depicted in the figures, spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and accordingly, the spatially relative descriptors used herein may be interpreted in a similar manner.

[0052] References to "an embodiment" or "embodiments" in the present specification throughout mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment, but does not imply that it exists in every embodiment. Thus, the phrase "in an embodiment" as used throughout this specification does not necessarily refer to the same embodiment. Additionally, in one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0053] The techniques herein include integrated methods for forming devices with silicide contacts. In the disclosed techniques, high-temperature processing can be maintained to preserve the desired power and performance of the devices, while 3D logic architectures such as CFETs or even conventional FINFETs or GAA devices can be supported by using wrap-around contacts. One embodiment includes using reverse or replacement silicide and reverse metal interconnect processes, where the replacement silicide and the replacement interconnect metal are substituted into the integration flow and then removed and replaced with the final silicide and interconnect metal after completion of FEOL (front-end-of-line) annealing.

[0054] The replacement silicide process herein can be used in many different fabrication processes. For applications of complementary FET devices, Figure 2A cross-sectional substrate segment up to the M0 metal track along the axis of the source, drain, and interconnect structure is shown. It can be understood that similar applications also apply to other devices such as FINFETs and gate-all-around (GAA) devices. The examples herein may mainly focus on the more complex cases applied to 3D logic. Applications to other devices should be readily understandable. In addition, 2D devices have fewer obstacles in implementing high-temperature processing, which is required for current devices to meet the necessary power and performance requirements.

[0055] Figure 2 is a perspective view of an exemplary complementary FET (CFET) device 200 formed according to some embodiments of the present disclosure based on replacement silicide and replacement interconnect methods. As Figure 2 shown, the CFET device 200 may have a plurality of silicon fins protruding from a substrate (not shown). For example, three fins 202a - 202c are included in FIG. 1. A plurality of power rails 204a - 204c may be disposed on the substrate and located between the fins 202. In some embodiments, the power rails 204 may further extend along the X direction of the substrate. The power rails 204 are buried in the bottom portion of the CFET device 200 and are configured to provide an operating voltage (e.g., Vdd or GND) to the CFET device 200. A plurality of first dielectric caps 206a - 206d are located on the power rails 204 and serve as isolation layers. Additionally, an insulating layer 208 may be located between the power rails 204 and the fins 202.

[0056] Still referring to Figure 2, a plurality of first source / drain (S / D) structures 212a - 212c are located above the fin 202. Each of the first S / D structures 212 can be located above a corresponding fin 202. For example, the first S / D structure 212a is located above the fin 202a. The first S / D structures 212 are arranged at the first end of a first channel structure (not shown). The first channel structure is located above the fin 202 and is aligned with the fin 202 in the Z direction. Each of the first channel structures can include one or more first nanosheets or first nanowires extending in the X direction. The first nanosheets or first nanowires are stacked above the fin 202 and spaced apart from each other. Additionally, a plurality of first silicide layers 214a - 214c are located above the top surface of the first S / D structures 212. The first silicide layer 214 further surrounds the first S / D structures 212 to improve the conductivity of the first S / D structures 212. A plurality of first local interconnect structures (also referred to as first interconnect structures) 218a - 218c are located above the first silicide layer 214 to be electrically coupled to the first S / D structures 212 through the first silicide layer 214. For example, the first local interconnect structure 118a is coupled to the first S / D structure 212a through the first silicide layer 214a. Additionally, one or more of the first local interconnect structures 218 can be further connected to the power rail 204. For example, the first local interconnect structure 218a can extend through the first dielectric cap 206 and be further connected to the power rail 204a.

[0057] The CFET device 200 can have a plurality of second dielectric caps 220a - 220c located on the first local interconnect structures 218 and serving as insulating layers. A plurality of second S / D structures 224a - 224c are located above the second dielectric caps 220. The second S / D structures 224 are aligned with the first S / D structures 212 in the Z direction. For example, the first S / D structure 212a is aligned with the second S / D structure 224a in the Z direction. The second S / D structures 224 are arranged at the first end of a second channel structure (not shown). The second channel structure is located above the fin 202 and the first channel structure. The fin 202, the first channel structure, and the second channel structure are aligned in the Z direction. Additionally, each of the second channel structures can include one or more second nanosheets or second nanowires extending in the X direction. A plurality of second silicide layers 226a - 226c are located above the top surface of the second S / D structures 224. The second silicide layer 226 further surrounds the second S / D structures 224 to improve the conductivity of the second S / D structures 224.

[0058] Still referring to Figure 2, the CFET device 200 may have a plurality of second local interconnect structures (also referred to as second interconnect structures) 228a - 228c, which are located above the second silicide layer 226, such that the second local interconnect structures 228 are coupled to the second S / D structures 224 through the second silicide layer 226. In some embodiments, one or more of the second local interconnect structures 228 may be further connected to the power rails 204. For example, the second local interconnect structure 228a may extend through the first dielectric cap 206b and be connected to the power rail 204b. A plurality of third dielectric caps 230a - 230c may be located on the second local interconnect structures 228 and serve as insulating layers. The CFET device 200 may also have a plurality of vias 232a - 232e extending into the first interlayer dielectric (ILD) 210, where the first S / D structures 212, the second S / D structures 224, the first local interconnect structures 218, and the second local interconnect structures 228 are located in the first ILD 210. The vias 232 may further extend through the second dielectric cap 220 and the third dielectric cap 230 to connect to the first local interconnect structures 218 and the second local interconnect structures 228. For example, the via 232a may extend into the first ILD 210, extend through the second dielectric cap 220a, and be connected to the first local interconnect structure 218a. The via 232e may extend through the third dielectric cap 230c to connect to the second local interconnect structure 228c.

[0059] In the CFET device 200, a plurality of isolation structures (also referred to as dielectric separations or insulating layers) 234a - 234d may be formed above the vias 232. For example, the isolation structure 234a is located above the via 232a. The isolation structure 234b is located above the via 232b. Further, a plurality of metal lines 238 may be located above the isolation structures 234 or the vias 232. The metal lines 238 may be formed in the second ILD 236, where the second ILD 236 may be located above the first ILD 210. In an embodiment, one or more of the metal lines 238 may be coupled to the first local interconnect structures 218 or the second local interconnect structures 228. For example, the metal line 238e is coupled to the second local interconnect structure 228c through the via 232e. In another embodiment, the isolation structures 234 may be arranged between the metal lines 238 and the first local interconnect structures 218 or between the metal lines 238 and the second local interconnect structures 228. Thus, the metal lines 238 are not connected to the first local interconnect structures 218 or the second local interconnect structures 228. For example, the isolation structure 234a is located between the metal line 238a and the via 232a, and thus, the first local interconnect structure 218a is not connected to the metal line 238a.

[0060] Still referring to Figure 2, a plurality of spacer structures 222a - 222d can be disposed in the first ILD 210. The spacer structures 222 can be located on the insulating layer 208 and extend in the X direction. The spacer structures 222 can be configured to separate the first S / D structure 212 and the second S / D structure 224 into a plurality of pairs. For example, the first S / D structure 212a and the second S / D structure 224a can be located between the spacer structures 222a and 222b. The first S / D structure 212b and the second S / D structure 224b can be located between the spacer structures 222b and 222c.

[0061] In an embodiment, the first S / D structure can be the S / D structure of an N-type transistor, and the second S / D structure can be the S / D structure of a P-type transistor. Thus, the first S / D structure can be made of silicon doped with phosphorus, and the second S / D structure can be made of silicon doped with boron. In another embodiment, the first S / D structure can be the S / D structure of a P-type transistor, and the second S / D structure can be the S / D structure of an N-type transistor. Thus, the first S / D structure can be made of silicon doped with boron, and the second S / D structure can be made of silicon doped with phosphorus. In Figure 2 an exemplary embodiment, the first S / D structure 212 is the S / D structure of a P-type transistor, and the second S / D structure 224 is the S / D structure of an N-type transistor.

[0062] In some embodiments, the power rail 204, the first local interconnect structure 218, the second local interconnect structure 228, the vias 232, the metal lines 238 can include W, Co, Ru, Al, Cu, or other conductive materials. The first dielectric capping layer 206, the second dielectric capping layer 220, the third dielectric capping layer 230, the isolation structure 234, and the spacer structures 222a - 222d can include SiN, SiCN, AlO, or other suitable dielectric materials. The first ILD 210 and the second ILD 236 can include SiO, TEOS, BPSG, PSG, USG, low-k dielectrics, or other suitable dielectric materials. The first silicide layer 214 and the second silicide layer 226 can include ruthenium silicide, titanium silicide, or other suitable silicides. In some embodiments, a barrier layer or liner can be formed between the first local interconnect structure 218 and the first silicide layer 214. A barrier layer or liner can also be formed between the second local interconnect structure 228 and the second silicide layer 226. The barrier layer or liner can include TiN, TaN, Ti, Ta, or other suitable barriers.

[0063] In Figure 2In an exemplary embodiment, the power rail 204, the first local interconnect structure 218, the second local interconnect structure 228, the vias 232, and the metal lines 238 are made of Ru. The first dielectric capping layer 206, the second dielectric capping layer 220, the third dielectric capping layer 230, and the isolation structure 234 are made of AlO. The insulating layer 208 and the first ILD 210 are made of SiO. The spacer structure 222 is made of SiN, and the second ILD 236 is made of a low-k dielectric. The first silicide layer 214 is made of ruthenium silicide, and the second silicide layer 226 is made of titanium silicide. The barrier layer or liner is made of TiN.

[0064] In the CFET device 200, a replacement silicidation process has been applied to form the first silicide layer 214 and the second silicide layer 226. In the replacement silicidation process, a first replacement silicide layer and a second replacement silicide layer can be formed first. Then, an RMG module can be applied to form the metal gate. A heat treatment can be applied to anneal the substrate. The first replacement silicide layer and the second replacement silicide layer can then be replaced with the first silicide layer 214 and the second silicide layer 226. An exemplary manufacturing process can be in Figures 3 to 45 shown.

[0065] Embodiments of the present disclosure include a combination of reverse metal contacts and a silicidation process. In this process, a temporary or sacrificial or replacement or alternative silicide material is selectively or non-selectively deposited over the source and drain device structures. The replacement material (alternative silicide material) can be a dielectric that has an etch selectivity with respect to the pre-metal dielectric (e.g., the first ILD 210) that includes the source and drain structures (e.g., the first S / D structure 212 or the second S / D structure 224). The replacement material can be used as an etch stop layer to protect the source and drain contacts (e.g., the first S / D structure 212 or the second S / D structure 224) when the pre-metal dielectric is opened in a typical via-to-drain process. During heat treatments such as reliability annealing, source and drain device formation within the upper device, dopant activation annealing, and silicon pre-clean annealing, the replacement material is used to efficiently and effectively prevent the diffusion of silicon, silicon germanium, phosphorus, boron, or other doping substances. The replacement material is selected not to interact with the silicon and / or silicon germanium source and drain contacts during the above front-end-of-line (FEOL) thermal annealing process. The replacement material is selected to be easily removable after the high heat treatment is completed. Thus, a clean tunnel or space can exist around the surface area of the source and drain contacts, and metal silicide can subsequently be grown thereon. A replacement material of sufficient thickness can be formed such that an isotropic etch process can remove (easily remove) all of the replacement silicide material from the surface of the source and drain contacts and be selective to the pre-metal dielectric so as to produce a uniform channel after removing the replacement silicide material. Example alternative silicide materials include, but are not limited to, silicon nitride, SiCN, SiC, etc.

[0066] Embodiments include forming a bottom local interconnect structure (e.g., the first local interconnect 218) after forming a replacement silicide. The bottom local interconnect can be considered a reverse / fictitious interconnect or reverse / fictitious contact composed of a replacement material. The replacement material (or replacement interconnect material) can withstand the high-temperature annealing treatment performed later in the RMG process flow. The bottom local interconnect structure itself maintains its structural characteristics, except for the material composition in the final device. This process and nomenclature are similar to replacement metal gates, where polysilicon or amorphous silicon is used to define the metal gate structure, and after the high-temperature FEOL annealing is completed, the polysilicon or amorphous silicon material is removed and subsequently replaced with a work function metal. In this process, the physical gate structure remains the same.

[0067] The replacement interconnect material is selected to have chemical and / or physical properties sufficient to withstand the high-temperature annealing operations in the RMG module and during the above device formation. The replacement interconnect material benefits from having excellent etch selectivity to both the replacement silicide material (for integration) and the pre-metal dielectric material (which may contain the replacement interconnect or replacement contact structure). The replacement interconnect material can be relatively easily removed by isotropic gas etching, chemical wet etching, or isotropic direct plasma or remote plasma etching processes.

[0068] The replacement interconnect material is such that a selectively deposited or grown dielectric film or cap can be formed above the upper surface of the intended replacement interconnect structure to act as a dielectric separation between the upper (or second) interconnect structure and the lower (or first) interconnect structure. The replacement interconnect material also has etch selectivity to the dielectric cap material deposited or grown above the local interconnect structure, such that the replacement interconnect material can be completely removed without causing any damage or deformation to the dielectric separation between the upper and lower interconnect structures. The replacement interconnect material is selected such that it can also not interact with the replacement silicide material, the pre-metal dielectric, or the dielectric cap (e.g., the second dielectric cap 220) used to isolate the upper and lower devices during the thermal annealing process.

[0069] After deposition into the interconnect patterned trenches within the pre-metal dielectric, the replacement interconnect material can be cyclically etched or recessed so that a uniform top surface of the interconnect structure can be formed. In such an approach, it is also beneficial for the replacement interconnect material to have chemical mechanical polishing (CMP) characteristics such that a planar film can be created prior to recessing within the interconnect trenches. Alternatively, an alternative to the CMP characteristics can be a superconformal deposition process, where a very planar top surface or an excessive portion of the replacement interconnect material can be deposited through a subsequent planarization that can be by CMP or recess etching operations. The replacement interconnect can be selectively deposited around or bottom-filled into the interconnect trenches over the reverse silicide material. Example materials for replacement interconnects include polysilicon and amorphous silicon, among others.

[0070] Embodiments include methods of creating a dielectric barrier (e.g., a second dielectric cap 220) having etch selectivity over the top of a bottom replacement local interconnect structure. Preferably, this dielectric isolation is performed by selectively depositing a dielectric directly on the surface of the replacement interconnect material. If the replacement dielectric material is composed of polysilicon or amorphous silicon, an alternative is to grow a dielectric over the top of the replacement local interconnect structure. The formation of this dielectric material can provide the benefit of good etch selectivity to the pre-metal dielectric material encapsulating the contacts and the local interconnect structure. It is also beneficial for the dielectric (e.g., the second dielectric cap 220) formed over the bottom replacement local interconnect to have a sufficiently low dielectric constant to maintain reasonable capacitance and prevent capacitive coupling between the upper and lower (or bottom) devices. For the case of selective deposition over polysilicon or amorphous silicon replacement local interconnects, the dielectric material can be a metal oxide such as alumina.

[0071] The process for creating replacement interconnects and a dielectric barrier with etch selectivity can be repeated sequentially for each stacked device, such as during the fabrication of a vertical stack of all-around gate channel devices or other 3D logic vertical stacks.

[0072] Embodiments include isotropically removing (pulling away) the replacement local interconnect material and the replacement silicide material after the RMG module and high temperature treatment are completed. For example, during the formation of the M0 trenches prior to metallization, all upper and lower replacement local interconnect structures can be opened. Since M0 extends perpendicular to the local interconnect structures, all local interconnect structures can be accessed through the M0 tracks. During the patterning of the TiN hard mask, for example, over a flat surface such as a contact area, the via-to-drain structures connected to the replacement local interconnect structures can be patterned regardless of whether the local interconnect is in the upper or lower device of a complementary FET device.

[0073] The via-to-drain structure can expose the replacement material in the local interconnect structure. Isotropic etching processes such as Tokyo Electron's vapor-phase CERTAS etching, chemical wet etching, or direct or remote plasma isotropic etching can be used to remove the replacement material in the local interconnect structure. The replacement material (e.g., polysilicon) in the local interconnect structure can be removed, while the pre-metal dielectric (e.g., silicon oxide) and the replacement silicide material (e.g., SiCN) can be minimally affected during the removal process. Selectivity is very important because any etching of the replacement silicide at this time may cause unwanted etching of the source and drain epitaxy.

[0074] Since the M0 track extends perpendicular to the local interconnect structure, the via-to-drain structure can be self-aligned. For example, the Y orientation of the via-to-drain structure is formed / controlled by the size of the M0 trench, while the X direction of the via-to-drain structure is formed / controlled by the size of the local interconnect structure. This self-alignment provides a means to form a via-to-drain structure that is over-sized, enabling complete removal of the replacement interconnect and replacement silicide materials.

[0075] Some embodiments may include using a buried power rail (BRP) (e.g., power rail 204 formed beneath the channel material in bulk silicon) in the device design. In some cases, the buried power rail may have been formed and metallized with a high-refractive-index metal such as ruthenium before forming any reverse or replacement local interconnect or silicide structures. This manufacturing flow imposes further etching selectivity limitations on the selection of replacement local interconnects during the formation of the local interconnect structure because the local interconnect structure can be coupled to the power rail through vias. In this case, the interface between the local interconnect structure and the power rail is preferably ruthenium or other types of metal in the BRP structure, with polysilicon as the replacement interconnect material. It should be noted that there should also be a high enough etching selectivity such that any etching of the replacement interconnect material (e.g., polysilicon) does not etch the formed buried power rail (e.g., ruthenium). This is typically challenging because similar etching chemistries will be used to etch polysilicon and metal. However, vapor-phase etching (such as using Tokyo Electron CERTAS etching) can be used to achieve extremely high etching selectivity between silicon and metal. Alternatively, other etching apparatuses using chemical wet etching and direct or remote plasmas can meet this high selectivity, depending on the chemistry used to etch the replacement interconnect material.

[0076] Embodiments can include connecting all local interconnect structures using the same access point established by forming a via to the drain structure. After removing the replacement local interconnect material by an etching process, the etching process is switched to remove the replacement silicide material on the source and drain contact surfaces. The height or thickness of the replacement silicide is produced such that the replacement silicide material (e.g., SiCN) can be easily and completely removed from the contact surface, i.e., a thickness sufficient to be removed without causing any damage or deformation to the contact itself. The etching selectivity is such that the pre-metal dielectric is not etched (or not significantly etched). Removing the replacement silicide material does not damage the source and drain contacts. The initial height or thickness of the reverse silicide material is sufficient to allow complete removal of the material during an isotropic etching process.

[0077] Embodiments include a method of forming self-aligned silicide in the space left by the replacement silicide. The self-aligned silicide can be performed by selective deposition, atomic layer deposition (ALD), or chemical vapor deposition (CVD), followed by wet removal or plasma etching of the unreacted metal from the silicide material. The deposition can fill the relatively small channels formed by removing the replacement silicide. Prior to the silicide formation process, an in-situ oxide cleaning process such as COR (chemical oxide removal) manufactured by Tokyo Electron can be incorporated to pre-clean the epitaxial surface. If a common silicide is to be used, the mask step can be done in one go for complementary FET devices. Otherwise, multiple mask steps can be used to produce different silicide materials over NMOS and PMOS sources and drains.

[0078] Embodiments include filling the local interconnect structures with a final high-conductivity metal and any required liner or adhesion layer. The deposition of the metal layer and the adhesion layer must be conformal such that the body of the local interconnect structure can be filled without first narrowing the via to the drain structure. It should be noted that the final higher-conductivity metal fill can not only fill the local interconnect structures, but also fill the via to the drain structure and the M0 tracks. The benefit of the fill process is that for complementary devices and other 3D logic devices, the local interconnect high-conductivity metal fill can be done in one go. Typically, in a CFET process, the fill process is performed through multiple integrated steps. It should be understood that the metals desired for cutting-edge logic are usually expensive, and keeping the deposition in a single unit process step can also be significantly cost-effective. Thus, in addition to correcting the thermal budget associated with the manufacturing process, the fill process can be used as a cost-saving measure.

[0079] Another process step may include isolating metallized interconnects for connection to any M0 tracks, such as interconnects that tap buried power rails or interconnects that do not connect upward to the back-end-of-line (BEOL). In cases where it is not desired to actually connect the interconnect structure to the M0 tracks, replacing the silicide and interconnect processes require access points at the M0 tracks. For these cases, a dielectric separation may be formed between the interconnect structure and the M0 tracks. In this way, after the final interconnect / via-to-drain / M0 metallization, an additional mask step is used to form a "contact" or "opening" pattern.

[0080] Some metals, such as ruthenium, have the advantage of being able to be etched well in an anisotropic etching process while having relatively high conductivity. The advantages of these properties enable ruthenium to be recessed only for via-to-drain structures that are selected to be electrically isolated based on the cell layout. When using isotropic etching, there is a risk that the isotropic etching may extend to adjacent via-to-drain structures that still require a connection between the local interconnect and the M0 tracks. After the metal has been well recessed within the desired via-to-drain structure, a dielectric may be selectively deposited, grown, or patterned by using a deposition and subsequent etch-back process to create the desired dielectric separation. The material selection in this disclosure may be a material having a low enough dielectric constant. For example, aluminum oxide (AlO) may be selected to form the dielectric film because AlO can be selectively deposited onto the recessed ruthenium. Any dielectric deposited on top of the bulk fill metal above the M0 tracks (referred to as the over-deposited portion) may be removed by chemical mechanical polishing or other methods. After depositing the dielectric separation, it is desirable to refill the M0 track regions from which the highly conductive metal has been removed. This can be achieved by a second metal deposition and subsequent CMP or etch-back process to reform the M0 tracks.

[0081] In some embodiments, the reverse interconnect and reverse silicide processes herein may be incorporated into FINFETs, gate-all-around (GAA), and stacked 3D logic devices such as complementary FETs. To facilitate the description of the embodiments herein, the example description focuses on the CFET as the most complex implementation. This is not restrictive, and the embodiments herein can be transferred to conventional wrap-around contact processes for FINFET or GAA devices.

[0082] An example process flow for a complementary FET device composed of vertically stacked nanoscale channels (nanowires or nanosheets) may be referred to Figures 3 to 45 for description.

[0083] In Figure 3 a semiconductor structure 300 may be provided. As Figure 3 shown, the semiconductor structure 300 may have a plurality of silicon fins protruding from a substrate (not shown). For example, Figure 3It includes three fins 202a - 202c. A plurality of power rails 204a - 204c can be arranged on the substrate and located between the fins 202. In some embodiments, the power rails 204 can further extend along the X direction of the substrate. The power rails 204 are buried in the bottom portion of the semiconductor structure 300 and are configured to provide an operating voltage (e.g., Vdd or GND). A plurality of first dielectric caps 206a - 206d are located on the power rails 204 and serve as isolation layers. Additionally, an insulating layer 208 can be located between the power rails 204 and the fins 202. Still referring to Figure 3 , a plurality of first channel structures 242a - 242c can be located above the fins 202. Each of the first channel structures 242 can be arranged above a corresponding fin 202. For example, the first channel structure 242a is located above the fin 202a. The first channel structures 242 are further aligned with the fins 202 along the Z direction. Each of the first channel structures 242 can include one or more first nanosheets or first nanowires extending along the X direction. The first nanosheets or nanowires can be stacked above the fins 202 and spaced apart from each other. In Figure 3 's embodiment, the first channel structure 242 includes two first nanosheets. The first channel structures 242 can be buried in a hard mask stack 244, which includes an underlayer 247 and a capping layer 248. In some embodiments, the underlayer 247 can be made of carbon, and the capping layer 248 can be made of SiN.

[0084] The sidewall spacer method can be used to form the covering spacers 246 to block Figure 3 the upper (or second) device nanosheets (or second channel structures), not shown, and open the lower (or first or bottom) device nanosheets (or first channel structures) 242. As Figure 3 shown, the first channel structures 242 can be exposed in the low - k gate spacers 240 and located in a plane (e.g., Figure 3 the Y - Z plane in

[0085] Figure 4 parallel / aligned with the intended contact and interconnect regions). By performing an in - situ high - temperature annealing or in - situ chemical oxide removal (COR) gas - phase etching process immediately before the source and drain epitaxial growth, the exposed silicon nanosheets (or first channel structures) 242 of the bottom device (e.g., P - type transistor) can be pre - cleaned. The exposed nanosheets (or first channel structures) 242 can be isotropically recessed within the low - k gate spacers 240 to reduce the gate extension of the channel structures. Figure 4In an exemplary embodiment, the bottom device may be a PMOS device. Thus, the first S / D structure 212 is composed of silicon germanium with in-situ doped boron. The source and drain contacts (or the first source / drain structure) 212 may be etched after formation to fit any desired minimum size specification so as to fit within the cell height of the proposed standard cell design. It should be noted that the bottom device including the first S / D structure 212 may be an NMOS device or a PMOS device, depending on factors such as circuit design and the number of connections between PMOS and NMOS to the upper metal tracks, thermal considerations of in-situ doping, etc.

[0086] Still referring to Figure 4 , the first S / D structure 212 of the bottom device may be located at the first end of the first channel structure 242, and these first ends are located on the first side 244a of the hard mask stack 244. Additionally, a second S / D structure (not shown) of the bottom device may be located at the second end of the first channel structure 242, and these second ends are located on the second side 244b of the hard mask stack 244. The first channel structure of the bottom device is correspondingly arranged between the first S / D structure 212 and the second S / D structure and is further embedded in the hard mask stack 244.

[0087] Figure 5 It shows the selective deposition or isotropic deposition of replacement silicide material around the surface of the source and drain contact structure (or the first S / D structure) 212 to form a plurality of first replacement silicide layers 250. The first replacement silicide layers 250 may be arranged on the surface of the first S / D structure 212. The preferred method herein is to achieve selective deposition of replacement silicide directly only above the surface of the source and drain contacts.

[0088] In Figure 6 , the capping spacers 246 are removed from the upper device (or the second device) to expose the silicon nanosheets (or the second channel structure) 252a - 252c of the upper complementary device. As Figure 6 shown, the second channel structure 252 is located above the fin 202 and the first S / D structure 212. Additionally, the second channel structure 252, the fin 202, and the first S / D structure 212 are aligned with each other in the Z direction. For example, the second channel structure 252a, the first S / D structure 212a, and the fin 202a are aligned in the Z direction. Each of the second channel structures 252 may include one or more nanos.

[0089] Via an in-situ high-temperature annealing or in-situ chemical oxide removal (COR) vapor etching process, the exposed silicon nanosheets (or second channel structure) 252 at the upper device can be pre-cleaned. The pre-cleaning process can be completed immediately before the source and drain epitaxial growth. The exposed nanosheets (or second channel structure) can be isotropically recessed within the low-k gate spacer 240 to reduce the gate extension of the channel.

[0090] In Figure 7 , a pre-metal dielectric 210 such as silicon oxide is deposited in the source and drain planes (e.g., the space between the hard mask stacks 244). The pre-metal dielectric 210 can be used as the first ILD 210, where the interconnect trench structure for the bottom device can be initially formed in subsequent manufacturing steps.

[0091] In Figure 8 , a hard mask 254 can be deposited over the pre-metal dielectric 210 and patterned using a lower local interconnect structure template. The lower local interconnect structure template can ultimately be transferred down through the pre-metal dielectric 210.

[0092] In Figure 9 , the via-to-rail opening 256 can be patterned by an etching process and partially transferred down into the pre-metal dielectric 210. The via-to-rail opening can form a via-to-rail structure in subsequent manufacturing steps. The via-to-rail structure can connect the bottom interconnect (or first local interconnect structure) to the buried power rail 204. In Figure 9 's exemplary embodiment, the via-to-rail opening and interconnect patterning for forming the bottom interconnect (or first interconnect structure) can be formed by a dual-damascene process. This dual-damascene process is similar to the dual-damascene process during BEOL metallization.

[0093] In Figure 10 , the lower device interconnect pattern is transferred down through the pre-metal dielectric 210, where first interconnect trenches 258a - 258c can be formed within the pre-metal dielectric 210 to expose the first S / D structure 212 and the replacement silicide (or first alternative silicide layer) 250, while the bottom of the via-to-rail opening 256 can stop at the first dielectric capping 206 of the buried power rail 204. For example, the first interconnect trench 258a can expose the first S / D structure 212a and the first alternative silicide layer 250, and the bottom of the via-to-rail opening 256a can stop at the first dielectric capping 206a of the buried power rail 204a.

[0094] In Figure 11In [the structure], the first dielectric cap 206 over the buried power rail 204 can be opened by an etching process. Considering that the etching chemistry used for anisotropic etching of the first dielectric cap 206 made of metal oxide is similar to the etching chemistry commonly used for etching silicon, the replacement silicide (or the first replacement silicide layer) 250 can be used to protect the source and drain epitaxy (or the first S / D structure) 212 from any damage during the etching process.

[0095] In Figure 12 [the structure], the first interconnect trench 258 and the via-to-rail opening 256 are then filled with a replacement interconnect material 260, which can be polysilicon or amorphous silicon in the Figure 12 embodiments. The replacement interconnect material 260 can be conformally filled and CMP planarized by using a nitride cap (e.g., a capping layer) 248 over the dummy gate as an effective and convenient etch stop layer (ESL). Alternatively, the replacement interconnect material 260 can be conformally "super-filled", where the uniformity of the excess portion of the film is sufficient to allow isotropic etch recessing, or the material can be bottom-filled by a unique capability available from Tokyo Electron Tools.

[0096] In Figure 13 [the structure], the replacement interconnect material 260 can then be isotropically etched recessed to form a plurality of first replacement interconnect structures 262a - 262c having a desired height. Thus, the first interconnect trenches 258a - 258c can be exposed. As Figure 13 shown, the first replacement interconnect structure 262a is located over the first replacement silicide layer 250 and the first S / D structure 212a, and is further connected to the power rail 204a. The first replacement interconnect structure 262b is located over the first replacement silicide layer 250 and the first S / D structure 212b, and is further connected to the power rail 204b. The first replacement interconnect structure 262c is located over the first replacement silicide layer 250 and the first S / D structure 212c. For the example cases of polysilicon or amorphous silicon, various etch hardware and chemistries with excellent selectivity to the pre-metal dielectric, low-k gate spacers, and the expected replacement silicide material can be used for this process.

[0097] In Figure 14In , a plurality of second dielectric caps 220a - 220c are formed above the top surface of the replacement interconnect structure (or first alternative interconnect structure) 262a - 262c. For example, the second dielectric cap 220a is located above the top surface of the first alternative interconnect structure 262a. The second dielectric cap 220b is located above the top surface of the first alternative interconnect structure 262b. The second dielectric cap 220c is located above the top surface of the first alternative interconnect structure 262c. The second dielectric caps 220a - 220c can be used for a variety of applications, including maintaining a fixed minimum dielectric separation between the upper device and the lower device through any self - alignment formation process of the interconnect structure to provide a "ceiling" for the replacement interconnect structure when removing the replacement material and replacing it with a highly conductive metal.

[0098] In Figure 15 , the pre - metallization dielectric 210 can then be used to fill the first interconnect trenches 258a - 258c and then be CMP planarized by using silicon nitride (e.g., capping layer) 248 above the dummy gate as a CMP stop layer to provide a flat surface.

[0099] In Figure 16 , the pre - metallization dielectric 210 is then etched anisotropically and recessed downward until the second channel structure 252 of the upper device is exposed. It should be noted that when the pre - metallization dielectric 210 is recessed, the low - k gate spacer 240 is also exposed. The second dielectric cap 220 above the top surface of the bottom replacement interconnect structure (or first alternative interconnect structure) 262 can be used as an etch stop point for the recessing of the silicon oxide film (e.g., pre - metallization dielectric) 210.

[0100] Figure 17 shows the formation of the upper source and drain contacts (or second S / D structures) 224a - 224c through an in - situ doped epitaxial growth process. In Figure 17 's exemplary embodiment, the upper (or second) device is an NMOS device, and the second S / D structure is composed of silicon with in - situ doped phosphorus. The source and drain contacts (or second S / D structures) 224a - 224c can be etched after formation to fit any desired minimum size specification in order to fit within the cell height of the proposed standard cell design. The bottom device can be NMOS or PMOS, and the choice of which one is used as the bottom device depends on the designer and factors such as the number of connections between PMOS and NMOS to the upper metal tracks, thermal considerations of in - situ doping, etc.

[0101] In Figure 18In, a replacement silicide material is selectively deposited or isotropically deposited around the surface of the second S / D structure 224 to form a plurality of second replacement silicide layers 264. Preferably, the deposition of the replacement silicide material is a selective deposition process for forming the second replacement silicide layer 264 on the surface of the second S / D structure 224.

[0102] In Figure 19 a pre-metal dielectric 210, such as silicon oxide, is redeposited within the source and drain planes (e.g., the space between the hard mask stacks). The pre-metal dielectric can be used as the first ILD 210, where the interconnect trench structures for the bottom and upper devices can be initially formed in subsequent manufacturing steps.

[0103] In Figure 20 a hard mask 265 can be deposited over the pre-metal dielectric 210 and patterned using an upper local interconnect structure template that can ultimately be transferred down through the pre-metal dielectric 210.

[0104] In Figure 21 a via-to-track opening 266 can be patterned by an etching process and partially transferred down into the pre-metal dielectric 210. The via-to-track opening 266 can form a via-to-track structure in subsequent manufacturing steps. The via-to-track structure can connect the upper interconnect (or the second local interconnect structure) to the buried power rail 204. In Figure 21 an exemplary embodiment of, the via-to-track opening and interconnect patterning for forming the upper interconnect can be formed by a dual damascene process. The dual damascene process is similar to the dual damascene process during BEOL metallization.

[0105] In Figure 22In [the structure], the upper device interconnect pattern is transferred downward through the pre-metal dielectric 210, where second interconnect trenches 267a - 267c may be formed within the pre-metal dielectric 210 to expose the second S / D structure 224 and the replacement silicide (or second replacement silicide layer) 264, and the bottom of the via-to-rail opening 266 may stop at the first dielectric cap 206 of the buried power rail 204. For example, the second interconnect trench 267a may expose the second S / D structure 224a and the second replacement silicide layer 264, and the bottom of the via-to-rail opening 266 may stop at the first dielectric cap 206b of the buried power rail 204b. In an embodiment, the upper (or second) interconnect structure may be merged with the lower (or first) interconnect structure to serve as the output terminal of an inverter. Thus, the interconnect trenches of the upper interconnect structure for forming the upper device may terminate at the top surface of the second dielectric cap covering the corresponding lower replacement interconnect structure (or first replacement interconnect structure) of the lower interconnect structure. For example, the second interconnect trench 267c may stop at the top surface of the second dielectric cap 220c covering the first replacement interconnect structure 262c.

[0106] In Figure 23 [the structure], the dielectric cap (e.g., the first dielectric cap) 206 over the buried power rail 204 may be opened. Additionally, the second dielectric cap 220c covering the lower replacement interconnect (e.g., the first replacement interconnect structure) 262c may also be opened. The second dielectric cap 220c is opened to form a merged NMOS / PMOS interconnect structure. Considering that the etch chemistries for anisotropically etching the first and second dielectric caps are common with those typically used for etching silicon, the replacement silicide (e.g., the second replacement silicide layer) 264 may be used to protect the source and drain epitaxy (e.g., the second S / D structure) 224 from any damage during etching.

[0107] In Figure 24 [the structure], the second interconnect trenches 267 and the via-to-rail opening 266 are then filled with a replacement interconnect material 268, which may be polysilicon or amorphous silicon in Figure 24 the embodiment. The replacement interconnect material 268 may be conformally filled and CMP planarized by using a nitride cap (e.g., the cap layer 248) as an effective etch stop layer (ESL) over the dummy gate, or the material may be conformally "overfilled" where the uniformity of the excess portion of the film is sufficient to allow isotropic etch recessing, or the material may be bottom-filled using a CVD tool from Tokyo Electron.

[0108] In Figure 25Therein, the replacement interconnect material 268 is then isotropically etched to recess and form a plurality of second replacement interconnect structures 269a - 269c having a desired height. When the replacement interconnect material 268 is recessed, the second interconnect trenches 267a - 267c are correspondingly exposed. When the replacement interconnect material 268 is polysilicon or amorphous silicon, various etching hardware and chemical reagents having excellent selectivity to the pre-metal dielectric 210, the low-k gate spacer 240, and the intended replacement silicide material (e.g., 250 or 264) can be used for this process.

[0109] In Figure 26 therein, a plurality of third dielectric caps 270a - 270c are formed over the top surfaces of the replacement interconnect structures (or second replacement interconnect structures) 269a - 269c. It should be noted that the second replacement interconnect structure 269c merges with the first replacement interconnect structure 262c to serve as the output terminal of the inverter.

[0110] In Figure 27 therein, a pre-metal dielectric 210 such as silicon oxide is deposited in the source and drain planes (e.g., the Y - Z plane) to fill into the second interconnect trenches 267. In subsequent manufacturing steps, the final interconnect structures for the bottom devices and the upper devices can be ultimately formed within the pre-metal dielectric 210.

[0111] In Figure 28 therein, the dummy gate can be replaced with a metal gate (not shown in the cross-sectional plane of Figure 28 ), and a plurality of spacer structures 222a - 222d can be disposed in the first ILD 210. The spacer structures 222 can be located on the insulating layer 208 and extend in the X direction. The spacer structures 222 can be configured to divide the first S / D structures 212 and the second S / D structures 224 into a plurality of pairs. For example, the first S / D structure 212a and the second S / D structure 224a can be located between the spacer structures 222a and 222b. The first S / D structure 212b and the second S / D structure 224b can be located between the spacer structures 222b and 222c.

[0112] The formation of the metal gate may include one or more high-temperature heat treatments applied to the semiconductor structure 300. The formation of the metal gate may include opening a dummy gate structure, pulling away polysilicon or amorphous silicon, removing a protective thermal oxide liner or chemical oxide liner that protects the channel material, depositing or forming an interface layer such as a thermal oxide or chemical oxide over the intended channel material(s), depositing a high-k dielectric film (such as HfO or various HfO) coupled with a dipole forming layer such as LaO and AlO over the interface layer material covering the channel material(s), covering the high-k dielectric with a conductive barrier material such as TiN, performing a high-k reliability anneal or a drive anneal to reduce the formation of charge traps (such a reliability anneal is typically performed in the range of 700 °C to 750 °C), performing a laser spike anneal (LSA) to activate dopants within the source and drain regions (such an anneal is performed in the range of 800 °C to 1250 °C and its duration ranges from sub-milliseconds to whole seconds), continuing with a replacement metal gate (RMG) process in which NMOS and PMOS work function metals are deposited, etched to adjust to set various threshold voltages, and then filled with a highly conductive metal.

[0113] In Figure 29 it, a second ILD 236 may be formed over the first ILD 210, and a hard mask 271 may be formed over the second ILD 236. The hard mask 271 may be patterned with a combined pattern of an intended M0 track structure (e.g., a metal line trench) and an M0 extension (e.g., a via opening), which may provide access to all individual replacement interconnect structures (e.g., the first and second alternative interconnect structures) and replacement silicide structures (e.g., the first and second alternative silicide layers). In addition to a via structure (or via opening) that provides access to an interconnect not electrically connected to the M0 track, the combined pattern includes an intended via-to-drain structure (or via-to-drain opening) that electrically connects the interconnect to the M0 track (or M0 metal line trench).

[0114] In Figure 30 it, the first via-to-drain structures (or via-to-drain openings) 273a - 273b may be patterned by a self-alignment method, in which the pattern for forming the first via-to-drain structures 273a - 273b may be captured within a film 272. The film 272 may be located over a patterned memory film (or hard mask) 271 that includes the M0 track structure and the M0 extension. The first via-to-drain structures 273a - 273b may be etched through the pre-metal dielectric 210, and the metal oxide cap (e.g., the second dielectric cap) 220 over the replacement interconnect (e.g., the first alternative interconnect structure) 262 is anisotropically opened to provide access to the replacement interconnect (e.g., the first alternative interconnect structure) 262 and the replacement silicide material (e.g., the first alternative silicide layer) 250.

[0115] In Figure 31 , in view of the fact that the number of via-to-drain structures is not large and considering that each replacement interconnect and replacement silicide material needs to be initially opened, in some processes, via patterning can be performed in a lithography-etch-lithography-etch scheme (LELE). As Figure 31 shown, LELE can include filling the first via-to-drain structures 273a-273b with a photoresist layer and forming another pattern in the film 272 to form the second via-to-drain structures (or via-to-drain openings) 274a-274b. The second via-to-drain structures 274a-274b can be formed by transferring another pattern in the film 272 to the pre-metal dielectric 210 via an etching process. The etching process can further open the third dielectric capping 270 to expose the second alternative interconnect structure 269.

[0116] In Figure 32 , the filled pattern material (e.g., film 272) can be removed isotropically through a simple ashing step to expose the opened replacement interconnects (e.g., the first and second alternative interconnect structures) and replacement silicide materials (e.g., the first and second alternative silicide layers). As Figure 32 shown, the first via-to-drain structure 273 can open the first alternative interconnect structure and the first alternative silicide layer. The second via-to-drain structure 274 can open the second alternative interconnect structure and the second alternative silicide layer.

[0117] In Figure 33 , the replacement interconnect materials (e.g., the first and second alternative interconnect structures), which will be polysilicon or amorphous silicon in an exemplary embodiment, can be etched isotropically by gas-phase etching such as Tokyo Electron CERTAS, or by wet etching, or by direct or remote plasma isotropic etching. The presence of the replacement silicide materials (e.g., the first and second alternative silicide layers) can prevent the etching or any damage to the source and drain contacts during the removal of the replacement interconnect materials. The benefit of incorporating CERTAS-type etching in the present disclosure is that excellent etch selectivity can be achieved between polycrystalline / amorphous silicon and ruthenium (Ru) as the metal for the buried power rail 204. Generally, both materials (e.g., polycrystalline / amorphous silicon and Ru) are etched using similar etching chemistries, but incorporating CERTAS etching can provide good selectivity between the metal and silicon. When the etching is completed, the first and second interconnect structures are removed. As Figure 33 shown, when the replacement interconnect materials are removed, the first interconnect trench 258 and the second interconnect trench 267 are exposed.

[0118] In Figure 34Once the replacement interconnect material is removed from the actual interconnect structure, the etch chemistry can be changed to selectively and isotropically remove the replacement silicide material (e.g., the first and second replacement silicide layers) while being selective to other dielectric materials present within the semiconductor structure 300. These materials can include pre-metalization dielectrics 210 such as silicon oxide, capping materials such as aluminum oxide (e.g., the second and third dielectric caps) that can be present as the top plate of the interconnect structure, and low-k gate spacers 240 such as SiOC. Once the selective etching is complete, the first and second replacement silicide layers are removed from the first S / D structure 212 and the second S / D structure 224, respectively.

[0119] In Figure 35 it, a silicon pre-clean can be performed on the surfaces of the source and drain epitaxies (e.g., the first S / D structure 212 and the second S / D structure 224) by using a low-temperature COR (chemical oxide removal) etch process provided by Tokyo Electron. Optionally, the etching of the replacement silicide can be performed in situ by depositing and forming the actual silicide material. It should be understood that in Figure 35 the exemplary embodiment of, both the upper device and the lower device use a common silicide material. For cases where different silicide materials are desired in the upper (or NMOS) and lower (or PMOS) devices, the deposition process can be performed in the following order: a first via-to-drain patterning (e.g., via-to-drain structure) 273 can be used to open the first replacement interconnect structure, the replacement interconnect material and the replacement silicide material can be removed only from the first S / D structure, a first silicide material can be deposited on the first S / D structure, and then trenches and the via-to-drain structure can be filled with a material such as spin-on carbon. The process can be repeated for the complementary device (e.g., the upper device) to deposit a second silicide material on the second S / D structure. In Figure 35 the exemplary embodiment of, the silicide material can be completed via a self-aligned silicide process, where metals such as Ti for NMOS devices (or upper devices) and Ru for PMOS devices (or lower devices) can be deposited by ALD or CVD methods, and the unreacted silicide can be removed in a wet etch process.

[0120] In Figure 36 it, an etch process can be performed to transfer the M0 track structure and M0 extension in the hard mask 271 into the low-k dielectric film (e.g., the second ILD) 236 to form a plurality of M0 trenches 275.

[0121] In Figure 37 it, Figure 36The first interconnect trench 258, the second interconnect trench 267, the M0 trench 275, the first via-to-drain structure 273, and the second via-to-drain structure 274 shown can be metallized simultaneously. In some embodiments, a via-to-gate structure (not shown) located above the channel structure can also be metallized together. The metallization process can include filling the first interconnect trench 258, the second interconnect trench 267, the M0 trench 275, and the first via-to-drain structure 273 and the second via-to-drain structure 274 with a highly conductive metal such as Ru. The metallization process can provide some cost benefits for the CFET device because the interconnect structures of the two devices (e.g., the upper device and the lower device) can be metallized at the end instead of forming interconnect structures for the upper device and the lower device separately. As Figure 37 shown, once the metallization process is completed, a first local interconnect structure (or first interconnect structure) 218 can be formed in the first interconnect trench 258, a second local interconnect structure (or second interconnect structure) 228 can be formed in the second interconnect trench 267, vias 232 can be formed in the first via-to-drain structure 273 and the second via-to-drain structure 274, and a metal wire 238 can be formed in the M0 trench 275 in the second ILD 236. Further, an ashing process or an etching process can be applied to remove the hard mask 271.

[0122] In Figure 38 , a certain amount of dielectric separation (or insulating layer) can be formed between the M0 track (or metal wire) and one or more first interconnect structures such that the one or more first interconnect structures are not electrically connected to the M0 track. To form the dielectric separation, an etching process can be applied to remove some portions of the metal wire, and the etching process can further extend into the vias to remove some portions of the vias. A hard mask such as the hard mask 276 can be deposited on the second ILD 236 to serve as a mask layer for the etching process. As Figure 38 shown, the hard mask 276 can have patterns 276a - 276b to expose the metal wires 238a and 238d respectively.

[0123] Figure 39 It is shown that some portions of the metal wire 238a and some portions of the metal wire 238d are removed by the etching process. The etching process further removes a portion of the via 232a and a portion of the via 232d. Thus, a gap 277a can be located above the via 232a to separate the first local interconnect structure 218a from the metal wire 238a. A gap 277b can be located above the via 232d to separate the first interconnect structure 218b from the metal wire 238d.

[0124] In Figure 40In [reference], patterns 278a - 278b can be formed in the hard mask 278 to repeat the process, thereby forming a certain amount of dielectric separation (or insulating layer) that separates one or more second interconnect structures from the metal lines. As Figure 41 shown, the hard mask 278 can have patterns 278a - 278b to expose the metal lines 238b and 238c, respectively. It should be noted that the hard mask 278 can further fill the gap 277.

[0125] In Figure 41 [reference], some portions of the metal line 238b and some portions of the metal line 238c are removed by an etching process. The etching process further removes a part of the via 232b and a part of the via 232c. Thus, a gap 279a can be located above the via 232b to separate the second local interconnect structure 228a from the metal line 238b. A gap 279b can be located above the via 232c to separate the second interconnect structure 228b from the metal line 238c. Further, the hard mask 278 made of spin - on carbon can be removed by an ashing process or an etching process.

[0126] In Figure 42 [reference], selective deposition or CVD filling can be applied to deposit a dielectric material 280 into the semiconductor structure 300. The dielectric material 280 can be filled into the gaps (e.g., gaps 277a - 277b and 279a - 279b) located in the second ILD 236 and further extending into the first ILD 210. In Figure 42 an exemplary embodiment of [reference], the dielectric material 280 can be alumina.

[0127] In Figure 43 [reference], CMP or recess etching of the dielectric material 280 can be performed. The dielectric material 280 remaining in the gaps (e.g., gaps 277a - 277b and 279a - 279b) can effectively become dielectric separations (also referred to as isolation structures or insulating layers) 234a - 234d to disconnect the overlying metal lines from the underlying interconnect structures. For example, the dielectric separation 234a can disconnect the metal line 238a from the first local interconnect structure 218a. The dielectric separation (or isolation structure or insulating layer) 234b can disconnect the metal line 238b from the second local interconnect structure 228a.

[0128] In Figure 44In [the context], the dielectric spacer (also referred to as an isolation structure or insulating layer) 234 can be further recessed by an etching process to remove the portion of the dielectric spacer that is located in the second ILD 236. In some embodiments, the etching process can further remove the portion of the dielectric spacer 234 that is in the first ILD 210. Thus, a plurality of recessed spaces can be formed above the dielectric spacer, and these recessed spaces are located in the first ILD 210. Subsequently, a highly conductive metal applied in Figure 37 can be used to fill these recessed spaces. The remaining dielectric spacer can prevent the need for additional "blocking" or "cutting" of the M0 pattern.

[0129] In Figure 45 , the recessed spaces can be refilled with a highly conductive metal and then CMP planarized or recess etched to produce a clean M0 track pattern. When the CMP or recess etching is completed, the CFET device 200 can be formed. Figure 45 The CFET device 200 shown can have a configuration similar to that of the CFET device 200 shown in Figure 2 . As shown in Figure 45 , the first silicide layer 214 and the second silicide layer 226 can be formed by a replacement process. The replacement process includes: forming a first replacement silicide layer 250 and a second replacement silicide layer 264; performing a heat treatment on the substrate; replacing the first replacement silicide layer 250 with the first silicide layer 214, and replacing the second replacement silicide layer 264 with the second silicide layer 226. Thus, the replacement process enables a high-temperature heat treatment to be performed while still maintaining the properties of the silicide layers.

[0130] The CFET device 200 can also have a dielectric spacer (or insulating layer) located between the metal wires and the interconnect structure to disconnect one or more metal wires from one or more interconnect structures. Thus, correspondingly, there is no need for additional "blocking" or "cutting" of the metal wire pattern.

[0131] In the foregoing description, specific details have been set forth, such as the specific geometry of the processing system and the descriptions of the various components and processes used therein. However, it should be understood that the techniques herein can be practiced in other embodiments that depart from these specific details, and such details are for purposes of explanation rather than limitation. The embodiments disclosed herein have been described with reference to the drawings. Similarly, for purposes of explanation, specific numbers, materials, and configurations have been set forth to provide a thorough understanding. However, the embodiments can be practiced without such specific details. Components having substantially the same functional construction are denoted by similar reference numerals, and thus any redundant description can be omitted.

[0132] Various techniques have been described as a number of discrete operations to assist in understanding the various embodiments. The order of description should not be construed as meaning that these operations are necessarily order-dependent. In fact, these operations need not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0133] As used herein, "substrate" or "target substrate" generally refers to an object to be processed in accordance with the present invention. A substrate may include any material portion or structure of a device (especially a semiconductor or other electronic device), and may be, for example, a base substrate structure (such as a semiconductor wafer, a mask), or a layer (such as a thin film) on or overlying the base substrate structure. Thus, a substrate is not limited to any particular base structure, underlying layer, or overlying layer that is patterned or unpatterned, but is contemplated to include any such layer or base structure, as well as any combination of layers and / or base structures. This description may refer to a particular type of substrate, but this is for illustrative purposes only.

[0134] Those skilled in the art will also understand that many changes may be made to the operations of the above techniques while still achieving the same purpose of the present invention. The scope of this disclosure is intended to encompass these changes. Thus, the foregoing description of embodiments of the present invention is not intended to be limiting. Instead, any limitations of embodiments of the present invention are presented in the appended claims.

Claims

1. A method for forming a semiconductor device, the method comprising: Forming a first source / drain (S / D) structure of a first field-effect transistor on a substrate, the first S / D structure being located at a first end of a first channel structure of the first field-effect transistor, the first channel structure being located above the substrate and extending along a top surface of the substrate; Depositing a first replacement silicide layer on a surface of the first S / D structure, the first replacement silicide layer being made of a first dielectric; Depositing a second dielectric covering the first replacement silicide layer and the first S / D structure of the first field-effect transistor; Forming a first interconnect opening in the second dielectric, the first interconnect opening exposing the first replacement silicide layer; Filling the first interconnect opening with a first replacement interconnect layer, the first replacement interconnect layer being made of a third dielectric; Performing a heat treatment on the substrate; Removing the first replacement interconnect layer and the first replacement silicide layer; And Depositing a first silicide layer on a surface of the first S / D structure of the first field-effect transistor.

2. The method according to claim 1, further comprising, before performing the heat treatment on the substrate: Recessing the first replacement interconnect layer in the first interconnect opening; Forming a first dielectric cap on the first replacement interconnect layer; Refilling the first interconnect opening with the second dielectric; Recessing the second dielectric to expose a second channel structure of a second field-effect transistor, the second channel structure being located above and spaced apart from the first channel structure; Forming a second S / D structure of the second field-effect transistor, the second S / D structure being located above and spaced apart from the first S / D structure, the second S / D structure being located at a first end of the second channel structure; Depositing a second replacement silicide layer on a surface of the second S / D structure, the second replacement silicide layer being made of the first dielectric; Depositing the second dielectric covering the second replacement silicide layer and the second S / D structure; Forming a second interconnect opening in the second dielectric, the second interconnect opening exposing the second replacement silicide layer; And Forming a second replacement interconnect layer in the second interconnect opening, the second replacement interconnect layer being made of the third dielectric.

3. The method according to claim 2, further comprising, after forming the second replacement interconnect layer in the second interconnect opening: Removing a portion of the second replacement interconnect layer, thereby forming a space above the second replacement interconnect layer, the space being further located in the second dielectric; Forming a second dielectric cap on the second replacement interconnect layer; And Refilling the space with the second dielectric.

4. The method according to claim 3, further comprising, after performing the heat treatment on the substrate: Removing the second replacement interconnect layer in the second interconnect opening and the second replacement silicide layer; And Depositing a second silicide layer on a surface of the second S / D structure.

5. The method according to claim 4, wherein Removing the second replacement interconnect layer and the second replacement silicide layer further comprises: Forming an interlayer dielectric (ILD) above the second dielectric; Forming a patterned mask above the ILD; An etching process is performed to form a first via opening and a second via opening based on the patterned mask, and the first via opening and the second via opening extend into the second dielectric and the ILD to expose the first alternative interconnect layer and the second alternative interconnect layer respectively; and An etching process is performed to further remove the first alternative interconnect layer and the first alternative silicide layer in the first interconnect opening, the second alternative interconnect layer in the second interconnect opening, and the second alternative silicide layer.

6. The method according to claim 5, after depositing the first silicide layer and the second silicide layer, further comprising: Based on the patterned mask, a first trench opening and a second trench opening are formed in the ILD, the first trench opening is connected to the first via opening, and the second trench opening is connected to the second via opening; A conductive material is deposited in the first trench opening, the second trench opening, the first via opening, the second via opening, the first interconnect opening and the second interconnect opening to form a first metal line in the first trench opening, a second metal line in the second trench opening, a first via in the first via opening, a second via in the second via opening, a first interconnect structure in the first interconnect opening and a second interconnect structure in the second interconnect opening, wherein: The first metal line, the first via and the first interconnect structure are connected together; and The second metal line, the second via and the second interconnect structure are connected together.

7. The method according to claim 6, further comprising: Removing a part of the first metal line and a part of the first via, thereby forming a first gap above the first via to separate the first interconnect structure from the first metal line, the first gap is disposed in the ILD and further extends into the second dielectric; Removing a part of the second metal line and a part of the second via, thereby forming a second gap above the second via to separate the second interconnect structure from the second metal line, the second gap is disposed in the ILD and further extends into the second dielectric; Depositing a first insulating layer in the first gap and depositing a second insulating layer in the second gap; Removing a part of the first insulating layer and a part of the second insulating layer in the ILD, thereby forming a first recessed space above the first insulating layer and the first recessed space is located in the ILD, and forming a second recessed space above the second insulating layer and the second recessed space is located in the ILD; And Depositing the conductive material in the first recessed space and the second recessed space to refill the first metal line and the second metal line respectively, wherein: The first insulating layer is located between the first metal line and the first interconnect structure; and The second insulating layer is located between the second metal line and the second interconnect structure.

8. The method according to claim 7, before performing heat treatment on the substrate, further comprising: Forming a first gate structure surrounding the top surface of the first channel structure and a second gate structure surrounding the top surface of the second channel structure, wherein: The first gate structure includes a first interface layer surrounding the top surface of the first channel structure, a first high-k dielectric film surrounding the first interface layer, and a first conduction barrier layer surrounding the first high-k dielectric film; and The second gate structure includes a second interface layer surrounding the top surface of the second channel structure, a second high-k dielectric film surrounding the second interface layer, and a second conduction barrier layer surrounding the second high-k dielectric film.

9. The method according to claim 8, after performing a heat treatment on the substrate, further comprising:[[]] Forming a first work function metal above the first conduction barrier layer; And Forming a second work function metal above the second conduction barrier layer.

10. The method according to claim 9, wherein, Performing a heat treatment on the substrate includes heating the substrate to a temperature above 500 degrees Celsius.

11. The method according to claim 10, wherein, The heat treatment includes an annealing process configured to anneal at least one of the first S / D structure, the second S / D structure, the first gate structure, or the second gate structure.

12. The method according to claim 11, wherein, The first dielectric, the second dielectric, and the third dielectric have different etch resistances relative to each other, manifested as: an etching process removes one of the first dielectric, the second dielectric, and the third dielectric, while not removing the other two dielectrics among the first dielectric, the second dielectric, and the third dielectric.

13. The method according to claim 12, wherein, The first channel structure includes one or more first nanosheets or first nanowires, the one or more first nanosheets or first nanowires are stacked above the substrate and extend along the top surface of the substrate, and the second channel structure includes one or more second nanosheets or second nanowires, the one or more second nanosheets or second nanowires are stacked above the substrate and extend along the top surface of the substrate.

14. A method for forming a semiconductor device, the method comprising:[[]] Forming a pair of channel structures above a substrate, the pair of channel structures including a first channel structure of a first field effect transistor above the substrate and a second channel structure of a second field effect transistor stacked above the first channel structure,[[]] The first channel structure and the second channel structure extend along the top surface of the substrate; Forming a first source / drain (S / D) structure at a first end of the first channel structure, forming a first replacement silicide layer on the surface of the first S / D structure, and forming a first replacement interconnect structure above the first replacement silicide layer; Forming a second S / D structure at a first end of the second channel structure, forming a second replacement silicide layer on the surface of the second S / D structure, and forming a second replacement interconnect structure above the second replacement silicide layer; Performing a heat treatment on the substrate; Removing the first replacement silicide layer, the first replacement interconnect structure, the second replacement silicide layer, and the second replacement interconnect structure; And Forming a first silicide layer on the first S / D structure and a second silicide layer on the second S / D structure.

15. The method according to claim 14, wherein, Forming the first replacement silicide layer on the surface of the first S / D structure and forming the first replacement interconnect structure above the first replacement silicide layer includes:[[]] Depositing a first dielectric on the surface of the first S / D structure to form the first replacement silicide layer; Deposit a second dielectric covering the first replacement silicide layer and the first S / D structure; Form a first interconnect opening in the second dielectric, the first interconnect opening exposing the first replacement silicide layer; and Fill the first interconnect opening with the first replacement interconnect structure made of a third dielectric.

16. The method according to claim 15, further comprising, before forming the second S / D structure at a first end of the second channel structure: Recess the first replacement interconnect structure in the first interconnect opening; Form a first dielectric cap on the first replacement interconnect structure; Refill the first interconnect opening with the second dielectric; And Recess the second dielectric to expose the second channel structure of the second field effect transistor, thereby forming the second S / D structure at the first end of the second channel structure.

17. The method according to claim 16, wherein, Forming the second replacement silicide layer on the surface of the second S / D structure and forming the second replacement interconnect structure above the second replacement silicide layer further comprises: Deposit the first dielectric on the surface of the second S / D structure to form the second replacement silicide layer; Deposit a second dielectric covering the second replacement silicide layer and the second S / D structure of the second field effect transistor; Form a second interconnect opening in the second dielectric, the second interconnect opening exposing the second replacement silicide layer; and Fill the second interconnect opening with the second replacement interconnect structure made of the third dielectric.

18. The method according to claim 17, further comprising, after forming the second replacement interconnect structure above the second replacement silicide layer: Remove a portion of the second replacement interconnect structure, thereby forming a space above the second replacement interconnect structure, the space further located in the second dielectric; Form a second dielectric cap on the second replacement interconnect structure; And Refill the space with the second dielectric.

19. The method according to claim 18, wherein, Removing the first replacement silicide layer, the first replacement interconnect structure, the second replacement silicide layer, and the second replacement interconnect structure further comprises: Form an interlayer dielectric ILD above the second dielectric; Form a patterned mask above the ILD; Perform an etching process to form a first via opening and a second via opening based on the patterned mask, the first via opening and the second via opening extending into the second dielectric and the ILD to expose the first replacement interconnect structure and the second replacement interconnect structure respectively; and Perform an etching process to remove the first replacement interconnect structure in the first interconnect opening, the first replacement silicide layer, the second replacement interconnect structure in the second interconnect opening, and the second replacement silicide layer.

20. The method according to claim 19, further comprising, after forming the first silicide layer on the first S / D structure and the second silicide layer on the second S / D structure: Form a first trench opening and a second trench opening in the ILD based on the patterned mask, the first trench opening connected to the first via opening, and the second trench opening connected to the second via opening; Deposit a conductive material in the first trench opening, the second trench opening, the first via opening, the second via opening, the first interconnect opening, and the second interconnect opening to form a first metal line in the first trench opening, a second metal line in the second trench opening, a first via in the first via opening, a second via in the second via opening, a first interconnect structure in the first interconnect opening, and a second interconnect structure in the second interconnect opening, respectively, wherein: The first metal line, the first via, and the first interconnect structure are connected together; and the second metal line, the second via, and the second interconnect structure are connected together.

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