Light emitting display device

Abstract

The present application relates to a light emitting display device. According to an embodiment, a light emitting display device includes a display area including a plurality of pixels, and a driving part located at one side of the display area, wherein the driving part includes at least two light emitting signal stages in one row, and further includes an input signal line for inputting a signal to the at least two light emitting signal stages, wherein the at least two light emitting signal stages are connected to the same input signal line.

Description

Technical Field

[0001] The present invention relates to a light-emitting display device, and more particularly to a light-emitting display device comprising a driving portion and pixels formed together on a panel by the same process. Background Technology

[0002] Display devices, as devices for displaying images, include liquid crystal displays (LCDs), organic light-emitting diode displays (OLEDs), and quantum dot displays. These display devices are used in a variety of electronic devices such as mobile phones, navigation devices, digital cameras, e-book readers, portable game consoles, and various terminals.

[0003] Organic light-emitting diode (OLED) displays are self-luminous and, unlike liquid crystal displays (LCDs), do not require an external light source, thus reducing thickness and weight. Furthermore, OLED displays offer high-quality characteristics such as low power consumption, high brightness, and fast response times. Summary of the Invention

[0004] The example is designed to reduce the width / area of ​​non-display areas where images are not displayed.

[0005] A light-emitting display device according to one embodiment includes: a display area including a plurality of pixels; and a driving unit located on one side of the display area, wherein the driving unit includes at least two light-emitting signal stages in a row, and further includes an input signal line for inputting signals to the at least two light-emitting signal stages, wherein the at least two light-emitting signal stages are connected to the same input signal line.

[0006] The at least two light emission signal generation stages may include at least two of the first light emission control signal generation unit, the second light emission control signal generation unit, the initialization control signal generation unit, and the bias control signal generation unit.

[0007] The input signal lines may include a pair of clock signal lines.

[0008] The at least two light-emitting signal stages that share the pair of clock signal lines can receive different start signals from each other.

[0009] The input signal line may also include high-voltage wiring or low-voltage wiring.

[0010] The pair of clock signal lines or the low-voltage wiring may be located between the at least two light-emitting signal stages.

[0011] The pair of clock signal lines can be configured as a double layer.

[0012] The at least two light emission signal generators can be the first light emission control signal generator and the second light emission control signal generator, or the initialization control signal generator and the bias control signal generator.

[0013] The driving unit may further include two scan signal stages in a row, the two scan signal stages being respectively included in the first scan signal generation unit and the second scan signal generation unit.

[0014] It may also include: input signal lines, which are connected to the two scan signal stages, and the input signal lines connected to the two scan signal stages may be a pair of clock signal lines.

[0015] An ELVSS wiring may be arranged between the at least two light-emitting signal stages and the two scanning signal stages to transmit the voltage applied to the cathode of the light-emitting element.

[0016] The ELVSS wiring can be formed as a double layer and is located in the portion where the organic protective film is removed.

[0017] The pixel circuit section of the display area can receive a first light emission control signal generated by the first light emission control signal generation section, a second light emission control signal generated by the second light emission control signal generation section, a first initialization control signal and a second initialization control signal generated by the initialization control signal generation section, a bias control signal generated by the bias control signal generation section, a first scan signal generated by the first scan signal generation section, and a second scan signal generated by the second scan signal generation section.

[0018] The light emission signal stage for generating the first initialization control signal in the initialization control signal generation unit may be located at the previous end compared to the light emission signal stage for generating the second initialization control signal in the initialization control signal generation unit.

[0019] The first scan signal may have a low voltage once in a frame, and the second scan signal may have a low voltage three times in a frame.

[0020] A light-emitting display device according to an embodiment includes: a display area including a plurality of pixels; and a driving unit located on one side of the display area, wherein the driving unit includes two scan signal stages in a row, and further includes an input signal line for inputting signals to the two scan signal stages, wherein the two scan signal stages are connected to the same input signal line.

[0021] The input signal lines that are connected to the two scanning signal stages can be a pair of clock signal lines.

[0022] The pair of clock signal lines can be located between the two scan signal stages.

[0023] The two scanning signal stages can be respectively included in the first scanning signal generation unit and the second scanning signal generation unit.

[0024] According to an embodiment, multiple driving units located in the non-display area can be configured to have a common connected input signal line, thereby reducing the width / area of ​​the non-display area. In particular, in a light-emitting display device that requires providing multiple signal lines to a pixel, even if the driving units that generate multiple signals are formed in the non-display area using the same process as the pixel, two adjacent driving units can be formed symmetrically with respect to the input signal line and can share the input signal line, thereby reducing the width / area of ​​the non-display area. Attached Figure Description

[0025] Figure 1 This is a simplified schematic diagram of a light-emitting display device according to an embodiment.

[0026] Figure 2 This is a circuit diagram of pixels located in the display area of ​​a light-emitting display device according to an embodiment.

[0027] Figure 3 The diagram is applied to Figure 2 Waveform diagram of multiple signals of the pixel and the voltage waveform of node G based thereon.

[0028] Figure 4 and Figure 5 This is a block diagram of driving units arranged in non-display areas on both sides of a display area, according to an embodiment.

[0029] Figure 6 This is a circuit diagram of one stage of the light emission control signal generation unit in the driving unit constituting the non-display area according to an embodiment.

[0030] Figure 7 The diagram is applied according to Figure 6 The waveform diagram of the input signal of the stage of the light emission control signal generation unit in the embodiment.

[0031] Figure 8 This is an illustration of the arrangement of two stages of the light emission control signal generation unit in an inverted configuration according to one embodiment.

[0032] Figure 9 and Figure 10 It is along Figure 8 The sectional view cut by the intercept lines IX-IX and XX.

[0033] Figure 11 This is an arrangement diagram illustrating the structure of the light emission control signal generation unit with two stages arranged in reverse order according to another embodiment.

[0034] Figure 12 and Figure 13 It is along Figure 11 The sectional view taken by the intercept lines XII-XII and XIII-XIII.

[0035] Figure 14 This is a simplified illustration of a structure in which two stages of the light emission control signal generation unit are connected together to the input signal line according to another embodiment.

[0036] Figure 15 This is a circuit diagram illustrating one stage of the scanning signal generation unit in the driving section of the non-display area according to an embodiment.

[0037] Figure 16 It is based on the diagram. Figure 15 The waveform diagram of the input signal applied by the scanning signal generation unit in the embodiment.

[0038] Figure 17 The illustration shows the application of an object according to yet another embodiment. Figure 2 Waveform diagrams of multiple signals of the pixels and the voltage waveforms of the G nodes based thereon.

[0039] Figure 18 This diagram is for generating Figure 17 The waveform of the input signal applied to the scanning signal generation stage by the signal.

[0040] Figure 19 This is an illustration of an embodiment in which two stages of the scanning signal generation unit are arranged in reverse order.

[0041] Figure 20 It is along Figure 19 The sectional view taken by section line XX-XX.

[0042] Figure 21 This is a diagram that clearly illustrates the reduction in width that occurs when multiple levels are formed in a non-display area in one embodiment.

[0043] Figure 22 yes Figure 21 A partial sectional view.

[0044] Explanation of reference numerals in the attached figures

[0045] 10: Light-emitting display device; 200, 250: Driving unit

[0046] 151: First scan line; 152: Second scan line

[0047] 153: First initialization control line; 153-1: Second initialization control line

[0048] 154, 155: Illumination control lines; 156: Bias control line

[0049] 171: Data line; 172: Drive voltage line

[0050] 173: Reference voltage line; 179: Bias voltage line

[0051] 127: Initialization voltage line; 2101, 3101: High voltage wiring

[0052] 2102, 3102: Low voltage wiring; 2105: ESR wiring

[0053] 2103, 2104, 2253, 2254, 3103, 3104, 3253, 3254: Clock wiring

[0054] 2201, 3201: Output wiring; 2551: High-level output section

[0055] 2552: Low-level output section; 2553: First node, first control section

[0056] 2554: First Node, Second Control Unit; 2555: Second Node, First Control Unit

[0057] 2556: Node 2-1 Holding Unit; 2557: Node 3 Control Unit

[0058] 2560: Initialization section; 3551: High-level output section

[0059] 3552: Low-level output section; 3553: First node, first control section

[0060] 3554: First node, second control unit; 3555: Second node, first control unit

[0061] 3556: Second Node, Second Control Unit

[0062] Ca2O1, Ca2O2, Ca2O3, Ca3O1, Ca3O2: Capacitors

[0063] Cpr: Input capacitor; Cst: Holding capacitor

[0064] 2001, 2005: First Light Emitting Control Signal Generation Unit

[0065] 2002, 2006: Second Light Emitting Control Signal Generation Unit

[0066] 2003, 2007: Initialization control signal generation unit

[0067] 2004, 2008: Bias control signal generation unit

[0068] 3001, 3003: First scan signal generation unit

[0069] 3002, 3004: Second Scan Signal Generation Unit

[0070] 110: Substrate; 141: First gate insulating film

[0071] 142: Second gate insulating film; 143: First interlayer insulating film

[0072] 144: Second interlayer insulating film; 145: Organic protective film Detailed Implementation

[0073] Hereinafter, several embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art to which this invention pertains can easily implement it. The present invention can be implemented in many different forms and is not limited to the embodiments described herein.

[0074] To clearly illustrate the present invention, parts unrelated to the description have been omitted, and the same reference numerals have been given to the same or similar constituent elements throughout the specification.

[0075] Furthermore, for ease of explanation, the sizes and thicknesses of the various components shown in the accompanying drawings are arbitrarily illustrated; therefore, the present invention is not necessarily limited to the content depicted. The thicknesses are enlarged in the accompanying drawings to clearly illustrate multiple layers and regions. Moreover, the thicknesses of some layers and regions are exaggerated in the accompanying drawings for ease of explanation.

[0076] Furthermore, when referring to a layer, membrane, region, plate, or other part as being "above" or "on top of" another part, this includes not only the case where it is "immediately above" the other part, but also the case where there are other parts in between. Conversely, when referring to a part as being "immediately above" another part, it means that there are no other parts in between. Moreover, the phrase "above" or "on top of" the reference part means being above or below the reference part, and does not necessarily mean being "above" or "on top of" in the direction opposite to gravity.

[0077] Furthermore, throughout the specification, when a part is mentioned as "including" a certain constituent element, it does not mean that other constituent elements are excluded, but rather that other constituent elements may be included, unless otherwise stated.

[0078] Furthermore, throughout the instruction manual, when "on a plane" is mentioned, it means that the object is viewed from above, and when "on a cross section" is mentioned, it means that the object is viewed from the side as a cross section that was vertically cut into the object.

[0079] Throughout the specification, when the term "connection" is used, it can refer not only to a direct connection between two or more constituent elements, but also to a connection between two or more constituent elements indirectly through other constituent elements, a physical connection, or an electrical connection. In addition, it can also refer to a connection between parts that are essentially one unit but are named differently according to their location or function.

[0080] The following is a detailed description focusing on the embodiments, with reference to the accompanying drawings.

[0081] Figure 1 This is a simplified schematic diagram of a light-emitting display device according to an embodiment.

[0082] The light-emitting display device 10 according to this embodiment includes a display area DA having a plurality of pixels PX and driving units 200 and 250 formed in non-display areas located on both sides of the display area DA.

[0083] The pixels PX of the light-emitting display device 10 generally include a pixel circuit section and a light-emitting element section that receives current from the pixel circuit section and emits light. The arrangement of the light-emitting element section can be varied. Figure 1 The rectangular pixel PX shown can be a pixel circuit part in a pixel, and the rectangular pixel circuit parts can be arranged along rows and columns.

[0084] First, through Figure 2 and Figure 3 The pixel PX formed in the light-emitting display device according to the embodiment will be described.

[0085] First, through Figure 2 Describe the circuit structure of the pixel.

[0086] Figure 2 This is a circuit diagram of pixels located in the display area of ​​a light-emitting display device according to an embodiment.

[0087] A pixel is generally composed of a pixel circuit section and a light-emitting element section, and the pixel circuit section may include: a driving transistor T1, which transmits output current to the anode of the light-emitting element section; an input capacitor Cpr; and a second transistor T2, which is connected to the data line 171 and transmits data voltage to the input capacitor Cpr.

[0088] according to Figure 2The pixel of the light-emitting display device in this embodiment includes multiple transistors T1, T2, T3, T4, T5, T6, T7, T8 connected to multiple signal lines 127, 151, 152, 153, 153-1, 154, 155, 156, 171, 172, 173, 179, multiple capacitors Cst, Cpr, and a light-emitting diode (LED). When a pixel is divided into a pixel circuit section and a light-emitting element section, the light-emitting element section is a LED, and the other transistors and capacitors constitute the pixel circuit section. The LED can be an organic LED or an inorganic LED.

[0089] The multiple transistors T1, T2, T3, T4, T5, T6, T7, and T8 may include: a driving transistor (also called the first transistor) T1, which generates the output current to be delivered to the light-emitting diode; and a second transistor T2, which applies the data voltage V to the data line 171. DATA The signal is transmitted to the pixel; the third transistor T3 connects the output electrode and gate electrode of the driving transistor T1; the fourth transistor T4 converts one end of the input capacitor Cpr to the reference voltage V. REF The fifth transistor T5 transmits the driving voltage ELVDD to the driving transistor T1; the sixth transistor T6 transmits the output current of the driving transistor T1 to the light-emitting diode; the seventh transistor T7 changes the voltage at the anode of the light-emitting diode to the initialization voltage V. INT ; and the eighth transistor T8, which transmits the bias voltage Vbias to the driving transistor T1.

[0090] Multiple signal lines 127, 151, 152, 153, 153-1, 154, 155, 156, 171, 172, 173, and 179 may include a first scan line 151, a second scan line 152, initialization control lines 153 and 153-1, emission control lines 154 and 155, a bias control line 156, a data line 171, a drive voltage line 172, a reference voltage line 173, a bias voltage line 179, and an initialization voltage line 127. The second initialization control line 153-1 may have the same wiring as the first initialization control line 153 connected to the pixel in the next row. The first emission control line 154 and the second emission control line 155 included in the emission control lines 154 and 155 may be applied with signals having different timing from each other.

[0091] Reference voltage line 173 transmits reference voltage V to the N node connected to the input capacitor Cpr and the second transistor T2. REF The driving voltage line 172 transmits the driving voltage ELVDD to the driving transistor T1; the driving low voltage line transmits the driving low voltage ELVSS to the cathode of the light-emitting diode; and the initialization voltage line 127 transmits the initialization voltage V to the anode of the light-emitting diode.INT The bias voltage line 179 transmits the bias voltage Vbias to the drive transistor T1.

[0092] Multiple capacitors Cst and Cpr include: a holding capacitor Cst, which keeps the voltage at the gate electrode of the driving transistor T1 constant during a frame; and an input capacitor Cpr, which receives the data voltage V transmitted through the second transistor T2. DATA The voltage is transmitted to one electrode of the driving transistor T1. According to an embodiment, the input capacitor Cpr may also be omitted, thus the data voltage V... DATA It is directly transmitted to one electrode of the driving transistor T1.

[0093] The connection relationships of the various elements included in a pixel are described in detail below.

[0094] The driving transistor T1 is based on the data voltage V applied to the gate electrode. DATA A transistor is used to adjust the magnitude of the output current. This output current is applied to the anode of the light-emitting diode (LED), causing the LED's brightness to change according to the data voltage V. DATA The voltage is adjusted. For this purpose, the first electrode of the driving transistor T1 is connected to the driving voltage line 172 via the fifth transistor T5 to receive the driving voltage ELVDD. Furthermore, the first electrode of the driving transistor T1 receives the bias voltage Vbias via the eighth transistor T8, maintaining the voltage of the first electrode of the driving transistor T1 at a predetermined level. Additionally, the second electrode (node ​​O) of the driving transistor T1 is arranged to output current to the light-emitting diode, and is connected to the anode of the light-emitting diode via the sixth transistor T6. The second electrode of the driving transistor T1 is connected to the input capacitor Cpr to receive the data voltage V input through the second transistor T2. DATA Additionally, the gate electrode (G node) of the driving transistor T1 is connected to the holding capacitor Cst. Therefore, the voltage at the gate electrode of the driving transistor T1 changes according to the voltage stored in the holding capacitor Cst, thereby changing the output current of the driving transistor T1. The gate electrode of the driving transistor T1 and the second electrode are connected through a third transistor T3.

[0095] The second transistor T2 is used to transmit the data voltage V. DATA Received within pixel ( Figure 2The second transistor T2 is an N-node transistor. The gate electrode of the second transistor T2 is connected to the first scan line 151, and the first electrode of the second transistor T2 is connected to the data line 171. The second electrode of the second transistor T2 is connected to the second electrode (O-node) of the driving transistor T1 via the input capacitor Cpr. If the second transistor T2 is turned on according to the first scan signal GW(n) transmitted through the first scan line 151, the data voltage V transmitted through the data line 171... DATA The signal is transmitted to the second electrode of the driving transistor T1 through the input capacitor Cpr.

[0096] The third transistor T3 serves the following function: It enables the data voltage V... DATA The voltage is transferred to the gate electrode of the driving transistor T1 and the holding capacitor Cst, and the threshold voltage of the driving transistor T1 is compensated to the voltage stored in the holding capacitor Cst and stored. The gate electrode of the third transistor T3 is connected to the second scan line 152, the first electrode of the third transistor T3 is connected to the O node and connected to the second electrode of the driving transistor T1 and the input capacitor Cpr, and the first electrode of the third transistor T3 is connected to the G node and connected to the gate electrode of the driving transistor T1 and the holding capacitor Cst. That is, if the driving transistor T1 is connected in a diode manner and the driving transistor T1 is turned on by applying a voltage to the holding capacitor Cst, the negative charge stored in the holding capacitor Cst is released, and the voltage of the holding capacitor Cst increases. Then, since the driving transistor T1 is turned off at its threshold voltage, the voltage no longer decreases, and the voltage stored in the holding capacitor Cst becomes the threshold voltage value of the driving transistor T1. Due to this structure, even if each driving transistor T1 has a different threshold voltage, compensation can be performed in each pixel circuit section.

[0097] The fourth transistor T4 initializes the voltage at the first electrode of the input capacitor Cpr (or the second electrode of the second transistor T2) to the reference voltage V. REF The function of the fourth transistor T4 is as follows: the gate electrode of the fourth transistor T4 is connected to the first initialization control line 153, the first electrode of the fourth transistor T4 is connected to the reference voltage line 173, and the second electrode of the fourth transistor T4 is connected to the first electrode of the input capacitor Cpr and the second electrode of the second transistor T2.

[0098] The fifth transistor T5 serves to transmit the driving voltage ELVDD to the driving transistor T1. The gate electrode of the fifth transistor T5 is connected to the first light-emitting control line 154, the first electrode of the fifth transistor T5 is connected to the driving voltage line 172, and the second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T1.

[0099] The sixth transistor T6 serves to transfer the output current from the driving transistor T1 to the light-emitting diode. The gate electrode of the sixth transistor T6 is connected to the second light-emitting control line 155, the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T1, and the second electrode of the sixth transistor T6 is connected to the anode of the light-emitting diode.

[0100] The seventh transistor, T7, initializes the voltage at the anode of the light-emitting diode to the initial voltage V. INT The function of the seventh transistor T7 is as follows: the gate electrode of the seventh transistor T7 is connected to the second initialization control line 153-1, the first electrode of the seventh transistor T7 is connected to the anode (A node) of the light-emitting diode, and the second electrode of the seventh transistor T7 is connected to the initialization voltage line 127. The second initialization control line 153-1 can be the same wiring as the first initialization control line 153 connected to the pixel in the next row.

[0101] The eighth transistor T8 applies a bias voltage Vbias to the first electrode of the driving transistor T1, thereby preventing the voltage level of the first electrode of the driving transistor T1 from exceeding a predetermined range. The gate electrode of the eighth transistor T8 is connected to the bias control line 156, the first electrode of the eighth transistor T8 is connected to the bias voltage line 179, and the second electrode of the eighth transistor T8 is connected to the first electrode of the driving transistor T1.

[0102] The first holding electrode of the holding capacitor Cst is connected to the driving voltage line 172, and the second holding electrode is connected to the G node (i.e., the gate electrode of the driving transistor T1 and the second electrode of the third transistor T3). As a result, the voltage of the second holding electrode is the same as the voltage of the gate of the driving transistor T1, and the voltage of the gate electrode of the driving transistor T1 remains constant during a frame.

[0103] The first electrode of the input capacitor Cpr is connected to the N node (i.e., the second electrode of the second transistor T2 and the second electrode of the fourth transistor), and the second electrode is connected to the second electrode (O node) of the driving transistor T1.

[0104] In addition, the anode (A node) of the light-emitting diode is connected to the second electrode of the sixth transistor T6 and the first electrode of the seventh transistor T7, and the cathode of the light-emitting diode receives the driving low voltage ELVSS.

[0105] Having as described above Figure 2 The pixels of the circuit structure can be applied with, for example Figure 3 The waveform of the signal.

[0106] Figure 3 It is applied to Figure 2 The waveform of the pixels.

[0107] To illustrate, Figure 3 The text is divided into intervals (A), (B), (C), (D), (E), (F), (G), and (H), with interval (H) preceding interval (A).

[0108] First, the description will begin with the (H) region (hereinafter also referred to as the luminescent region).

[0109] In region (H), only the first light-emitting control signal EM1 and the second light-emitting control signal EM2 applied to the fifth transistor T5 and the sixth transistor T6 are given a low-level on-state voltage. As a result, the fifth transistor T5 and the sixth transistor T6 are turned on, thus enabling the driving transistor T1 to receive the driving voltage ELVDD and connect to the light-emitting diode. Consequently, an output current is generated based on the driving voltage ELVDD and the voltage at the gate electrode of the driving transistor T1 (G_node voltage), and this output current is transmitted to the light-emitting diode. The brightness of the light-emitting diode is determined by the magnitude of the received output current.

[0110] Subsequently, the first light-emitting control signal EM1 first changes to a high-level voltage and enters interval (A). At this time, the first initialization control signal EB1(n) and the second initialization control signal EB1(n+1) sequentially change to a low-level voltage. The time difference between the first initialization control signal EB1(n) and the second initialization control signal EB1(n+1) changing to a low-level voltage can be more than 1H, and can be varied according to the embodiment. In interval (A), no driving voltage ELVDD is applied to the driving transistor T1, and the driving transistor T1 does not generate output current. Furthermore, the voltage of node N (the second electrode of the second transistor T2 and the second electrode of the fourth transistor T4) is initialized to the reference voltage V by the fourth transistor T4. REF And the voltage at node A (the anode of the LED) is initialized to the initial voltage V input through the seventh transistor T7. INT In interval (A), since the sixth transistor T6 is turned on, the initial voltage V... INT The voltage at node O is initialized by passing the signal from node A to node O. Since node O is connected to the second electrode of driving transistor T1, the first electrode of third transistor T3, and the second electrode of input capacitor Cpr, they are all initialized to the initial voltage V. INT .

[0111] Subsequently, upon entering interval (B), the second scan signal GC(n) first changes to a low-level voltage, thereby applying the initialization voltage V to node O. INT It is passed to node G, and the voltage of node G is also initialized to the initial voltage V.INT The voltage at the gate electrode of the driving transistor T1 connected to node G and the voltage at the second electrode of the holding capacitor Cst are also initialized to the initialization voltage V. INT .

[0112] Subsequently, the second scan signal GC(n) repeats a high-level voltage and a low-level voltage several times, and applies a low-level voltage in the data writing interval ((E) interval), and then maintains a high-level voltage. According to the embodiment, the number of times the second scan signal GC(n) changes to a low-level voltage can be varied, and only needs to be at least once until the next light-emitting interval (H).

[0113] After the second light emission control signal EM2 changes to a high level voltage, the first light emission control signal EM1 changes from a high level voltage to a low level voltage and enters the (C) interval.

[0114] The (C) interval is also called the threshold voltage compensation interval. In the (C) interval, the first light emission control signal EM1 and the second scan signal GC(n) have low-level voltages, thereby driving transistor T1 to be driven by the driving voltage ELVDD, and having a diode-connected structure through the third transistor T3.

[0115] At this time, since the voltage of node G is the initial voltage V INT Therefore, the driving transistor T1 turns on, the negative charge stored in the holding capacitor Cst escapes, and the voltage of the holding capacitor Cst increases. Then, the driving transistor T1 turns off at its threshold voltage. As a result, the voltage value V in the holding capacitor Cst, which is based on the driving voltage ELVDD and is lower than the threshold voltage Vth of the driving transistor T1, is... ELVDD -Vth is stored on node G.

[0116] In addition, within interval (C), nodes N and A are continuously maintained at the reference voltage V by the first initialization control signal EB1(n) and the second initialization control signal EB1(n+1). REF and initial voltage V INT .

[0117] Subsequently, the first light emission control signal EM1, the first initialization control signal EB1(n), and the second initialization control signal EB1(n+1) are changed to high-level voltages and enter the (D) interval. At this time, the timing can also be adjusted so that the second scan signal GC(n) is changed to a high-level voltage. The (D) interval is the interval where the operation of compensating for the threshold voltage ends and preparations are made for the subsequent (E) interval (also known as the data writing interval).

[0118] Subsequently, during the interval where the second scan signal GC(n) changes to a low voltage level, the first scan signal GW(n) changes to a low voltage level and enters the (E) interval.

[0119] In region (E), the second transistor T2 is turned on, thus the data voltage V... DATA The data is transmitted to node O via the input capacitor Cpr. At this time, since the third transistor T3 is also turned on via the second scan signal GC(n), the data voltage V... DATA The data voltage value transmitted to node G is reduced by a factor of 1 when transmitted to nodes O and G, depending on the capacitance of the input capacitor Cpr. As described above, the data voltage value for which a factor of 1 (α) is reduced and transmitted is called αV. DATA At that time, since the previous voltage value of node G was V ELVDD -Vth, therefore the voltage at the final G node in the (E) interval can have V ELVDD -Vth+αV DATA The value of .

[0120] As a result, the holding capacitor Cst is compensated for the threshold voltage of the driving transistor T1, and also includes the data voltage.

[0121] Subsequently, the first scan signal GW(n) changes to a high level voltage and enters interval (F). At this time, the second scan signal GC(n) also changes to a high level voltage, and the second scan signal GC(n) remains high from interval (F) to the next interval (B).

[0122] In interval (F), the first initialization control signal EB1(n) and the second initialization control signal EB1(n+1) are changed to low-level voltages to re-initialize the voltages of nodes N and A. Furthermore, the bias control signal EB2(n) is also changed to a low-level voltage, and a bias voltage Vbais is applied to the driving transistor T1. The bias voltage Vbais can have a predetermined voltage value set according to the characteristics of the panel, and can have various voltage values ​​depending on the panel. The bias voltage Vbais can be set to have a predetermined voltage value within a panel, ensuring that the voltage of the first electrode of the driving transistor T1 does not change due to variations in the surrounding voltage.

[0123] Subsequently, the bias control signal EB2(n) is changed to a high level and enters the (G) interval. In the (G) interval, the second light emission control signal EM2 is applied to a low level in preparation for entering the light emission interval (H), and the first initialization control signal EB1(n) and the second initialization control signal EB1(n+1) remain at a low level.

[0124] Subsequently, the first initialization control signal EB1(n) and the second initialization control signal EB1(n+1) are changed to high voltage, and the first light emission control signal EM1 is changed to low voltage, and the light emission interval ((H) interval) is entered.

[0125] In the (H) region, the driving transistor T1 receives the driving voltage ELVDD and generates an output current according to the voltage of node G, and transmits it to the light-emitting diode so that it emits light with a predetermined brightness.

[0126] In order to address the above, such as Figure 2 Applying such pixels Figure 3 The timing signals are located on both sides of the display area DA, and the driving units 200 and 250 will be transmitted through... Figure 4 and Figure 5 Provide a detailed description.

[0127] Figure 4 and Figure 5 This is a block diagram of driving units arranged in non-display areas on both sides of a display area, according to one embodiment.

[0128] First of all, with Figure 4 Based on this, the first driving unit 200 located on the left side of the display area DA will be described.

[0129] The first driving unit 200 includes a total of six sub-driving units, including a first light emission control signal generation unit (EM1_D) 2001 for generating a first light emission control signal EM1, a second light emission control signal generation unit (EM2_D) 2002 for generating a second light emission control signal EM2, an initialization control signal generation unit (EB1_D) 2003 for generating a first initialization control signal EB1(n), a bias control signal generation unit (EB2_D) 2004 for generating a bias control signal EB2(n), a first scan signal generation unit (GW_D) 3001 for generating a first scan signal GW(n), and a second scan signal generation unit (GC_D) 3002 for generating a second scan signal GC(n). Here, the second initialization control signal EB1(n+1) applied to the pixel is received from the initialization control signal generation unit (EB1_D) 2003 of the next row.

[0130] In the first driving unit 200 located on the left side of the display area DA, a first light emission control signal generation unit (EM1_D) 2001, a second light emission control signal generation unit (EM2_D) 2002, an initialization control signal generation unit (EB1_D) 2003, a bias control signal generation unit (EB2_D) 2004, a second scan signal generation unit (GC_D) 3002 and a first scan signal generation unit (GW_D) 3001 are arranged sequentially from the outside towards the display area DA.

[0131] in addition, Figure 5 The diagram shows the second drive unit 250 located to the right of the display area DA.

[0132] Similar to the first driving unit 200, the second driving unit 250 includes a total of six sub-driving units, including a first light emission control signal generation unit (EM1_D) 2005 for generating a first light emission control signal EM1, a second light emission control signal generation unit (EM2_D) 2006 for generating a second light emission control signal EM2, an initialization control signal generation unit (EB1_D) 2007 for generating a first initialization control signal EB1(n), a bias control signal generation unit (EB2_D) 2008 for generating a bias control signal EB2(n), a first scan signal generation unit (GW_D) 3003 for generating a first scan signal GW(n), and a second scan signal generation unit (GC_D) 3004 for generating a second scan signal GC(n). Here, the second initialization control signal EB1(n+1) applied to the pixel is received from the initialization control signal generation unit (EB1_D) 2007 of the next row.

[0133] In the second driving unit 250 located on the right side of the display area DA, a first light emission control signal generation unit 2005 (EM1_D), a second light emission control signal generation unit 2006 (EM2_D), an initialization control signal generation unit 2007 (EB1_D), a bias control signal generation unit 2008 (EB2_D), a second scan signal generation unit 3004 (GC_D), and a first scan signal generation unit 3003 (GW_D) are arranged sequentially from the outside towards the display area DA.

[0134] That is, refer to Figure 4 and Figure 5 The first scan signal generation units (GW_D) 3001 and 3003 are arranged at the closest position relative to the display area DA. From this position outward, the second scan signal generation units (GC_D) 3002 and 3004, the bias control signal generation units (EB2_D) 2004 and 2008, the initialization control signal generation units (EB1_D) 2003 and 2007, the second light emission control signal generation units (EM2_D) 2002 and 2006, and the first light emission control signal generation units (EM1_D) 2001 and 2005 are arranged in sequence.

[0135] The same signal generation units belonging to the first drive unit 200 and the second drive unit 250 are connected to the same signal line, and generate the same signal and apply it to the signal line. As an example, the first scan signal generation units (GW_D) 3001 and 3003 of the first drive unit 200 and the second drive unit 250 are connected to both ends of the same first scan line 151, and output a first scan signal whose voltage changes at the same timing.

[0136] Since the same signal is output as described above, according to the embodiment, only one of the first drive unit 200 and the second drive unit 250 may be included. That is, although according to Figure 1 , Figure 4 and Figure 5 The illustration shows an embodiment in which two driving portions 200 and 250 are formed on both sides of the display area DA, so that the same driving portions are symmetrically formed on both sides. However, according to the embodiment, the driving portion may be formed only on one side of the display area DA.

[0137] Furthermore, identical generating units in the first driving unit 200 and the second driving unit 250 can be removed, so that each generating unit is included only in one of the first driving unit 200 and the second driving unit 250. That is, a total of six generating units are divided into generating units included in the first driving unit 200 and generating units included in the second driving unit 250. At this time, according to the embodiment, the first scan signal generating units (GW_D) 3001, 3003, the second scan signal generating units (GC_D) 3002, 3004 can be located in one driving unit, and the first light emission control signal generating units (EM1_D) 2001, 2005, the second light emission control signal generating units (EM2_D) 2002, 2006, the initialization control signal generating units (EB1_D) 2003, 2007, and the bias control signal generating units (EB2_D) 2004, 2008 can be located in the remaining driving units. Furthermore, according to the embodiments, the first driving unit 200 and the second driving unit 250 may each include three generating units.

[0138] In one embodiment, the first drive unit 200 and the second drive unit 250 may generally include only two types of stages. That is, a total of six generation units are constituted using the first stage and the second stage.

[0139] The first stage can be configured as a first light emission control signal generation unit (EM1_D) 2001, 2005, a second light emission control signal generation unit (EM2_D) 2002, 2006, an initialization control signal generation unit (EB1_D) 2003, 2007, and a bias control signal generation unit (EB2_D) 2004, 2008. The second stage can be configured as a first scan signal generation unit (GW_D) 3001, 3003 and a second scan signal generation unit (GC_D) 3002, 3004. That is, although the first and second stages have the same circuit configuration, the output signals can be formed differently by using different input signals.

[0140] Hereinafter, since the most representative signal among the signals generated by the first stage is the light emission control signal, the first stage may also be referred to as a stage of the light emission control signal generation unit. Furthermore, since the most representative signal among the signals generated by the second stage is the scan signal, the second stage may also be referred to as a stage of the scan signal generation unit.

[0141] First, the following, through Figures 6 to 14 The signal generation unit, including the first stage, is described.

[0142] Below, firstly through Figure 6 The configuration of the first stage (hereinafter also referred to as the light emission signal stage) that can constitute the first light emission control signal generation unit (EM1_D) 2001, 2005, the second light emission control signal generation unit (EM2_D) 2002, 2006, the initialization control signal generation unit (EB1_D) 2003, 2007, and the bias control signal generation unit (EB2_D) 2004, 2008 will be described.

[0143] Figure 6 This is a circuit diagram of one stage of the light emission control signal generation unit in the driving unit constituting the non-display area according to an embodiment.

[0144] Each of the light-emitting signal stages according to this embodiment includes a high-level output unit 2551, a low-level output unit 2552, a first node first control unit 2553, a first node second control unit 2554, a second node first control unit 2555, a second-first node holding unit 2556, a third node control unit 2557, a first connection unit 2558, a second connection unit 2559, and an initialization unit 2560.

[0145] The core structure of each emission signal stage is described as follows.

[0146] The high-level output section 2551 outputs a high voltage VGH signal, and the low-level output section 2552 outputs a low voltage VGL signal. Both the high-level output section 2551 and the low-level output section 2552 are connected to the output terminal Out. When the high-level output section 2551 outputs a high voltage VGH, the low-level output section 2552 does not output; conversely, when the low-level output section 2552 outputs a low voltage VGL, the high-level output section 2551 does not output.

[0147] The high-level output unit 2551 is controlled according to the voltage of the first node EM_QB, and the voltage of the first node EM_QB is controlled by the first node first control unit 2553 and the first node second control unit 2554.

[0148] The low-level output unit 2552 is controlled according to the voltage of the second node SR_Q, which is controlled by the second node first control unit 2555. Specifically, the low-level output unit 2552 is connected to the second node SR_Q via the second connection unit 2559, and is thus controlled according to the voltage of the second-1st node SR_Q_F. However, since the second 212 transistor T212 included in the second connection unit 2559 remains in an on-state by receiving a low voltage VGL at its control terminal, the low-level output unit 2552 is actually controlled according to the voltage of the second node SR_Q.

[0149] The first node second control unit 2554 is controlled by the voltage of the third node SR_QB, and the voltage of the third node SR_QB is controlled by the third node control unit 2557. Specifically, the first node second control unit 2554 is connected to the third node SR_QB via the first connection unit 2558, and is thus controlled according to the voltage of the third-1st node SR_QB_F. However, since the 211th transistor T211 included in the first connection unit 2558 remains in an on state by receiving a low voltage VGL at its control terminal, the first node second control unit 2554 is actually controlled according to the voltage of the third node SR_QB.

[0150] Figure 6 The LED signal receives two clock signals EM_CLK1 and EM_CLK2 at the stage, and the LED signal of the next row is connected to the stage by exchanging the two clock signals. Furthermore, although... Figure 6 The light-emitting signal stage is illustrated as receiving the FLM signal through the input terminal, but in the presence of a preceding light-emitting signal stage (the previous light-emitting signal stage), the output of the preceding light-emitting signal stage can be input to the input terminal.

[0151] The detailed description of each part of each emission signal stage is as follows.

[0152] The high-level output section 2551 includes a 209th transistor T209, the gate electrode of which is connected to the first node EM_QB, the input electrode of which is connected to the high-voltage VGH terminal, and the output electrode of which is connected to the output terminal Out. As a result, when the voltage of the first node EM_QB is low, the high voltage VGH is output through the output terminal Out; when the voltage of the first node EM_QB is high, the 209th transistor T209 is turned off and does not output any voltage.

[0153] The low-level output section 2552 includes a 210th transistor T210. The gate electrode of the 210th transistor T210 is connected to the 2-1 node SR_Q_F, the input electrode is connected to the low-voltage VGL terminal, and the output electrode is connected to the output terminal Out. As a result, when the voltage of the 2-1 node SR_Q_F is low, the low-voltage VGL is output through the output terminal Out; when the voltage of the 2-1 node SR_Q_F is high, the 210th transistor T210 does not output any voltage. Since the 212th transistor T212 included in the second connection section 2559 remains in an on-state by receiving the low-voltage VGL through its control terminal, the voltage of the 2-1 node SR_Q_F has the same voltage as the voltage of the second node SR_Q. Therefore, the low-level output section 2552 is controlled by the second node SR_Q.

[0154] The first control unit 2553 and the second control unit 2554 of the first node, which control the voltage of the first node EM_QB, are described.

[0155] The first node first control unit 2553 includes a transistor (transistor T208, number 208) and a capacitor (capacitor Ca201, number 201). The gate of transistor T208 is connected to the second node SR_Q, its input electrode is connected to a high voltage VGH, and its output electrode is connected to the first node EM_QB. When the voltage at the second node SR_Q is low, transistor T208 transfers the high voltage VGH to the first node EM_QB. Therefore, the first node first control unit 2553 performs the function of changing the voltage of the first node EM_QB to the high voltage VGH. Furthermore, the two electrodes of capacitor Ca201 are connected to the input and output electrodes of transistor T208, respectively, thus connecting capacitor Ca201 between the first node EM_QB and the high voltage VGH terminal. Therefore, capacitor Ca201 stores and maintains the voltage of the first node EM_QB.

[0156] Additionally, the second control unit 2554 of the first node includes two transistors (transistor T206, number 206, and transistor T207, number 207) and one capacitor (capacitor Ca202, number 202). The gate electrode of transistor T206 is connected to the first clock input terminal. Figure 6 The input terminal of transistor T207 is connected to the first node EM_QB, and the output electrode is connected to the fourth node EM_C. The gate electrode of transistor T207 is connected to the third-to-first node SR_QB_F, the output electrode is connected to the fourth node EM_C, and the input electrode is connected to the first clock input terminal. Figure 6 The input terminal of EM_CLK2 is applied. Since the 211th transistor T211 included in the first connection section 2558 remains in the on state by receiving a low voltage VGL through the control terminal, the voltage of the 3-1 node SR_QB_F has the same voltage as the voltage of the third node SR_QB. Therefore, the 207th transistor T207 is controlled by the third node SR_QB. Therefore, the first node second control section 2554 functions as follows: when the voltage of the third node SR_QB and the clock signal EM_CLK2 input to the first clock input terminal are low, it changes the voltage of the first node EM_QB to the low voltage of the clock signal EM_CLK2. In addition, the 202nd capacitor Ca202 can be connected between the 3-1 node SR_QB_F and the fourth node EM_C, and the voltage difference between the two nodes is used to reduce the voltage change at both ends.

[0157] The first control unit 2555 of the second node, which controls the voltage of the second node SR_Q, is described.

[0158] The second node's first control unit 2555 is constructed using a single transistor (transistor T201, number 201). The gate electrode of transistor T201 is connected to the second clock input terminal. Figure 6 The input terminal of EM_CLK1 is applied, and the input electrode is connected to the start signal input terminal (the input terminal of the start signal FLM or the output terminal of the previous light-emitting signal stage), and the output electrode is connected to the second node SR_Q. The 201st transistor T201 is applied to the second clock input terminal ( Figure 6 When the clock signal EM_CLK1 (the input terminal of EM_CLK1) is low, the voltage of the second node SR_Q is changed to the voltage of the start signal FLM or the output signal of the previous light-emitting stage. That is, the first control unit 2555 of the second node changes the voltage of the second node SR_Q to a carry signal (the start signal FLM or the output signal of the previous light-emitting stage) according to the clock signal EM_CLK1.

[0159] The 212th transistor T212 included in the second connection section 2559 is kept in the on state by receiving a low voltage VGL through the control terminal, so the voltage of the 2-1 node SR_Q_F has the same voltage as the voltage of the second node SR_Q.

[0160] Since the voltage of SR_Q_F at node 2-1 is the voltage of transistor T210 of the low-level output section 2552, the voltage of SR_Q_F at node 2-1 is stored and stabilized by the holding section 2556 at node 2-1.

[0161] The 2-1 node holding section 2556 is constructed using two transistors (transistor 202 T202 and transistor 203 T203) and one capacitor (capacitor 203 Ca203). The gate electrode of transistor 202 T202 is connected to the third node SR_QB, its input electrode is connected to the high-voltage VGH terminal, and its output electrode is connected to the fifth node EM_A. The gate electrode of transistor 203 T203 is connected to the 2-1 node SR_Q_F, its input electrode is connected to the fifth node EM_A, and its output electrode is connected to the first clock input terminal (…). Figure 6 (The input terminal of EM_CLK2 is applied). The 203rd capacitor Ca203 is connected between the input electrode and the gate electrode of the 203rd transistor T203 and the fifth node EM_A. With the help of the 203rd capacitor Ca203, the 2-1st node holding section 2556 keeps the voltage of the 2-1st node SR_Q_F constant relative to the voltage of the fifth node EM_A, which has a high voltage VGH or a clock signal EM_CLK2 input to the first clock input terminal, thereby reducing the voltage variability of the 2-1st node SR_Q_F.

[0162] The third node control unit 2557, which controls the voltage of the third node SR_QB, is described.

[0163] The third node control unit 2557 is constructed using two transistors (transistor T204, number 204, and transistor T205, number 205). The control terminal of transistor T204 is connected to the second node SR_Q, and its input terminal is connected to the second clock input terminal. Figure 6 The input terminal of EM_CLK1 is applied, and the output terminal is connected to the third node SR_QB. Figure 6 Transistor T204, number 204, comprises two transistors, each with its control terminals connected to the second node SR_Q for identical operation. The input terminal of one transistor and the output terminal of the other are connected to the sixth node EM_B. Transistor T205, number 205, has its control terminal connected to the second clock input. Figure 6The input terminal of EM_CLK1 is applied, the input terminal is connected to the low voltage VGL terminal, and the output terminal is connected to the third node SR_QB. Transistor T205 (205) converts the voltage of the third node SR_QB to the low voltage VGL, and transistor T204 (204) converts the voltage of the third node SR_QB to the voltage of the clock signal EM_CLK1 when the second node SR_Q has a low voltage.

[0164] Additionally, the initialization unit 2560 includes a transistor (transistor T213, number 213) that functions to change the voltage of the second node SR_Q to a high voltage VGH via an ESR signal. Specifically, the control terminal of transistor T213 receives the ESR signal, its input terminal is connected to the high voltage VGH terminal, and its output terminal is connected to the second node SR_Q. (See reference...) Figure 7 The ESR signal is a signal that initializes the light-emitting signal stage with a low voltage when the light-emitting display device is initially driven, which can eliminate pixel flickering that may occur when the light-emitting display device is initially driven. The ESR signal can be applied before the clock signals EM_CLK1 and EM_CLK2 are applied, so that it has a low voltage before the clock signals EM_CLK1 and EM_CLK2 are applied, and then has a high voltage when the clock signals EM_CLK1 and EM_CLK2 are applied.

[0165] Unlike the above description, the input and output electrodes can be named in reverse order, depending on the magnitude of the voltage they are connected to.

[0166] The light-emitting signal stage, configured as described above, determines its operation based on the signals applied to the two clock input terminals and the start signal input terminal, respectively, by means of... Figure 7 Describe it.

[0167] Figure 7 The diagram is applied to according to Figure 6 The waveform diagram of the input signal of the stage of the light emission control signal generation unit in the embodiment.

[0168] exist Figure 7 In addition to the two clock signals EM_CLK1 and EM_CLK2 and the ESR signal, multiple start signals FLM are also illustrated. That is, the light emission signal generation stage includes the first light emission control signal generation unit (EM1_D) 2001, 2005, the second light emission control signal generation unit (EM2_D) 2002, 2006, the initialization control signal generation unit (EB1_D) 2003, 2007, and the bias control signal generation unit (EB2_D) 2004, 2008, and each generation unit outputs a signal with a different timing from each other, thereby providing different start signals FLM for each.

[0169] That is, when the light emission signal generation stage is used as the first light emission control signal generation unit (EM1_D) 2001, 2005, in order to generate Figure 3 The first light emission control signal EM1, EM1_FLM signal is input to the start signal input terminal of the light emission signal stage as the start signal FLM. Figure 7 The high and low voltages of the EM1_FLM signal are used to... Figure 3 The first light-emitting control signal EM1 changes at the same intervals. Figure 3 The diagram illustrates the time required for switching between high and low voltage due to delays, etc. The signal output from the light-emitting signal stage and the signal input to the start signal input can have a time difference of 1H and the same waveform. The first light-emitting control signal generation units (EM1_D) 2001 and 2005 include multiple light-emitting signal stages and are configured such that the output of the previous light-emitting signal stage is transmitted not only through the first light-emitting control line 154 but also input to the start signal input of the next light-emitting signal stage. Therefore, although the start signal input of the first light-emitting signal stage receives the EM1_FLM signal as the start signal FLM, the start signal inputs of other light-emitting signal stages can also be input with the output of the previous light-emitting signal stage. As a result, the first light-emitting control signal generation units (EM1_D) 2001 and 2005 can sequentially output the first light-emitting control signal EM1 with the same waveform every 1H in multiple stages based on the EM1_FLM signal.

[0170] exist Figure 7 In this context, a frame of EM1_FLM signal can sequentially have EM1_FLTE, EM1_FLWE1, and EM1_FLWE2 intervals, and the EM1_FLTE interval starts from the reference timing V of the clock signals EM_CLK1 and EM_CLK2 when they are first applied. sync The process begins. During one frame, the EM1_FLM signal may have a high voltage in the EM1_FLTE interval, followed by a low voltage in the EM1_FLWE1 interval, then a high voltage during the EM1_FLWE2 interval, and then a low voltage for the remaining intervals. If clock signals EM_CLK1 and EM_CLK2 are applied, the clock signal EM_CLK2 input to the first clock input begins with a high voltage and is alternately applied with low / high voltage, while the clock signal EM_CLK1 input to the second clock input begins with a low voltage and is alternately applied with high / low voltage. In an embodiment where the voltages of clock signals EM_CLK1 and EM_CLK2 change every 1H, the EM1_FLTE, EM1_FLWE1, and EM1_FLWE2 intervals may have widths of 10H, 2H, and 16H, respectively.

[0171] In cases where the light emission signal generation stage is used as the second light emission control signal generation unit (EM2_D) 2002, 2006, in order to generate Figure 3 The second light emission control signal EM2, EM2_FLM signal is input to the start signal input terminal of the light emission signal stage as the start signal FLM. Figure 7 The high and low voltages of the EM2_FLM signal are used to... Figure 3 The second light-emitting control signal EM2 changes at the same intervals. Figure 3 The diagram illustrates the time required for switching between high and low voltage due to delays, etc. The signal output from the light-emitting signal stage and the signal input to the start signal input can have a time difference of 1 hour and the same waveform. The second light-emitting control signal generation units (EM2_D) 2002 and 2006 include multiple light-emitting signal stages and are configured such that the output of the previous light-emitting signal stage is not only transmitted through the second light-emitting control line 155 but also input to the start signal input of the next light-emitting signal stage. Therefore, although the start signal input of the first light-emitting signal stage receives the EM2_FLM signal as the start signal FLM, the start signal inputs of other light-emitting signal stages can also be input with the output of the previous light-emitting signal stage. As a result, the second light-emitting control signal generation units (EM2_D) 2002 and 2006 can sequentially output a second light-emitting control signal EM2 with the same waveform every 1 hour in multiple stages based on the EM2_FLM signal.

[0172] exist Figure 7 In this frame, the EM2_FLM signal has EM2_FLTE and EM2_FLWE intervals sequentially, and the reference timing V starts from the beginning of the application of clock signals EM_CLK1 and EM_CLK2. sync The signal initially has an EM2_FLTE interval. During one frame, the EM2_FLM signal has a low voltage during the EM2_FLTE interval, followed by a high voltage during the EM2_FLWE interval, and then a low voltage for the remaining interval. In an embodiment where the voltages of clock signals EM_CLK1 and EM_CLK2 change every 1H, the EM2_FLTE and EM2_FLWE intervals of the EM2_FLM signal can have widths of 8H and 16H, respectively.

[0173] In cases where the light emission signal stage is used as the initialization control signal generation unit (EB1_D) 2003, 2007, in order to generate Figure 3 The first initialization control signal EB1(n) and the EB1_FLM signal are input to the start signal input terminal of the light emission signal stage as the start signal FLM. Figure 7The high and low voltages of the EB1_FLM signal are used to... Figure 3 The first initialization control signal EB1(n) changes at the same intervals. Figure 3 The diagram illustrates the time required for switching between high and low voltage due to delays, etc. The signal output from the light-emitting signal stage and the signal input to the start signal input can have a time difference of 1H and the same waveform. The initialization control signal generation units (EB1_D) 2003 and 2007 include multiple light-emitting signal stages and are configured such that the output of the previous light-emitting signal stage is transmitted not only through the first initialization control line 153 but also input through the start signal input of the next light-emitting signal stage. Therefore, although the start signal input of the first light-emitting signal stage receives the EB1_FLM signal as the start signal FLM, the start signal inputs of other light-emitting signal stages can also be input with the output of the previous light-emitting signal stage. As a result, the initialization control signal generation units (EB1_D) 2003 and 2007 can sequentially output the first initialization control signal EB1(n) with the same waveform every 1H in multiple stages based on the EB1_FLM signal.

[0174] exist Figure 7 In this frame, the EB1_FLM signal has the intervals EB1_FLTE, EB1_FLWE1, EB1_FLWE2, and EB1_FLWE3 in sequence, and the reference timing V starts from the time when the clock signals EM_CLK1 and EM_CLK2 are applied. sync The signal begins with the EB1_FLTE interval. During one frame, the EB1_FLTE interval has a high voltage, the EB1_FLWE1 interval has a low voltage, the EB1_FLWE2 interval has a high voltage, the EB1_FLWE3 interval has a low voltage, and the remaining intervals have a high voltage. In an embodiment where the voltages of clock signals EM_CLK1 and EM_CLK2 change every 1H, the EB1_FLTE, EB1_FLWE1, EB1_FLWE2, and EB1_FLWE3 intervals of the EB1_FLM signal can have widths of 2H, 10H, 8H, and 6H, respectively.

[0175] In addition to the first initialization control signal EB1(n), the initialization control signal generation units (EB1_D) 2003 and 2007 also generate a second initialization control signal EB1(n+1), which is then applied to the second initialization control line 153-1.

[0176] Here, the second initialization control signal EB1(n+1) is a signal output from the light-emitting signal stage of the initialization control signal generation unit (EB1_D) 2003, 2007 at the next end, relative to the first initialization control signal EB1(n). That is, the light-emitting signal stage of the initialization control signal generation unit (EB1_D) 2003, 2007 that generates the first initialization control signal EB1(n) is located at the previous end relative to the light-emitting signal stage of the initialization control signal generation unit (EB1_D) 2003, 2007 that generates the second initialization control signal EB1(n+1). Therefore, the first initialization control signal EB1(n) has a waveform that precedes the second initialization control signal EB1(n+1) by 1H.

[0177] In this embodiment, the output signal of a light-emitting signal stage included in the initialization control signal generation unit (EB1_D) 2003, 2007 is transmitted through the start signal input terminal of the next light-emitting signal stage, the first initialization control line 153 of this end, and the second initialization control line 153-1 of the previous end.

[0178] In cases where the light emission signal stage is used as the bias control signal generation unit (EB2_D) 2004, 2008, in order to generate Figure 3 The bias control signal EB2(n) and the EB2_FLM signal are input to the start signal input terminal of the light emission signal stage as the start signal FLM. Figure 7 The high and low voltages of the EB2_FLM signal are used to... Figure 3 The bias control signal EB2(n) changes at the same intervals. Figure 3 The diagram illustrates the time required for switching between high and low voltage due to delays, etc. The signal output from the light-emitting signal stage and the signal input to the start signal input can have a time difference of 1H and the same waveform. The bias control signal generation units (EB2_D) 2004 and 2008 include multiple light-emitting signal stages and are configured such that the output of the previous light-emitting signal stage is transmitted not only through the bias voltage line 179 but also input to the start signal input of the next light-emitting signal stage. Therefore, although the start signal input of the first light-emitting signal stage receives the EB2_FLM signal as the start signal FLM, the start signal inputs of other light-emitting signal stages can also be input with the output of the previous light-emitting signal stage. As a result, the bias control signal generation units (EB2_D) 2004 and 2008 can sequentially output bias control signals EB2(n) with the same waveform every 1H in multiple stages based on the EB2_FLM signal.

[0179] exist Figure 7In this frame, the EB2_FLM signal has EB2_FLTE and EB2_FLWE intervals sequentially, and the reference timing V starts from the beginning of the application of clock signals EM_CLK1 and EM_CLK2. sync The signal initially has an EB2_FLTE interval. During one frame, the EB2_FLTE interval has a high voltage, the EB2_FLWE interval has a low voltage, and the remaining intervals have a high voltage. In an embodiment where the voltages of clock signals EM_CLK1 and EM_CLK2 change every 1H, the EB2_FLTE and EB2_FLWE intervals of the EB2_FLM signal can have widths of 20H and 2H, respectively.

[0180] According to Figure 7 waveform Figure 6 The emitted light signal is described using level operations.

[0181] Since the operation of each signal generator is similar, they are roughly classified into cases where the start signal FLM has a high voltage and cases where it has a low voltage at the light emission signal stage, and the operation according to the voltage level change of the clock signal is described in each classification.

[0182] First, the operation will be described in the case where a high voltage is applied to the start signal input terminal of the light emission signal stage, the clock signal EM_CLK2 input to the first clock input terminal has a high voltage, and the clock signal EM_CLK1 input to the second clock input terminal has a low voltage (hereinafter referred to as the first case).

[0183] Because of the high-voltage clock signal EM_CLK2, transistor T206 is turned off, so the voltage of the first node EM_QB will not change to a low voltage.

[0184] Due to the low-voltage clock signal EM_CLK1, transistors 201 (T201) and 205 (T205) are turned on.

[0185] The high voltage input to the start signal input terminal via transistor T201 is applied to the second node SR_Q and the second-to-first node SR_Q_F, thereby changing the voltage of the second node SR_Q and the voltage of the second-to-first node SR_Q_F to a high voltage. Due to the high voltage of the second-to-first node SR_Q_F, transistor T210 becomes cut off. Furthermore, due to the high voltage of the second node SR_Q, transistors T208, T204, and T203 become cut off.

[0186] Additionally, with transistor T205 (205) turned on, a low voltage VGL is applied to the third node SR_QB and the third (3-1) node SR_QB_F. At this time, since the second node SR_Q has a high voltage, transistor T204 (204) is turned off, thus the voltages of the third node SR_QB and the third (3-1) node SR_QB_F are controlled by transistor T205 and changed to the low voltage VGL.

[0187] Due to the low voltage at the third node SR_QB, transistor T202 (202) is turned on, thus applying a high voltage VGH to the fifth node EMA, which becomes the voltage at one terminal of capacitor Ca203 (203). This prevents the voltages at the second node SR_Q and the second-first node SR_Q_F from decreasing by increasing their high voltage levels. At this time, transistor T203 (203) is in the off state.

[0188] Due to the low voltage at node 3-1 SR_QB_F, transistor 207 T207 is turned on. Because transistor 207 T207 is turned on, the clock signal EM_CLK2, which is applied at node 4 EM_C, is high. As a result, capacitor 202 Ca202 is applied with a high voltage (node ​​4 EM_C) and a low voltage (node ​​3-1 SR_QB_F). Furthermore, although transistor 207 T207 is turned on, transistor 206 T206 is turned off, thus the voltage at node 1 EM_QB remains unchanged. Also, because transistor 208 T208 is turned off, the voltage at node 1 EM_QB does not change to the high voltage VGH and remains at its previous voltage level.

[0189] That is, when the light-emitting signal stage is in the first case, the voltage of the first node EM_QB remains unchanged, maintaining the previous voltage level. As an example, when the light-emitting signal stage outputs a high voltage VGH through transistor T209, it can continuously output a high voltage VGH. At this time, since the second node SR_Q and the second-1 node SR_Q_F have high voltages, a low voltage is not output through transistor T210.

[0190] The second case of the light emission signal stage will be described. That is, the operation will be described when a high voltage is applied to the start signal input terminal of the light emission signal stage, the clock signal EM_CLK2 input to the first clock input terminal has a low voltage, and the clock signal EM_CLK1 input to the second clock input terminal has a high voltage (hereinafter referred to as the second case).

[0191] First, transistors 201 (T201) and 205 (T205) are turned off due to the high-voltage clock signal EM_CLK1.

[0192] Transistor T201 (201) is turned off, thus keeping the voltages of the second node SR_Q and the second-to-first node SR_Q_F unchanged. Similarly, transistor T205 (205) is turned off, thus keeping the voltages of the third node SR_QB and the third-to-first node SR_QB_F unchanged.

[0193] Additionally, due to the low-voltage clock signal EM_CLK2, transistor T206 (206th transistor) is turned on. At this time, transistor T207 (207th transistor) is turned on by the voltage of node SR_QB_F (3-1), i.e., the voltage stored in capacitor Ca202 (202nd capacitor). As a result, the low-voltage clock signal EM_CLK2 is applied to node EM_QB, changing it to a low voltage.

[0194] Therefore, when the light emission signal stage is in the second case, the voltage of the first node EM_QB changes to a low voltage, thereby starting the output of the high voltage VGH through the 209th transistor T209.

[0195] In addition, since the second node SR_Q and the second-1st node SR_Q_F retain the previously stored voltages, the 210th transistor T210 continues the previous operation and does not output a low voltage.

[0196] The third case of the light emission signal stage will be described. That is, the operation will be described in the case where a low voltage is applied to the start signal input terminal of the light emission signal stage, the clock signal EM_CLK2 input to the first clock input terminal has a high voltage, and the clock signal EM_CLK1 input to the second clock input terminal has a low voltage (hereinafter referred to as the third case).

[0197] Because of the high-voltage clock signal EM_CLK2, transistor T206 is turned off, thus preventing the voltage of the first node EM_QB from changing to a low voltage.

[0198] Due to the low-voltage clock signal EM_CLK1, transistors 201 (T201) and 205 (T205) are turned on.

[0199] The low voltage input to the start signal input terminal via transistor T201 is applied to the second node SR_Q and the second-to-first node SR_Q_F, thereby changing the voltage of the second node SR_Q and the voltage of the second-to-first node SR_Q_F to a low voltage. Due to the low voltage of the second-to-first node SR_Q_F, transistor T210 becomes turned on and begins to output a low voltage VGL.

[0200] Furthermore, due to the low voltage of the second node SR_Q, transistors 208 (T208), 204 (T204), and 203 (T203) become conductive. Since transistor T208 is conductive, the voltage of the first node EM_QB changes to a high voltage VGH, thus transistor T209 becomes cut off.

[0201] Additionally, since transistor T205 (205th transistor) is turned on, a low voltage VGL is applied to the third node SR_QB and the third-to-first node SR_QB_F. At this time, transistor T204 (204th transistor) is also turned on due to the low voltage of the second node SR_Q. Thus, the voltages of the third node SR_QB and the third-to-first node SR_QB_F are controlled by transistors T205 (205th transistor) and T204 (204th transistor), and are changed to the low voltage VGL.

[0202] Due to the low voltage at the third node SR_QB, transistor T202 (202) is turned on, and due to the low voltage at the second node SR_Q, transistor T203 (203) is turned on. This results in a high voltage VGH and clock signal EM_CLK2 being applied to the fifth node EMA (205). Consequently, the voltage at one terminal of capacitor Ca203 (203) becomes high, and it serves to store and maintain the low voltages at the second node SR_Q and the second-first node SR_Q_F (2-1).

[0203] Due to the low voltage at node 3-1 SR_QB_F, transistor 207 T207 is turned on. However, because transistor 206 T205 is turned off, the voltage at node 1 EM_QB remains unchanged.

[0204] That is, when the light emission signal stage is the third case, the voltage of the first node EM_QB changes to a high voltage VGH, so the 209th transistor T209 does not operate, and the voltage of the second node SR_Q and the voltage of the 2-1th node SR_Q_F change to a low voltage, so that the low voltage VHL starts to be output through the 210th transistor T210.

[0205] The fourth case of the light emission signal stage will be described. That is, the operation will be described when a low voltage is applied to the start signal input terminal of the light emission signal stage, the clock signal EM_CLK2 input to the first clock input terminal has a low voltage, and the clock signal EM_CLK1 input to the second clock input terminal has a high voltage (hereinafter referred to as the fourth case).

[0206] First, due to the high-voltage clock signal EM_CLK1, transistors 201 (T201) and 205 (T205) are turned off.

[0207] Transistor T201 (201) is turned off, thus keeping the voltages of the second node SR_Q and the second-to-first node SR_Q_F unchanged. Similarly, transistor T205 (205) is turned off, thus keeping the voltages of the third node SR_QB and the third-to-first node SR_QB_F unchanged.

[0208] Additionally, due to the low-voltage clock signal EM_CLK2, transistor 206 T206 is turned on. At this time, transistor 207 T207 is turned on through the voltage of node 3-1 SR_QB_F (i.e., the voltage stored in capacitor 202 Ca202). As a result, although a low-voltage clock signal EM_CLK2 can be applied, transistor 208 remains turned on due to the low voltage of the second node SR_Q, so the first node EM_QB is continuously subjected to a high voltage VGH without voltage fluctuation.

[0209] Therefore, in the case where the light emission signal stage is the fourth case, since the voltage of the first node EM_QB remains high, the 209th transistor T209 does not operate, and the voltage of the second node SR_Q and the voltage of the 2-1th node SR_Q_F remain at the previously stored low voltage. Therefore, the 210th transistor T210 continues to perform the previous operation and outputs a low voltage.

[0210] Through the basic operation described above, the signal input to the input terminal can be delayed by 1H before being output.

[0211] Figure 7 V in sync This indicates the positions where clock signals EM_CLK1 and EM_CLK2 are first applied in the light-emitting display device, and the illustration shows that the EM1_FLM signal is directly subjected to a high voltage. However, according to an embodiment, V sync The position can be varied. However, the ESR signal is located before the applied clock signals EM_CLK1 and EM_CLK2, that is, compared to V. sync Located on the left.

[0212] Figure 7 The illustration shows a scenario where, if clock signals EM_CLK1 and EM_CLK2 are initially applied, the clock signal EM_CLK2 input to the first clock input terminal starts at a high voltage and is alternately applied with low / high voltage, while the clock signal EM_CLK1 input to the second clock input terminal starts at a low voltage and is alternately applied with high / low voltage, and the voltages of clock signals EM_CLK1 and EM_CLK2 change every 1H. However, according to an embodiment, the initial voltages may be different, or the range of variation may be different.

[0213] The following uses Figures 8 to 10 For the actual formation on the substrate, such as Figure 6 The emitted light signal is described using a stage structure.

[0214] Figure 8 This is an illustration showing the arrangement of two stages of the light emission control signal generation unit in an inverted configuration according to one embodiment. Figure 9 and Figure 10 It is along Figure 8 The sectional view cut by the intercept lines IX-IX and XX.

[0215] Reference Figure 8 The diagram illustrates a structure where two light-emitting signal stages share an input signal line and are arranged on the left and right sides.

[0216] For reference, Figure 8 In the diagram, the marking with an 'x' inside the quadrilateral indicates an opening in the insulating film, allowing the upper conductive layer to be electrically connected to the lower conductive layer.

[0217] Since the light emission signal generation stage can be respectively included in the first light emission control signal generation unit (EM1_D) 2001, 2005, the second light emission control signal generation unit (EM2_D) 2002, 2006, the initialization control signal generation unit (EB1_D) 2003, 2007, and the bias control signal generation unit (EB2_D) 2004, 2008, the four generation units can be separated in pairs, thus achieving the desired effect. Figure 8 As shown, they are configured to share signal lines and located on the left and right sides. According to the embodiment, the light emission signal stages belonging to the first light emission control signal generation units (EM1_D) 2001 and 2005 and the light emission signal stages belonging to the second light emission control signal generation units (EM2_D) 2002 and 2006 can share signal lines with each other, and the light emission signal stages belonging to the initialization control signal generation units (EB1_D) 2003 and 2007 and the light emission signal stages belonging to the bias control signal generation units (EB2_D) 2004 and 2008 can share signal lines with each other.

[0218] exist Figure 8 In this embodiment, there are three shared signal lines: ESR wiring 2105, which is subject to ESR signal, first clock wiring 2104, which is subject to CLK2 clock signal, and second clock wiring 2103, which is subject to CLK1 clock signal.

[0219] Located in Figure 8 The structure can be described using the level as the center for the light emission signal on the left side as follows.

[0220] as Figure 10The transistors shown, in the light-emitting signal stage, each transistor includes a semiconductor layer, a first gate insulating film 141, and a gate electrode located above the substrate 110. A channel is arranged in the overlapping portion of the semiconductor layer and the gate electrode, and source and drain regions, which are conductive by plasma treatment or doping, are arranged on both sides of the channel in the semiconductor layer. The layered structure includes the substrate 110, the semiconductor layer, the first gate insulating film 141, the first gate conductive layer, the second gate insulating film 142, the second gate conductive layer, the first interlayer insulating film 143, the source / drain conductive layer, and the second interlayer insulating film 144. The first gate conductive layer includes the gate electrodes of all transistors.

[0221] The gate electrode G201 of transistor T201 extends and is electrically connected to the second clock wiring 2103 to which the clock signal CLK1 is applied. A channel, a source region, and a drain region are arranged in the semiconductor layer C201. One side of the semiconductor layer C201 is electrically connected to a connection line 2205 that transmits the start signal FLM or the output of the previous light-emitting stage, and the other side is connected to a connection portion 2301 electrically connected to the gate electrode G204 of transistor T204. The connection portion 2301 is located in the source / drain conductive layer.

[0222] The gate electrode G202 of transistor T202 extends and is electrically connected to the connection portion 2302 connecting transistor T204 and transistor T211. One side of semiconductor layer C202 is electrically connected to the high-voltage wiring 2101 to which a high voltage VGH is applied, and the other side is electrically connected to the connection portion 2303 electrically connected to capacitor Ca203. The connection portion 2303 is located in the source / drain conductive layer. Both ends of semiconductor layer C202 extend and are connected to the semiconductor layer C203 of transistor T203, the semiconductor layer C208 of transistor T208, the semiconductor layer C213 of transistor T213, and the semiconductor layer C212 of transistor T212.

[0223] The gate electrode G203 of transistor T203 extends to form one electrode of capacitor Ca203, and further extends to the gate electrode of transistor T210. One side of semiconductor layer C203 is connected to connection portion 2303, thereby also connecting to one side of transistor T202, and the other side is electrically connected to connection portion 2304, which is electrically connected to transistor T207. Connection portion 2304 is located in the source / drain conductive layer.

[0224] The gate electrode G204 of transistor T204 consists of two parts and extends to the gate electrode G208 of transistor T208. It is electrically connected to one side of transistor T212 and one side of transistor T213 via connection portion 2305. One side of semiconductor layer C204 is connected to one side of transistor T201 via connection portion 2301, and the other side is electrically connected to one end of transistor T205 and transistor T211 via connection portion 2306. Connection portions 2305 and 2306 are located in the source / drain conductive layer.

[0225] The gate electrode G205 of transistor T205 extends and is electrically connected to the second clock wiring 2103 to which the clock signal CLK1 is applied. One side of semiconductor layer C205 is electrically connected to low-voltage wiring 2102 to which a low voltage VGL is applied, and the other side is electrically connected to one end of transistor T204 and transistor T211 via connection portion 2306.

[0226] The gate electrode G206 of transistor T206 extends and is electrically connected to the first clock wiring 2104 to which the clock signal CLK2 is applied, and is connected to the connection portion 2304 and is electrically connected to one end of transistors T203 (203) and T207 (207). One side of semiconductor layer C206 is connected to the connection portion 2307 and is connected to one side of transistor T208 (208), while the other side is electrically connected to one side of transistor T207 (207) and capacitor Ca202 (202) via the connection portion 2308. Connection portions 2307 and 2308 are located in the source / drain conductive layer.

[0227] The gate electrode G207 of transistor T207 extends to form one electrode of capacitor Ca202 of transistor T202, and also extends to the other side to connect with connection portion 2309, thereby connecting with one end of transistor T211 of transistor T211. One side of semiconductor layer C207 is connected to connection portion 2304 and is connected to the gate electrode G206 of transistor T206 of transistor T206 and one end of transistor T203 of transistor T203. The other side is connected to connection portion 2308 and is electrically connected to one side of transistor T206 of transistor T206 and capacitor Ca202 of transistor T202.

[0228] The gate electrode G208 of transistor T208 extends to the gate electrode G204 of transistor T204, and is electrically connected to one side of transistor T212 and one side of transistor T213 via connection portion 2305. One side of semiconductor layer C208 is connected to one side of transistor T206 via connection portion 2307, and the other side is electrically connected to high-voltage wiring 2101 to which a high voltage VGH is applied, and extends to one end of transistor T202 and transistor T213.

[0229] The gate electrode G209 of transistor T209 is divided into multiple ( Figure 11 The semiconductor layer C209 is constructed using three gate electrodes and extends to connect to the 201st capacitor Ca201. One side of the semiconductor layer C209 is electrically connected to the high-voltage wiring 2101, and the other side is connected to the output wiring 2201.

[0230] The gate electrode G210 of transistor T210 is divided into multiple ( Figure 11 The semiconductor layer C210 is constructed using three gates and extends to connect to one end of the 203rd capacitor Ca203 and the 212th transistor T212. One side of the semiconductor layer C210 is electrically connected to one side 2102-1 of the low-voltage wiring 2102, and the other side is connected to the output wiring 2201.

[0231] The output wiring 2201 is electrically connected to the connection line 2202 extending to the signal line, and the connection line 2202 is formed on the second gate conductive layer.

[0232] The gate electrode G211 of transistor T211 extends through the gate electrode G212 of transistor T212 and is electrically connected to the low-voltage wiring 2102. One side of semiconductor layer C211 is connected to connection portion 2309 and connected to one end of transistor T207, and the other side is connected to connection portion 2302 and connected to one end of transistor T204 and transistor T205.

[0233] The gate electrode G212 of transistor T212 extends and is electrically connected to low-voltage wiring 2102. One side of semiconductor layer C212 is electrically connected to the gate electrode G210 of transistor T210, and the other side extends and is connected to semiconductor layer C213 of transistor T213. It is also connected to the connection portion 2305 and connected to the gate electrodes of transistor T204 and transistor T208.

[0234] The gate electrode G213 of transistor T213 extends and is electrically connected to ESR wiring 2105. One side of semiconductor layer C213 is electrically connected to high voltage wiring 2101, and the other side extends and is connected to semiconductor layer C213 of transistor T212.

[0235] Capacitors Ca201, Ca202, and Ca203 have a first gate conductive layer and a second gate conductive layer as two electrodes, and a second gate insulating film 142 located between them serves as the cross-sectional structure of the dielectric.

[0236] One electrode 2212 of capacitor Ca201 is connected to high-voltage wiring 2101, and the other electrode 2211 extends to be connected to the gate electrode G209 of transistor T209, transistor T206, and one end of transistor T208.

[0237] One electrode 2222 of capacitor Ca202 is connected to one end of transistors T206 and T207 via connection portion 2308, and the other electrode 2221 extends to be connected to the gate electrode G207 of transistor T207.

[0238] One electrode 2232 of capacitor Ca203 is connected to one end of transistors T202 and T203 via connection portion 2303, and the other electrode 2231 extends to connect to the gate electrode G203 of transistor T203 and the gate electrode G210 of transistor T210. According to an embodiment, the connection electrode SD212 connecting the other electrode 2231 to semiconductor layer C212 can be located on the first interlayer insulating film 143.

[0239] exist Figure 8 In this embodiment, there are three shared signal lines: ESR wiring 2105, to which the ESR signal is applied; first clock wiring 2104, to which the CLK2 clock signal is applied; and second clock wiring 2103, to which the CLK1 clock signal is applied. Furthermore, in Figure 8 In the embodiment, the first clock wiring 2104 and the second clock wiring 2103 are formed on the source / drain conductive layer and are formed as a single layer.

[0240] However, according to the embodiment, the first clock wiring 2104 and the second clock wiring 2103 can also be formed as a double layer. This can be achieved through... Figures 11 to 13 Describe it.

[0241] Figure 11 This is an arrangement diagram illustrating the two inverted stages of the light emission control signal generation unit according to another embodiment. Figure 12 and Figure 13It is along Figure 11 The sectional view taken by the intercept lines XII-XII and XIII-XIII.

[0242] For reference, Figure 11 In the diagram, the marking with an 'x' inside the quadrilateral indicates an opening in the insulating film, allowing the upper conductive layer to be electrically connected to the lower conductive layer.

[0243] With Figures 8 to 10 The different aspects of the embodiments are described as follows.

[0244] exist Figures 11 to 13 In some embodiments, a second source / data conductive layer is further included. Consequently, an organic protective film 145 covering the second source / data conductive layer is also further included.

[0245] That is, the layered structure is composed of a substrate 110, a semiconductor layer, a first gate insulating film 141, a first gate conductive layer, a second gate insulating film 142, a second gate conductive layer, a first interlayer insulating film 143, a source / drain conductive layer (also called a first source / drain conductive layer), a second interlayer insulating film 144, a second source / data conductive layer, and an organic protective film 145.

[0246] In this embodiment, the first clock wiring 2104 and the second clock wiring 2103 are located in the first source / drain conductive layer. The first-second clock wiring 2253 and the second-second clock wiring 2254 are located in the second source / data conductive layer and are electrically connected to the first clock wiring 2104 and the second clock wiring 2103, respectively.

[0247] like Figures 11 to 13 As shown, when the clock wiring is formed as a double layer, the resistance is less than that when it is formed as a single layer, thus having the advantage of reducing RC delay.

[0248] exist Figures 8 to 13 In the embodiments described, an example is described whereby the signal lines shared between two adjacent light-emitting signal stages are ESR wiring 2105, first clock wiring 2104, and second clock wiring 2103.

[0249] However, according to the embodiments, the number of signal lines between two adjacent light-emitting signals can be more or less.

[0250] The following is through Figure 14 An embodiment in which two adjacent light-emitting signals share a total of four input signal lines is described.

[0251] Figure 14 This is a simplified illustration of a structure in which two stages of the light emission control signal generation unit are connected together to the input signal line according to another embodiment.

[0252] exist Figure 14 The illustration shows an embodiment in which two adjacent light emission signal generators are respectively included in the first light emission control signal generator (EM1_D) 2001 and the second light emission control signal generator (EM2_D) 2002.

[0253] Furthermore, in Figure 14 In addition, a low-voltage wiring 2102 is added as an input signal line shared by the light-emitting signal stages. That is, the illustration shows the case where two adjacent light-emitting signal stages share the low-voltage wiring 2102, ESR wiring 2105, first clock wiring 2104 and second clock wiring 2103.

[0254] Although Figure 14 The illustration shows a case where the light emission signal stages, including the first light emission control signal generation unit (EM1_D) 2001 and the second light emission control signal generation unit (EM2_D) 2002, share input signal lines with each other. However, according to the embodiment, the light emission signal stages belonging to the initialization control signal generation units (EB1_D) 2003, 2007 and the bias control signal generation units (EB2_D) 2004, 2008 can also share input signal lines with each other.

[0255] Furthermore, the light emission signal stage can share the input signal line on both the left and right sides of the display area DA.

[0256] If, as described above, two adjacent light-emitting signal stages share the input signal line with each other, the width occupied by the driving sections 200 and 250 can be reduced, resulting in the advantage that the area of ​​the driving sections 200 and 250 is also reduced.

[0257] The above, through Figures 6 to 14 The signal generation unit, including the first stage (the stage for emitting light signals), has been described below. Figures 15 to 20 The scanning signal generation unit, including the second stage (also known as the scanning signal generation stage), is described.

[0258] Figure 2 The pixel in the diagram needs to receive the first scan signal GW(n) and the second scan signal GC(n) from two scan signal generation units (first scan signal generation units (GW_D) 3001, 3003, and second scan signal generation units (GC_D) 3002, 3004). Therefore, the following... Figures 15 to 20 The description is centered on the scanning signal level.

[0259] First, through Figure 15 The circuit configuration of a scanning signal is described using stages.

[0260] Figure 15This is a circuit diagram illustrating one stage of the scanning signal generation unit in the driving section of the non-display area according to an embodiment.

[0261] According to this embodiment, each scanning signal stage 3000 includes a high-level output section 3551, a low-level output section 3552, a first node first control section 3555, a first node second control section 3556, a second node first control section 3553, a second node second control section 3554, and a first connection section 3557.

[0262] The core structure of each scanning signal stage is described as follows.

[0263] The high-level output section 3551 outputs the high voltage VGH of the scan signal, and the low-level output section 3552 outputs the low voltage VGL of the scan signal. Both the high-level output section 3551 and the low-level output section 3552 are connected to the output terminal Out. When the high-level output section 3551 outputs the high voltage VGH, the low-level output section 3552 does not output; conversely, when the low-level output section 3552 outputs the low voltage VGL, the high-level output section 3551 does not output.

[0264] The high-level output unit 3551 is controlled according to the voltage of the first node QB, and the voltage of the first node QB is controlled by the first node first control unit 3553 and the first node second control unit 3556.

[0265] The low-level output unit 3552 is controlled according to the voltage of the second node Q, which is controlled by the first control unit 3555 and the second control unit 3554 of the second node. Specifically, the low-level output unit 3552 is connected to the second node Q through the first connection unit 3557, and is thus controlled according to the voltage of the second-first node QF. However, since the 308 transistor T308 included in the first connection unit 3557 remains in an on state by receiving a low voltage VGL through the control terminal, the low-level output unit 3552 is actually controlled according to the voltage of the second node Q.

[0266] Figure 15 The scan signal receives two clock signals CLK1 and CLK2 at the stage, and the scan signal for the next row is connected at the stage by exchanging the two clock signals. Furthermore, although... Figure 15 The scan signal stage is illustrated as receiving the start signal (FLM signal) through the input terminal, but in the presence of a preceding scan signal stage (the previous scan signal stage), the output of the preceding scan signal stage can be input to the input terminal.

[0267] The following is a detailed description of each part of each scanning signal stage.

[0268] The high-level output section 3551 includes a 306th transistor T306 and a 301st capacitor Ca301. The gate electrode of the 306th transistor T306 is connected to the first node QB, the input electrode is connected to the high-voltage VGH terminal, and the output electrode is connected to the output terminal Out. As a result, when the voltage of the first node QB is low, the high voltage VGH is output through the output terminal Out; when the voltage of the first node QB is high, the 306th transistor T306 is turned off and does not output any voltage. One end of the 301st capacitor Ca301 is supplied with the high voltage VGH, and the other end is connected to the first node QB, thereby maintaining the voltage of the first node QB.

[0269] The low-level output section 3552 includes a 307th transistor T307 and a 302nd capacitor Ca302. The gate electrode of the 307th transistor T307 is connected to the 2-1st node QF, the input electrode is connected to the first input terminal to which the first clock signal CLK1 is applied, and the output electrode is connected to the output terminal Out. Therefore, when the voltage of the 2-1st node QF is low, the voltage of the first clock signal CLK1 is output through the output terminal Out; when the voltage of the 2-1st node QF is high, the 307th transistor T307 does not output any voltage. Here, to make the 2-1st node QF low, the second node Q needs to receive a low voltage as a start signal FLM, and the low voltage applied to the 2-1st node QF is stored in the 302nd capacitor Ca302. At this time, the voltage of the first clock signal CLK1 is output through the output terminal Out. The transistor T308 included in the first connection section 3557 remains on by receiving a low voltage VGL at its control terminal, thus the voltage of the second-1 node QF is the same as the voltage of the second node Q. Therefore, the low-level output section 3552 is controlled by the second node SR_Q. One end of the capacitor Ca302 (302) is connected to the output terminal Out, and the other end is connected to the second-1 node QF, thereby storing and maintaining the voltage of the second-1 node QF.

[0270] The first control unit 3555 and the second control unit 3556 of the first node, which control the voltage of the first node QB, are described.

[0271] The first node first control unit 3555 includes a third transistor T304. The gate of the third transistor T304 is connected to the second node Q, the input electrode is connected to the first input terminal to which the second clock signal CLK2 is applied, and the output electrode is connected to the first node QB. As a result, the voltage of the first node QB is changed according to the voltage control of the second node Q, and in this embodiment, the voltage of the first node QB is changed to the high voltage of the clock signal.

[0272] The first node second control unit 3556 includes a 305th transistor T305. The gate electrode of the 305th transistor T305 is connected to the first input terminal to which a second clock signal CLK2 is applied, the input electrode receives a low voltage VGL, and the output electrode is connected to the first node QB. As a result, the voltage of the first node QB is changed to the low voltage VGL according to the second clock signal CLK2 input to the first input terminal.

[0273] The first control unit 3553 and the second control unit 3554 of the second node, which control the voltage of the second node Q, are described.

[0274] The second node first control unit 3553 includes a 301st transistor T301. The gate electrode of the 301st transistor T301 is connected to the first input terminal to which the second clock signal CLK2 is applied, its input electrode is connected to the start signal input terminal (the input terminal of the output of the start signal FLM or the previous scan signal stage), and its output electrode is connected to the second node Q. The 301st transistor T301 can be constructed using two transistors, whose gate electrodes can be connected to the first input terminal. One transistor's input electrode is connected to the start signal input terminal, and the other transistor's output electrode is connected to the second node Q. Furthermore, the output electrode of one transistor and the input electrode of the other transistor are connected to each other. As a result, the voltage of the second node Q is changed to the voltage input to the start signal input terminal according to the second clock signal CLK2 input to the first input terminal.

[0275] The second node's second control unit 3554 includes a 302nd transistor T302 and a 303rd transistor T303. The gate electrode of the 302nd transistor T302 is connected to the first node QB, its input electrode receives a high voltage VGH, and its output electrode is connected to the input electrode of the 303rd transistor T303. The gate electrode of the 303rd transistor T303 is connected to the second input terminal to which a first clock signal CLK1 is applied, and its input electrode is connected to the output electrode of the 302nd transistor T302, which is connected to the second node Q. Consequently, when the voltage of the first node QB is low and the first clock signal CLK1 is low, the voltage of the second node Q becomes a high voltage VGH. Therefore, when the voltage of the first node QB is low (VGL), the voltage of the second node Q has a high voltage VGH value.

[0276] Unlike the above description, the input and output electrodes can be named in reverse order, depending on the magnitude of the connected voltage.

[0277] Having such as Figure 15 The scanning signal stage, which is composed of a circuit, determines the operation based on the signals applied to the two clock input terminals and the start signal input terminal, respectively, of the two clock signals.

[0278] First, through Figure 16 The operation of the scan signal generation stages included in the first scan signal generation units (GW_D) 3001, 3003 and the second scan signal generation units (GC_D) 3002, 3004 will be described. Figure 3 When the signals shown are applied to the pixel, the first scan signal GW(n) and the second scan signal GC(n) are generated.

[0279] Figure 16 It is based on the diagram. Figure 15 The waveform diagram of the input signal applied by the scanning signal generation unit in the embodiment.

[0280] exist Figure 16 The diagram illustrates the start signal GW_FLM and clock signals GW_CLK1 and GW_CLK2 applied to the first scan signal generation units (GW_D) 3001 and 3003, and the start signal GC_FLM and clock signals GC_CLK1, GC_CLK2, GC_CLK3, GC_CLK4, GC_CLK5, and GC_CLK6 applied to the second scan signal generation units (GC_D) 3002 and 3004. Figure 16 In the embodiments, even if the first scan signal generation unit (GW_D) 3001, 3003 and the second scan signal generation unit (GC_D) 3002, 3004 include Figure 15 The scan signal stages with the same circuit structure shown do not have the same clock signal. As a result, the scan signal stages included in the first scan signal generation unit (GW_D) 3001, 3003 and the second scan signal generation unit (GC_D) 3002, 3004 cannot share clock signals with each other.

[0281] When the scan signal generation stage is used as the first scan signal generation unit (GW_D) 3001, 3003, in order to generate Figure 3 The first scan signal GW(n), GW_FLM signal, is input to the start signal input terminal of the scan signal stage as the start signal FLM. (Similar to...) Figure 3 The first scan signal GW(n) shown is... Figure 16 The GW_FLM signal has a low voltage only during period 1H in a frame, and a high voltage for the rest of the interval. Figure 3The diagram illustrates the time required for switching between high and low voltage due to delays, etc. The signal output from the scan signal stage and the signal input to the start signal input can have a time difference of 1H and the same waveform. The first scan signal generation units (GW_D) 3001 and 3003 include multiple scan signal stages and are configured such that the output of the previous scan signal stage is transmitted not only through the first scan line 151 but also input to the start signal input of the next scan signal stage. Therefore, although the start signal input of the first scan signal stage receives the GW_FLM signal as the start signal FLM, the start signal inputs of other scan signal stages can also be input to the output of the previous scan signal stage. As a result, the first scan signal generation units (GW_D) 3001 and 3003 can sequentially output first scan signals GW(n) with the same waveform at 1H intervals in multiple stages based on the GW_FLM signal.

[0282] Reference Figure 16 A frame of GW_FLM signal can sequentially have GW_FLTE and GW_FLWE intervals, corresponding to the reference timing V. sync The matching ground is aligned with the clock signals GW_CLK1 and GW_CLK2, and the GW_FLTE interval starts from the reference timing V. sync Start. During one frame, the GW_FLM signal has a high voltage in the GW_FLTE interval, followed by a temporary low voltage during the GW_FLWE interval. If clock signals GW_CLK1 and GW_CLK2 are applied, the clock signal GW_CLK2 input to the first clock input starts with a high voltage and is alternately applied with low / high voltage, while the clock signal GW_CLK1 input to the second clock input starts with a low voltage and is alternately applied with high / low voltage. The voltages of clock signals GW_CLK1 and GW_CLK2 can be changed every 1H. Figure 16 In the embodiments, the GW_FLTE and GW_FLWE intervals can have widths of 17H and 1H, respectively.

[0283] When the scan signal generation stage is used as the second scan signal generation unit (GC_D) 3002, 3004, in order to generate Figure 3 The second scan signal GC(n), GC_FLM signal, is input to the start signal input terminal of the light emission signal stage as the start signal FLM. Figure 16 The GC_FLM signal is applied Figure 3The second scan signal GC(n) has a low voltage during the second scan signal GC(n) interval and a high voltage during the other intervals. The signal output from the scan signal stage and the signal input to the start signal input can be signals with a time difference of 1H and the same waveform. The second scan signal generation units (GC_D) 3002 and 3004 include multiple scan signal stages and are configured such that the output of the previous scan signal stage is not only transmitted through the second scan line 152, but also input to the start signal input of the next scan signal stage. Therefore, although the start signal input of the first scan signal stage receives the GC_FLM signal as the start signal FLM, the start signal inputs of other scan signal stages are also input with the output of the previous scan signal stage. The second scan signal generation units (GC_D) 3002 and 3004 are as follows Figure 16 Six clock signals GC_CLK1, GC_CLK2, GC_CLK3, GC_CLK4, GC_CLK5, and GC_CLK6 are applied in total, and each clock signal has a 1H difference. Therefore, each pair of the six clock signals has a signal that is out of phase with each other. Furthermore, a pair of clock signals applied to the scan signal stage at this end is applied with a clock signal that is 1H later than a pair of clock signals applied to the scan signal stage at the previous end. As a result, the second scan signal generation units (GC_D) 3002 and 3004 can output a second scan signal GC(n) with the same waveform sequentially at 1H intervals in multiple stages due to the difference in the applied clock signals.

[0284] exist Figure 16 In the middle, a frame of GC_FLM signal has GC_FLTE and GC_FLWE intervals in sequence, and is consistent with the reference time sequence V. sync The ground is aligned with the clock signals GW_CLK1 and GW_CLK2, and the GC_FLTE interval starts from the reference timing V. sync Begin. During one frame, the GC_FLM signal has a high voltage in the GC_FLTE interval, a low voltage in the GC_FLWE interval, and a high voltage again for the remaining interval. Clock signals GC_CLK1 and GC_CLK2 can change their voltage every 3 hours. In the GC_FLM signal, the GC_FLTE and GC_FLWE intervals can have widths of 1 hour and 17 hours, respectively.

[0285] The second scan signal generation units (GC_D) 3002 and 3004 receive six clock signals GC_CLK1, GC_CLK2, GC_CLK3, GC_CLK4, GC_CLK5, and GC_CLK6, and change the voltage level of every two clock signals at the same timing. Hereinafter, two clock signals that are inverted at the same timing to produce different voltages are also referred to as a pair of inverted clock signals.

[0286] Clock signal GC_CLK1 is based on reference timing V sync Starting with a high voltage, after passing through the GC_SCTE1 interval, a low / high voltage is alternately applied, with the clock signal GC_CLK2 based on the reference timing V. sync Starting with a low voltage, high / low voltages are applied alternately after passing through the GC_SCTE1 interval. In the clock signal GC_CLK2, based on the reference timing V... sync The timing sequence for the first low voltage occurs after passing through the GC_SCTE2 interval.

[0287] Clock signal GC_CLK3 is based on reference timing V sync Starting with a high voltage, after passing through the GC_SCTE3 interval, a low / high voltage is alternately applied, with the clock signal GC_CLK4 based on the reference timing V. sync Starting with a low voltage, high / low voltages are applied alternately after passing through the GC_SCTE3 interval. In clock signal GC_CLK4, based on reference timing V... sync The timing sequence for the first low voltage occurs after passing through the GC_SCTE4 interval.

[0288] Clock signal GC_CLK5 is based on reference timing V sync Starting with a high voltage, after passing through the GC_SCTE5 interval, a low / high voltage is alternately applied, with the clock signal GC_CLK6 based on the reference timing V. sync Starting with a low voltage, high / low voltages are applied alternately after passing through the GC_SCTE5 interval. In clock signal GC_CLK6, based on reference timing V... sync The timing sequence for the first low voltage occurs after passing through the GC_SCTE5 interval.

[0289] The six clock signals GC_CLK1, GC_CLK2, GC_CLK3, GC_CLK4, GC_CLK5, and GC_CLK6 can have their voltages changed every GC_SCWE. In this embodiment, GC_SCWE can have a length of 3H. Figure 16 In the embodiments, the intervals GC_SCTE1, GC_SCTE2, GC_SCTE3, GC_SCTE4, GC_SCTE5, and GC_SCTE6 can have widths of 1H, 4H, 2H, 5H, 3H, and 6H, respectively.

[0290] Only one pair of inverted clock signals (two clock signals) from six clock signals GC_CLK1, GC_CLK2, GC_CLK3, GC_CLK4, GC_CLK5, and GC_CLK6 are applied to a scan signal stage included in the second scan signal generation unit (GC_D) 3002 and 3004. Hereinafter, the description will focus on the scan signal stage that receives GC_CLK1 and GC_CLK2.

[0291] According to Figure 16 waveform Figure 15 The emitted light signal is described using level operations.

[0292] The operation of the scanning signal using stages is described in simple terms as follows.

[0293] The output of the output terminal OUT is determined by the operation of transistors 306 (T306) and 307 (T307).

[0294] In transistor T306 (306) that outputs a high voltage VGH, when transistor T305 (305) is turned on, the first node QB has a low voltage VGL, and a high voltage VGH is output through the output terminal OUT. Transistor T305 (305) will only turn on when the second clock signal CLK2 applied to the first input terminal has a low voltage. Therefore, if the second clock signal CLK2 applied to the first input terminal has a low voltage, the scan signal stage outputs a high voltage VGH.

[0295] Additionally, when the second clock signal CLK2 is low, transistor 301 T301 is also turned on, so the output of the start signal FLM or the previous scan signal stage is transmitted to the second node Q and the 2-1 node QF and stored in capacitor 302 Ca302. At this time, if the output of the start signal FLM or the previous scan signal stage has a high voltage, transistor 307 T307 is not turned on and does not operate. However, if the output of the start signal FLM or the previous scan signal stage has a low voltage, transistor 307 T307 is turned on and outputs the first clock signal CLK1. However, if the second clock signal CLK2 has a low voltage, a high voltage VGH is applied by transistor 306 T306, so the output terminal OUT of the scan signal stage has a high voltage. However, if the second clock signal CLK2 has a high voltage, transistor 307 T307 will turn on according to the low voltage stored in capacitor 302 Ca302 at this time, and output the first clock signal CLK1 at this time (i.e., low voltage).

[0296] Therefore, in the scan signal stage, the start signal FLM or the output of the previous scan signal stage is stored in capacitor Ca302 (302) when the second clock signal CLK2 is low, and outputs a low-voltage first clock signal CLK1 through transistor T307 (307) when the second clock signal CLK2 is high. Thus, compared to the previous scan signal stage, the output delay is equivalent to a signal width of one clock signal, GW_SCWE, or GC_SCWE.

[0297] As mentioned above, according to Figure 16 The input signal shown is Figure 3 The signal shown is applied to the pixel.

[0298] according to Figure 16 Even if the first scan signal generation unit (GW_D) 3001, 3003 and the second scan signal generation unit (GC_D) 3002, 3004 include Figure 15 The scan signal stages with the same circuit structure shown cannot share a clock signal with adjacent scan signal stages because their clock signals are different. That is, even if the scan signal stages belonging to the first scan signal generation units (GW_D) 3001, 3003 and the scan signal stages belonging to the second scan signal generation units (GC_D) 3002, 3004 are arranged adjacent to each other, separate clock signal lines are required due to the different clock signals. Therefore, it is impossible to reduce the width / area of ​​the drive units 200, 250 by reducing the number of clock signal lines in the first scan signal generation units (GW_D) 3001, 3003 and the second scan signal generation units (GC_D) 3002, 3004. However, as with reference to... Figures 7 to 13 As described above, since the light emission signal generation stages included in the first light emission control signal generation units (EM1_D) 2001, 2005, the second light emission control signal generation units (EM2_D) 2002, 2006, the initialization control signal generation units (EB1_D) 2003, 2007, and the bias control signal generation units (EB2_D) 2004, 2008 belonging to the drive units 200, 250 can share input signal lines (clock signal lines, etc.), the overall width / area of ​​the drive units 200, 250 is reduced.

[0299] However, according to the embodiment, the first scan signal generation units (GW_D) 3001, 3003 and the second scan signal generation units (GC_D) 3002, 3004 may also share the input signal line. Hereinafter, through... Figure 17 and Figure 18An example of the signal applied to the pixel and the input signal applied to the scan signal generation unit in an embodiment where the scan signal generation units (GW_D) 3001, 3003 and GC_D 3002, 3004 can share the input signal line (clock signal line, etc.) is described.

[0300] Figure 17 The illustration shows the application of an object according to yet another embodiment. Figure 2 Waveform diagrams of multiple signals of the pixels and the voltage waveform of the G node based thereon. Figure 18 This diagram is for generating Figure 17 The waveform of the input signal applied to the scanning signal generation stage by the signal.

[0301] exist Figure 3 In one embodiment, the first scan signal GW(n) applies a low voltage once in a frame, and the second scan signal GC(n) has three low voltages in a frame. However, according to the embodiment, it is not limited to this; the two scan signals may have the same number of low voltages during a frame. Figure 17 The diagram illustrates an example where two scan signals apply a low voltage once within a frame.

[0302] First of all, Figure 17 In, with Figure 3 Unlike other signals, the second scan signal GC(n) can change to a low voltage only once during a frame, and the length of the interval during which the change occurs is 1H.

[0303] In order to generate as described above Figure 17 The second scan signal GC(n), and Figure 16 Different, only apply Figure 18 The start signal GC_FLM and two clock signals CLK1 and CLK2.

[0304] Two clock signals, CLK1 and CLK2, are jointly input to the scan signal stages included in the first scan signal generation units (GW_D) 3001 and 3003 and the second scan signal generation units (GC_D) 3002 and 3004. As a result, the scan signal stages belonging to the first scan signal generation units (GW_D) 3001 and 3003 and the scan signal stages belonging to the second scan signal generation units (GC_D) 3002 and 3004 can share the input signals of the two clock signals, CLK1 and CLK2, etc.

[0305] Figure 18 The scan signal used to generate the second scan signal GC(n) can be operated in the same way as the scan signal stage. Figure 16The operation of the scanning signal stage used to generate the first scanning signal GW(n) described in the previous section is essentially the same, so the description is omitted.

[0306] exist Figure 17 and Figure 18 In one embodiment, the following is illustrated: Figure 3 In one embodiment, the second scan signal GC(n) is matched with the first scan signal GW(n), but in another embodiment, conversely, the second scan signal GC(n) can be matched with the first scan signal GW(n). Figure 3 The first scan signal GW(n) is matched with the second scan signal GC(n) and thus changed to be applied three times in one frame.

[0307] The following is through Figure 19 and Figure 20 The structure is described in detail when two adjacent scan signals share the signal lines of two clock signals CLK1 and CLK2 applied between the two scan signal stages.

[0308] Figure 19 This is an arrangement diagram illustrating a structure in which two stages of the scan signal generation unit are arranged in reverse order according to one embodiment. Figure 20 It is along Figure 19 The sectional view taken by section line XX-XX.

[0309] For reference, Figure 19 In the diagram, the marking with an 'x' inside the quadrilateral indicates an opening in the insulating film, allowing the upper conductive layer to be electrically connected to the lower conductive layer.

[0310] exist Figure 19 and Figure 20 In the implementation, an embodiment is described in which two adjacent scan signals use a signal line shared between stages as a first clock routing 3103 and a second clock routing 3104.

[0311] exist Figure 19 In this configuration, if the scan signal stage located on one side belongs to the first scan signal generation unit (GW_D) 3001, 3003, then the other scan signal stage belongs to both the scan signal stage and the second scan signal generation unit (GC_D) 3002, 3004. The first clock wiring 3103 and the second clock wiring 3104 in the input signal lines applied between the two are shared.

[0312] by Figure 19 The scanning signal located on the left side is described using the level as the center of the structure as follows.

[0313] as Figure 20The transistors shown include a semiconductor layer, a first gate insulating film 141 and a gate electrode located on the substrate 110. A channel is arranged in the overlapping part of the semiconductor layer and the gate electrode. Source regions and drain regions that are conductive by plasma treatment or doping are arranged on both sides of the channel in the semiconductor layer.

[0314] Furthermore, in Figure 19 and Figure 20 In this embodiment, the first clock wiring 3103 and the second clock wiring 3104 are formed as a double layer. As a result, the layered structure is constructed using a substrate 110, a semiconductor layer, a first gate insulating film 141, a first gate conductive layer, a second gate insulating film 142, a second gate conductive layer, a first interlayer insulating film 143, a source / drain conductive layer (also referred to as a first source / drain conductive layer), a second interlayer insulating film 144, a second source / data conductive layer, and an organic protective film 145. The first gate conductive layer includes the gate electrodes of all transistors.

[0315] In this embodiment, the first clock wiring 3103 and the second clock wiring 3104 are located in the first source / drain conductive layer. The first-second clock wiring 3253 and the second-second clock wiring 3254 are located in the second source / data conductive layer and are electrically connected to the first clock wiring 3103 and the second clock wiring 3104, respectively. According to the embodiment, it can be formed using a single line.

[0316] The individual transistors and capacitors included in the scanning signal stage are described below.

[0317] The gate electrode G301 of transistor T301 is constructed in two parts, extending from one side to the gate electrode G305 of transistor T305, and extending from the other side to be electrically connected to the first clock wiring 3103 to which the CLK2 clock signal is applied. A channel, source region, and drain region are arranged in the semiconductor layer C301. One side of the semiconductor layer C301 is electrically connected to the connection line 3205 for transmitting the start signal FLM or the output of the previous scan signal stage, and the other side is connected to a connection portion 3301 electrically connected to the gate electrode G304 of transistor T304, one side of transistor T308, and one side of transistor T303. The connection portion 3301 is located in the source / drain conductive layer.

[0318] The gate electrode G302 of transistor 302 extends to one electrode 3211 of transistor 306 and capacitor Ca301. One side of semiconductor layer C302 is electrically connected to a high-voltage wiring 3101 to which a high voltage VGH is applied, and the other side is directly connected to one side of transistor 303 through semiconductor layer C303. That is, semiconductor layer C302 extends and forms an integral part of semiconductor layer C303 of transistor 303.

[0319] The gate electrode G303 of transistor T303 extends from one side and is electrically connected to the second clock wiring 3104 to which the CLK1 clock signal is applied, and extends from the other side and is connected to one side of transistor T307. One side of semiconductor layer C303 is connected to one side of transistor T301 via connection portion 3301, and semiconductor layer C303 extends to be directly connected to one side of transistor T302 via semiconductor layer C302.

[0320] The gate electrode G304 of transistor T304 extends from one side and is connected to transistors T301 and T303 via connection portion 3301, and extends from the other side and is connected to one side of transistor T308 via connection portion 3302. One side of semiconductor layer C304 is connected to the gate electrode G301 of transistor T301 via connection portion 3303, and the other side is electrically connected to the gate electrode G302 of transistor T302, the gate electrode G306 of transistor T306, and one side of transistor T305 via connection portion 3304. Connection portions 3303 and 3304 are located in the source / drain conductive layer.

[0321] The gate electrode G305 of transistor T305 extends and connects to the gate electrode G301 of transistor T301, and is electrically connected to the first clock wiring 3103 to which the CLK2 clock signal is applied. One side of semiconductor layer C305 is electrically connected to low-voltage wiring 3102 to which a low voltage VGL is applied, and the other side is electrically connected to the gate electrode G302 of transistor T302, the gate electrode G306 of transistor T306, and one side of transistor T304 via connection portion 3304.

[0322] The gate electrode G306 of transistor T306 is divided into multiple ( Figure 19The semiconductor layer C306 is constructed using four gate electrodes and extends to connect to the gate electrode G302 of the 301 capacitor Ca301 and the 302 transistor T302. One side of the semiconductor layer C306 is connected to one electrode 3212 of the 301 capacitor Ca301 via the connection electrode SD306, and is electrically connected to the high-voltage wiring 3101 via the 301 capacitor Ca301. The other side of the semiconductor layer C306 is connected to the output wiring 3201. The connection electrode SD306 is located in the source / drain conductive layer.

[0323] The gate electrode G307 of transistor T307 is divided into multiple ( Figure 19 The structure utilizes four gate electrodes. A portion forms one electrode 3221 of the 302 capacitor Ca302 and extends to connect to one end of the 308 transistor T308 via a connection portion 3305. One side of the semiconductor layer C307 is electrically connected to the gate electrode G303 of the 303 transistor T303 via a connection electrode SD307, and is also connected to the second clock wiring 3104, where the CLK1 clock signal is applied, via the gate electrode G303 of the 303 transistor T303. The other side of the semiconductor layer C307 is connected to the output wiring 3201. The connection electrode SD307 is located in the source / drain conductive layer.

[0324] The output wiring 3201 is electrically connected to the signal line through the connecting line 3202, and the output wiring 3201 is located in the source / drain conductive layer.

[0325] The gate electrode G308 of transistor T308 extends and is electrically connected to the low-voltage wiring 3102 to which a low voltage VGL is applied. One side of semiconductor layer C308 is electrically connected to the gate electrode G307 of transistor T307 via connection portion 3305, and the other side is electrically connected to the gate electrode G304 of transistor T304 via connection portion 3302.

[0326] Capacitors Ca301 and Ca302 have a cross-sectional structure in which a first gate conductive layer and a second gate conductive layer are used as two electrodes, and a second gate insulating film 142 located between them is used as a dielectric.

[0327] One electrode 3212 of capacitor Ca301 extends to be connected to high voltage wiring 3101, and the other electrode 3211 extends to be located in part of the gate electrode G306 of transistor T306.

[0328] One electrode 3222 of capacitor Ca302 is electrically connected to output wiring 3201, and the other electrode 3221 is located in part of the gate electrode G307 of transistor T307.

[0329] exist Figure 19 In this embodiment, there are two shared signal lines: a first clock line 3103 to which the CLK2 clock signal is applied and a second clock line 3104 to which the CLK1 clock signal is applied. However, according to the embodiment, the high-voltage line 3101 to which a high voltage VGH is applied and the low-voltage line 3102 to which a low voltage VGL is applied may also be shared.

[0330] If combined Figures 8 to 14 Implementation examples and Figures 17 to 20 In one embodiment, the four generating units of the light emission signal stage can share signal lines with each other, and the two generating units of the scan signal stage also share signal lines with each other, thereby minimizing the width / area of ​​the driving units 200 and 250.

[0331] pass Figure 21 and Figure 22 The structure of the entire drive unit 200, 250 as described above will be schematically described.

[0332] Figure 21 This diagram clearly illustrates the reduction in width that occurs when multiple levels are formed in a non-display area in one embodiment. Figure 22 yes Figure 21 A partial sectional view.

[0333] exist Figure 21 The diagram shows, for example Figure 4 The first drive unit 200 is located to the left of the display area DA.

[0334] In the first driving unit 200 located on the left side of the display area DA, a first light emission control signal generation unit (EM1_D) 2001, a second light emission control signal generation unit (EM2_D) 2002, an initialization control signal generation unit (EB1_D) 2003, a bias control signal generation unit (EB2_D) 2004, a second scan signal generation unit (GC_D) 3002 and a first scan signal generation unit (GW_D) 3001 are arranged sequentially from the outside towards the display area DA.

[0335] However, in Figure 21 In one embodiment, a VIA valley portion is formed in a portion that is separated by a predetermined interval between a bias control signal generation unit (EB2_D) 2004, which includes a light emission signal generation stage, and a second scan signal generation unit (GC_D) 3002, which includes a scan signal generation stage.

[0336] VIA valley is the portion where the organic film is at least partially removed, and wiring (hereinafter also referred to as ELVSS wiring) can be arranged there to transmit the voltage applied to the cathode of the light-emitting element (ELVSS voltage). Figure 22The diagram shows the cross-sectional structure of VIA Valley, which is formed as a double-layer structure.

[0337] according to Figure 22 VIA Valley can have a structure in which the organic protective film 145 is removed, and a structure in which the second interlayer insulating film 144 located below it is also partially removed.

[0338] The wiring for transmitting the ELVSS voltage is configured as a double layer, with a first ELVSS wiring ELVSS1 located on a first source / drain conductive layer and a second ELVSS wiring ELVSS2 located on a second source / data conductive layer. Specifically, the first ELVSS wiring ELVSS1 is covered by a second interlayer insulating film 144, and at least a portion of the first ELVSS wiring ELVSS1 is exposed through an opening in the second interlayer insulating film 144. The second ELVSS wiring ELVSS2 is disposed above it, and is electrically connected to the first ELVSS wiring ELVSS1 through the opening in the second interlayer insulating film 144. An organic protective film 145 is disposed above the second ELVSS wiring ELVSS2. The organic protective film 145 has openings that continuously expose the second ELVSS wiring ELVSS2, and because the organic protective film 145 is only located on both sides, it has a structure similar to a valley, and therefore can be referred to as a VIA valley.

[0339] Here, the second interlayer insulating film 144 can be an inorganic film or an organic film.

[0340] Figure 22 The diagram illustrates a case where no conductive or semiconductor layer is disposed at the lower part of the first interlayer insulating film 143, but depending on the location, a conductive or semiconductor layer may be disposed in a certain area.

[0341] exist Figure 21 and Figure 22 In some embodiments, wiring for transmitting ELVSS voltage via VIA Valley is included, and drive units 200 and 250 are formed therein. However, as... Figure 21 As shown, compared to the comparative example, the width is reduced by Ws, thus the area can be reduced.

[0342] That is, the comparative examples are compared with this embodiment by using Table 1 below.

[0343] [Table 1]

[0344]

[0345] Here, the comparative example is the case where input signal lines are not shared between adjacent stages.

[0346] In Table 1, the number of wirings for each generation unit refers to the number of signal lines that need to be input to a stage. The stage for emitting signals can have a total of four wirings CLK1, CLK2, VGH, and VGL, and the stage for scanning signals can have a total of four wirings CLK1, CLK2, VGH, and VGL, or a total of ten wirings GC_CLK1, GC_CLK2, GC_CLK3, GC_CLK4, GC_CLK5, GC_CLK6, VGH, VGL, GW_CLK1, and GW_CLK2. This is the same as in the comparative example and the embodiment.

[0347] In the comparative example, since there are a total of four stages for the light emission signal, a total of 16 stages are required. Since there are a total of two stages for the scan signal, a total of 8 or 12 stages are required.

[0348] However, in this embodiment, the number of input signal lines is reduced compared to this.

[0349] If the four luminous signal stages share two clock traces CLK1 and CLK2 respectively, the total number of clock traces CLK1 and CLK2 is reduced by four. However, if the high-voltage trace VGH or the low-voltage trace VGL is additionally shared, the number of traces will be further reduced.

[0350] Furthermore, if the two light-emitting signal stages share two clock traces CLK1 and CLK2, a total of two or six traces are reduced. If the high-voltage trace VGH or the low-voltage trace VGL is additionally shared, the trace count will be further reduced.

[0351] Specifically, a single level can typically be formed to be approximately 300 μm, and even in the embodiment formed with the minimum width, at least 100 μm is required. If a total of six levels are formed, at least 700 μm is required, thus the width margin of the non-display area can be relatively small. In this case, the width of a single wiring is approximately 12 μm. Considering the space required for insulation between adjacent wirings, a reduction of approximately 60 μm can be achieved by reducing four wirings.

[0352] In particular, if the input signal line is also shared in the scanning signal stage, the total reduction can be 120μm.

[0353] In addition, such as Figure 14 As described in the embodiments, in the case of shared power wiring (low voltage wiring), each wiring can be reduced by approximately 12.5 μm.

[0354] When considering that the width of the driving units 200 and 250 is 700 μm, it can be reduced by 60 μm to 130 μm. Furthermore, the width can be reduced on both sides of the display area DA. Therefore, due to the reduction in the width of the driving units 200 and 250 according to the present invention, sufficient margin can be generated.

[0355] Even when only the input signal lines are shared among the light-emitting signal stages, the area of ​​the driving sections 200 and 250 can be sufficiently reduced. In particular, since a total of four light-emitting signal stages are formed, two pairs of signal lines can be reduced to just two pairs, resulting in a significant reduction in width / area. However, to further reduce the width of the driving sections 200 and 250, the scan signal stages can also share input signal lines. Furthermore, although only clock signal lines can be shared, high-voltage wiring or low-voltage wiring can also be shared to form the driving sections 200 and 250 with a narrower width.

[0356] Furthermore, according to the embodiments, only the scanning signal stage may share the input signal line, while the light emission signal stage may not share the input signal line.

[0357] The embodiments of the present invention have been described in detail above. However, the scope of the present invention is not limited thereto. Various modifications and improvements made by those skilled in the art using the basic concepts of the present invention as defined in the claims also fall within the scope of the present invention.

Claims

1. A light-emitting display device, comprising: The display area includes multiple pixels; as well as The driving unit is located on one side of the display area. The driving unit includes at least two light-emitting signal stages in a row, and also includes input signal lines for inputting signals to the at least two light-emitting signal stages. Wherein, the at least two light-emitting signals are connected in stages to the same input signal line. Each of the light-emitting signal stages includes: The high-level output section is controlled by the voltage of the first node to output a high voltage light emission signal; The low-level output section is controlled by the voltage of the second node to output a low voltage of the light emission signal; The first node, first control unit, controls the voltage of the first node to be changed to a high voltage; The second control unit of the first node changes the voltage of the first node to the low voltage of the second clock signal when the voltage of the third node and the second clock signal input to the first clock input terminal are low. The first control unit of the second node changes the voltage of the second node to the voltage of the start signal or the output signal of the previous light-emitting stage based on the first clock signal input to the second clock input terminal; and The third node control unit includes a 205 transistor that converts the voltage of the third node to a low voltage and a 204 transistor that changes the voltage of the third node to the voltage of the first clock signal when the second node has a low voltage. In the light emission signal stage of any one of the multiple rows of the drive unit, the first clock signal and the second clock signal are out of phase with each other, and in the light emission signal stage of the next row, the first clock signal and the second clock signal are exchanged and input.

2. The light-emitting display device according to claim 1, wherein, The at least two light emission signal generation stages are included in at least two of the first light emission control signal generation unit, the second light emission control signal generation unit, the initialization control signal generation unit, and the bias control signal generation unit.

3. The light-emitting display device according to claim 2, wherein, The input signal lines also include a pair of clock signal lines.

4. The light-emitting display device according to claim 3, wherein, The pair of clock signal lines or the low-voltage wiring is located between the at least two light-emitting signal stages.

5. The light-emitting display device according to claim 3, wherein, The driving unit further includes two scan signal stages in one row. The two scanning signal stages are respectively included in the first scanning signal generation unit and the second scanning signal generation unit.

6. The light-emitting display device according to claim 5, wherein, Also includes: The input signal lines are connected together to the two scan signal stages. The input signal lines that are connected to the two scanning signal stages are a pair of clock signal lines.

7. The light-emitting display device according to claim 5, wherein, The pixel circuit section of the display area receives a first light emission control signal generated by the first light emission control signal generation section, a second light emission control signal generated by the second light emission control signal generation section, a first initialization control signal and a second initialization control signal generated by the initialization control signal generation section, a bias control signal generated by the bias control signal generation section, a first scan signal generated by the first scan signal generation section, and a second scan signal generated by the second scan signal generation section.

8. The light-emitting display device according to claim 1, wherein, Each transistor in the light-emitting signal stage includes a semiconductor layer, a first gate insulating film, and a gate electrode located above the substrate. The input signal lines include high-voltage wiring for high-voltage input or low-voltage wiring for low-voltage input. The semiconductor layer is electrically connected to either the high-voltage wiring or the low-voltage wiring.

9. A light-emitting display device, comprising: The display area includes multiple pixels; as well as The driving unit is located on one side of the display area. The driving unit includes two scan signal stages in a row, and also includes input signal lines for inputting signals to the two scan signal stages. The two scan signals are connected in stages to the same input signal line. Each of the scan signal stages includes: The high-level output section is controlled by the voltage of the first node to output a high voltage for the scanning signal; The low-level output section is controlled by the voltage of the second node to output a low voltage for the scan signal; The first node first control unit includes a 304 transistor whose input electrode is connected to a first input terminal to which a second clock signal is applied, and whose output electrode is connected to the first node, to control the voltage of the first node; The second control unit of the first node has a gate electrode connected to a first input terminal to which the second clock signal is applied, and an input electrode receiving a low voltage. The output electrode is connected to the first node via a transistor 305 to control the voltage of the first node. The second node's first control unit includes a 301 transistor, the gate electrode of which is connected to the first input terminal to which the second clock signal is applied, the input electrode of which is connected to the input terminal of the output of the input start signal or the previous scan signal stage, and the output electrode of which is connected to the second node to control the voltage of the second node; and The second node, a second control unit, includes a 302 transistor and a 303 transistor. The gate electrode of the 302 transistor is connected to the first node, its input electrode receives the high voltage, and its output electrode is connected to the input electrode of the 303 transistor. The gate electrode of the 303 transistor is connected to a second input terminal to which a first clock signal is applied, and its input electrode is connected to the output electrode of the 302 transistor. The output electrode is connected to the second node to control the voltage of the second node. In the scan signal stage of any one of the multiple rows of the drive unit, the first clock signal and the second clock signal are out of phase with each other, and in the scan signal stage of the next row, the first clock signal and the second clock signal are exchanged and input.

10. The light-emitting display device according to claim 9, wherein, The input signal lines connected to the two scanning signal stages are a pair of clock signal lines. The pair of clock signal lines are located between the two scan signal stages.

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