Semiconductor memory device

Abstract

Embodiments provide a semiconductor storage device that operates at high speed. The semiconductor storage device of the embodiments includes a first memory die. The first memory die includes a first memory plane including a plurality of first memory blocks, a second memory plane including a plurality of second memory blocks, a first sequencer operable to write a program, and a second sequencer operable to write the program.

Description

[0001] [Related Applications]

[0002] This application enjoys priority to Japanese Patent Application No. 2020-186895 (filed on November 10, 2020). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] A semiconductor memory device with multiple memory planes is known. Summary of the Invention

[0005] One implementation provides a high-speed semiconductor memory device.

[0006] One embodiment of a semiconductor memory device includes a first memory die. The first memory die includes: a first memory plane having a plurality of first memory blocks; a second memory plane having a plurality of second memory blocks; a first sequencer capable of writing a program; and a second sequencer capable of writing a program.

[0007] One embodiment of a semiconductor memory device includes a first memory die. The first memory die includes: a first memory plane having a plurality of first memory blocks; and a second memory plane having a plurality of second memory blocks. After a first instruction set for writing an input indication to one of the plurality of first memory blocks, before the write procedure corresponding to the first instruction set ends, when a second instruction set for writing an input indication to one of the plurality of first memory blocks has been executed, the write procedure corresponding to the second instruction set is not executed; when a third instruction set for writing an input indication to one of the plurality of second memory blocks has been executed, the write procedure corresponding to the third instruction set is executed.

[0008] One embodiment of a semiconductor memory device includes a first memory die. The first memory die includes: a first memory plane having a plurality of first memory blocks; and a second memory plane having a plurality of second memory blocks. After a first instruction set for writing a program to one of the plurality of first memory blocks, before the writing program corresponding to the first instruction set ends, during a second instruction set for writing a program to one of the plurality of first memory blocks, after a first time elapses since the input of the first instruction set ends, the writing program corresponding to the second instruction set ends. During a third instruction set for writing a program to one of the plurality of second memory blocks, after a second time elapses since the input of the first instruction set ends, the writing program corresponding to the third instruction set ends. The second time is shorter than the first time. Attached Figure Description

[0009] Figure 1 This is a schematic block diagram showing the configuration of the memory system 10 in the first embodiment.

[0010] Figure 2 This is a schematic side view showing a configuration example of the memory system 10 of the first embodiment.

[0011] Figure 3 This is a schematic top view showing a configuration example of the first embodiment.

[0012] Figure 4 This is a schematic block diagram representing the structure of a memory die (MD).

[0013] Figure 5 This is a schematic circuit diagram representing a partial configuration of a memory die (MD).

[0014] Figure 6 This is a schematic circuit diagram representing a partial configuration of a memory die (MD).

[0015] Figure 7 This is a schematic circuit diagram representing a partial configuration of a memory die (MD).

[0016] Figure 8 This is a schematic top view of a memory die (MD).

[0017] Figure 9 It is Figure 8 A schematic top view shown in enlarged form.

[0018] Figure 10 This is a schematic 3D diagram showing a partial structure of a memory die (MD).

[0019] Figure 11 yes Figure 10 A partial enlarged schematic diagram shown in Figure A.

[0020] Figure 12 (a) to (c) are schematic diagrams used to illustrate the threshold voltage of the storage unit MC that records 3 bits of data.

[0021] Figure 13 It is a waveform diagram used to illustrate the writing process.

[0022] Figure 14 It is a flowchart used to illustrate the writing process.

[0023] Figure 15 It is a schematic cross-sectional view used to illustrate the programming actions included in the written program.

[0024] Figure 16 It is a schematic cross-sectional view used to illustrate the verification actions included in the writing program.

[0025] Figure 17 It is a waveform diagram used to illustrate the writing process.

[0026] Figure 18 It is a waveform diagram used to illustrate the writing process.

[0027] Figure 19 It is a waveform diagram used to illustrate the writing process.

[0028] Figure 20 This is a waveform diagram used to illustrate the writing procedure of the second embodiment.

[0029] Figure 21 This is a waveform diagram used to illustrate the writing procedure of the second embodiment.

[0030] Figure 22 This is a waveform diagram used to illustrate the writing procedure of the third embodiment.

[0031] Figure 23 This is a waveform diagram used to illustrate the writing procedure of the fourth embodiment.

[0032] Figure 24 This is a waveform diagram used to illustrate the writing procedure of the fifth embodiment.

[0033] Figure 25 This is a waveform diagram used to illustrate the writing procedure of the sixth embodiment.

[0034] Figure 26 This is a schematic top view of the memory die MD2 of the semiconductor memory device according to the seventh embodiment.

[0035] Figure 27 This is a schematic top view of the memory die MD3 of the semiconductor memory device according to the eighth embodiment.

[0036] Figure 28 This is a schematic top view of the memory die MD4 of the semiconductor memory device according to the ninth embodiment.

[0037] Figure 29 This is a schematic top view illustrating another embodiment of a semiconductor memory device.

[0038] Figure 30 This is a schematic perspective view illustrating another embodiment of a semiconductor memory device.

[0039] Figure 31 This is a schematic perspective view illustrating another embodiment of a semiconductor memory device.

[0040] Figure 32 This is a schematic perspective view illustrating another embodiment of a semiconductor memory device.

[0041] Figure 33 This is a schematic perspective view illustrating another embodiment of a semiconductor memory device.

[0042] Figure 34 This is a schematic circuit diagram illustrating another embodiment of a semiconductor memory device. Detailed Implementation

[0043] Next, the semiconductor memory device according to embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the present invention. Additionally, the following drawings are schematic diagrams, and for ease of explanation, some components may be omitted. Furthermore, common parts in multiple embodiments are labeled with the same symbols, and sometimes descriptions are omitted.

[0044] Furthermore, when this specification refers to "semiconductor memory device," it sometimes means a memory die, and sometimes it means a memory system that includes a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). Moreover, it sometimes also refers to a device that includes a host, such as a smartphone, tablet, or personal computer.

[0045] In addition, when the term "control circuit" is mentioned in this specification, it sometimes refers to peripheral circuits such as sequencers installed on the memory die, sometimes to controller dies or controller chips connected to the memory die, and sometimes to a configuration that includes both.

[0046] Furthermore, when this specification mentions that the first component and the second component are "electrically connected," the first component can be directly connected to the second component, or the first component can be connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0047] Additionally, when this specification mentions that the first component is "connected" "between" the second and third components, it sometimes means that the first, second, and third components are connected in series, and that the second component is connected to the third component via the first component.

[0048] In addition, when this specification mentions that a circuit or the like "makes two wirings conduct", it sometimes means, for example, that the circuit or the like contains a transistor or the like, which is located in the current path between the two wirings, and that the transistor or the like is in an ON state.

[0049] In addition, in this specification, a specified direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0050] In addition, in this specification, a direction along a specified plane is sometimes referred to as the first direction, a direction intersecting the first direction along the specified plane is referred to as the second direction, and a direction intersecting the specified plane is referred to as the third direction. The first direction, the second direction, and the third direction may or may not correspond to any of the X direction, the Y direction, and the Z direction.

[0051] In addition, in this specification, expressions such as "upper" or "lower" are based on the substrate. For example, a direction away from the substrate along the Z direction is referred to as upper, and a direction approaching the substrate along the Z direction is referred to as lower. In addition, when referring to the lower surface or the lower end of a certain component, it means the surface or the end on the substrate side of the component, and when referring to the upper surface or the upper end, it means the surface or the end on the side opposite to the substrate of the component. In addition, a surface intersecting the X direction or the Y direction is referred to as a side surface, etc.

[0052] [First Embodiment]

[0053] [Memory System 10]

[0054] Figure 1 is a schematic block diagram showing the configuration of the memory system 10 according to the first embodiment.

[0055] The memory system 10 reads, writes, erases, etc. user data according to signals sent from the host 20. The memory system 10 is, for example, a memory chip, a memory card, an SSD, or other systems capable of storing user data. The memory system 10 includes a plurality of memory dies MD for storing user data, and a controller die CD connected to the plurality of memory dies MD and the host 20. The controller die CD includes, for example, a processor, a RAM (Random Access Memory), etc., and performs processing such as conversion between logical addresses and physical addresses, bit error detection / correction, garbage collection (compression), wear leveling, etc.

[0056] Figure 2 is a schematic side view showing a configuration example of the memory system 10 according to this embodiment. Figure 3 is a schematic top view showing a configuration example of this embodiment. For ease of explanation, Figure 2 and Figure 3 a part of the configuration is omitted.

[0057] As Figure 2As shown, the memory system 10 of this embodiment includes a mounting substrate (MSB), multiple memory dies (MDs) stacked on the MSB, and a controller die (CD) stacked on the memory dies. A bonding pad electrode P is provided at the Y-direction end region of the upper surface of the MSB, and another portion of the region is bonded to the lower surface of the memory die MD via an adhesive or the like. A bonding pad electrode P is provided at the Y-direction end region of the upper surface of the memory die MD, and other regions are bonded to the lower surface of other memory dies MDs or controller die CDs via adhesives or the like. A bonding pad electrode P is provided at the Y-direction end region of the upper surface of the controller die CD.

[0058] like Figure 3 As shown, the mounting substrate MSB, multiple memory dies MD, and controller die CD each have multiple pad electrodes P arranged in the X direction. The multiple pad electrodes P disposed on the mounting substrate MSB, multiple memory dies MD, and controller die CD are interconnected via bonding lines B.

[0059] also, Figure 2 and Figure 3 The configuration shown is merely an example; the actual configuration can be adjusted accordingly. For example, in Figure 2 and Figure 3 In the example shown, a controller die CD is stacked on multiple memory dies MD, and these components are connected by bonding wires B. In this configuration, multiple memory dies MD and controller die CD are contained within a single package. However, the controller die CD may also be contained in a different package than the memory dies MD. Furthermore, multiple memory dies MD and controller die CD may be connected to each other via through electrodes or the like, rather than bonding wires B.

[0060] [Circuit configuration of a memory die (MD)]

[0061] Figure 4 This is a schematic block diagram showing the configuration of the memory die MD in the first embodiment. Figures 5-7 This is a schematic circuit diagram representing a partial configuration of a memory die (MD).

[0062] also, Figure 4 The diagram illustrates multiple control terminals. These control terminals sometimes correspond to a high-state active signal (positive logic signal), sometimes to a low-state active signal (negative logic signal), and sometimes to both high-state and low-state active signals. Figure 4 In this specification, the symbols for control terminals corresponding to the active low-state signal include an overline (superscript). Furthermore, the symbols for control terminals corresponding to the active low-state signal include a forward slash (" / "). Figure 4Taking the recorded data as an example, the specific state can be adjusted appropriately. For example, it is also possible to make some or all of the high-state effective signals into low-state effective signals, or to make some or all of the low-state effective signals into high-state effective signals.

[0063] [Circuit Structure]

[0064] like Figure 4 As shown, the memory die MD has a memory module MM and peripheral circuitry PC.

[0065] [Circuit configuration of memory module MM]

[0066] The memory module MM has plane groups PG0 and PG1. Plane group PG0 has storage planes MP0 to MP7. Plane group PG1 has storage planes MP8 to MP15. Storage planes MP0 to MP15 each have a memory cell array MCA, a line decoder RD, a sense amplifier module SAM, and a cache memory CM.

[0067] like Figure 5 As shown, the memory cell array MCA has multiple memory blocks BLK. Each of these memory blocks BLK has multiple string components SU. Each of these string components SU has multiple memory strings MS. One end of each of these memory strings MS is connected to the sense amplifier module SAM via a bit line BL. The other end of each of these memory strings MS is connected to a source line driver (not shown) via a common source line SL.

[0068] The memory string (MS) includes a drain-side selection transistor (STD) connected in series between the bit line (BL) and the source line (SL), multiple memory cells (MCs) (memory transistors), a source-side selection transistor (STS), and a source-side selection transistor (STSb). Hereinafter, the drain-side selection transistor (STD), the source-side selection transistor (STS), and the source-side selection transistor (STSb) are sometimes simply referred to as selection transistors (STD, STS, STSb).

[0069] A memory cell (MC) is a field-effect transistor (FET) comprising a semiconductor layer that functions as a channel region, a gate insulating film containing a charge storage film, and a gate electrode. The threshold voltage of the memory cell (MC) varies depending on the amount of charge in the charge storage film. The memory cell (MC) stores one or more bits of data. Furthermore, multiple memory cells (MCs) corresponding to a memory string (MS) are connected to word lines (WL). These word lines (WL) function as the gate electrodes of the memory cells (MCs) contained in all memory strings (MS) within a memory block (BLK).

[0070] The selection transistors (STD, STS, STSb) are field-effect transistors, each containing a semiconductor layer that functions as a channel region, a gate insulating film, and a gate electrode. The gate electrodes of the selection transistors (STD, STS, STSb) are connected to selection gate lines (SGD, SGS, SGSb), respectively. The drain-side selection gate line SGD is correspondingly provided with each string assembly SU, serving as the gate electrode of the drain-side selection transistors STD contained in all memory strings MS within a single string assembly SU. The source-side selection gate line SGS serves as the gate electrode of the source-side selection transistors STS contained in all memory strings MS within a memory block BLK. The source-side selection gate line SGSb serves as the gate electrode of the source-side selection transistors STSb contained in all memory strings MS within a memory block BLK.

[0071] For example, Figure 6 As shown, the row decoder RD has multiple block decoding components blkd. These multiple block decoding components blkd are configured corresponding to multiple memory blocks BLK in the memory cell array MCA. The block decoding component blkd has multiple transistors T BLK These multiple transistors T BLK These are configured corresponding to the multiple word lines WL and select gate lines (SGD, SGS, SGSb) in the memory block BLK. Transistor T BLK For example, a field-effect NMOS transistor.

[0072] transistor T BLK The drain electrode is connected to the word line WL or the select gate line (SGD, SGS, SGSb). Transistor T BLK The source electrode is connected to the wiring CG ( Figure 6 In this example, the wiring is CG0A and CG1A. Transistor T BLK The gate electrode is connected to the signal supply line BLKSEL. Multiple signal supply lines BLKSEL are provided corresponding to all block decoding components (blkd). Additionally, the signal supply lines BLKSEL are connected to all transistors T in the block decoding component (blkd). BLK .

[0073] Wiring CG0A is electrically connected to storage planes MP0 and MP4 ( Figure 4 All memory blocks BLK contained in storage planes MP8 and MP12. Wiring CG1A is electrically connected to all memory blocks BLK contained in storage planes MP8 and MP12. Wiring CG1B ( Figure 4Wiring CG0B is electrically connected to all memory blocks BLK contained in storage planes MP9 and MP13. Wiring CG0C is electrically connected to all memory blocks BLK contained in storage planes MP2 and MP6. Wiring CG1C is electrically connected to all memory blocks BLK contained in storage planes MP10 and MP14. Wiring CG1D is electrically connected to all memory blocks BLK contained in storage planes MP11 and MP15. Wiring CG0D is electrically connected to all memory blocks BLK contained in storage planes MP3 and MP7.

[0074] Sensing Amplifier Module SAM ( Figure 4 For example, it has multiple bit lines BL ( Figure 5 The system comprises multiple sense amplifier modules. Each sense amplifier module includes a sense amplifier connected to the bit line BL. Each sense amplifier includes a sense circuit connected to the bit line BL, a voltage transfer circuit connected to the bit line BL, and a latch circuit connected to both the sense circuit and the voltage transfer circuit. The sense circuit includes a sense transistor that becomes conductive based on the voltage or current of the bit line BL; and a wiring that charges or discharges based on the conductive / discontinuous state of the sense transistor. The latch circuit latches data "1" or "0" based on the voltage of the wiring. The voltage transfer circuit connects the bit line BL to either of the two voltage supply lines based on the data latched in the latch circuit. The sense amplifier module SAM is connected to the sequencer module SQCM.

[0075] Cache memory CM ( Figure 4 It has multiple latch circuits connected to the latch circuits within the sense amplifier module (SAM). The data contained in these multiple latch circuits is sequentially transmitted to the sense amplifier module (SAM) or the input / output control circuit (I / O).

[0076] Additionally, the cache memory CM is connected to a decoding circuit and a switching circuit (not shown). The decoding circuit controls the address register ADR (...). Figure 4 The column address stored in the database is decoded. The switching circuit, based on the output signal of the decoding circuit, causes the latch circuit corresponding to the column address to interact with the bus DB (…). Figure 4 ) Conduction.

[0077] [Circuit configuration of the peripheral circuit PC]

[0078] The peripheral circuit PC includes driver modules DRVM0 and DRVM1, voltage output circuits VO0 and VO1, and a sequencer module SQCM. Additionally, the peripheral circuit PC includes a register module RM and an address comparator circuit ADC. Furthermore, the peripheral circuit PC includes input / output control circuitry (I / O) and logic circuitry CTR.

[0079] [Circuit configuration of driver modules DRVM0 and DRVM1]

[0080] For example, Figure 7 As shown, the driver module DRVM0 includes a word line decoder WLD, a driver circuit DRV, and an address decoder (not shown).

[0081] The word line decoder (WLD) has multiple word line decoding components (wlds) configured corresponding to multiple memory cells (MCs) in the memory string (MS). In the illustrated example, the word line decoding component wld has two transistors T. WL Transistor T WL For example, a field-effect NMOS transistor. Transistor T WL The drain electrode is connected to the wiring CG ( Figure 7 In this example, the wiring is CG0A. Transistor T WL The source electrode is connected to the wiring CG. S Or wired CG U Transistor T WL The gate electrode is connected to the signal supply line WLSEL. S Or signal supply line WLSEL U Signal supply line WLSEL S One of the transistors T contained in all word line decoding components wld WL Correspondingly, multiple signal supply lines (WLSEL) are provided. U Another transistor T is included in all word line decoding components wld. WL There are multiple corresponding locations.

[0082] In addition, transistor T in the driver module DRVM0 WL Connected to wiring CG0A, wiring CG0B, wiring CG0C or wiring CG0D ( Figure 4 ).

[0083] For example, Figure 7 As shown, the driver circuit DRV has wiring CG S and wiring CG U Correspondingly, two driver components (drv) are configured. Each driver component (drv) has multiple transistors (T). DRV Transistor T DRV For example, a field-effect NMOS transistor. Transistor T DRV The drain electrode is connected to the wiring CG. S Or wired CG U Transistor T DRV The source electrode is connected to the voltage supply line L. VG Or voltage supply line L P Voltage supply line LVG Connected to one of the multiple output terminals of the voltage output circuit VO0. Voltage supply line L P Connected to the supplied ground voltage V SS The bonding pad electrode P. Transistor T. DRV The gate electrode is connected to the signal supply line VSEL.

[0084] An address decoder not shown is, for example, a reference address register (ADR). Figure 4 The row address within ) will supply the signal lines BLKSEL and WLSEL. S WLSEL U The voltage control is in either "H" or "L" state.

[0085] Although driver module DRVM1 is not shown in the diagram, its configuration is largely the same as that of driver module DRVM0. However, the transistor T within driver module DRVM1... WL Connected to wiring CG1A, wiring CG1B, wiring CG1C or wiring CG1D ( Figure 4 Additionally, the voltage supply line L within the driver module DRVM1 VG It is connected to one of the multiple output terminals of the voltage output circuit VO1.

[0086] also, Figure 7 In the example, each word line decoding component wld has 2 transistors T WL However, this configuration is merely an example, and the specific configuration can be adjusted accordingly. For instance, when the voltage of the word line WL is controlled to be three or more, each word line decoding component wld can have three transistors T. WL Furthermore, as a case where the voltage of the word line WL is controlled to be three or more, for example, a case in which a larger voltage is supplied to the non-selected word line WL next to the selected word line WL than to the other selected word lines WL.

[0087] [Circuit configuration of voltage output circuits VO0 and VO1]

[0088] The voltage output circuit VO0 is connected to the driver module DRVM0. For example... Figure 7 As shown, the voltage output circuit VO0 includes multiple voltage generating components vg. During the read operation, write procedure, and erase procedure, the voltage generating component vg generates a voltage of a specified magnitude and supplies it to the voltage supply line L. VG Output. The voltage generating component Vg can be, for example, a boost circuit such as a charge pump circuit, or a buck circuit such as a regulator. These buck and boost circuits are respectively connected to the power supply voltage V. CC and grounding voltage V SS ( Figure 4 voltage supply line LP These voltage supply lines L P For example, connected to a reference Figure 2 , Figure 3 The pad electrode P is described.

[0089] For example, Figure 4 As shown, the voltage output circuit VO1 is connected to the driver module DRVM1. Although the diagram is omitted, the voltage output circuit VO1 is configured to be approximately the same as the voltage output circuit VO0.

[0090] The voltage output circuits VO0 and VO1 are, for example, based on the sequencer module SQCM ( Figure 4 The control signals generate various operating voltages applied to the bit line BL, source line SL, word line WL, and select gate lines (SGD, SGS, SGSb) during read, write, and erase operations, and simultaneously output to multiple voltage supply lines L. VG From voltage supply line L VG The output operating voltage can be adjusted appropriately according to the control signal from the sequencer module SQCM.

[0091] [Circuit configuration of the sequencer module SQCM]

[0092] Sequencer Module SQCM ( Figure 4 For example, it has sequencer SQCa, sequencer SQCb, multiplexer MUX0 and multiplexer MUX1.

[0093] The sequencer SQCa can be used for read operations, write programs, and erase programs. Based on the instruction data stored in the instruction register CMR, the sequencer SQCa performs read operations, write programs, and erase programs on one or both of plane groups PG0 and PG1. That is, it outputs internal control signals used to perform these operations. Furthermore, in the sequencer SQCa, the circuit area for the program writing section is larger than the circuit area for the read operation section.

[0094] The sequencer SQCb can be used for writing programs. When executing the program write operation of sequencer SQCa on one of the plane groups PG0 and PG1, sequencer SQCb executes the program write operation on the other plane group PG0 or PG1 according to the instruction data stored in the instruction register CMR. That is, it outputs internal control signals used to execute the program write operation. Furthermore, the circuit area of ​​sequencer SQCb is the same as the circuit area of ​​the part of sequencer SQCa used for program writing, and is larger than the circuit area of ​​the part of sequencer SQCa used for read operations.

[0095] The input terminals of the multiplexer MUX0 are connected to the output terminals of the sequencers SQCa and SQCb, and the output terminals are connected to the driver module DRVM0, the voltage output circuit VO0, and the sense amplifier module SAM in the planar group PG0. The multiplexer MUX0 outputs the output signal of either the sequencer SQCa or the sequencer SQCb based on the control signal from the sequencer SQCa and the address data in the address register.

[0096] The input terminals of the multiplexer MUX1 are connected to the output terminals of the sequencers SQCa and SQCb, and the output terminals are connected to the driver module DRVM1, the voltage output circuit VO1, and the sense amplifier module SAM in the planar group PG1. The multiplexer MUX1 outputs the output signal of either the sequencer SQCa or the sequencer SQCb based on the control signal from the sequencer SQCa, the address data in the address register, etc.

[0097] In addition, the sequencer module SQCM appropriately outputs state data representing its own state to the state register STR.

[0098] Additionally, the sequencer module SQCM generates a ready / busy signal and outputs this signal to the terminal RY / / BY. The terminal RY / / BY is connected, for example, via a reference... Figure 2 , Figure 3 The pad electrode P described is implemented. In this embodiment, the memory die MD can output a ready / busy signal indicating the state of the memory die MD via the RY / / BY terminal, and can also output a ready / busy signal indicating the state of the plane group PG0, and can also output a ready / busy signal indicating the state of the plane group PG1.

[0099] [Circuit configuration of register module RM]

[0100] Register module RM( Figure 4 For example, it includes an address register (ADR) for latching address data, an instruction register (CMR) for latching instruction data, and a status register (STR) for latching status data. Additionally, the register module (RM) latches other parameters and variables used during control. The register module (RM) may, for example, have multiple latching circuits. These multiple latching circuits may, for example, include a pair of CMOS (Complementary Metal Oxide Semiconductor) inverters.

[0101] [Circuit configuration of the address comparison circuit ADC]

[0102] Address comparison circuit ADC ( Figure 4For example, it includes logic circuitry connected to a portion of the latching circuitry within the register module RM. This logic circuitry, for instance, outputs a signal determining whether the memory planes corresponding to the two instruction sets belong to the same memory plane group when two instruction sets are input twice within a fixed time period, intended to execute a write program.

[0103] [Circuit configuration of input / output control circuit (I / O)]

[0104] Input / output control circuit I / O ( Figure 4 It features data input / output terminals DQ0-DQ7, switching signal input / output terminals DQS and / DQS, comparators connected to data input / output terminals DQ0-DQ7, and output circuits such as an OCD (Off-Chip Driver) circuit. Furthermore, the input / output I / O circuit includes shift registers and buffer circuits connected to these input and output circuits. The input circuits, output circuits, shift registers, and buffer circuits are connected to the supplied power supply voltage V. CCQ and grounding voltage V SS The terminal connections are as follows: Data input / output terminals DQ0~DQ7, switching signal input / output terminals DQS, / DQS, and the supplied power supply voltage V. CCQ Terminals, for example, via reference Figure 2 , Figure 3 The pad electrode P described is implemented as follows. Data input via data input / output terminals DQ0 to DQ7 is output from the buffer circuit to the cache memory CM, address register ADR, or instruction register CMR based on internal control signals from the logic circuit CTR. Conversely, data output via data input / output terminals DQ0 to DQ7 is input to the buffer circuit from the cache memory CM or status register STR based on internal control signals from the logic circuit CTR.

[0105] [Circuit configuration of the CTR logic circuit]

[0106] The logic circuit CTR receives external control signals from the controller die CD via external control terminals / CEn, CLE, ALE, / WE, RE, and / RE, and outputs internal control signals to the input / output control circuit (I / O) based on these external control signals. Furthermore, the external control terminals / CEn, CLE, ALE, / WE, RE, and / RE are connected, for example, via reference... Figure 2 , Figure 3 The pad electrode P described is implemented.

[0107] [Construction of Memory Die (MD)]

[0108] Figure 8 This is a schematic top view of a memory die (MD). Figure 9 It is Figure 8A schematic top view shown in enlarged form. Figure 10 This is a schematic 3D diagram showing a partial structure of a memory die (MD). Figure 11 yes Figure 10 A partial enlarged schematic diagram shown in Figure A.

[0109] like Figure 8 As shown, the memory die MD includes a semiconductor substrate 100. In the illustrated example, four memory cell array regions R, each consisting of four cells arranged in the Y direction, are provided on the semiconductor substrate 100 along the X direction. MCA The columns that make up the column. Additionally, from one side in the X direction (e.g., Figure 8 Between the first and second columns (counting from the negative X-axis), there is a peripheral circuit region R. PC2 Similarly, a peripheral circuit region R is provided between the 3rd and 4th columns counting from one side in the X direction. PC2 Additionally, a peripheral circuit region R is provided at the end of the semiconductor substrate 100 in the Y direction. PC1 .

[0110] In the example shown, the region R closest to the peripheral circuit is... PC1 The four memory cell array regions R MCA The internal structure, starting from one side in the X direction, functions as part of storage planes MP0 to MP3. Additionally, the second region near the peripheral circuitry R... PC1 The four memory cell array regions R MCA The internal structure, starting from one side in the X direction, functions as part of storage planes MP4 to MP7. Additionally, the third region, R, is close to the peripheral circuitry. PC1 The four memory cell array regions R MCA The internal structure, starting from one side in the X direction, functions as part of storage planes MP8 to MP11. Additionally, the fourth region, R, is close to the peripheral circuitry. PC1 The four memory cell array regions R MCA The internal structure, starting from one side in the X direction, functions as part of storage planes MP12 to MP15 in sequence.

[0111] Additionally, in the illustrated example, the Y-direction corresponds to the memory cell array region R. MCA A line decoder region R is located at an adjacent position. RD Additionally, in the X direction, it is related to the memory cell array region R. MCA The adjacent location has a sensing amplifier module area R. SAM Additionally, in the peripheral circuit region R... PC1 There is an input / output circuit area R. IO Additionally, in the peripheral circuit region R...PC2 There are multiple wirings arranged in the X direction and extending in the Y direction. A portion of these wirings functions as wiring CG. For example, in... Figure 8 In the example shown, along four storage planes MP2, MP6, MP10, and MP14 arranged in the Y direction, there are multiple wirings CG0C and multiple wirings CG1C extending in the Y direction. In the illustrated example, the positions of the multiple wirings CG0C in the X direction are closer to the storage planes MP2, MP6, MP10, and MP14 in the X direction than the positions of the multiple wirings CG1C in the X direction.

[0112] In the storage cell array region R MCA It is equipped with a memory cell array (MCA) Figure 4 In the line decoder region R RD A line decoder RD is provided. Figure 4 In the sensing amplifier module region R SAM It is equipped with a sensing amplifier module (SAM). Figure 4 In the peripheral circuit region R PC1 R PC2 It is equipped with a peripheral circuit PC ( Figure 4 In the input / output circuit region R IO It is equipped with input / output control circuit (I / O). Figure 4 ) and solder pad electrode P( Figure 2 , Figure 3 ).

[0113] The semiconductor substrate 100 is, for example, a semiconductor substrate containing p-type silicon (Si) containing p-type impurities such as boron (B). On the surface of the semiconductor substrate 100, for example, there are N-type well regions containing N-type impurities such as phosphorus (P), P-type well regions containing P-type impurities such as boron (B), a semiconductor substrate region without N-type and P-type well regions, and an insulating region. The N-type well regions, P-type well regions, and semiconductor substrate regions function as part of multiple transistors and multiple capacitors constituting a peripheral circuit PC.

[0114] like Figure 9 As shown, in the storage cell array region R MCA There are multiple memory blocks (BLKs) arranged in the X direction. For example, ... Figure 10 As shown, the memory block BLK includes a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor layers 120 extending in the Z direction, and a plurality of gate insulating films 130 respectively disposed between the plurality of conductive layers 110 and the plurality of semiconductor layers 120. In addition, an inter-block structure ST is provided between two adjacent memory blocks BLK in the X direction.

[0115] The conductive layer 110 is a generally plate-shaped conductive layer extending in the Y direction. The conductive layer 110 may include a laminate of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Alternatively, the conductive layer 110 may also include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 such as silicon oxide (SiO2) is provided between the plurality of conductive layers 110 arranged in the Z direction.

[0116] Below the conductive layer 110, a conductive layer 111 is provided. The conductive layer 111 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). In addition, an insulating layer 101 such as silicon oxide (SiO2) is provided between the conductive layer 111 and the conductive layer 110.

[0117] Conductive layer 111 serves as the source-side gate selection line SGSb ( Figure 5 The gate electrodes of the plurality of source-side select transistors STSb connected to the source-side select gate line SGSb function. The conductive layer 111 is electrically independent in each memory block BLK.

[0118] Additionally, one or more of the bottommost conductive layers 110 among the plurality of conductive layers 110 serve as the source-side selected gate line (SGS). Figure 5 The gate electrodes of the plurality of source-side select transistors STS connected to the source-side select gate line SGS function.

[0119] Additionally, the plurality of conductive layers 110 located above the plurality of conductive layers 110 serve as word lines WL ( Figure 5 ) and multiple memory cells MC connected to the word line WL. Figure 5 The gate electrode of the memory block BLK functions. These multiple conductive layers 110 are electrically independent in each memory block BLK.

[0120] Additionally, one or more conductive layers 110 located above the plurality of conductive layers 110 serve as drain-side selected gate lines SGD and a plurality of drain-side selected transistors STD connected to the drain-side selected gate lines SGD. Figure 5 The gate electrode of the ) functions. Between two adjacent conductive layers 110 in the X direction, an inter-string insulating layer (SHE) such as silicon oxide (SiO2) is provided. These multiple conductive layers 110 are respectively positioned in each string assembly SU( Figure 5 The electrical properties are independent.

[0121] Furthermore, at the Y-direction ends of these multiple conductive layers 110, there are connection portions for multiple contacts CC. These multiple contacts CC extend in the Z-direction and are connected to the conductive layers 110 at their lower ends. The contacts CC may, for example, comprise a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0122] Semiconductor layer 120 is arranged in a prescribed pattern in the X and Y directions. Semiconductor layer 120 serves as a memory string (MS). Figure 5 The semiconductor layer 120 comprises multiple memory cells (MCs) and channel regions of selection transistors (STD, STS, STSb). The semiconductor layer 120 is, for example, a polysilicon (Si) semiconductor layer. The semiconductor layer 120 has, for example, a generally bottomed cylindrical shape, with an insulating layer 125 such as silicon oxide disposed in the central portion. Furthermore, the outer peripheral surfaces of the semiconductor layer 120 are each surrounded by a conductive layer 110, facing the conductive layer 110.

[0123] At the upper end of the semiconductor layer 120, there is an impurity region 121 containing N-type impurities such as phosphorus (P). The impurity region 121 is connected to a bit line BL extending in the X direction via a contact Ch and a contact Cb.

[0124] The lower end of the semiconductor layer 120 is connected to the P-type well region of the semiconductor substrate 100 via a semiconductor layer 122 containing monocrystalline silicon (Si) or the like. The semiconductor layer 122 functions as the channel region of the source-side select transistor STSb. The outer peripheral surface of the semiconductor layer 122 is surrounded by a conductive layer 111 and faces the conductive layer 111. An insulating layer 123, such as silicon oxide, is provided between the semiconductor layer 122 and the conductive layer 111.

[0125] The gate insulating film 130 has a generally cylindrical shape that covers the outer peripheral surface of the semiconductor layer 120.

[0126] For example, Figure 11 As shown, the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 deposited between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the block insulating film 133 are insulating films such as silicon oxide (SiO2). The charge storage film 132 is a film capable of storing charge, such as silicon nitride (Si3N4). The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a generally cylindrical shape and extend along the outer peripheral surface of the semiconductor layer 120 in the Z direction.

[0127] also, Figure 11 The diagram shows an example where the gate insulating film 130 has a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may also have a floating gate such as polysilicon containing N-type or P-type impurities.

[0128] For example, Figure 10As shown, the inter-block structure ST includes a conductive layer 140 extending in the Z and Y directions, and an insulating layer 141 disposed on the X-direction side of the conductive layer 140. The conductive layer 140 is connected to an N-type impurity region disposed in the P-type well region of the semiconductor substrate 100. The conductive layer 140 may, for example, comprise a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 140 serves, for example, as a source line SL ( Figure 5 It plays a part of the function.

[0129] [Threshold voltage of memory cell MC]

[0130] Next, refer to Figure 12 This is to explain the threshold voltage of the memory cell MC.

[0131] Figure 12 (a) is a schematic bar chart illustrating the threshold voltage of the memory cell MC that records 3 bits of data. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC. Figure 12 (b) is a table showing an example of the relationship between the threshold voltage of the storage cell MC that records 3 bits of data and the recorded data. Figure 12 (c) is another example of the relationship between the threshold voltage of the storage cell MC that records 3 bits of data and the recorded data.

[0132] Figure 12 In example (a), the threshold voltage of the memory cell MC is controlled to eight states. The threshold voltage of the memory cell MC controlled to the Er state is less than the erase verification voltage V. VFYEr Additionally, for example, the threshold voltage of the memory cell MC controlled in state A is greater than the verification voltage V. VFYA Less than the verification voltage V VFYB Additionally, for example, the threshold voltage of the memory cell MC controlled in state B is greater than the verification voltage V. VFYB Less than the verification voltage V VFYC Similarly, the threshold voltages of memory cells MC controlled in states C through F are respectively greater than the verification voltage V. VFYC ~Verification voltage V VFYF Less than the verification voltage V VFYD ~Verification voltage V VFYG Additionally, for example, the threshold voltage of the memory cell MC controlled in state G is greater than the verification voltage V. VFYG Less than the readout voltage V READ .

[0133] in addition, Figure 12 In example (a), a readout voltage V is set between the threshold distribution corresponding to state Er and the threshold distribution corresponding to state A. CGARAdditionally, a readout voltage V is set between the threshold distribution corresponding to state A and the threshold distribution corresponding to state B. CGBR Similarly, readout voltage V is set between the threshold distribution corresponding to state B and the threshold distribution corresponding to state C, and between the threshold distribution corresponding to state F and the threshold distribution corresponding to state G. CGBR ~Read the voltage V CGGR .

[0134] For example, the Er state corresponds to the lowest threshold voltage (the threshold voltage of the memory cell MC in the erase state). The memory cell MC corresponding to the Er state is, for example, assigned the data "111".

[0135] Additionally, state A corresponds to a threshold voltage higher than the threshold voltage corresponding to state Er. The memory cell MC corresponding to state A is, for example, assigned the data "101".

[0136] Furthermore, state B corresponds to a threshold voltage that is higher than the threshold voltage corresponding to state A. The memory cell MC corresponding to state B is, for example, assigned the data "001".

[0137] Similarly, in the diagram, states C through G correspond to threshold voltages that are higher than those corresponding to states B through F. The memory cells MC corresponding to these distributions are, for example, assigned the data “011”, “010”, “110”, “100”, and “000”.

[0138] In addition, in the like Figure 12 (b) In the case of the allocation shown in the example, the data of the lower bit can be read through a single read voltage V. CGDR To determine the median bit data, it can be obtained through three readout voltages V. CGAR V CGCR V CGFR To determine this, the data in the higher-order bit can be read through three readout voltages V. CGBR V CGER V CGGR This is used to make a judgment. Sometimes this data allocation is called 1-3-3 encoding.

[0139] Furthermore, the number of bits, the number of states, and the data allocation for each state recorded in the storage unit MC can be changed appropriately.

[0140] For example, in the case of Figure 12 (c) In the case of the allocation shown in the example, the data of the lower bit can be read through a single read voltage V. CGDR To determine this, the data in the median bit can be obtained through two readout voltages V. CGBR V CGFR To determine this, the data in the upper-level bit can be read through four readout voltages V.CGAR V CGCR V CGER V CGGR This is used to make a judgment. Sometimes, this type of data allocation is called 1-2-4 encoding.

[0141] [Write program]

[0142] Next, the writing procedure of this embodiment will be described. Figure 13 It is a waveform diagram used to illustrate the writing process.

[0143] Figure 13 The example illustrates a portion of the instruction set input to the memory die MD during a write operation. This instruction set includes data 8Xh, data Plane0, and data 10h.

[0144] During the period from time point t101 to time point t102, the controller die CD inputs data 8Xh to the memory die MD as instruction data. Data 8Xh is the instruction input at the beginning of the write program.

[0145] When inputting command data, connect the data input / output terminals DQ0 to DQ7. Figure 4 The voltage corresponding to each bit of data 8Xh is set to "H" or "L". When "H" is input to the external control terminal CLE and "L" is input to the external control terminal ALE, the input signals of the switching signal input / output terminals DQS and / DQS are switched.

[0146] During time points t102 and t103, the controller die CD inputs address data and user data to the memory die MD. The diagram illustrates data Plane0 as part of the address data. Data Plane0 is a specified reference. Figure 4 The data refers to the storage plane MP0 as described above. Furthermore, in the following description, the data for storage planes MP1 to MP15 may sometimes be referred to as data Plane1 to data Plane15. In addition to the data from any of the storage planes M0 to MP15, the address data also includes the data for the specified memory die MD, the data for the specified memory block BLK, the data for the specified string assembly SU, and the data for the specified word line WL, etc.

[0147] When inputting address data, connect the data input / output terminals DQ0 to DQ7. Figure 4The voltage corresponding to each bit of the 8-bit data that constitutes part of the address data is set to "H" or "L". With "L" input to the external control terminal CLE and "H" input to the external control terminal ALE, the input signals of the switching signal input / output terminals DQS and / DQS are switched. Thus, the 8-bit data is input to the memory die MD as part of the address data. Similarly, the data input / output terminals DQ0 to DQ7 are switched sequentially below. Figure 4 The voltage is applied and the same action is performed, while the address data is input into the memory die MD.

[0148] When inputting user data, connect the data input / output terminals DQ0 to DQ7. Figure 4 The voltage corresponding to each bit of the 8-bit data that constitutes part of the user data is set to "H" or "L". With "L" input to the external control terminal CLE and "L" input to the external control terminal ALE, the input signals of the switching signal input / output terminals DQS and / DQS are switched. Thus, the 8-bit data is input to the memory die MD as part of the user data. Similarly, the data input / output terminals DQ0 to DQ7 are switched sequentially below. Figure 4 The voltage is applied and the same action is performed, while user data is input into the memory die MD.

[0149] During time points t103 and t104, the controller die CD inputs data 10h to the memory die MD as instruction data. Data 10h indicates that the input of the instruction set related to the writing program has ended.

[0150] At time t104, no read operations or write programs are performed in the memory die MD. In this case, access to the sequencer SQCa is allowed, and the write program for the sequencer SQCa begins. Additionally, the ready / busy signal of the memory die MD ( Figure 13 The ready / busy signals of R / / B(Chip) and plane group PG0 ( Figure 13 R / / B(PG0) changes from the "H" state to the "L" state.

[0151] At time t105, the write procedure for the memory die MD ends. Additionally, the ready / busy signal for the memory die MD... Figure 13 The ready / busy signals of R / / B(Chip) and plane group PG0 ( Figure 13 R / / B(PG0) changes from the "L" state to the "H" state.

[0152] Then, the controller die CD inputs instruction data, such as instruction data intended to perform a status read, to the memory die MD. Accompanying this, the memory die MD outputs the status register STR. Figure 4 The state data is latched in ).

[0153] Furthermore, the instruction set described above is simplified. The specific configuration of the instruction set actually input to the memory die (MD) during program writing can be appropriately adjusted. For example, in this embodiment, as referred to... Figure 12 The explanation illustrates an example where 3 bits of data are recorded in the memory cell MC. In this case, during the write program, instruction sets corresponding to the lower bit, the middle bit, and the upper bit can be input to the memory die MD. The instruction set corresponding to the lower bit may, for example, include data KKh, data 8Xh, data Plane0, and data 11h. The instruction set corresponding to the middle bit may, for example, include data LLh, data 8Xh, data Plane0, and data 11h. The instruction set corresponding to the upper bit may, for example, include data MMh, data 8Xh, data Plane0, and data 10h. Furthermore, data KKh, LLh, and MMh represent the instructions corresponding to the lower, middle, and upper bits, respectively. Additionally, data 11h indicates the end of input for the first instruction set related to the write program, and the input of the next instruction set before starting the write program.

[0154] Figure 14 It is a flowchart used to illustrate the writing process. Figure 15 It is a schematic cross-sectional view used to illustrate the programming actions included in the written program. Figure 16 It is a schematic cross-sectional view used to illustrate the verification actions included in the writing program. Figure 17 It is a waveform diagram used to illustrate the writing process.

[0155] In addition, in the following explanation, the word line WL that is the object of the action is sometimes referred to as the selection word line WL. S The word lines WL other than these are called non-selective word lines WL. U Additionally, the following explanation will illustrate the following example: For the multiple storage units MC contained in the string component SU, which is the object of the action, connected to the select word line WL... S The memory cell MC (hereinafter, sometimes referred to as "select memory cell MC") performs the write procedure. In the following description, a structure that contains multiple select memory cells MCs is sometimes referred to as a select page PG.

[0156] In step S101, for example, Figure 14 As shown, the number of iterations n W Set to 1. Number of loops n W This is a variable representing the number of times the loop is written. This action, for example, in... Figure 17 The execution occurs at time point t104. Additionally, for example, in the sensing amplifier module SAM ( Figure 4 In the latching circuit within the memory cell MC, user data is latched and written to the memory cell MC.

[0157] In step S102, a programming action is performed. The programming action involves selecting the word line WL. S The action of increasing the threshold voltage of the memory cell MC by supplying a programming voltage. This action, for example, occurs in... Figure 17 The execution will take place from time point t111 to time point t116.

[0158] At programming point t111, for example, the bit line BL connected to the select memory cell MC (hereinafter, sometimes referred to as the "write memory cell MC") that performs threshold voltage adjustment with multiple select memory cells MC. W Supply voltage V SRC The bit line BL connected to the selected memory cell MC (hereinafter sometimes referred to as the "disabled memory cell MC") that has not undergone threshold voltage adjustment among multiple selected memory cells MC is... P Supply voltage V DD Voltage V SRC For example, it has a ground voltage V SS The same magnitude. Voltage V SRC For example, compared to the grounding voltage V SS Larger, specific voltage V DD Small.

[0159] At time t112 of the programming action, select word line WL S and non-selective word line WL U Supply write through voltage V PASS Additionally, a gate line SGD supply voltage V is selected on the drain side. SGD Write through voltage V PASS It can have the same as the reference ( Figure 12 The readout through voltage V is described in the diagram. READ For the same magnitude, the readings of the voltage V can also be compared. READ Large. Voltage V SGD The degree to which a drain-side selected transistor STD is turned on or off depends on the voltage on bit line BL.

[0160] At time t114 of the programming action, select word line WL S Supply programming voltage V PGM Programming voltage V PGM Write voltage V PASS big.

[0161] Here, for example, Figure 15 As shown, for bit line BL W The channel supply voltage V of the connected semiconductor layer 120 SRCIn this semiconductor layer 120 and select word line WL S A relatively large electric field is generated between them. As a result, electrons in the channels of semiconductor layer 120 pass through tunnel insulating film 131 ( Figure 11 ) tunneling to the charge storage membrane 132 ( Figure 11 This leads to an increase in the threshold voltage for writing to the memory cell MC.

[0162] On the other hand, with bit line BL P The channel of the connected semiconductor layer 120 becomes electrically floating, and the potential of this channel is controlled by the non-select word line WL. U Capacitive coupling rises to write pass voltage V PASS Degree. In this semiconductor layer 120 with select word line WL S Between them, only an electric field smaller than either of the aforementioned electric fields is generated. Therefore, electrons in the channels of semiconductor layer 120 do not tunnel to charge storage film 132. Figure 11 Therefore, the threshold voltage of the memory cell MC was not increased.

[0163] At time t115 of the programming action, select word line WL. S and non-selective word line WL U Supply write through voltage V PASS .

[0164] At time t116 of the programming action, select word line WL S Non-selective word line WL U and select the gate line (SGD, SGS, SGSb) to supply ground voltage V SS .

[0165] In step S103 ( Figure 14 In the selection line WL, a verification action is performed. S The process involves supplying a verification voltage to confirm whether the threshold voltage of the memory cell (MC) has reached the expected value. This action, for example, is performed from... Figure 17 The execution will take place from time point t121 to time point t132.

[0166] At the verification point t121, for example... Figure 16 As shown, for the non-selected word line WL U Supply readout voltage V READ This turns all memory cells MC on. Additionally, a voltage V is supplied to the select gate lines (SGD, SGS, SGSb). SG This turns the selector transistors (STD, STS, STSb) on. Voltage V SG Although it is the voltage of bit line BL, it represents the degree to which the drain-side selection transistor STD becomes in the on state. Voltage VSG Greater than voltage V SGD .

[0167] At time t122 ​​of the verification action, select word line WL. S Supply the specified verification voltage V VFY (Refer to Figure 12 (a) The verification voltage V described VFYA ~V VFYG (any one of them). Thus, for example, Figure 16 As shown, some selected memory cells MC are in the on state, while the remaining selected memory cells MC are in the off state.

[0168] Additionally, at time point t122, for example, charging of the bit line BL is performed. At this time, for example, based on data from the latch circuit within the sense amplifier module SAM, the connection to a specific state ( Figure 17 In the example, state A) corresponds to the bit line BL of the memory cell MC. Figure 17 In the example, it is the bit line BL A Supply voltage V DD Supply voltage V to other bit lines BL SRC .

[0169] During the verification of actions at time points t123 to t124, for example... Figure 17 As shown, using the sensing amplifier module SAM ( Figure 4 Perform sensing actions. For example, based on bit lines BL. A The current value detection is connected to the bit line BL. A The on / off state of the storage cell MC is acquired and used as data representing the state of the storage cell MC. At the same time, the latch circuit within the sense amplifier module SAM can also latch data representing the on / off state of the storage cell MC.

[0170] During the verification process from time point t125 to time point t127, the storage units MC in other states are... Figure 17 In the example, state B) undergoes the same processing as at time points t122 ​​to t124. Furthermore, in Figure 17 In the diagram, the bit line BL connected to the memory cell MC corresponding to state B is recorded as bit line BL. B .

[0171] During the verification process from time point t128 to time point t130, the storage units MC in other states are... Figure 17 In the example, state C) undergoes the same processing as at time points t122 ​​to t124. Furthermore, in Figure 17 In the diagram, the bit line BL connected to the memory cell MC corresponding to state C is recorded as bit line BL.C .

[0172] At time t131 of the verification action, the alignment line BL is... C Supply voltage V SRC .

[0173] At time t132 of the verification action, select word line WL. S Non-selective word line WL U and select the gate line (SGD, SGS, SGSb) to supply ground voltage V SS .

[0174] Then, the data latched in the latch circuit within the sensing amplifier module SAM is transmitted to a counter circuit (not shown) to count the number of memory cells MC whose threshold voltage reaches the desired value or the number of memory cells MC whose threshold voltage does not reach the desired value.

[0175] also, Figure 17 The example shows the selection word line WL during the verification action. S Supply 3 verification voltages V VFYA V VFYB V VFYC Examples. However, in the verification action, the selection word line WL... S The supplied verification voltage V VFY The number of types can be 2 or less, or 4 or more, and can also be determined based on the number of loops n. W change.

[0176] In step S104 ( Figure 14 In step S105, the result of the verification action is determined. For example, if the number of memory cells MC whose threshold voltage has not reached the expected value is above a fixed number, the verification is determined to be FAIL and the process proceeds to step S107. On the other hand, if the number of memory cells MC whose threshold voltage has not reached the expected value is below a fixed number, the verification is determined to be PASS and the process proceeds to step S107.

[0177] In step S105, the number of iterations n is determined. W Has the specified number of attempts (N) been reached? W Before the specified number of attempts N is reached. W In the case where the specified number of times N is reached, proceed to step S106. W In this case, proceed to step S108.

[0178] In step S106, the number of iterations n W Add 1, proceed to step S102. Additionally, in step S106, for example, the programming voltage V... PGM Add the specified voltage ΔV. Therefore, the programmed voltage VPGM With the number of loops n W Simultaneously increase.

[0179] In step S107, in the status register STR( Figure 4 The system stores status data indicating the normal completion of the write program, and then terminates the write program. Furthermore, the status data is output to the controller's bare die CD via a status read operation. Figure 1 ).

[0180] In step S108, in the status register STR( Figure 4 The program stores state data indicating that the writing process did not end normally, and then terminates the writing process.

[0181] [Perform multiple write operations]

[0182] Next, the operation of the controller die CD inputting multiple instruction sets into the memory die MD within a fixed time period will be explained.

[0183] For example, as mentioned above, the planar group PG0 ( Figure 4 It has storage planes MP0 to MP7. When a write procedure is started for at least one of these storage planes MP0 to MP7, the write procedure for sequencer SQCa is started, and access to plane group PG0 and sequencer SQCa is prohibited.

[0184] When an instruction set whose purpose is to execute a write procedure is entered in this state, and the instruction set contains data for at least one of the specified storage planes MP0 to MP7, the write procedure specified by the instruction set is not executed.

[0185] On the other hand, when an instruction set whose purpose is to execute a write program is input in this state, and the instruction set contains data for at least one of the specified storage planes MP8 to MP15, the sequencer SQCb's write program is executed on the specified storage plane.

[0186] Similarly, planar group PG1 ( Figure 4 It has storage planes MP8 to MP15. When a write procedure is started for at least one of these storage planes MP8 to MP15, the write procedure for sequencer SQCa is started, and access to plane group PG1 and sequencer SQCa is disabled.

[0187] When an instruction set whose purpose is to execute a write procedure is entered in this state, and the instruction set contains data for at least one of the specified storage planes MP8 to MP15, the write procedure specified by the instruction set is not executed.

[0188] On the other hand, when the input in this state is an instruction set whose purpose is to execute a write program, and the instruction set contains data for at least one of the specified storage planes MP0 to MP7, the sequencer SQCb's write program is executed on the specified storage plane.

[0189] Figure 18 It is a waveform diagram used to illustrate this writing process.

[0190] During the period from time point t141 to time point t142, the controller die CD inputs data 8Xh to the memory die MD as instruction data.

[0191] During time points t142 and t143, the controller die CD inputs address data and user data to the memory die MD. The figure illustrates data Plane0 as part of the address data.

[0192] During the period from time point t143 to time point t144, the controller die CD inputs data 10h to the memory die MD as instruction data.

[0193] At time t144, no read operations or write programs are performed in the memory die MD. In this case, access to plane groups PG0 and PG1 and sequencer SQCa is allowed, while access to sequencer SQCb is prohibited. Therefore, the write program to sequencer SQCa begins. Additionally, the ready / busy signal of the memory die MD ( Figure 18 The ready / busy signals of R / / B(Chip) and plane group PG0 ( Figure 18 R / / B(PG0) changes from the "H" state to the "L" state.

[0194] During the period from time point t145 to time point t146, the controller die CD inputs data 8Xh to the memory die MD as instruction data.

[0195] During time points t146 and t147, the controller die CD inputs address data and user data to the memory die MD. The figure illustrates data Plane8 as part of the address data.

[0196] During the period from time point t147 to time point t148, the controller die CD inputs data 10h to the memory die MD as instruction data.

[0197] At time t148, a write procedure is executed for plane group PG0. In this case, access to plane group PG1 and sequencer SQCb is allowed, while access to plane group PG0 and sequencer SQCa is prohibited. Therefore, the write procedure for sequencer SQCb begins. Additionally, the ready / busy signal of plane group PG1 ( Figure 18 R / / B(PG1) changes from the "H" state to the "L" state.

[0198] At time t149, the write procedure for memory plane MP0 ends. Additionally, the ready / busy signal for plane group PG0 ( Figure 18 R / / B(PG0) changes from the "L" state to the "H" state.

[0199] At time t150, the write procedure for memory plane MP8 ends. Additionally, the ready / busy signal for the memory die MD is activated. Figure 18 The ready / busy signals of R / / B (Chip) and plane group PG1 ( Figure 18 R / / B(PG1) changes from the "L" state to the "H" state.

[0200] Figure 19 It is a waveform diagram used to illustrate this writing process. Figure 19 The figure shows the select word line WL within the storage plane MP0. S The supplied voltage, and the select word line WL within the storage plane MP8. S The supplied voltage.

[0201] Figure 19 In the example, during the period from time t144 to time t148, the write procedure for memory plane MP0 begins, refer to... Figure 14 The number of loops n as described above W Increase from 1 to 8. Additionally, execute 7 times. Figure 17 The actions corresponding to time points t111 to t132.

[0202] Additionally, during the period from time t148 to time t149, a write procedure is performed for memory plane MP0, with a loop count of n. W The value increases from 8 to 19, at which point the program ends. Additionally, it is executed 11 times. Figure 17 The actions corresponding to time points t111 to t132. Additionally, the writing program for storage plane MP8 begins, with a loop count n. W Increase from 1 to 12. Also, execute 11 times. Figure 17 The actions corresponding to time points t111 to t132.

[0203] Additionally, during the period from time t149 to time t150, a write procedure is performed for storage plane MP8, with a loop count of n. W The value increases from 12 to 19, at which point the writing process ends. Additionally, it is executed 8 times. Figure 17 The actions corresponding to time points t111 to t132.

[0204] also, Figure 19 In the example, Figure 17The actions corresponding to time points t111 to t132 are repeatedly executed at fixed time intervals T1.

[0205] However, in the number of loops n W In the case of 1, 2, or 17-19, only the selection word line WL is applied. S Supply one verification voltage V VFYA V VFYG In this situation, Figure 17 From time point t125 to time point t132, the selected word line WL can be used. S Supply ground voltage V SS wait.

[0206] Similarly, in the loop count n W In the case of 3, 4, 15, or 16, only select the word line WL. S Supply two verification voltages V VFYA V VFYB Or 2 verification voltages V VFYF V VFYG In this situation, Figure 17 From time point t128 to time point t132, the selected word line WL can be used. S Supply ground voltage V SS wait.

[0207] in addition, Figure 19 In the example, during the period from time t148 to time t149, between the write program for memory plane MP0 and the write program for memory plane MP8, the corresponding... Figure 17 The processing at time points t111 to t132. For example, in this embodiment, sequencers SQCa and SQCb can be controlled based on the same clock signal. In this case, for example, the time points controlled by sequencer SQCa and the time points controlled by sequencer SQCb can be consistent within the period of the clock signal. Alternatively, in this embodiment, sequencers SQCa and SQCb can be controlled based on the same timing signal other than the clock signal.

[0208] [Effects of the semiconductor memory device according to the first embodiment]

[0209] The memory die (MD) in this embodiment is configured to execute two write programs in parallel. For example, see reference... Figure 4 As explained, the memory die MD in this embodiment includes plane groups PG0 and PG1, and two sequencers SQCa and SQCb that can be used to write programs.

[0210] With this configuration, while executing a write program on one of the plane groups PG0 and PG1, it is possible to begin executing a write program on the other plane group PG0 or PG1 without waiting for that write program to finish. Therefore, a high-speed semiconductor memory device can be provided.

[0211] Additionally, the controller bare CD ( Figure 1 After receiving user data from host 20, the user data must be temporarily stored until it is input into the memory die MD as part of an instruction set. The longer the controller die CD stores user data, the more data must be stored in the controller die CD, necessitating the installation of a large amount of memory on the controller die CD. The semiconductor memory device according to this embodiment can shorten this time and reduce the cost of the controller die CD.

[0212] Additionally, as referenced Figure 8 As explained, the memory die MD of this embodiment has multiple wirings CG arranged in the X direction and extending in the Y direction. In this configuration, the voltage of the word line WL may sometimes fluctuate due to crosstalk between the wirings CG. For example, when simultaneously performing programming operations for memory plane MP2 and verification operations for memory plane MP10, the voltage of the wirings CG0C ( Figure 4 Supply programming voltage V PGM At certain points, the voltage of the wiring CG1C may rise significantly, making it impossible to properly detect the threshold voltage of the memory cell MC in the memory plane MP10, or an undesirable rise in the threshold voltage of the memory cell MC may occur in the memory plane MP10.

[0213] Therefore, in the memory die MD of this embodiment, as referred to Figure 19 As explained, the programming voltage V is supplied to the plane group PG0. PGM The timing and the programming voltage V supplied to the plane group PG1 PGM The timing is consistent.

[0214] According to this method, the effects of crosstalk as described above can be suppressed. Therefore, a suitable and controllable semiconductor memory device can be provided.

[0215] [Second Implementation]

[0216] Next, refer to Figure 20 and Figure 21 The second embodiment will be described below. Figure 20 and Figure 21 This is a waveform diagram used to illustrate the writing procedure of the second embodiment.

[0217] The semiconductor memory device of the second embodiment is configured the same as the semiconductor memory device of the first embodiment.

[0218] Figure 20 and Figure 21 The diagram illustrates a portion of the instruction set input to the memory die MD during the write process. This instruction set is essentially the same as the referenced instruction set. Figure 13 The instruction set described is the same. However, Figure 20 and Figure 21 The instruction set shown in the example replaces data 10h and includes data 15h.

[0219] Figure 20 This illustrates the action when two input instructions are given within a fixed time period for the write procedure of the same plane group PG0.

[0220] During the period from time point t201 to time point t202, the controller die CD inputs data 8Xh to the memory die MD as instruction data.

[0221] During the period from time point t202 to time point t203, the controller die CD inputs address data and user data to the memory die MD. The figure illustrates data Plane0 as part of the address data.

[0222] During time points t203 and t204, the controller die CD inputs data 15h to the memory die MD as instruction data. Data 15h indicates that the input of the instruction set related to the writing program has ended.

[0223] At time t204, no read operations or write programs are performed in the memory die MD. In this case, access to plane groups PG0 and PG1 and sequencer SQCa is allowed, while access to sequencer SQCb is prohibited. Therefore, the write program to sequencer SQCa begins. Additionally, the ready / busy signal of the memory die MD ( Figure 20 The ready / busy signals of R / / B(Chip) and plane group PG0 ( Figure 20 R / / B(PG0) changes from the "H" state to the "L" state.

[0224] During time points t204 and t205, user data in the cache memory CM corresponding to the storage plane MP0 is transferred to the latch circuit in the sense amplifier module SAM, making the cache memory CM usable. Simultaneously, at time point t205, the ready / busy signal of the memory die MD is activated. Figure 20 The R / / B(Chip) changes from the "L" state to the "H" state.

[0225] During the period from time point t206 to time point t207, the controller die CD inputs data 8Xh to the memory die MD as instruction data.

[0226] During time points t207 and t208, the controller die CD inputs address data and user data to the memory die MD. The figure illustrates data Plane0 as part of the address data.

[0227] During the period from time point t208 to time point t209, the controller die CD inputs data 15h to the memory die MD as instruction data.

[0228] At time t209, a write program is executed on plane group PG0. In this case, access to plane group PG1 and sequencer SQCb is allowed, while access to plane group PG0 and sequencer SQCa is prohibited. Therefore, a write program cannot begin at time t209. In this case, the address data contained in the instruction set input between time t206 and time t209 is temporarily latched into the address register ADR. Figure 4 Additionally, the user data contained in this instruction set is temporarily latched into the cache memory CM corresponding to the storage plane MP0.

[0229] At time t211, the write program corresponding to the instruction set input during time t201 to time t204 ends, and the write program corresponding to the instruction set input during time t206 to time t209 begins.

[0230] At time t212, the write program corresponding to the instruction set input between time t206 and time t209 ends. Additionally, the ready / busy signal of plane group PG0 ( Figure 20 R / / B(PG0) changes from the "L" state to the "H" state.

[0231] Figure 21 Examples are given of actions taken when inputting instruction sets for writing to plane group PG0 and instruction sets for writing to plane group PG1 within a fixed time period.

[0232] The processing at time points t221 to t229 and related Figure 20 The processing at time points t201 to t209 is performed in the same manner. However, during time points t227 to t228, data Plane0 is replaced by input data Plane8.

[0233] At time t229, a write procedure is executed for plane group PG0. In this case, access to plane group PG1 and sequencer SQCb is allowed, while access to plane group PG0 and sequencer SQCa is prohibited. Therefore, the write procedure for sequencer SQCb begins. Additionally, the ready / busy signal of the memory die MD ( Figure 21 The ready / busy signals of R / / B (Chip) and plane group PG1 ( Figure 21 R / / B(PG1) changes from the "H" state to the "L" state.

[0234] At time t230, the ready / busy signal of the memory die MD ( Figure 21 An R / / B(Chip) changes from the "L" state to the "H" state.

[0235] At time t231, the write procedure for memory plane MP0 ends. Additionally, the ready / busy signal for plane group PG0 ( Figure 21 R / / B(PG0) changes from the "L" state to the "H" state.

[0236] At time t232, the write procedure for storage plane MP8 ends. Additionally, the ready / busy signal for plane group PG1 ( Figure 21 R / / B(PG1) changes from the "L" state to the "H" state.

[0237] also, Figure 20 In this context, the time from time point t204 to time point t212 is denoted as time T0. Additionally, Figure 21 In the diagram, the time from time t224 to time t232 is denoted as time T0'. As shown in the figure, time T0' is shorter than time T0.

[0238] Furthermore, the semiconductor memory device of the second embodiment may also be capable of performing the operation of the first embodiment.

[0239] Furthermore, the instruction set described above is simplified. The specific configuration of the instruction set actually input to the memory die MD during program writing can be adjusted appropriately. For example, during program writing, the instruction set corresponding to the lower bit data, the instruction set corresponding to the middle bit data, and the instruction set corresponding to the upper bit data, as described above, can also be input to the memory die MD. Additionally, when inputting the instruction set corresponding to the upper bit data, data 15h can be input instead of data 10h.

[0240] [Effects of the Semiconductor Memory Device of the Second Embodiment]

[0241] The semiconductor memory device according to the second embodiment can perform the same effect as the semiconductor memory device according to the first embodiment.

[0242] [Third Implementation]

[0243] Next, refer to Figure 22 The third embodiment will be described. Figure 22 This is a waveform diagram used to illustrate the writing procedure of the third embodiment. Figure 22 The diagram illustrates the selection word line WL within storage planes MP0 and MP1. S The supplied voltage, and the select word line WL in the storage planes MP8 and MP9. S The supplied voltage.

[0244] The preceding descriptions have illustrated an example of executing one write procedure on one memory plane. However, for example, the write procedure of sequencer SQCa can be executed simultaneously on some or all of the multiple memory planes MP0 to MP15 belonging to plane groups PG0 and PG1. Similarly, the write procedure of sequencer SQCb can be executed simultaneously on some or all of the multiple memory planes MP0 to MP15 belonging to plane groups PG0 and PG1. This aspect will be explained below.

[0245] The semiconductor memory device of the third embodiment is configured the same as the semiconductor memory device of the first embodiment.

[0246] The writing procedure of the third embodiment is basically the same as that of the reference. Figure 19 The described writing procedure is executed in the same way. However, Figure 19 In the example, the controller die CD inputs two instruction sets to the memory die MD. On the other hand, Figure 22 In the example, the controller die CD inputs four instruction sets to the memory die MD.

[0247] The first instruction set contains data 8Xh, data Plane0, and data 11h. The second instruction set contains data 8Xh, data Plane1, and data 10h. The third instruction set contains data 8Xh, data Plane8, and data 11h. The fourth instruction set contains data 8Xh, data Plane9, and data 10h.

[0248] Figure 22 In the example, before time point t144, the controller die CD inputs the first instruction set and the second instruction set to the memory die MD.

[0249] Additionally, during time points t144 to t148, the writing process for memory planes MP0 and MP1 begins. Furthermore, the controller die CD inputs the third and fourth instruction sets to the memory die MD.

[0250] Additionally, during time points t148 and t149, write operations are performed on storage planes MP0 and MP1, and then the write operations are terminated. Next, write operations begin on storage planes MP8 and MP9.

[0251] Additionally, during the period from time t149 to time t150, a write procedure is performed for storage plane MP8 and storage plane MP9, and then the write procedure is terminated.

[0252] Furthermore, the semiconductor memory device of the third embodiment may also be capable of performing the operations of the first and second embodiments.

[0253] Furthermore, the instruction sets described above are simplified. The specific configuration of the instruction sets actually input to the memory die MD during program writing can be adjusted appropriately. For example, during program writing, the instruction sets corresponding to the lower bits, the middle bits, and the upper bits can be input to the memory die MD as described above. However, after inputting the instruction set corresponding to the lower bits of memory plane MP0, when inputting the instruction set corresponding to the lower bits of memory plane MP1, data 1Ah can be input instead of data 11h. Similarly, after inputting the instruction set corresponding to the middle bits of memory plane MP0, when inputting the instruction set corresponding to the middle bits of memory plane MP1, data 1Ah can be input instead of data 11h. In addition, data 1Ah indicates the end of the input of the first instruction set related to the program writing and the input of the next instruction set before starting the program writing.

[0254] [Effects of the Semiconductor Memory Device in the Third Embodiment]

[0255] The semiconductor memory device according to the third embodiment can achieve the same effects as the semiconductor memory devices of the first and second embodiments. Furthermore, compared to the semiconductor memory devices of the first and second embodiments, the semiconductor memory device according to the third embodiment can write a larger amount of data in a single write operation. Therefore, compared to the semiconductor memory devices of the first and second embodiments, a semiconductor memory device with higher operating speed can be provided.

[0256] [Fourth Implementation]

[0257] Next, refer to Figure 23 The fourth embodiment will be described. Figure 23 This is a waveform diagram used to illustrate the writing procedure of the fourth embodiment. Figure 23 The diagram shows the selection word line WL within the storage plane MP0. S The supplied voltage, and the select word line WL within the storage plane MP8.S The supplied voltage.

[0258] The semiconductor memory device of the fourth embodiment is configured the same as the semiconductor memory device of the first embodiment.

[0259] The writing procedure of the fourth embodiment is basically in accordance with, as referred to Figure 19 The described writing procedure is executed in the same way. However, Figure 19 In the example, during the execution of the write program, the controller die CD did not input the instruction set to the memory die MD, etc. On the other hand, Figure 23 In the example, during the execution of the write program, the controller die CD inputs the instruction set to the memory die MD.

[0260] Figure 23 In the example, during the period from time point t148 to time point t301, the write procedure is performed for storage plane MP0 and storage plane MP8.

[0261] Additionally, at time t301, the controller die CD inputs data XXh to the memory die MD as instruction data. Data XXh is an instruction that temporarily interrupts (suspends) the write program.

[0262] Additionally, during time points t301 and t302, the write programs for memory planes MP0 and MP8 are temporarily interrupted (suspended). Furthermore, the controller die CD inputs a set of instructions to the memory die MD. This set of instructions includes data 00h, data Plane8, and data 30h. Data 00h is the instruction input at the start of the read operation. Data 30h is the instruction indicating that the input of the instruction set related to the read operation has ended.

[0263] Additionally, during time points t303 and t304, a read operation is performed on storage plane MP8. Furthermore, Figure 23 In the example, the select word line WL within the storage plane MP8 S Supply Reference Figure 12 The readout voltage V described CGAR V CGCR V CGFR This allows us to read the median data.

[0264] Additionally, at time t304, the controller die CD inputs data YYh to the memory die MD as instruction data. Data YYh is the instruction to restart (restore) the write program.

[0265] Additionally, at time t305, the writing process for storage planes MP0 and MP8 is restarted.

[0266] Furthermore, the semiconductor memory device of the fourth embodiment may also be capable of performing the operations of the first to third embodiments.

[0267] [Effects of the Semiconductor Memory Device in the Fourth Embodiment]

[0268] The semiconductor memory device according to the fourth embodiment can achieve the same effects as the semiconductor memory devices of the first to third embodiments. Furthermore, in the fourth embodiment, when a read operation is performed on a plane group PG1, the write operation to other plane groups PG0 is also interrupted. Therefore, the influence of the write operation on the read operation can be eliminated. Thus, a semiconductor memory device with high reliability can be provided.

[0269] [Fifth Implementation]

[0270] Next, refer to Figure 24 The fifth embodiment will now be described. Figure 24 This is a waveform diagram used to illustrate the writing procedure of the fifth embodiment. Figure 24 The diagram illustrates the selection word line WL within the storage plane MP0. S The supplied voltage, and the select word line WL within the storage plane MP8. S The supplied voltage.

[0271] The semiconductor memory device of the fifth embodiment is configured the same as the semiconductor memory device of the first embodiment.

[0272] The writing procedure in the fifth embodiment is basically the same as that in the reference. Figure 23 The described writing procedure is executed in the same way. However, Figure 23 In the example, with the input of data XXh, not only is the write procedure for storage plane MP8, which is the target of the read operation, interrupted, but the write procedure for storage plane MP0 is also interrupted. On the other hand, Figure 24 In the example, with the input of data XXh, the write procedure for storage plane MP8, which is the object of the read operation, is interrupted, while the write procedure for storage plane MP0 is not interrupted.

[0273] also, Figure 24 In the example, during the read operation for the storage plane MP8, the selection word line WL is... S Supply readout voltage V CGAR V CGCR V CGFR The timing points are respectively related to the verification action for the storage plane MP0, and the selection word line WL. S Supply verification voltage V VFYC V VFYD V VFYE The point in time (and) Figure 17 (The corresponding time points t122, t125, and t128) are also present.

[0274] Furthermore, the semiconductor memory device of the fifth embodiment may also be capable of performing the operations of the first to fourth embodiments.

[0275] In addition, when executing the writing procedure of the fifth embodiment, information that can determine whether to interrupt the writing procedure for any plane group can be input to the memory die MD before time point t301.

[0276] [Effects of the Semiconductor Memory Device in the Fifth Embodiment]

[0277] The semiconductor memory device according to the fifth embodiment can achieve the same effects as the semiconductor memory devices of the first to third embodiments. Furthermore, in the fifth embodiment, the timing of the read operation on one plane group PG1 differs from the timing of the programming operation on another plane group PG0. Additionally, in the fifth embodiment, the write operation on the other plane group PG0 is not interrupted while the read operation on one plane group PG1 is being performed. Therefore, a semiconductor memory device that suppresses the influence of the write operation on the read operation and operates at high speed can be provided.

[0278] [Sixth Implementation]

[0279] Next, refer to Figure 25 The sixth embodiment will now be described. Figure 25 This is a waveform diagram used to illustrate the writing procedure of the sixth embodiment. Figure 25 The diagram illustrates the select word line WL within the storage plane MP0. S The supplied voltage, and the select word line WL within the storage plane MP8. S The supplied voltage.

[0280] The semiconductor memory device of the sixth embodiment is configured the same as the semiconductor memory device of the first embodiment.

[0281] The writing procedure of the sixth embodiment is basically in accordance with, as referred to Figure 19 The writing procedure described is executed in the same way.

[0282] but, Figure 19 In the example, corresponding to Figure 17 The processes at time points t111 to t132 are always executed at fixed time intervals T1. For example, in loop number n... W When the value is 1, 2, or 17-19, select the word line WL. S Only one verification voltage is supplied. In this case, for example, omitting... Figure 17The processing after time point t125. However, Figure 19 In the example, the time equivalent to the processing after time point t125 is set as the waiting time, and the time interval T1 for executing each process is unified to a fixed size.

[0283] On the other hand, in this embodiment, such as Figure 25 As illustrated, during the periods t144 to t148 and t149 to t401 when only one of the storage planes MP0 and MP8 is written, the waiting time described above is omitted. That is, when only one or two verification voltages are supplied during the verification operation, the processing after t125 or after t128 is omitted. Furthermore, when two verification voltages are supplied during the verification operation, the time interval T3 is shorter than the time interval T1. Additionally, when only one verification voltage is supplied during the verification operation, the time interval T2 is shorter than the time interval T3.

[0284] In addition, in this embodiment, such as Figure 25 As illustrated, even when writing to both storage planes MP0 and MP8, if the number of verification voltages supplied during the verification operation is two or less, the processing after time point t128 is omitted. Furthermore, if the number of verification voltages supplied during the verification operation is one or less, the processing after time point t125 is omitted. For example, Figure 25 In the example, during the period after time point t401, the number of loops n for the write procedure against storage plane MP0 is... W Increase from 1 to 5. Additionally, in the stated number of cycles n... W During the period when it is 1, the number of verification voltages corresponding to storage plane MP0 is 1, and the number of verification voltages corresponding to storage plane MP8 is 2. The processes in the write program are executed at the time interval T3. Additionally, during the loop count n... W During the period of 2 iterations, the number of verification voltages corresponding to storage plane MP0 is 1, and the number of verification voltages corresponding to storage plane MP8 is 1. The processes in the write program are executed at the time interval T2. Additionally, during the loop count n... W During the three-time period, there are two verification voltages corresponding to storage plane MP0 and one verification voltage corresponding to storage plane MP8. The processes in the program are executed at the time interval T3.

[0285] Furthermore, the semiconductor memory device of the sixth embodiment may also be capable of performing the operations of the first to fifth embodiments.

[0286] [Effects of the Semiconductor Memory Device in Embodiment 6]

[0287] The semiconductor memory device according to the sixth embodiment can achieve the same effects as the semiconductor memory devices of the first to fifth embodiments. Furthermore, in the sixth embodiment, compared to the first to fifth embodiments, the time required for writing to a single plane can be reduced. Therefore, compared to the first to fifth embodiments, a semiconductor memory device with higher operating speed can be provided.

[0288] [Seventh Implementation]

[0289] Next, refer to Figure 26 The seventh embodiment will be described. Figure 26 This is a schematic top view of the memory die MD2 of the semiconductor memory device according to the seventh embodiment.

[0290] In the explanation up to this point, as referred to Figure 4 As explained above, the memory module MM includes plane groups PG0 and PG1. Furthermore, plane group PG0 includes storage planes MP0 to MP7, and plane group PG1 includes storage planes MP8 to MP15. However, this configuration is merely an example, and the actual configuration can be adjusted accordingly. This aspect will be explained below.

[0291] like Figure 26 As shown, the memory die MD2 is essentially the same as the reference. Figure 8 The memory die MD is constructed in the same manner as described above. However, unlike memory die MD which has two plane groups PG0 and PG1, memory die MD2 has four plane groups PG0' to PG3'. Plane group PG0' includes storage planes MP0 to MP3. Plane group PG1' includes storage planes MP4 to MP7. Plane group PG2' includes storage planes MP8 to MP11. Plane group PG3' includes storage planes MP12 to MP15.

[0292] Furthermore, like memory die MD, memory die MD2 can have two, three, or four write sequencers. Additionally, the wiring CG corresponding to plane group PG0' can be the same as or different from the wiring CG corresponding to plane group PG1'. Similarly, the wiring CG corresponding to plane group PG2' can be the same as or different from the wiring CG corresponding to plane group PG3'.

[0293] In addition, the semiconductor memory device of the seventh embodiment may also be capable of performing the operations of the first to sixth embodiments.

[0294] [Effects of the Semiconductor Memory Device in Embodiment 7]

[0295] The semiconductor memory device according to the seventh embodiment can achieve the same effects as the semiconductor memory devices of the first to sixth embodiments. Furthermore, in the seventh embodiment, compared to the first to sixth embodiments, a larger number of plane groups to be accessed can be selected. Therefore, the semiconductor memory device of the seventh embodiment sometimes operates at a higher speed compared to the semiconductor memory devices of the first to sixth embodiments.

[0296] [Eighth Implementation]

[0297] Next, refer to Figure 27 The eighth embodiment will now be described. Figure 27 This is a schematic top view of the memory die MD3 of the semiconductor memory device according to the eighth embodiment.

[0298] In the explanation up to this point, as referred to Figure 8 and Figure 26 As illustrated, multiple storage planes arranged in the X direction belong to the same plane group. However, this configuration is merely an example, and the actual configuration can be adjusted accordingly. This aspect will be explained below.

[0299] like Figure 27 As shown, the memory die MD3 is basically in line with the reference. Figure 8 and Figure 26 The memory die MD is constructed in the same way as described. However, while the four storage planes MP0 to MP3 arranged in the X direction in memory dies MD and MD2 belong to the same plane group PG0 and PG0', the four storage planes arranged in the Y direction in memory die MD3 belong to the same plane group.

[0300] That is, the memory die MD3 has four planar groups PG0” to PG3”. Planar group PG0” includes memory planes MP0, MP4, MP8, and MP12. Planar group PG1” includes memory planes MP1, MP5, MP9, and MP13. Planar group PG2” includes memory planes MP2, MP6, MP10, and MP14. Planar group PG3” includes memory planes MP3, MP7, MP11, and MP15.

[0301] Additionally, for example, as referenced Figure 8 As explained above, in the peripheral circuit region R of the memory die MD PC2 Corresponding to the four storage planes MP arranged in the Y direction, there are two sets of wiring CG. For example, Figure 8 In the example, corresponding to storage planes MP2, MP6, MP10, and MP14, there are groups consisting of multiple wiring CG0Cs and groups consisting of multiple wiring CG1Cs. On the other hand, as... Figure 27As shown, in the peripheral circuit region R of the memory die MD3 PC2 Corresponding to the four storage planes MP arranged in the Y direction, there is one set of wiring CG. For example, Figure 27 In the example, corresponding to storage planes MP2, MP6, MP10, and MP14, there is a group consisting of multiple wiring CGs.

[0302] Furthermore, the semiconductor memory device of the eighth embodiment may also be capable of performing the operations of the first to sixth embodiments.

[0303] [Effects of the Semiconductor Memory Device in Embodiment 8]

[0304] The semiconductor memory device according to the eighth embodiment can perform the same effects as the semiconductor memory devices of the first to sixth embodiments.

[0305] Furthermore, the memory dies MD and MD2 in embodiments 1 to 7 have multiple planar groups arranged in the Y direction. Each planar group also has multiple memory planes arranged in the X direction. In this configuration, in order to supply different voltages to memory planes such as WL belonging to different planar groups, it is necessary to provide a group of wiring CGs with the same number as the number of planar groups arranged in the Y direction. Therefore, the increase in the number of wiring CGs may lead to an increase in circuit area. Additionally, crosstalk may occur between two groups of wiring CGs located close to ground.

[0306] On the other hand, the memory die MD3 of the eighth embodiment has multiple planar groups arranged in the X direction. Furthermore, each planar group has multiple memory planes arranged in the Y direction. In particular, Figure 27 In the example, multiple storage planes belonging to the same plane group are all arranged in the Y direction. Therefore, it is sufficient to set one group of wiring CGs corresponding to each plane group. Therefore, the semiconductor memory device of the eighth embodiment can reduce the circuit area compared with the semiconductor memory devices of the first to seventh embodiments. In addition, the effects of crosstalk between wiring CGs as described above can be significantly suppressed.

[0307] [Ninth Implementation]

[0308] Next, refer to Figure 28 The ninth embodiment will be described. Figure 28 This is a schematic top view of the memory die MD4 of the semiconductor memory device according to the ninth embodiment.

[0309] In the explanation up to this point, as referred to Figure 4As explained above, the memory die MD has 16 memory planes MP0 to MP15. However, this configuration is merely an example, and the actual configuration can be adjusted accordingly. This will be explained below.

[0310] like Figure 28 As shown, the memory die MD4 is basically in line with the reference. Figure 8 The memory die MD is constructed in the same manner as described above. However, unlike the memory die MD which has two plane groups PG0 and PG1, the memory die MD4 has eight plane groups PG0” to PG7”. Plane group PG0” includes storage planes MP0 to MP3. Plane group PG1” includes storage planes MP4 to MP7. Plane group PG2” includes storage planes MP8 to MP11. Plane group PG3” includes storage planes MP12 to MP15. Plane group PG4” includes storage planes MP16 to MP19. Plane group PG5” includes storage planes MP20 to MP23. Plane group PG6” includes storage planes MP24 to MP27. Plane group PG7” includes storage planes MP28 to MP31.

[0311] Furthermore, the memory die MD4, like the memory die MD, can have two write sequencers, or three to eight write sequencers. Additionally, the wiring CG corresponding to plane group PG0” can be the same as or different from the wiring CG corresponding to plane group PG2”. Similarly, the wiring CG corresponding to plane group PG1” can be the same as or different from the wiring CG corresponding to plane group PG3”. Furthermore, the wiring CG corresponding to plane group PG4” can be the same as or different from the wiring CG corresponding to plane group PG6”. Finally, the wiring CG corresponding to plane group PG5” can be the same as or different from the wiring CG corresponding to plane group PG7”.

[0312] Furthermore, the semiconductor memory device of the ninth embodiment may also be capable of performing the operations of the first to sixth embodiments.

[0313] [Effects of the semiconductor memory device according to the ninth embodiment]

[0314] The semiconductor memory device according to the ninth embodiment can perform the same effects as the semiconductor memory devices of the first to sixth embodiments.

[0315] [Other Implementation Methods]

[0316] The semiconductor memory devices according to Embodiments 1 to 9 have been described above. However, this configuration is merely illustrative, and the specific configuration and method can be appropriately adjusted.

[0317] For example, in the semiconductor memory devices of embodiments 1 to 9, as referred to Figure 10 As explained above, the word line WL extends in the Y direction and the bit line BL extends in the X direction. However, this configuration is merely illustrative. For example, the word line WL could also extend in the X direction and the bit line BL could extend in the Y direction.

[0318] Furthermore, in the semiconductor memory devices of embodiments 1 to 9, multiple memory planes are grouped into multiple memory groups, and access is determined on a group-by-group basis. However, this configuration is merely an example. For instance, the semiconductor memory device may also be configured to determine access on a plane-by-plane basis.

[0319] Furthermore, in the semiconductor memory devices of embodiments 1 to 9, the lower end of the semiconductor layer 120 is connected to the semiconductor substrate 100. Additionally, all the transistors included in the peripheral circuit PC are formed on the upper surface of the semiconductor substrate 100. However, this configuration is merely an example. The writing process and other methods described above can also be applied to semiconductor memory devices with other structures. Hereinafter, the structure of such a semiconductor memory device will be illustrated.

[0320] For example, Figure 30 As shown, Figure 29 and Figure 30 The illustrated memory die MD5 includes a semiconductor substrate 100 and a transistor layer L disposed above the semiconductor substrate 100. TR and set in transistor layer L TR The upper storage cell array layer L MCA .

[0321] transistor layer L TR It has multiple transistors Tr. These multiple transistors Tr are field-effect transistors that use the upper surface of the semiconductor substrate 100 as the channel region. In the configuration shown, the peripheral circuit PC includes these multiple transistors Tr.

[0322] Storage cell array layer L MCA Basically with reference Figure 10 It is configured in the same manner as the semiconductor substrate 100 described above. However, the memory cell array layer L... MCA The system includes a conductive layer 112 disposed below the plurality of conductive layers 110. Furthermore, the lower end of the semiconductor layer 120 is connected to the conductive layer 112, rather than the semiconductor substrate 100.

[0323] in addition, Figure 29 In the example, in the peripheral circuit region R of the memory die MD5 PC2Wiring CG0C and CG1C are provided. Wiring CG0C is located in the area corresponding to plane group PG0. Wiring CG1C is located in the area corresponding to plane group PG1.

[0324] In this configuration, there is also a reference. Figure 27 The memory die MD3 described herein is the same, and compared with the semiconductor memory devices of Embodiments 1 to 7, the circuit area can be reduced. Furthermore, the effects of crosstalk between wiring CGs as described above can be significantly suppressed.

[0325] In addition, for example, Figure 31 The illustrated memory die MD6 has a chip C MCA and chip C TR These chips C MCA and chip C TR Possesses multiple bonding electrodes P containing copper (Cu) and the like. I Through these multiple bonding electrodes P I Electrical connection and physical connection.

[0326] For example, Figure 32 As shown, chip C MCA References may be included Figure 10 The configuration on the semiconductor substrate 100 described may also include Figure 30 Storage cell array layer L MCA The composition of the chip. Additionally, chip C... MCA It may or may not contain transistor Tr. In chip C... MCA Without transistor Tr, chip C MCA It may or may not include a semiconductor substrate 100. Additionally, in chip C... MCA In the case of including transistor Tr, such as Figure 33 As shown, chip C MCA May include references Figure 30 The transistor layer L described TR and storage cell array layer L MCA .

[0327] Chip C TR It includes a semiconductor substrate 200 and a plurality of transistors Tr'. The semiconductor substrate 200 may, for example, be configured to be substantially the same as the semiconductor substrate 100. The plurality of transistors Tr' are field-effect transistors that use the upper surface of the semiconductor substrate 200 as the channel region. Figure 32 and Figure 33 In the example, the peripheral circuit PC includes a chip C MCA and chip C TR The multiple transistors Tr and Tr' contained therein.

[0328] In this configuration, it is also relatively easy to adopt, as in reference... Figure 29 The wiring pattern of the wiring CG described. In this case, compared with the reference... Figure 27 Similarly, the memory die MD3 described herein can reduce the circuit area compared to the semiconductor memory devices of embodiments 1 to 7. Furthermore, it can significantly suppress the effects of crosstalk between wiring CGs as described above.

[0329] Additionally, in the above explanation, if you refer to Figure 19 The descriptions provided illustrate a semiconductor memory device capable of executing two or more write programs in parallel. Furthermore, the selection word line WL is used in one write program. S Supply programming voltage V PGM The timing of the selection word line WL in another write procedure S Supply programming voltage V PGM The timing is consistent. However, this method is merely an example, and the specific method can be adjusted accordingly. For example, as mentioned above, for the reference... Figure 27 The memory die MD3 and reference described Figure 29 The described memory die MD5 can significantly suppress the effects of crosstalk between wiring CGs as described above. Therefore, in this configuration, the select word line WL can be selected during a write operation. S Supply programming voltage V PGM The timing of the selection word line WL in another write procedure S Supply programming voltage V PGM The timing is consistent.

[0330] Additionally, the address comparison circuit (ADC) of the semiconductor memory device capable of executing the write program of the fifth embodiment... Figure 4 For example, corresponding to multiple plane groups, it can have multiple such Figure 34 The illustrated address comparison component is adc.

[0331] The address comparison component ADC is, for example, multiple latch circuits connected within the register module RM. As such latch circuits... Figure 34The diagram illustrates latch circuits DIL_0 to DIL_7, latch circuits ACL_0 to ACL_7, and latch circuits SPL_0 to SPL_7. Latch circuits DIL_0 to DIL_7 latch "H" when input with an instruction set the subject of performing a write operation on memory planes MP0 to MP7; otherwise, they latch "L". Latch circuits ACL_0 to ACL_7 latch "H" during the execution of a write operation on memory planes MP0 to MP7; otherwise, they latch "L". Latch circuits SPL_0 to SPL_7 latch "H" when input with information the subject of performing a read operation on memory planes MP0 to MP7; otherwise, they latch "L".

[0332] The address comparison component ADC, for example, includes multiple OR circuits 51_0 to 51_7, multiple AND circuits 52_0 to 52_7, and an OR circuit 53. Each of the OR circuits 51_0 to 51_7 has two input terminals. One input terminal is connected to latch circuits DIL_0 to DIL_7, and the other input terminal is connected to latch circuits ACL_0 to ACL_7. Each of the AND circuits 52_0 to 52_7 has two input terminals. One input terminal is connected to the output terminal of the OR circuits 51_0 to 51_7, and the other input terminal is connected to latch circuits SPL_0 to SPL_7. The OR circuit 53 has eight input terminals. These eight input terminals are connected to the output terminals of the AND circuits 52_0 to 52_7.

[0333] also, Figure 34 The image shows the address comparison component ADC corresponding to plane group PG0. The address comparison component corresponding to plane group PG1 is configured to... Figure 34 The illustrated address comparison components (adc) are largely the same. However, the address comparison component corresponding to plane group PG1 has multiple latch circuits corresponding to plane group PG1 instead of multiple latch circuits corresponding to plane group PG0.

[0334] For example, when executing the write procedure of the fifth embodiment, with the input of the instruction set intended to execute the write procedure, "H" can be latched into latch circuits DIL_0 to DIL_7 or any latch circuit corresponding to latch circuits DIL_0 to DIL_7. Additionally, with the start of the write procedure execution, "L" can be latched into latch circuits ACL_0 to ACL_7 or any latch circuit corresponding to latch circuits ACL_0 to ACL_7. Furthermore, "H" can also be latched into latch circuits SPL_0 to SPL_7 or any latch circuit corresponding to latch circuits SPL_0 to SPL_7 before the write procedure is interrupted (suspended). Furthermore, if the write procedure is interrupted, for example, if the output signal MTCH0 of the address comparison component adc corresponding to plane group PG0 is "H", the write procedure for plane group PG0 can be interrupted; if it is "L", it can remain uninterrupted. Similarly, when the output signal of the address comparison component corresponding to plane group PG1 is "H", the write procedure for plane group PG1 can be interrupted; when it is "L", it can be left uninterrupted.

[0335] [other]

[0336] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways and can be omitted, substituted, or modified in various ways without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention and are included within the scope of the invention as set forth in the claims and their equivalents.

[0337] [Explanation of Symbols]

[0338] MC storage unit

[0339] MCA storage cell array

[0340] BL bitline

[0341] WL lettering.

Claims

1. A semiconductor memory device, Equipped with a first memory die, The first memory die comprises: The first storage plane has multiple first memory blocks; The second storage plane has multiple second memory blocks; The first sequencer is capable of performing read operations, write operations, and erase operations on the first and second storage planes; and The second sequencer is capable of being used for writing programs to the first storage plane and the second storage plane, and when the first sequencer is used for writing programs to the first storage plane, the second sequencer is capable of being used for writing programs to the second storage plane, and when the first sequencer is used for writing programs to the second storage plane, the second sequencer is capable of being used for writing programs to the first storage plane.

2. The semiconductor memory device according to claim 1, wherein The circuit area of ​​the second sequencer is smaller than that of the first sequencer.

3. A semiconductor memory device, Equipped with a first memory die, The first memory die comprises: The first storage plane has multiple first memory blocks; and The second storage plane has multiple second memory blocks; After the first instruction set of the write program is executed on one of the plurality of first memory blocks, and before the write program corresponding to the first instruction set ends, When the second instruction set of the write procedure has already been written to one of the plurality of first memory blocks, the write procedure corresponding to the second instruction set is not executed. When the third instruction set has been written to one of the plurality of second memory blocks, the write procedure corresponding to the third instruction set is executed. If, after the third instruction set is input, the first instruction is input before the write program corresponding to the first instruction set ends, the write program corresponding to at least one of the first and third instruction sets is interrupted. If the second instruction is entered after the first instruction is entered, the interrupted writing process will restart.

4. The semiconductor memory device according to claim 3, comprising: Multiple first wirings are connected to the multiple first memory blocks; and Multiple second wirings are connected to the multiple second memory blocks; When the write procedure for one of the plurality of first memory blocks is set as the first write procedure, When the write procedure for one of the plurality of second memory blocks is set as the second write procedure, From the start of the first write procedure until the start of the second write procedure, a programming voltage is supplied to one of the plurality of first wirings one or more times. From the start of the second write procedure until the end of the first write procedure, the programming voltage is supplied to one of the plurality of first wirings and one of the plurality of second wirings one or more times.

5. The semiconductor memory device of claim 4, wherein during the period from the start of the second write procedure to the end of the first write procedure, the programming voltage is supplied to one of the plurality of first wirings and one of the plurality of second wirings at fixed time intervals, and the timing of supplying the programming voltage to one of the plurality of first wirings coincides with the timing of supplying the programming voltage to one of the plurality of second wirings.

6. The semiconductor memory device according to claim 4, wherein From the start of the second write procedure to the end of the first write procedure, The timing at which the programming voltage is first supplied to one of the plurality of first wirings coincides with the timing at which the programming voltage is first supplied to one of the plurality of second wirings. The timing of ending the supply of the programming voltage to one of the plurality of first wirings coincides with the timing of ending the supply of the programming voltage to one of the plurality of second wirings.

7. The semiconductor memory device according to claim 5, wherein From the start of the second write procedure to the end of the first write procedure, The timing at which the programming voltage is first supplied to one of the plurality of first wirings coincides with the timing at which the programming voltage is first supplied to one of the plurality of second wirings. The timing of ending the supply of the programming voltage to one of the plurality of first wirings coincides with the timing of ending the supply of the programming voltage to one of the plurality of second wirings.

8. The semiconductor memory device according to any one of claims 4 to 7, wherein If, after the first instruction is input and before the second instruction is input, a fourth instruction set instructing a read operation on one of the plurality of first memory blocks or the plurality of second memory blocks contained in one of the first storage plane and the second storage plane is input, a read voltage is supplied once or multiple times to one of the plurality of first wirings and the plurality of second wirings corresponding to the fourth instruction set. During the execution of the read operation, the programming voltage is not supplied to the plurality of first wirings or the plurality of second wirings corresponding to the other of the first storage plane and the second storage plane.

9. The semiconductor memory device according to claim 8, wherein If the first instruction is input after the third instruction set is input, but before the write program corresponding to the first instruction set ends, The write procedure corresponding to either the first instruction set or the third instruction set is interrupted. A verification voltage is supplied once or multiple times to one of the plurality of first wirings and the plurality of second wirings corresponding to the other of the first instruction set and the third instruction set. The timing of supplying the readout voltage to one of the plurality of first wirings and plurality of second wirings corresponding to the fourth instruction set is consistent with the timing of supplying the verification voltage to one of the plurality of first wirings and plurality of second wirings corresponding to the other of the first instruction set and the third instruction set.

10. The semiconductor memory device according to any one of claims 3 to 7, further comprising: The first sequencer is capable of performing read operations, write operations, and erase operations on the first and second storage planes; and The second sequencer is capable of being used for writing programs to the first storage plane and the second storage plane, and when the first sequencer is used for writing programs to the first storage plane, the second sequencer is capable of being used for writing programs to the second storage plane, and when the first sequencer is used for writing programs to the second storage plane, the second sequencer is capable of being used for writing programs to the first storage plane.

11. The semiconductor memory device according to claim 8, further comprising: The first sequencer is capable of performing read operations, write operations, and erase operations on the first storage plane and the second storage plane; and The second sequencer is capable of being used for writing programs to the first storage plane and the second storage plane, and when the first sequencer is used for writing programs to the first storage plane, the second sequencer is capable of being used for writing programs to the second storage plane, and when the first sequencer is used for writing programs to the second storage plane, the second sequencer is capable of being used for writing programs to the first storage plane.

12. The semiconductor memory device according to claim 9, further comprising: The first sequencer is capable of performing read operations, write operations, and erase operations on the first storage plane and the second storage plane; and The second sequencer is capable of being used for writing programs to the first storage plane and the second storage plane, and when the first sequencer is used for writing programs to the first storage plane, the second sequencer is capable of being used for writing programs to the second storage plane, and when the first sequencer is used for writing programs to the second storage plane, the second sequencer is capable of being used for writing programs to the first storage plane.

13. The semiconductor memory device of claim 10, wherein... The circuit area of ​​the second sequencer is smaller than that of the first sequencer.

14. The semiconductor memory device of claim 11, wherein The circuit area of ​​the second sequencer is smaller than that of the first sequencer.

15. The semiconductor memory device according to claim 12, wherein The circuit area of ​​the second sequencer is smaller than that of the first sequencer.

16. A semiconductor memory device, Equipped with a first memory die, The first memory die comprises: The first storage plane has multiple first memory blocks; and The second storage plane has multiple second memory blocks; After the first instruction set of the write program is executed on one of the plurality of first memory blocks, and before the write program corresponding to the first instruction set ends, When the second instruction set of the program has been written to one of the plurality of first memory blocks, the writing program corresponding to the second instruction set ends after a first time interval following the completion of the input to the first instruction set. When the third instruction set of the program has been written to one of the plurality of second memory blocks, after a second time interval following the completion of the input to the first instruction set, the writing program corresponding to the third instruction set ends. The second time is shorter than the first time. If, after the third instruction set is input, the first instruction is input before the write program corresponding to the first instruction set ends, the write program corresponding to at least one of the first and third instruction sets is interrupted. If the second instruction is entered after the first instruction is entered, the interrupted writing process will restart.

17. The semiconductor memory device according to claim 16, comprising: Multiple first wirings are connected to the multiple first memory blocks; and Multiple second wirings are connected to the multiple second memory blocks; When the write procedure for one of the plurality of first memory blocks is set as the first write procedure, When the write procedure for one of the plurality of second memory blocks is set as the second write procedure, From the start of the first write procedure until the start of the second write procedure, a programming voltage is supplied to one of the plurality of first wirings one or more times. From the start of the second write procedure until the end of the first write procedure, the programming voltage is supplied to one of the plurality of first wirings and one of the plurality of second wirings one or more times.

18. The semiconductor memory device of claim 17, wherein during the period from the start of the second write procedure to the end of the first write procedure, the programming voltage is supplied to one of the plurality of first wirings and one of the plurality of second wirings at fixed time intervals, the timing of supplying the programming voltage to one of the plurality of first wirings coincides with the timing of supplying the programming voltage to one of the plurality of second wirings.

19. The semiconductor memory device according to claim 17, wherein From the start of the second write procedure to the end of the first write procedure, The timing at which the programming voltage is first supplied to one of the plurality of first wirings coincides with the timing at which the programming voltage is first supplied to one of the plurality of second wirings. The timing of ending the supply of the programming voltage to one of the plurality of first wirings coincides with the timing of ending the supply of the programming voltage to one of the plurality of second wirings.

20. The semiconductor memory device of claim 18, wherein... From the start of the second write procedure to the end of the first write procedure, The timing at which the programming voltage is first supplied to one of the plurality of first wirings coincides with the timing at which the programming voltage is first supplied to one of the plurality of second wirings. The timing of ending the supply of the programming voltage to one of the plurality of first wirings coincides with the timing of ending the supply of the programming voltage to one of the plurality of second wirings.

21. The semiconductor memory device according to any one of claims 17 to 20, wherein If, after the first instruction is input and before the second instruction is input, a fourth instruction set instructing a read operation on one of the plurality of first memory blocks or the plurality of second memory blocks contained in one of the first storage plane and the second storage plane is input, a read voltage is supplied once or multiple times to one of the plurality of first wirings and the plurality of second wirings corresponding to the fourth instruction set. During the execution of the read operation, the programming voltage is not supplied to the plurality of first wirings or the plurality of second wirings corresponding to the other of the first storage plane and the second storage plane.

22. The semiconductor memory device of claim 21, wherein... If the first instruction is input after the third instruction set is input, but before the write program corresponding to the first instruction set ends, The write procedure corresponding to either the first instruction set or the third instruction set is interrupted. A verification voltage is supplied once or multiple times to one of the plurality of first wirings and the plurality of second wirings corresponding to the other of the first instruction set and the third instruction set. The timing of supplying the readout voltage to one of the plurality of first wirings and plurality of second wirings corresponding to the fourth instruction set is consistent with the timing of supplying the verification voltage to one of the plurality of first wirings and plurality of second wirings corresponding to the other of the first instruction set and the third instruction set.

23. The semiconductor memory device according to any one of claims 16 to 20, further comprising: The first sequencer is capable of performing read operations, write operations, and erase operations on the first and second storage planes; and The second sequencer is capable of being used for writing programs to the first storage plane and the second storage plane, and when the first sequencer is used for writing programs to the first storage plane, the second sequencer is capable of being used for writing programs to the second storage plane, and when the first sequencer is used for writing programs to the second storage plane, the second sequencer is capable of being used for writing programs to the first storage plane.

24. The semiconductor memory device according to claim 21, further comprising: The first sequencer is capable of performing read operations, write operations, and erase operations on the first and second storage planes; and The second sequencer is capable of being used for writing programs to the first storage plane and the second storage plane, and when the first sequencer is used for writing programs to the first storage plane, the second sequencer is capable of being used for writing programs to the second storage plane, and when the first sequencer is used for writing programs to the second storage plane, the second sequencer is capable of being used for writing programs to the first storage plane.

25. The semiconductor memory device according to claim 22, further comprising: The first sequencer is capable of performing read operations, write operations, and erase operations on the first and second storage planes; and The second sequencer is capable of being used for writing programs to the first storage plane and the second storage plane, and when the first sequencer is used for writing programs to the first storage plane, the second sequencer is capable of being used for writing programs to the second storage plane, and when the first sequencer is used for writing programs to the second storage plane, the second sequencer is capable of being used for writing programs to the first storage plane.

26. The semiconductor memory device of claim 23, wherein... The circuit area of ​​the second sequencer is smaller than that of the first sequencer.

27. The semiconductor memory device of claim 24, wherein The circuit area of ​​the second sequencer is smaller than that of the first sequencer.

28. The semiconductor memory device of claim 25, wherein... The circuit area of ​​the second sequencer is smaller than that of the first sequencer.

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