Semiconductor memory device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor storage device and a manufacturing method thereof, and relates to the technical field of semiconductor. The semiconductor storage device comprises: an insulating layer; an active region formed on the upper surface of the insulating layer, the active region comprising a channel region, a source and a drain, the source and the drain being located on both sides of the channel region; a charge trapping layer formed on the upper surface of the channel region, a plurality of charge trapping layers being arranged at intervals; a gate formed on the upper surface of the charge trapping layer, one gate corresponding to one charge trapping layer; and a word line formed on the upper surface of the gate, the word line being connected to the gate. The present disclosure can improve the integration of the semiconductor storage device.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor memory device and a method for manufacturing the same. Background Technology

[0002] To meet consumer demand for superior performance and low prices, high integration is the development direction of semiconductor memory devices. Generally, integration level is determined by the area occupied by a single memory cell.

[0003] To improve integration, a capacitor-free memory cell has been proposed, which can significantly reduce the area occupied by the memory cell, based on the traditional memory cell with one transistor and one capacitor.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a semiconductor memory device and a method for manufacturing the same, which can improve the integration of the semiconductor memory device.

[0006] According to one aspect of this disclosure, a semiconductor memory device is provided, comprising:

[0007] Insulating layer;

[0008] An active region is formed on the upper surface of the insulating layer. The active region includes a channel region, a source, and a drain, with the source and the drain located on opposite sides of the channel region.

[0009] A charge trapping layer is formed on the upper surface of the channel region, and multiple charge trapping layers are spaced apart.

[0010] A gate is formed on the upper surface of the charge trapping layer, and one gate corresponds to one charge trapping layer;

[0011] A word line is formed on the upper surface of the gate and is connected to the gate.

[0012] Optionally, the active region includes multiple sub-active regions, which are spaced apart, and each sub-active region includes the channel region, the source, and the drain.

[0013] Optionally, the extension direction of the sub-active region is perpendicular to the extension direction of the charge trapping layer.

[0014] Optionally, the gate includes:

[0015] A gate oxide layer is formed on the upper surface of the charge trapping layer, and the gate oxide layer is in contact with the charge trapping layer. One gate oxide layer corresponds to one charge trapping layer.

[0016] A gate metal layer is formed on the upper surface of the gate oxide layer.

[0017] Optionally, the charge trapping layer, the gate oxide layer, the gate metal layer, and the word line have the same length and width in the extension direction.

[0018] Optional, also includes:

[0019] A protective layer is formed on the surface of the word line, the gate and the charge trapping layer, and on the upper surface of the active region;

[0020] An isolation layer is formed on the surface of the protective layer and fills the gaps between the word lines.

[0021] Optional, also includes:

[0022] A first conductor penetrates the isolation layer and the protective layer and is in contact with the source electrode;

[0023] The second conductor penetrates the isolation layer and the protective layer and is in contact with the drain electrode.

[0024] According to one aspect of this disclosure, a method for manufacturing a semiconductor memory device is provided, comprising:

[0025] Form an insulating layer;

[0026] An active region is formed on the surface of the insulating layer, and a source and a drain are formed at both ends of the active region. The region between the source and the drain is a channel region.

[0027] A trapping layer, a gate oxide layer, a gate metal layer, and a blocking layer are sequentially deposited on the surface of the active region;

[0028] The trapping layer, the gate oxide layer, the gate metal layer, and the barrier layer are etched to form a charge trapping layer, a gate, and a word line, wherein the charge trapping layer is in contact with the channel region.

[0029] Optionally, forming an active region on the surface of the insulating layer includes:

[0030] A silicon layer is deposited on the surface of the insulating layer;

[0031] The silicon layer is etched to form multiple spaced sub-active regions;

[0032] The two ends of the sub-active region are doped with ions of opposite types to form the source and the drain.

[0033] Optionally, etching the silicon layer to form a plurality of spaced sub-active regions includes:

[0034] The silicon layer is etched to form multiple spaced wire structures;

[0035] The sub-active region is formed by ion doping the wire structure.

[0036] Optionally, ion doping of the wire structure to form the sub-active region includes:

[0037] The sub-active region is formed by P-type ion doping of the wire structure.

[0038] Optionally, the extension direction of the sub-active region is perpendicular to the extension direction of the charge trapping layer.

[0039] Optionally, the method further includes:

[0040] Provide silicon substrates;

[0041] The insulating layer is deposited on the surface of the silicon substrate.

[0042] Optionally, the method further includes:

[0043] A protective layer is deposited on the surface of the charge trapping layer, the gate, the word line, and the upper surface of the active region;

[0044] An isolation layer is formed on the surface of the protective layer, and the isolation layer fills the gaps between the letter lines.

[0045] Optionally, the method further includes:

[0046] A first through-hole and a second through-hole are formed, penetrating the protective layer and the isolation layer; wherein the first through-hole exposes the source electrode and the second through-hole exposes the drain electrode;

[0047] The first through hole is filled with conductive material to form a first conductor, and the second through hole is filled with conductive material to form a second conductor.

[0048] The semiconductor memory device provided by the exemplary embodiments of this disclosure provides a method for creating a semiconductor memory device by providing multiple charge trapping layers at corresponding positions in the channel region and forming corresponding gates on the upper surface of the charge trapping layers. On the one hand, when there are multiple gates, the multiple gates can share the same source and drain pair, thereby reducing the area occupied by the memory cell; on the other hand, since the charge trapping layers are located above the channel region and do not directly contact the source and drain, there is no charge leakage, thus enhancing the data retention time of the charge trapping layers.

[0049] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0050] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0051] Figure 1 A cross-sectional view of a capacitorless dynamic random access memory is shown.

[0052] Figure 2 This is a schematic diagram of the structure of a semiconductor memory device provided as an exemplary embodiment of the present disclosure.

[0053] Figure 3 It shows Figure 2 A schematic cross-sectional view of the provided semiconductor memory device in the active region.

[0054] Figure 4 A diagram showing the positional relationship between a sub-active region and a gate in a semiconductor memory device according to an exemplary embodiment of the present disclosure is provided.

[0055] Figures 5(a)-5(h) are explanatory diagrams of the fabrication of a semiconductor memory device provided by an exemplary embodiment of the present disclosure. Detailed Implementation

[0056] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that the invention will be thorough and complete, and the concept of the exemplary embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0057] The features, structures, or characteristics described above can be combined in any suitable manner in one or more embodiments, and the features discussed in the various embodiments are interchangeable where possible. In the above description, numerous specific details are provided to give a full understanding of embodiments of the invention. However, those skilled in the art will recognize that the technical solutions of the invention can be practiced without one or more of the specific details described, or other methods, materials, etc., can be employed. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring various aspects of the invention.

[0058] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0059] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and that other elements / components / etc. may exist in addition to those listed. The terms “first” and “second” are used only as markers and are not a limitation on the number of objects.

[0060] Reference Figure 1 The diagram shows a cross-sectional view of a capacitorless dynamic random access memory (DRAM).

[0061] like Figure 1 As shown, the gate 110 can be formed on a silicon substrate 120. The silicon substrate 120 is formed by sequentially stacking a first silicon layer 121, an oxide layer 123, and a second silicon layer 125. The gate 110 is formed by sequentially stacking a gate insulating layer 111 and a gate conductive layer 113. The source 130 and drain 140 are formed in the second silicon layer 125 on both sides of the gate 110. A floating channel body 150, electrically isolated from the first silicon layer 121, is formed in the second silicon layer 125 between the source 130 and the drain 140. This capacitorless dynamic random access memory stores data values ​​"1" or "0" by accumulating holes or electrons within the floating channel body 150.

[0062] Further research by the applicant revealed that there is still room for reduction in the area occupied by the memory cells in the aforementioned capacitorless dynamic random access memory.

[0063] Based on this, the exemplary embodiments of this disclosure provide a semiconductor memory device to further reduce the footprint of memory cells in capacitor-free dynamic random access memory, thereby improving the integration density of the semiconductor memory device. (Refer to...) Figure 2 The semiconductor memory device may include an insulating layer 210, a charge trapping layer 230, an active region 250, a gate 270, and a word line 290, wherein:

[0064] The insulating layer 210 is mainly used to support the active region 250 and provide an insulating environment for the active region 250. The structure of the insulating layer 210 can be cuboid or the like, and the thickness can be set according to the actual situation, for example, a few micrometers, etc. This exemplary embodiment does not make any special limitation in this regard. In the actual manufacturing process, the insulating layer 210 can be an oxide insulating layer and is deposited on the surface of the silicon substrate 200.

[0065] An active region 250 is formed on the upper surface of the insulating layer 210. In an exemplary embodiment of this disclosure, the active region 250 is a semiconductor layer, such as a polysilicon layer. The active region 250 includes a channel region 251, a source 252, and a drain 253, wherein the source 252 and the drain 253 are located on both sides of the channel region 251, which is in contact with the charge trapping layer 230.

[0066] In an exemplary embodiment of this disclosure, a charge trapping layer 230 is formed on the upper surface of the channel region 251. In order to improve the space utilization of the storage cell, there can be multiple charge trapping layers 230, that is, multiple charge trapping layers 230 are arranged at intervals, and adjacent charge trapping layers 230 can be arranged in a parallel interval manner.

[0067] In practical applications, the charge trapping layer 230 can be a silicon nitride layer or a graphene layer. Taking the charge trapping layer 230 as a silicon nitride layer as an example, from the perspective of data storage, when a voltage is applied to the gate and drain, and the source is grounded, an electric field is generated in the channel region 251, which accelerates electrons. These electrons are trapped and stored in the charge trapping layer 230 for data storage.

[0068] exist Figure 1 In the capacitorless DRAM shown, due to the relatively large contact area of ​​the floating channel 150 with the source 130 and drain 140, a significant amount of charge leaks through the contact surface between them. Consequently, the data retention time in the floating channel 150 is reduced.

[0069] The semiconductor memory device provided in the exemplary embodiments of this disclosure has no charge leakage because the charge trapping layer 230 is disposed above the channel region 251 and does not directly contact the source 252 and the drain 253. Therefore, the data retention time of the charge trapping layer 230 is longer than that of the floating channel body 150.

[0070] In an exemplary embodiment of this disclosure, a gate 270 is formed on the upper surface of the charge trapping layer 230, and the gate 270 is in contact with the charge trapping layer 230. Depending on the number of charge trapping layers 230, multiple gates 270 may be provided, with one gate 270 corresponding to one charge trapping layer 230. Thus, as... Figure 2The multiple gates 270 shown can share the same pair of source 252 and drain 253, thereby reducing the area occupied by the memory cell.

[0071] In practical applications, if Figure 2 When there is only one gate 270, multiple active regions 250 can be configured. This allows multiple pairs of source 252 and drain 253 to share a single gate 270, thus reducing the area occupied by the memory cell. The configuration for multiple pairs of source 252 and drain 253 can be found in [reference needed]. Figure 3 As shown.

[0072] Figure 3 It shows Figure 2 The provided schematic diagram shows a cross-sectional view of the active region of the semiconductor memory device. Figure 3 As can be seen, the active region 250 of the semiconductor memory device may include multiple sub-active regions 254, and the multiple sub-active regions 254 are arranged at intervals. Each sub-active region 254 includes a channel region 251, a source 252, and a drain 253. Each sub-active region 254 corresponds to a pair of source 252 and drain 253. That is to say, in this case, even if there is only one gate 270, multiple pairs of source 252 and drain 253 can share the same gate 270, which can also achieve the effect of reducing the area occupied by the memory cell.

[0073] like Figure 4 This diagram shows the positional relationship between the active region and the gate. Figure 4 In this configuration, there are three sub-active regions 254 and three gates 270, with the sub-active regions 254 and gates 270 arranged vertically. Each gate 270 has a corresponding charge trapping layer 230 underneath. In this case, multiple gates 270 can share multiple pairs of source electrodes 252 and drain electrodes 253, which can greatly reduce the area occupied by the memory cell.

[0074] In practical applications, the number of sub-active regions 254, gates 270, and charge trapping layers 230 can be set according to actual conditions. In the exemplary embodiment of this disclosure, when there is one sub-active region 254, there are at least two gates 270; when there is one gate 270, there are at least two sub-active regions 254, so as to reduce the occupied area.

[0075] It should be noted that the gate 270 mainly includes a gate oxide layer 271 and a gate metal layer 272. The gate oxide layer 271 is formed on the upper surface of the charge trapping layer 230 and is in contact with the charge trapping layer 230. One gate oxide layer 271 corresponds to one charge trapping layer 230. The gate metal layer 272 is formed on the upper surface of the gate oxide layer 271. The charge trapping layer 230, the gate oxide layer 271, the gate metal layer 272, and the word line 290 have the same length and width in the extending direction.

[0076] In an exemplary embodiment of this disclosure, word lines 290 are formed on the upper surface of gates 270, and one word line 290 connects to one gate 270. To further improve the integration of the semiconductor memory device and reduce the occupied area of ​​the memory cell, word lines 290 may be embedded word lines.

[0077] Specifically, in order to achieve embedded word lines, the semiconductor memory device further includes a protective layer 220 and an isolation layer 240. The protective layer 220 is formed on the surface of the word line 290 and the gate 270, and on the upper surface of the active region 250. The isolation layer 240 is formed on the surface of the protective layer 220 and fills the gap between the word lines 290 to isolate the word lines 290 and avoid leakage risk between the word lines 290 and adjacent word lines 290.

[0078] In practical applications, power can be supplied to the source 252 and drain 253 by providing terminals on their sides. Alternatively, a first conductor 260 and a second conductor 280 can be provided, where the first conductor 260 penetrates the isolation layer 240 and the protective layer 220 and contacts the source 252; while the second conductor 280 penetrates the isolation layer 240 and the protective layer 220 and contacts the drain 253. The first conductor 260 and the second conductor 280 can serve as terminals to supply power to the source 252 and drain 253.

[0079] In practical applications, the formation of the first conductor 260 and the second conductor 280 can be set according to the actual situation, for example, Figure 2 As shown, the cross-sectional shape of the first conductor 260 and the second conductor 280 is trapezoidal, but it can also be rectangular. This exemplary embodiment does not impose any special limitations on the specific shape of the first conductor 260 and the second conductor 280.

[0080] The semiconductor memory device provided by the exemplary embodiments of this disclosure provides multiple charge trapping layers at corresponding positions in the channel region, and corresponding gates are formed on the upper surface of the charge trapping layers. On the one hand, when there are multiple gates, the multiple gates can share the same pair of source and drain electrodes, thereby reducing the area occupied by the memory cell. On the other hand, when there is only one gate, multiple channel regions can be provided, resulting in multiple pairs of source and drain electrodes. In this case, multiple pairs of source and drain electrodes can share a single gate, which also reduces the area occupied by the memory cell. Furthermore, since the charge trapping layers are disposed above the channel region and do not directly contact the source and drain electrodes, there is no charge leakage. Therefore, the data retention time of the charge trapping layers is enhanced.

[0081] The method for manufacturing a semiconductor memory device according to an exemplary embodiment of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0082] It should be understood that the accompanying drawings are not drawn to scale according to the actual device structure in order to illustrate the process effect.

[0083] In an exemplary embodiment of this disclosure, the main fabrication process steps of the semiconductor memory device are as follows:

[0084] Step 10: Form an insulating layer;

[0085] Step 20: An active region is formed on the surface of the insulating layer, and a source and a drain are formed at both ends of the active region. The region between the source and the drain is the channel region.

[0086] Step 30: Sequentially deposit a trapping layer, a gate oxide layer, a gate metal layer, and a blocking layer on the surface of the active region;

[0087] Step 40: Etch the trap layer, gate oxide layer, gate metal layer and barrier layer to form the charge trap layer, gate and word line, with the charge trap layer in contact with the channel region.

[0088] The following will illustrate the manufacturing process of semiconductor memory devices through two specific implementation methods.

[0089] Specifically, the manufacturing process steps for the first type of semiconductor memory device are as follows:

[0090] As shown in Figure 5(a), a silicon substrate 200 is provided, and an insulating layer 210 is formed by depositing an oxide layer on the surface of the silicon substrate 200.

[0091] As shown in Figure 5(b), a silicon layer 510 is deposited on the surface of the insulating layer 210. The silicon layer 510 can be a polycrystalline silicon layer.

[0092] As shown in Figure 5(c), the silicon layer 510 is etched, for example, by patterned etching, to form multiple spaced wire structures. These wire structures are then ion-doped, for example, with P-type ions to form a sub-active region 254. Opposite-type ions are doped at both ends of the sub-active region 254 to form a source 252 and a drain 253. The specific shape and doping concentration of the patterned mask layer can be determined according to actual conditions and will not be elaborated here.

[0093] As shown in Figure 5(d), a trapping layer 520, a gate oxide layer 271, a gate metal layer 272, and a barrier layer 530 are sequentially deposited on the surface of the sub-active region 254 formed in Figure 5(c). The barrier layer 530 is mainly used to form word lines 290. Specifically, during the deposition process, the gate metal layer 272 can be a single layer of metal or multiple layers of metal.

[0094] As shown in Figure 5(e), the trapping layer 520, gate oxide layer 271, gate metal layer 272, and barrier layer 530 are patterned and etched to form a charge trapping layer 230, gate 270, and word line 290. Multiple charge trapping layers 230 contact the same channel region 251. Figure 4 As shown, there are multiple pairs of gate 270 and word lines 290 formed. The extension direction of the word lines 290 is perpendicular to the extension direction of the sub-active region 254.

[0095] As shown in Figure 5(f), a protective layer 220 is deposited on the surface of the charge trapping layer 230, the gate 270, the word line 290, and the upper surface of the active region 250, so that the protective layer 220 covers the surface of the structure shown in Figure 5(e).

[0096] As shown in Figure 5(g), an isolation layer 240 is formed on the surface of the protective layer 220. The isolation layer 240 fills the gaps between the word lines 290 to achieve the purpose of isolating the word lines 290, and the top surface of the isolation layer 240 is a horizontal plane. The isolation layer 240 can be deposited from an insulating material such as silicon dioxide.

[0097] As shown in Figure 5(h), based on the structure shown in Figure 5(g), a first through-hole and a second through-hole are formed, penetrating the protective layer 220 and the isolation layer 240; wherein, the first through-hole exposes the source electrode 252, and the second through-hole exposes the drain electrode 253; and conductive material is filled into the first through-hole to form a first conductor 540, and conductive material is filled into the second through-hole to form a second conductor 550, thereby obtaining the following... Figure 2 The semiconductor memory device shown.

[0098] It should be noted that the method for manufacturing a semiconductor memory device provided in the exemplary embodiments of this disclosure is merely illustrative, and this disclosure does not limit the manufacturing process of each component.

[0099] It should be understood that in the various embodiments of this disclosure, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the exemplary embodiments of this disclosure.

[0100] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A semiconductor memory device, characterized in that, include: Insulating layer; An active region is formed on the upper surface of the insulating layer. The active region includes a channel region, a source, and a drain, with the source and the drain located on opposite sides of the channel region. A charge trapping layer is formed on the upper surface of the channel region, and multiple charge trapping layers are spaced apart. A gate is formed on the upper surface of the charge trapping layer. Multiple gates can be provided, with one gate corresponding to one charge trapping layer. Multiple gates share the same pair of source and drain electrodes. A word line is formed on the upper surface of the gate and is connected to the gate.

2. The semiconductor memory device according to claim 1, characterized in that, The active region includes multiple sub-active regions, which are spaced apart. Each sub-active region includes the channel region, the source, and the drain.

3. The semiconductor memory device according to claim 2, characterized in that, The extension direction of the sub-active region is perpendicular to the extension direction of the charge trapping layer.

4. The semiconductor memory device according to claim 1, characterized in that, The gate includes: A gate oxide layer is formed on the upper surface of the charge trapping layer, and the gate oxide layer is in contact with the charge trapping layer. One gate oxide layer corresponds to one charge trapping layer. A gate metal layer is formed on the upper surface of the gate oxide layer.

5. The semiconductor memory device according to claim 4, characterized in that, The charge trapping layer, the gate oxide layer, the gate metal layer, and the word line have the same length and width in the extension direction.

6. The semiconductor memory device according to any one of claims 1-5, characterized in that, Also includes: A protective layer is formed on the surface of the word line, the gate and the charge trapping layer, and on the upper surface of the active region; An isolation layer is formed on the surface of the protective layer and fills the gaps between the word lines.

7. The semiconductor memory device according to claim 6, characterized in that, Also includes: A first conductor penetrates the isolation layer and the protective layer and is in contact with the source electrode; The second conductor penetrates the isolation layer and the protective layer and is in contact with the drain electrode.

8. A method for manufacturing a semiconductor memory device, characterized in that, include: Form an insulating layer; An active region is formed on the surface of the insulating layer, and a source and a drain are formed at both ends of the active region. The region between the source and the drain is a channel region. A trapping layer, a gate oxide layer, a gate metal layer, and a blocking layer are sequentially deposited on the surface of the active region; The capture layer, the gate oxide layer, the gate metal layer, and the barrier layer are etched to form a charge capture layer, a gate, and a word line. Multiple charge capture layers and gates can be provided, with one gate corresponding to one charge capture layer. Multiple gates share the same pair of source and drain electrodes. The charge capture layer is in contact with the channel region.

9. The method for manufacturing a semiconductor memory device according to claim 8, characterized in that, Forming an active region on the surface of the insulating layer includes: A silicon layer is deposited on the surface of the insulating layer; The silicon layer is etched to form multiple spaced sub-active regions; The two ends of the sub-active region are doped with ions of opposite types to form the source and the drain.

10. The method for manufacturing a semiconductor memory device according to claim 9, characterized in that, Etching the silicon layer to form a plurality of spaced sub-active regions includes: The silicon layer is etched to form multiple spaced wire structures; The sub-active region is formed by ion doping the wire structure.

11. The method for manufacturing a semiconductor memory device according to claim 10, characterized in that, Forming the sub-active region by ion doping the wire structure includes: The sub-active region is formed by P-type ion doping of the wire structure.

12. The method for manufacturing a semiconductor memory device according to claim 10, characterized in that, The extension direction of the sub-active region is perpendicular to the extension direction of the charge trapping layer.

13. The method for manufacturing a semiconductor memory device according to claim 8, characterized in that, The method further includes: Provide silicon substrates; The insulating layer is deposited on the surface of the silicon substrate.

14. A method for manufacturing a semiconductor memory device according to any one of claims 8-13, characterized in that, The method further includes: A protective layer is deposited on the surface of the charge trapping layer, the gate, the word line, and the upper surface of the active region; An isolation layer is formed on the surface of the protective layer, and the isolation layer fills the gaps between the letter lines.

15. The method for manufacturing a semiconductor memory device according to claim 14, characterized in that, The method further includes: A first through-hole and a second through-hole are formed, penetrating the protective layer and the isolation layer; wherein the first through-hole exposes the source electrode and the second through-hole exposes the drain electrode; The first through hole is filled with conductive material to form a first conductor, and the second through hole is filled with conductive material to form a second conductor.

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