Semiconductor package and method of forming a semiconductor package

Abstract

A semiconductor package includes a first die, a second die, an encapsulation material, and a redistribution structure. The second die is disposed above the first die and includes a plurality of bond pads bonded to the first die, a plurality of through-holes extending through a substrate of the second die, and a plurality of alignment marks, wherein a pitch between adjacent two of the plurality of alignment marks is different from a pitch between adjacent two of the plurality of through-holes. The encapsulation material is disposed above the first die and laterally encapsulates at least the second die. The redistribution structure is disposed above the second die and the encapsulation material and is electrically connected to the plurality of through-holes. Embodiments of the invention also relate to methods of forming a semiconductor package.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor packages and methods for forming semiconductor packages. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers over a semiconductor substrate, and then using photolithography to pattern the individual layers to form circuit components and elements on each layer. Many integrated circuits are typically fabricated on a single semiconductor wafer. The wafer die can be processed and packaged at the wafer level, and various technologies have been developed for wafer-level packaging. Summary of the Invention

[0003] Embodiments of the present invention provide a semiconductor package comprising: a first die, wherein the first die includes a first bonding pad; a second die disposed above the first die, wherein the second die includes a second bonding pad, wherein the first bonding pad is bonded to the second bonding pad, wherein the second die includes a substrate and a plurality of through-holes extending through the substrate, wherein the second die includes a plurality of alignment marks, wherein the pitch between two adjacent alignment marks is different from the pitch between two adjacent through-holes; a sealing material disposed above the first die, the sealing material laterally sealing the second die; and a redistribution structure disposed above the second die and the sealing material, wherein the redistribution structure includes a conductive component, wherein the conductive component is electrically connected to a corresponding through-hole among the plurality of through-holes.

[0004] Another embodiment of the present invention provides a semiconductor package comprising: a first die; a second die disposed above and bonded to the first die, wherein the second die includes a substrate and a plurality of through-holes extending through the substrate, wherein the second die includes a plurality of alignment marks, wherein the depth of the plurality of alignment marks is different from the depth of the plurality of through-holes; a first sealing material laterally sealing the first die and the second die; and a first redistribution structure disposed above the second die and the first sealing material, wherein the first redistribution structure includes a first conductive member electrically connected to the first die and the second die.

[0005] Another embodiment of the present invention provides a method for forming a semiconductor package, comprising: bonding a first die to a second die, wherein the first die includes a plurality of first bonding pads, wherein the second die includes a plurality of second bonding pads bonded to corresponding first bonding pads among the plurality of first bonding pads, wherein the second die includes a plurality of through holes electrically connected to corresponding second bonding pads among the plurality of second bonding pads; forming a sealing material over the first die, wherein the sealing material laterally seals the second die; forming a plurality of alignment marks on the second die, wherein the pitch between two adjacent alignment marks among the plurality of alignment marks is different from the pitch between two adjacent through holes among the plurality of through holes; and forming a redistribution structure over the second die and the sealing material. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figures 1 to 10 A cross-sectional view is shown of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present invention.

[0008] Figure 11 A schematic diagram of alignment marks for a semiconductor package according to some embodiments of the present invention is shown.

[0009] Figures 12 to 16 A schematic top view of various alignment marks according to some embodiments of the present invention is shown.

[0010] Figure 17 A schematic cross-sectional view of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present invention is shown.

[0011] Figure 18 A schematic cross-sectional view of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present invention is shown.

[0012] Figure 19 A schematic cross-sectional view of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present invention is shown.

[0013] Figure 20 A schematic cross-sectional view of a semiconductor package according to some embodiments of the present invention is shown.

[0014] Figure 21 A schematic cross-sectional view of a semiconductor package according to some embodiments of the present invention is shown.

[0015] Figure 22 A schematic cross-sectional view of a semiconductor package according to some embodiments of the present invention is shown.

[0016] Figure 23 Schematic cross-sectional views and partial enlarged views of semiconductor packages according to some embodiments of the present invention are shown.

[0017] Figure 24 Schematic cross-sectional views and partial enlarged views of semiconductor packages according to some embodiments of the present invention are shown.

[0018] Figures 25 to 26 A cross-sectional view is shown of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present invention.

[0019] Figures 27 to 28 A cross-sectional view is shown of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present invention.

[0020] Figures 29 to 32 A cross-sectional view is shown of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present invention.

[0021] Figure 33 A partial top view of a die of a semiconductor package according to some embodiments of the present invention is shown.

[0022] Figure 34 A schematic top view and a partial enlarged view of a die for a semiconductor package according to some embodiments of the present invention are shown.

[0023] Figure 35 A schematic top view and a partial enlarged view of a die for a semiconductor package according to some embodiments of the present invention are shown.

[0024] Figures 36 to 37 A cross-sectional view is shown of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present invention. Detailed Implementation

[0025] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the individual embodiments and / or configurations discussed.

[0026] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0027] Semiconductor packages and methods of manufacturing semiconductor packages are provided according to various exemplary embodiments. In some embodiments, the semiconductor package may be a system-on-a-chip (SoIC) package, and intermediate stages of forming a SoIC package are shown according to some embodiments. Some variations of some embodiments are discussed. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. It should be understood that although the formation of a SoIC package is used as an example to explain the concept of embodiments of the invention, embodiments of the invention can be readily applied to package structures and packaging methods in which alignment marks and through-holes (substrate vias) are formed on one of the dies.

[0028] Figures 1 to 10 A cross-sectional view is shown of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present invention. According to some embodiments of the present invention, a method for manufacturing a semiconductor package may include the following steps. First, refer to... Figure 1A first die 110 is provided, and a second die 120 is bonded over the first die 110. In some embodiments, for example, the first die 110 and the second die 120 may be application-specific integrated circuit (ASIC) chips, system-on-a-chip (SoC) chips, analog chips, sensor chips, wireless and radio frequency chips, voltage regulator chips, logic dies (such as central processing unit (CPU) dies, microcontroller unit (MCU) dies, baseband (BB) dies, application processor (AP) dies), or memory chips (such as dynamic random access memory (DRAM) dies or static random access memory (SRAM) dies), or other types of dies. The first die 110 and the second die 120 may be the same type of die or different types of dies; the type of die is not limited in this invention. Various suitable bonding techniques can be applied to the bonding of the first die 110 and the second die 120. For example, the second die 120 may be bonded to the first die 110 by hybrid bonding, fusion bonding, or a combination thereof. Although a die 110 and a die 120 are shown in the figure, the present invention does not limit the number of dies 110 and 120.

[0029] In some embodiments, the first die 110 may be a chip included in a semiconductor wafer at this stage. Although one die 110 is shown, it should be understood that a semiconductor wafer includes a plurality of dies 110, and each die 110 is located within a die region of the wafer and spaced apart from each other by scribe lines. Dividing of the dies 110 may be performed in a subsequent process. The second die 120 may be a die that has been diced from another semiconductor wafer and mounted on top of the first die 110 by a pick-and-place process. In some embodiments, the first die 110 and the second die 120 may have similar structures, and the detailed structure of the dies will be described below.

[0030] In some embodiments, the first die 110 includes a semiconductor substrate 111, at least one integrated circuit device 1131, an interconnect structure 113, and a plurality of conductive pads 112. The integrated circuit device 1131 may include transistors and / or diodes, passive devices (e.g., capacitors, inductors, resistors, etc.). For simplicity, the integrated circuit device 1131 is omitted in the following figures. According to some embodiments of the present invention, the first die 110 is a logic die, which may be a central processing unit (CPU) die, a microcontroller unit (MCU) die, an input / output (IO) die, a baseband (BB) die, an application processor (AP) die, etc. In some embodiments, the first die 110 may also be a memory die such as a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc. According to some embodiments of the present invention, the first die 110 may be an interposer wafer without active devices such as transistors and / or diodes. In some embodiments, the first die 110 may be without passive components such as capacitors, inductors, resistors, etc., or may include passive components.

[0031] According to some embodiments of the present invention, the semiconductor substrate 111 may be formed of crystalline silicon, crystalline germanium, crystalline silicon-germanium, and / or III-V compound semiconductors such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc. In some embodiments, the semiconductor substrate 111 may also include other components, such as various doped regions, buried layers, and / or epitaxial layers. The semiconductor substrate 111 may also be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or silicon-on-sapphire, etc. Shallow trench isolation (STI) regions (not shown) may be formed in the semiconductor substrate 111 to isolate active regions in the semiconductor substrate 111. Although not shown, a plurality of through-holes may be formed to extend into the semiconductor substrate 111, and the through-holes may be used to electrically couple conductive components (e.g., conductive pads 112) on opposite sides of the first die 110 to each other.

[0032] According to some embodiments of the present invention, the first die 110 includes at least one integrated circuit device 1131 formed on the upper surface of the semiconductor substrate 111. The integrated circuit device 1131 may include a complementary metal-oxide-semiconductor (CMOS) transistor, a resistor, a capacitor, a diode, a photodiode, a fuse device, or a combination thereof. For brevity, details of the integrated circuit device 1131 are not shown herein. According to some embodiments, the first die 110 is used to form an interposer layer, wherein the semiconductor substrate 111 may be a semiconductor substrate or a dielectric substrate.

[0033] In some embodiments, the first die 110 may further include an interconnect structure 113 (shown as a layer in an abstract form for ease of illustration), the interconnect structure 113 being formed over the semiconductor substrate 111 to electrically connect various integrated circuit devices 1131 to form functional circuitry. The interconnect structure 113 may include metallization structures (e.g., wires and vias) embedded in one or more dielectric layers (such as interlayer dielectric (ILD) and intermetallic dielectric (IMD)). The ILD is formed over the semiconductor substrate 111 and fills the space between the gate stacks of transistors (not shown) in the integrated circuit device 1131. According to some embodiments, the ILD may be formed from phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), etc. In some embodiments, the ILD may be formed using spin coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), etc. In some embodiments, a plurality of contact vias are formed in the ILD and are used to electrically connect the integrated circuit device 1131 to the metal lines and vias thereon.

[0034] The IMD layer is located above the ILD. According to some embodiments of the invention, some IMD layers (e.g., lower IMD layers) are formed of a low-k dielectric material having a dielectric constant (k value) lower than about 3.0 or about 2.5. The IMD layer can be made of... (A registered trademark of Applied Materials, Inc.), carbon-containing low-k dielectric materials, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. According to some embodiments of the invention, some or all of the IMD layers are formed of non-low-k dielectric materials, such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon carbonitride oxycarbonate (SiOCN), etc.

[0035] In some embodiments, the metallization structure includes a plurality of conductive components interconnected with each other and embedded in one or more dielectric layers. The conductive components may include multiple layers of wires, conductive vias, and conductive contacts. Conductive contacts may be formed in an ILD to electrically connect wires to the integrated circuit device 1131, and conductive vias may be formed in an IMD to electrically connect wires in different layers. The conductive components of the metallization structure may include metals, metal alloys, or combinations thereof. For example, conductive components may include tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, or combinations thereof. In some embodiments, the topmost conductive component of the metallization structure has a top surface that is substantially coplanar with the top surface of the dielectric structure (e.g., within process variations), but the invention is not limited thereto.

[0036] In some embodiments, conductive pads 112 are formed in the surface dielectric layer of interconnect structure 113. According to some embodiments of the invention, conductive pads 112 are formed using a single damascene process and may further include barrier layers and copper-containing material formed over each barrier layer. According to an alternative embodiment of the invention, conductive pads 112 are formed using a dual damascene process. The top dielectric layer and conductive pads 112 are planarized such that their top surfaces are coplanar within a process variation, possibly due to CMP during the formation of conductive pads 112. Conductive pads 112 are configured to bond to other device dies (e.g., a second die 120).

[0037] Still referencing Figure 1 In some embodiments, the second die 120 includes a structure that may be similar to that of the first die 110. For example, the second die 120 includes a substrate 121, at least one integrated circuit device 1231, an interconnect structure 123 (shown as a layer in abstract form for ease of illustration), and a plurality of bonding pads 122 bonded to conductive pads 112 of the first die 110. The interconnect structure 123 is formed over the substrate 121 to electrically connect the respective integrated circuit devices 1231 to form functional circuitry. The materials and configurations of the substrate 121, integrated circuit device 1231, interconnect structure 123, and bonding pads 122 of the second die 120 may be substantially similar and formed using similar processes and / or materials as those described above with respect to the first die 110, and will not be repeated here.

[0038] According to some embodiments of the present invention, the second die 120 may include a logic die, such as a central processing unit (CPU) die, a microcontroller unit (MCU) die, an input / output (I / O) die, a baseband (BB) die, an application processor (AP) die, etc. In some embodiments, the second die 120 may also include a memory die, such as a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc. Furthermore, a plurality of second dies 120 may be coupled above the first die 110, and the second dies 120 may be different types of dies selected from the types listed above. Furthermore, one of the second dies 120 may be a digital circuit die, while another may be an analog circuit die. In some embodiments, the first die 110 may be a logic die, and the second die 120 may be a memory die, and dies 110 and 120 are combined as a system. Decomposing the functions and circuitry of the system into different dies (such as dies 110 and 120) can optimize the formation of these dies and can reduce manufacturing costs.

[0039] In some embodiments, the second die 120 further includes a plurality of through-holes 124, which may be formed in the substrate 121 and electrically connected to conductive components and bonding pads 122 in the interconnect structure 123. In embodiments, the through-holes 124 (sometimes referred to as semiconductor vias or substrate vias) are formed to penetrate the semiconductor substrate 121. The through-holes 124 are used to connect the integrated circuit device 1231 and a metal line (shown as the bottom side) formed on the front side of the substrate 121 to the back side. In some embodiments, the through-holes 124 may extend into the interconnect structure 123 to make physical and electrical contact with conductive components of the interconnect structure 123. In some embodiments, the through-holes 124 may include a pad (not shown) for covering their surface. The pad is disposed between the through-holes 124 and the substrate 121 to separate the through-holes 124 from the substrate 121. The pad may surround the sidewalls and / or top surface of the through-holes 124. The through-hole 124 may include copper, copper alloy, aluminum, aluminum alloy, Ta, TaN, Ti, TiN, CoW, or combinations thereof. The pad may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0040] In some embodiments, the second die 120 is bonded to the first die 110 via a hybrid bonding process, and the hybrid bonding involves at least two types of bonding, including, for example, metal-to-metal bonding and non-metal-to-non-metal bonding (such as dielectric-to-dielectric bonding). In other words, the bonding pads 122 of the second die 120 are in direct contact with the conductive pads 112 of the first die 110. In some embodiments, the bonding pads 122 of the second die 120 are bonded to the conductive pads 112 of the first die 110 via metal-to-metal bonding, and the dielectric layer of the second die 120 is bonded to the dielectric layer of the first die 110 via dielectric-to-dielectric bonding. According to some embodiments of the invention, metal-to-metal bonding may include copper-to-copper direct bonding. Furthermore, dielectric-to-dielectric bonding may include fusion bonding. In some embodiments, the bonding process may include the following steps. First, to avoid the appearance of unbonded areas (i.e., interface bubbles), the surfaces of the second die 120 and the first die 110 to be bonded may be treated to be sufficiently clean and smooth bonding surfaces. The second die 120 can then be picked up and placed on the first die 110. In some embodiments, the first die 110 and the second die 120 are aligned with slight pressure at room temperature and placed in physical contact to initiate the bonding operation. Subsequently, a heat treatment (such as an annealing process) is performed to allow the metals in the conductive pads 112 of the first die 110 to interdiffuse with the corresponding bonding pads 122 on the second die 120, and to convert chemical bonds into covalent bonds. The size of the bonding pads 122 may be greater than, equal to, or smaller than the size of the corresponding conductive pads 112.

[0041] Through hybrid bonding, the bonding pad 122 is bonded to the corresponding conductive pad 112 via direct metal bonding caused by interdiffusion of metals. The dielectric layer of the second die 120 is also bonded to the dielectric layer of the first die 110, forming a bond between them. For example, an atom (such as an oxygen atom) in one of the dielectric layers of the second die 120 forms a chemical bond or covalent bond with an atom (such as a silicon atom) in one of the dielectric layers of the first die 110. The resulting bond between the dielectric layers of the first die 110 and the second die 120 is a dielectric-to-dielectric bond. In other words, a bonding interface exists between the first die 110 and the second die 120. In some embodiments, the bonding interface is a hybrid bonding interface, which includes a metal-to-metal bonding interface between the conductive pad 112 and the bonding pad 122, and a dielectric-to-dielectric bonding interface between the dielectric layers of the first die 110 and the second die 120.

[0042] In some embodiments, the second die 120 is bonded to the first die 110 in a face-to-face configuration. That is, the front (active) surface of the second die 120 faces the front of the first die 110. However, the invention is not limited thereto. In some embodiments, the second die 120 may be bonded to the first die 110 in a face-to-back configuration. In other words, the front of the second die 120 may face the back of the first die 110. Throughout this specification, the “front” of the die refers to the surface having a device (e.g., integrated circuit device 1131 / 1231) or close to a conductive pad (e.g., conductive pad 112 / 122), and may also be referred to as the active surface. The “back” of the die is the surface opposite the front, and may be the surface of the substrate, and may also be referred to as the rear surface.

[0043] Although two device dies 110 and 120 are shown, hybrid bonding can be performed at the wafer level and pre-bonded with multiple device die groups that are the same as or similar to the illustrated die group (including device dies 110 and 120), and arranged in rows and columns. In some embodiments, hybrid bonding can also be a die-to-wafer bonding process. The invention is not limited thereto.

[0044] refer to Figure 2 In some embodiments, after the second die 120 is bonded to the first die 110, a back-side grinding process can be performed to thin the second die 120 and expose the through-hole 124. For example... Figure 2As shown, in some embodiments, the through-hole 124 may extend through the substrate 121 and expose from the top surface (e.g., the back surface) of the second die 120, the top surface of the through-hole 124 being substantially coplanar with the top surface (e.g., the back surface) of the substrate 121 within process variations. In some embodiments, the through-hole 124 may not be exposed, and back-side grinding may be stopped when a thin layer of substrate 121 covering the through-hole 124 is present. In some embodiments, the back-side grinding process may be skipped. In some embodiments, the through-hole 124 may be... Figure 2 or Figure 3 The steps shown are exposed.

[0045] Still referencing Figure 2 A sealing material 130 is provided above the first die 110 to cover the sidewalls and top surface of the second die 120. In some embodiments, the sealing material 130 may be a molding compound, a molded underfill, an epoxy resin, a resin, or a combination thereof. In such embodiments, the sealing material 130 may be formed by molding processes, molded underfill (MUF) processes, etc. In some embodiments, the sealing material 130 may include silicon oxide or TEOS, but other dielectric materials such as silicon carbide, silicon oxynitride, silicon carbonitride, PSG, BSG, BPSG, etc. may also be used. In such embodiments, the sealing material 130 may be formed using CVD, high-density plasma chemical vapor deposition (HDPCVD), flowable CVD, spin coating, etc.

[0046] In some embodiments, the top surface of the sealing material 130 may initially be higher than the back surface of the second die 120, meaning that the sealing material 130 covers the back surface of the second die 120. A planarization process is then performed to remove a portion of the sealing material 130 above the top of the second die 120, such that the sealing material 130 laterally seals the second die 120. The planarization process may include a chemical mechanical polishing (CMP) process. Figure 1 In some embodiments where the through-hole 124 is not exposed during the planarization process, a portion of the substrate 121 above the top of the through-hole 124 may also be removed to expose the through-hole 124.

[0047] In some embodiments, multiple planarization processes may be performed. For example, in some embodiments, multiple planarization processes may be performed on... Figure 1 The structure shown performs a first planarization process to initially thin the second die 120. After this first planarization process, the through-hole 124 can remain covered by the substrate 121. After this first planarization, a sealing material 130 can be formed, and then a second planarization process can be performed to remove excess sealing material 130 and further thin the substrate 121 to expose the through-hole 124.

[0048] After forming the sealing material 130 and performing one or more planarization processes, the sealing material 130 covers a portion of the top surface of the first die 110 and the sidewalls of the second die 120. In some embodiments, within process variations, the top surface of the sealing material 130 is substantially coplanar with the top surface of the second die 120. In embodiments, within process variations, the top surface of the sealing material 130 is substantially coplanar with the top surface (e.g., the back surface) of the substrate 121 and the top surface of the through-hole 124 of the second die 120. In some embodiments, the sealing material 130 may also be referred to as a gap-filling dielectric layer or an insulating structure or dielectric structure.

[0049] refer to Figure 3 In some embodiments, a back-side portion of the substrate 121 of the second die 120 is removed, such that the through-hole 124 protrudes from the back side of the substrate 121, forming a recess RC across the substrate 121. In some embodiments, the sealing material 130 and the through-hole 124 define the sidewalls of the recess RC. In some embodiments, the removal of the back-side portion of the substrate 121 is achieved by further thinning the substrate 121. For example, the back-side portion of the substrate 121 located laterally adjacent to the through-hole 124 can be removed by an etching process (such as a wet etching process, a dry etching process, or a combination thereof). The etching process can have a high etch selectivity between the substrate 121 and other adjacent materials (e.g., the sealing material 130, the through-hole 124, etc.). In some embodiments, the sealing material 130 may be substantially not removed by the etching process, but the invention is not limited thereto. In some embodiments, a portion of the sealing material 130 may also be removed by an etching process. After performing the thinning (e.g., by etching) process, the top surface of the substrate 121 is lower than the top surface of the through-hole 124 and the top surface of the sealing material 130. In other words, the through-hole 124 has a portion that protrudes from the top surface of the substrate 121. In some embodiments, the groove RC may have a depth ranging from about 0.5 μm to about 2 μm.

[0050] Now for reference Figure 4An isolation layer 125 is provided over the substrate 121 and the sealing material 130 of the second die 120 to cover the top surface of the substrate 121. In some embodiments, the isolation layer 125 may also cover the top surface of the through-hole 124 and the top surface of the sealing material 130. In some embodiments, the isolation layer 125 is a conformal layer, i.e., the isolation layer 125 has a substantially equal thickness extending along the region on which the isolation layer 125 is formed. The isolation layer 125 may include dielectric materials such as silicon nitride (SiN), HDP OX (SiO2), TEOS OX (SiO2), silicon oxide, silicon carbide (SiC), silicon oxycarbide (SiOC), silicon oxynitride (SiON), oxygen-doped silicon carbide, nitrogen-doped silicon carbide, polymers (which may be photosensitive materials such as PBO, polyimide, or BCB), and low-k dielectric materials (such as PSG, BPSG, FSG, SiO2). x C y SOG, spin-coated polymers, silicon carbide materials, their compounds, their composites, their combinations, etc., can also be used for the isolation layer 125. The isolation layer 125 can be formed using a suitable deposition process, such as CVD, atomic layer deposition (ALD), etc. In some embodiments, the isolation layer 125 is formed to have a thickness at least equal to the height of the groove RC (i.e., the thickness of the portion of the through-hole 124 protruding from the substrate 121). In other words, the isolation layer 125 completely fills the groove RC.

[0051] Then, a planarization process is performed to remove a portion of the isolation layer 125 above the top of the through-hole 124 to expose the through-hole 124 and form the isolation layer 125. Thus, the through-hole 124 extends through the isolation layer 125. The planarization process may include a CMP process. Therefore, the isolation layer 125 is located on the substrate 121 and laterally seals a portion of the through-hole 124 protruding from the substrate 121. In some embodiments, the isolation layer 125 is laterally located between the through-hole 124 and the sealing material 130. Within process variations, the top surface of the isolation layer 125 may be substantially coplanar with the top surface of the through-hole 124 and the top surface of the sealing material 130. In some embodiments, this may be omitted. Figures 3 to 4 The isolation layer 125 is shown to be formed. In some embodiments, the isolation layer may be formed prior to the formation of the sealing material 130, and the isolation layer may be formed to extend along the top surface and sidewalls of the second die 120 and the top surface of the first die 110. In some embodiments, the isolation layer may further extend to cover the top surface of the sealing material 130. In some embodiments, the isolation layer 125 may have a thickness ranging from about 0.5 μm to about 2 μm.

[0052] Now for reference Figure 5 and Figure 6A plurality of alignment marks 126 are formed on the second die 120. In some embodiments, the formation of the alignment marks 126 may include the following steps. First, a mask layer PR is provided over the top surface of the second die 120 (e.g., the isolation layer 125). The mask layer PR may include a photosensitive material, which includes organic materials and may be a positive or negative photosensitive material. The mask layer PR is placed over the isolation layer 125 using, for example, a spin coating technique. Once in place, the mask layer PR may be exposed to a patterned energy source (e.g., a patterned light source) to induce a chemical reaction in those portions of the mask layer PR exposed to the patterned light source. A developer is then applied to the exposed mask layer PR to selectively remove the exposed or unexposed portions of the mask layer PR by utilizing physical changes and depending on the desired pattern, and to form the desired pattern for the alignment marks 126 (e.g., openings on the mask layer PR). Other masking materials may be used instead of or in addition to the photosensitive material.

[0053] Once the mask layer PR has been patterned, an etching process is used to transfer the pattern of the mask layer PR to the isolation layer 125 (which may be the substrate 121 of the second die 120). That is, an etching process is performed to form a plurality of openings OP on the isolation layer 125. The etching process is anisotropic, such that the openings in the mask layer PR extend through the isolation layer 125 and have approximately the same size (or slightly smaller) in the isolation layer 125 as if they were located in the mask layer PR.

[0054] Alignment marks 126 are then formed within the opening OP. In one embodiment, alignment marks 126 are formed by filling the opening OP with a material different from the surrounding material. In some embodiments, the alignment marks comprise a conductive material that can be easily distinguished from the surrounding material. For example, alignment marks 126 may comprise one or more conductive materials, such as copper, tungsten, other conductive metals, etc., and may be formed, for example, by electroplating, electroless plating, etc. The conductive material of alignment marks 126 may be the same as the conductive material of through-hole 124. In some embodiments, the conductive material of alignment marks 126 may be different from the conductive material of through-hole 124 because they are formed by different processes in separate steps. In other embodiments, alignment marks 126 are formed by filling the opening OP with a dielectric material, which will be described below. The mask layer PR can then be removed using a suitable removal process, such as an ashing process. In an embodiment, a plasma ashing process can be used to remove the mask layer PR, thereby increasing the temperature of the mask layer PR until the mask layer PR undergoes thermal decomposition and can be removed. However, any other suitable process, such as wet stripping, may be optionally utilized. In some embodiments, a planarization process may be performed on the top surfaces of the isolation layer 125, the through-hole 124, and the alignment mark 126. The planarization process may include a polishing process. Figure 6 The resulting structure is shown in the figure. Due to the planarization process, the top surface of the through-hole 124 is substantially flush with the top surface of the alignment mark 126 and also substantially flush with the top surface of the isolation layer 125. In some embodiments, the thickness of the alignment mark 126 can range from about 0.3 μm to about 3 μm.

[0055] Figure 11 A schematic diagram of alignment marks for a semiconductor package according to some embodiments of the present invention is shown. Referring now to... Figure 6 and Figure 11 According to some embodiments of the present invention, since the alignment marks 126 and the through holes 124 are formed by different processes in separate steps, the pitch P2 between two adjacent alignment marks 126 may be different from the pitch P1 between two adjacent through holes 124. In some embodiments, the dimensions (e.g., diameter, depth) of the alignment marks 126 may also be different from the dimensions of the through holes 124. In some embodiments, the pitch P2 of the alignment marks 126 is substantially smaller than the pitch P1 of the through holes 124. In some embodiments, the alignment marks 126 may have different sets of pitches P21, P22, P23, P24, such as... Figure 11As shown. In some embodiments, alignment marks 126 may consist of multiple subsets of alignment marks 1261, 1262, 1263, and 1264, and the respective pitches P21, P22, P23, and P24 of the subsets of alignment marks 1261, 1262, 1263, and 1264 are different from each other. For example, the pitch P21 and diameter of alignment mark 1261 may be in the range of about 7 μm to about 9 μm (e.g., 8 μm), the pitch P22 and diameter of alignment mark 1262 may be in the range of about 1 μm to about 2 μm (e.g., 1.6 μm), the pitch P23 and diameter of alignment mark 1263 may be in the range of about 0.5 μm to about 0.8 μm (e.g., 1.15 μm), and the pitch P24 and diameter of alignment mark 1264 may be in the range of about 8 μm to about 10 μm (e.g., 8.8 μm). In some embodiments, the pitch P1 of the through-hole 124 can be from about 2 μm to about 6 μm, and the diameter of each through-hole 124 can be about 2 μm. However, the dimensions and quantities listed above are for illustrative purposes only, and the invention is not limited thereto. Therefore, the design flexibility of the alignment marks 126 is increased, and the alignment marks 126 can meet fine pitch requirements (at least less than or about 2 μm) for better resolution. In some embodiments, the pitch P2 between two adjacent alignment marks 126 can be 0.4 μm or less. In some embodiments, the total length L1 of the alignment marks 126 (including the lengths of alignment marks 1261, 1262, 1263, 1264) is from about 800 μm to 830 μm (e.g., 822 μm), and the width W1 of the alignment marks 126 is from about 50 μm to about 70 μm (e.g., 60 μm), but the invention is not limited thereto.

[0056] According to some embodiments of the invention, alignment mark 126 allows identification of the correct die orientation. In some embodiments, alignment mark 126 is a pseudo-structure in the sense that it is not electrically coupled to bonding pad 122 or via 124. In some embodiments, alignment mark 126 may be electrically coupled to bonding pad 122 and subsequently formed redistribution structure 140 via via 124. In some embodiments, alignment mark 126 may be grounded. Alignment mark 126 may include optical alignment marks, scanning electron microscope (SEM) marks, and other alignment marks. Alignment mark 126 may provide components for alignment during photolithography, testing, inspection, or measurement.

[0057] refer to Figure 7 and Figure 8 A redistribution structure 140 (see above) is formed over the second core 120 (e.g., insulating layer 125) and the sealing material 130. Figure 8Thus, the isolation layer 125 is disposed between the substrate 121 of the second die 120 and the redistribution structure 140, and the alignment mark 126 extends from the upper surface of the isolation layer 125 facing the redistribution structure 140 and toward the substrate 121 of the second die 120. Figure 7 The formation of the first layer 142 of the redistribution structure 140 is illustrated. In detail, for example, one or more dielectric layers (collectively referred to as dielectric layers 1423 for illustrative purposes) may be formed over the second die 120 and the sealing material 130 to cover the top surfaces of the second die 120 (e.g., the insulating layer 125) and the sealing material 130. Dielectric layers 1423 may include oxides such as silicon oxide, nitrides such as silicon nitride, USG, or combinations thereof. Dielectric layers 1423 may be formed by a suitable deposition process (such as CVD). A plurality of dielectric vias 1421 and redistribution layers 1422 are then formed, for example, by a single / dual damascene process. In some embodiments, during the formation of the redistribution structure 140, alignment marks 126 may be used to identify and align the relative positioning between the die 120 and the components of the redistribution structure 140 (e.g., dielectric vias and redistribution layers). In some embodiments, viewed from a top view, the alignment mark 126 does not overlap with the conductive layer (e.g., dielectric via and redistribution layer) of the redistribution structure 140, so the alignment mark 126 is not blocked during the alignment process.

[0058] In some embodiments, a patterning process is performed to form a plurality of vias and a plurality of trenches in the dielectric layer 1423. The patterning process removes a portion of the dielectric layer 1423 to expose the top surface of the through-hole 124 of the second die 120. The patterning process may include multiple photolithography and / or etching processes. The sidewalls of the vias and trenches may be straight or angled. The vias and trenches are then filled with a conductive material to form Figure 7 The dielectric via 1421 and redistribution layer 1422 are shown. The conductive material includes a suitable metallic material, such as copper or a copper alloy. In some embodiments, the method of forming the conductive material may include a plating process (such as electroplating or electrochemical plating) or a suitable deposition process (such as CVD, PVD, etc.). Thereafter, a planarization process, such as CMP, may be performed to remove excess portions of the conductive material until the dielectric layer 1423 is exposed. In some embodiments, after performing the planarization process, within a process variation, the top surfaces of the dielectric via 1421 and the redistribution layer 1422 are substantially coplanar with the top surface of the dielectric layer 1423.

[0059] refer to Figure 8In some embodiments, a passivation layer 1443 is formed over the dielectric layer 1423, and a via 1441 is formed in the passivation layer 1443 to electrically connect to the redistribution layer 1422. Then, a redistribution layer (or conductive pad) 1442 is formed over the passivation layer 1443 and the via 1441, and is electrically coupled to the redistribution layer 1422 through the via 1441. The materials of the redistribution layer (or conductive pad) 1442 and the via 1441 may each include suitable metallic materials, such as aluminum, copper, alloys thereof, or combinations thereof. In some embodiments, the conductive pad 1442 may be an aluminum pad or an aluminum-copper pad, and other metallic materials may be used. The via 1441 and the conductive pad 1442 may be formed separately with an interface between them, or formed simultaneously without an interface between them.

[0060] In some embodiments, passivation layer 1445 may be formed over passivation layer 1443 to at least laterally seal conductive pad 1442. Passivation layers 1443 and 1445 may be monolayers or composite layers, and may be formed of non-porous materials. In some embodiments, each of passivation layers 1443 and 1445 may include silicon oxide, silicon nitride, or a combination thereof. In some embodiments, one or both of passivation layers 1443 and 1445 are composite layers comprising a silicon oxide layer (not shown separately) and a silicon nitride layer (not shown separately) situated above the silicon oxide layer. Passivation layers 1443 and 1445 may also be formed of other non-porous dielectric materials, such as undoped silicate glass (USG), silicon oxynitride, or a combination thereof. A planarization process, such as a CMP process, may then be performed to remove excess portions of passivation layer 1445 until conductive pad 1442 is exposed. In some embodiments, after performing a planarization process, the top surface of the conductive pad 1442 is substantially coplanar with the top surface of the passivation layer 1445.

[0061] At this point, the resulting package structure can be in wafer form, and then can be mounted (e.g., frame mounting) onto a dicing tape. Afterward, the package structure can be diced or cut (e.g., along a dicing line) to form a plurality of semiconductor packages 100, each of which can be coupled with… Figure 8 The semiconductor package 100 shown is substantially the same as or similar to the semiconductor package shown.

[0062] refer to Figure 9 and Figure 10 According to some embodiments of the present invention, the semiconductor package 100 described above can be applied to an integrated fan-out (InFO) packaging process to form such a Figure 10 The stacked packaging structure 10 is shown. In detail, in some embodiments, reference is now made to... Figure 8 and Figure 9 It can Figure 8The semiconductor package 100 shown is provided on a carrier C1 such that the back side of the semiconductor substrate 111 of the first die 110 is attached to the carrier C1. In some embodiments, the carrier C1 may be a glass carrier, a ceramic carrier, or the like. An adhesive layer AD, such as a photothermal conversion release coating (LTHC), may be disposed on the carrier C1. In some embodiments, a dielectric layer 400 may optionally be disposed above the carrier C1 (e.g., on the adhesive layer AD).

[0063] During the placement of the semiconductor package 100, alignment marks 126 are used to align the position of the semiconductor package 100 (e.g., the second die 120 of the semiconductor package 100) to ensure that the semiconductor package 100 is placed in the desired position and that the semiconductor package 100 does not shift or rotate from its intended position and orientation. Alignment is performed by determining the relative alignment of the position of the semiconductor package 100 with respect to the alignment marks 126.

[0064] In some embodiments, the interlayer via 500 may be pre-formed and then placed on the carrier C1. In some embodiments, the interlayer via 500 may be formed by, for example, a plating process. The plating of the interlayer via 500 may be performed before the semiconductor package 100 is placed, and may include forming a seed layer (not shown) over the carrier C1, forming and patterning a photoresist layer (not shown), and plating the interlayer via 500 on the portion of the seed layer exposed by the photoresist layer. The photoresist layer and the portion of the seed layer covered by the photoresist layer may then be removed. The semiconductor package 100 may then be placed over the carrier C1. The material of the interlayer via 500 may include copper, aluminum, etc. Thus, the bottom end of the interlayer via 500 is substantially flush with the back side of the semiconductor package 100. In some embodiments, the interlayer via 500 may be provided after the semiconductor package 100 is placed.

[0065] Then, the semiconductor package 100 and the interlayer via 500 on the carrier C1 are sealed with sealing material 200. In other words, sealing material 200 is provided over the carrier C1 to at least laterally seal the semiconductor package 100 (e.g., Figure 8 The diagram shows a first die 110, a sealing material 130, and a redistribution structure 140, and an interlayer via 500. In some embodiments, the sealing material 200 fills the gap between the semiconductor package 100 and the interlayer via 500. Therefore, the interlayer via 500 extends through the sealing material 200. The sealing material 200 may include molding compounds, epoxy resins, or resins, etc. In some embodiments, the top surface of the sealing material 200 may initially be higher than the top of the interlayer via 500 and the top surface of the semiconductor package 100 (e.g., ...). Figure 8(The top surface of the redistribution layer 140 shown). That is, the sealing material 200 covers the top of the interlayer via 500 and the top surface of the semiconductor package 100. Then, a thinning process (which may be a polishing process) is performed to thin the sealing material 200 until the top of the interlayer via 500 and the top surface of the conductive pads 1442 of the semiconductor package 100 are exposed. Due to the thinning process, the top of the interlayer via 500 is substantially flush with the top surface of the sealing material 200.

[0066] Then, in the semiconductor package 100 (e.g., Figure 8 A redistribution structure 300 is formed over the sealing material 130 and redistribution structure 140 shown, and over the sealing material 200. The redistribution structure 300 is electrically connected to the semiconductor package 100 and the interlayer via 500. In some embodiments, conductive components of the redistribution structure 300 are electrically connected to the conductive pads 1442 of the semiconductor package 100 and the interlayer via 500. In some embodiments, the redistribution structure 300 may also interconnect the conductive pads 1442 and the interlayer via 500.

[0067] The redistribution structure 300 can be formed, for example, by first depositing a dielectric layer (not shown separately) on the sealing material 130, the interlayer via 500, and the semiconductor package 100. In some embodiments, the dielectric layer is formed of a photosensitive material such as PBO, polyimide, BCB, etc., and the photosensitive material can be patterned using a photomask. The dielectric layer can be formed by spin coating, lamination, CVD, etc., or combinations thereof. The dielectric layer is then patterned to form openings that expose portions of the interlayer via 500 and / or the conductive pads 1442 of the semiconductor package 100. Patterning can be performed by acceptable processes, such as by exposing the dielectric layer to light and developing when the dielectric layer is a photosensitive material, or by etching, for example, anisotropic etching.

[0068] A metallization pattern is then formed over the dielectric layer. The metallization pattern includes conductive elements that extend along the main surface of the dielectric layer and through the dielectric layer to be physically and electrically coupled to the interlayer via 500 and / or the conductive pads 1442 of the semiconductor package 100. As an example of forming the metallization pattern 126, a seed layer is formed over the dielectric layer and in the openings extending through the dielectric layer. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, PVD. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the desired metallization pattern. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating. The conductive material may include metals such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the underlying seed layer forms a metallized pattern. The photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as wet etching or dry etching. This process can be repeated once or multiple times to form the redistributed structure 300. In some embodiments, a single / dual damascene process may be used.

[0069] Still referencing Figure 9 In some embodiments, according to some exemplary embodiments, a plurality of electrical connections 310 are disposed on the redistribution structure 300. In some embodiments, the plurality of electrical connections 310 may include an under-bump metallization (UBM) layer formed on the redistribution structure 300 by sputtering, evaporation, or chemical plating. The formation of the electrical connections 310 may include placing solder balls on the redistribution structure 300 (or on the UBM layer) and then reflowing the solder balls. In alternative embodiments, the formation of the electrical connections 310 may include performing a plating process to form solder regions on the redistribution structure 300 and then reflowing the solder regions. The electrical connections 310 may also include conductive pillars, or conductive pillars with solder caps, which may also be formed by plating. In some embodiments, at least one integrated passive device (IPD) may also be disposed on the redistribution structure 300. The IPD may be manufactured using standard wafer fabrication techniques such as thin-film and photolithography processes and may be mounted on the redistribution structure 300 by, for example, flip-chip bonding or wire bonding.

[0070] Now for reference Figure 9 and Figure 10The carrier C1 can be removed. In some embodiments, the carrier C1 is detached from the structure above (hereinafter, the package structure PK) by causing the adhesive layer AD to lose or reduce its adhesiveness. The adhesive layer AD is then removed together with the carrier C1. For example, the adhesive layer AD can be exposed to ultraviolet light, causing the adhesive layer AD to lose or reduce its adhesiveness, thus allowing the carrier C1 and the adhesive layer AD to be removed from the package structure PK. After removing the carrier C1, the bottom end of the interlayer via 500 is exposed. In the structure shown, the bottom end of the interlayer via 500 is flush with the bottom surface of the semiconductor package 100 and the bottom surface of the sealing material 200. In embodiments where the dielectric layer 400 is omitted, a polishing process may optionally be performed to lightly polish the back side of the semiconductor package 100 (e.g., the back side of the first die 110) and the bottom end of the interlayer via 500.

[0071] In embodiments having a dielectric layer 400, a patterning process can then be performed on the dielectric layer 400 to form a plurality of openings. The openings are located on the interlayer vias 500 to expose the bottom end of the interlayer vias 500. In some embodiments, the openings can be formed by photolithography, laser drilling, or the like.

[0072] Still referencing Figure 10 Multiple electrical terminals 610 can be formed above the package structure PK to electrically connect to the interlayer via 500. In some embodiments, the electrical terminals 610 are disposed in openings in the dielectric layer 400 to connect to the interlayer via 500. Then, another package structure 600 is disposed on the package structure PK and electrically connected to the interlayer via 500 via the electrical terminals 610. The package structure 600 is mounted on the package structure PK. Therefore, the resulting structure is as follows. Figure 10 The stacked package structure 600 is shown. In some embodiments, the package structure 600 may be a package, a device die, a passive device, etc. In some embodiments, the stacked package structure 600 may combine vertically discrete memory and logic packages, but the invention is not limited thereto. In some embodiments, the bonding between the package structure PK and the package structure 600 may be performed using flip-chip bonding via electrical terminals 610, which may include, for example, solder. In some embodiments, underfill 620 may be formed between the package structure PK and the package structure 600 to seal the electrical terminals 610.

[0073] It should be understood that the device dies in the package structure 600 may be arranged differently from those shown in the exemplary embodiment. In some embodiments, the device dies are sealed with a sealing material. The wafer-level package can then be sawn into a plurality of stacked package structures 10 that are independent of each other, wherein each stacked package structure 10 includes a package structure 600 that is coupled to a package structure PK.

[0074] Figures 12 to 16A schematic top view of various alignment marks according to some embodiments of the present invention is shown. Because the alignment marks 126 are formed in a separate step by a different process than the through hole 124, the design of the alignment marks 126 can be more flexible. For example, the cross-sectional shape of one of the alignment marks 126 can differ from that of the through hole 124. Figure 8 The cross-sectional shape of one of the shown (e.g., a circle). Figures 12 to 16 Only some possible embodiments of alignment mark 126 are shown, but the invention is not limited thereto.

[0075] First refer to Figure 12 In one embodiment, viewed from a top view, each alignment mark 126a can be rectangular. That is, each alignment mark 126a can be a rectangular strip. For example, the width of one of the alignment marks 126a can be about 4 μm to 6 μm (e.g., 5 μm), while the length of one of the alignment marks 126a can be about 12 μm to 14 μm (e.g., 13.5 μm). In one embodiment, the alignment marks 126a can include two sets of alignment marks 1261a and 1262a, and the length direction of alignment mark 1261a is substantially perpendicular to the length direction of alignment mark 1262a, and as shown... Figure 12 As shown, alignment marks 1261a and 1262a can be arranged alternately. In one embodiment, the total length of alignment marks 126 (including alignment marks 1261a and 1262a) is in the range of about 50 μm to about 70 μm (e.g., 60 μm), and the total width of alignment marks 126 (including alignment marks 1261a and 1262a) is in the range of about 50 μm to about 70 μm (e.g., 60 μm), but the invention is not limited thereto.

[0076] refer to Figure 13 In some embodiments, viewed from a top view, alignment marks 126b may be a ring of rectangles (e.g., squares) arranged concentrically. For example, alignment marks 126b may include a first alignment mark 1261b and a second alignment mark 1262b located within the first alignment mark 1261b, such as... Figure 13 As shown. In some embodiments, the width / length of the first alignment mark 1261b can be in the range of about 4 μm to about 6 μm (e.g., 5 μm), while the width / length of the second alignment mark 1262b can be in the range of about 2 μm to about 3 μm (e.g., 2.5 μm). In one embodiment, the width / length of the alignment mark 126b can be in the range of about 50 μm to about 70 μm (e.g., 60 μm), but the invention is not limited thereto.

[0077] refer to Figure 14In some embodiments, the alignment mark 126c may have different shapes. For example, the alignment mark 126c may include two sets of alignment marks 1261c and 1262c, with each alignment mark 1261c having a circular cross-sectional shape and each alignment mark 1262c having a rectangular cross-sectional shape. Figure 14 As shown, alignment marks 1261c and 1262c can be arranged alternately. In some embodiments, the width of the rectangular alignment mark 1262c can be about 4 μm to 6 μm (e.g., 5 μm), while the length of the rectangular alignment mark 1262c can be about 12 μm to 15 μm (e.g., 13.5 μm). Some circular alignment marks 1261c are arranged along the length direction of the rectangular alignment mark 1262c. In some embodiments, the total length / width of the alignment marks 126c (including alignment marks 1261c and 1262c) can be in the range of about 50 μm to about 70 μm (e.g., 60 μm), but the invention is not limited thereto.

[0078] refer to Figure 15 In some embodiments, the shape of the alignment mark 126d may be different. For example, the alignment mark 126d may include two types of alignment marks 1261d and 1262d, and viewed from a top view, the alignment mark 1262d may be a rectangular (e.g., square) ring defining a closed area, and the alignment mark 1261d is disposed within the closed area. In some embodiments, the alignment mark 1261d may be a plurality of through holes arranged in a cross pattern within the closed area defined by the alignment mark 1262d, such as... Figure 15 As shown. In some embodiments, the total width / length of the alignment mark 126d can be in the range of about 50 μm to about 70 μm (e.g., 60 μm), but the invention is not limited thereto.

[0079] refer to Figure 16 In some embodiments, alignment marks 126e may include two types of alignment marks 1261e and 1262e, and alignment mark 1261e is a plurality of through holes surrounding the area where alignment mark 1262e is disposed. In some embodiments, alignment marks 1261e may surround a rectangular (e.g., square) area, and alignment marks 1262e disposed within the rectangular area are cross-shaped. In some embodiments, the width of the cross-shaped alignment mark 1262e may be about 2 μm to 3 μm (e.g., 2.5 μm), while the length of the cross-shaped alignment mark 1262e may be in the range of about 8 μm to about 12 μm (e.g., 10 μm). In some embodiments, the total width / length of alignment marks 126e is in the range of about 50 μm to about 70 μm (e.g., 60 μm), but the invention is not limited thereto. It should be noted that regarding Figures 12 to 16The dimensions and quantities mentioned in the embodiments are for illustrative purposes only and are not intended to limit the invention.

[0080] Figure 17 A schematic cross-sectional view is shown of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present invention. It should be noted that... Figure 17 The semiconductor package shown includes semiconductor packages similar to those disclosed in the previous embodiments (e.g., Figure 6 The semiconductor package shown contains many components that are the same as or similar to those in the drawings. For clarity and simplicity, detailed descriptions of the same or similar components may be omitted, and the same or similar reference numerals denote the same or similar components.

[0081] refer to Figure 17 According to some embodiments of the invention, the depth d2 of each alignment mark 126 is different from the depth d1 of each through hole 124. In some embodiments, the depth d2 of each alignment mark 126 is substantially smaller than the depth d1 of each through hole 124. In situations such as Figure 6 In the illustrated embodiment, the alignment mark 126 extends through the isolation layer 125. In some embodiments, the alignment mark 126 further extends into the substrate 121 of the second die 120, but does not extend all the way through the substrate 121 of the second die 120, such as... Figure 17 As shown. That is, the depth d2 of each alignment mark 126 is greater than the thickness of the isolation layer 125.

[0082] Figure 18 A schematic cross-sectional view is shown of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present invention. It should be noted that... Figure 18 The semiconductor package shown includes semiconductor packages similar to those disclosed in the previous embodiments (e.g., Figure 6 The semiconductor package shown contains many components that are the same as or similar to those in the original. For clarity and simplicity, detailed descriptions of the same or similar components may be omitted, and the same or similar reference numerals denote the same or similar components.

[0083] refer to Figure 18 According to some embodiments of the invention, the depth of each alignment mark 126 may be approximately the same as the depth of each through-hole 124. In some embodiments, the alignment mark 126 may extend through the isolation layer 125 and the substrate 121 of the second die 120, and may further extend into the interconnect structure 123, but the alignment mark 126 is not electrically connected to an integrated circuit device (e.g., in the interconnect structure 123). Figure 1(The integrated circuit device 1231 shown). That is, the depth of the alignment mark 126 is greater than the sum of the thickness of the isolation layer 125 and the thickness of the substrate 121, and can be substantially equal to the depth of each through hole 124. In some embodiments, the depth of the alignment mark 126 can be approximately the same as the depth of the through hole 124, while the pitch of the alignment mark 126 is different from the pitch of the through hole 124.

[0084] Figure 19 A schematic cross-sectional view is shown of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present invention. It should be noted that... Figure 19 The semiconductor package shown includes semiconductor packages similar to those disclosed in the previous embodiments (e.g., Figure 6 The semiconductor package shown contains many components that are the same as or similar to those in the original. For clarity and simplicity, detailed descriptions of the same or similar components may be omitted, and the same or similar reference numerals denote the same or similar components.

[0085] refer to Figure 19 According to some embodiments of the present invention, the depth of each alignment mark 126 is different from the depth d1 of each through hole 124. In some embodiments, the depth of each alignment mark 126 is less than the depth of each through hole 124. In some embodiments, the alignment mark 126 extends from the upper surface of the isolation layer 125, but does not extend all the way through the isolation layer 125. That is, the depth of the alignment mark 126 is less than the thickness of the isolation layer 125.

[0086] Figure 20 A schematic cross-sectional view of a semiconductor package according to some embodiments of the present invention is shown. It should be noted that... Figure 20 The semiconductor package shown includes many components that are the same as or similar to those disclosed in the previous embodiments. For clarity and simplicity, detailed descriptions of the same or similar components may be omitted, and the same or similar reference numerals denote the same or similar components.

[0087] refer to Figure 20According to some embodiments of the invention, at least one of the conductive layers of the redistribution structure 140 includes an alignment pattern 1424 that overlaps with the alignment mark 126 when viewed from a top view. In some embodiments, the conductive layer including the redistribution layer 1422 may also include the alignment pattern 1424. That is, the alignment pattern 1424 is at the same level (layer) as the redistribution layer 1422 and may be formed in the same step (simultaneously) as the redistribution layer 1422. In some embodiments, the alignment pattern 1424 is aligned with the alignment mark 126 when viewed from a top view, which allows identification of the correct orientation of the redistribution structure 140. In some embodiments, the alignment pattern 1424 is electrically insulated from the redistribution layer 1422. In some embodiments, the alignment pattern 1424 may have the same pattern as the alignment mark 126. In some embodiments, the alignment pattern 1424 may have a different pattern than the alignment mark 126.

[0088] Figure 21 A schematic cross-sectional view of a semiconductor package according to some embodiments of the present invention is shown. It should be noted that... Figure 21 The semiconductor package shown includes many components that are the same as or similar to those disclosed in the previous embodiments. For clarity and simplicity, detailed descriptions of the same or similar components may be omitted, and the same or similar reference numerals denote the same or similar components.

[0089] refer to Figure 21 According to some embodiments of the invention, at least one of the conductive layers of the redistribution structure 140 includes an alignment pattern that overlaps with the alignment mark 126 when viewed from a top view. In some embodiments, in addition to the alignment pattern 1424 described above, the conductive layer including the redistribution layer (or conductive pad) 1442 may also include an alignment pattern 1444 that overlaps with the alignment mark 126 when viewed from a top view. That is, in such embodiments, the redistribution structure 140 includes an alignment pattern 1424 at the same level (layer) as the redistribution layer 1422, and an alignment pattern 1444 at the same level (layer) as the conductive pad 1442. In some embodiments, the alignment patterns 1424 and 1444 are aligned with the alignment mark 126 respectively when viewed from a top view, which allows identification of the correct orientation of the redistribution structure 140. In some embodiments, the alignment pattern 1424 is electrically insulated from the redistribution layer 1422, while the alignment pattern 1444 is electrically insulated from the conductive pad 1442. In some embodiments, each of the alignment patterns 1424 and 1444 may have the same pattern as the alignment mark 126. In some embodiments, each of the alignment patterns 1424 and 1444 may have a different pattern than the alignment mark 126.

[0090] Figure 22 A schematic cross-sectional view of a semiconductor package according to some embodiments of the present invention is shown. It should be noted that... Figure 22 The semiconductor package shown includes many components that are the same as or similar to those disclosed in the previous embodiments. For clarity and simplicity, detailed descriptions of the same or similar components may be omitted, and the same or similar reference numerals denote the same or similar components.

[0091] refer to Figure 22 According to some embodiments of the invention, at least one of the conductive layers of the redistribution structure 140 includes an alignment pattern that overlaps with the alignment mark 126 when viewed from a top view. In some embodiments, the conductive layer including the redistribution layer (or conductive pad) 1442 may further include an alignment pattern 1444. That is, the alignment pattern 1444 is at the same level (layer) as the conductive pad 1442 and may be formed in the same step (simultaneously) as the conductive pad 1442. In some embodiments, the alignment pattern 1444 is aligned with the alignment mark 126 when viewed from a top view, which allows identification of the correct orientation of the redistribution structure 140. In some embodiments, the conductive layer including the redistribution layer 1422 does not overlap with the alignment mark 126 when viewed from a top view. That is, the conductive layer including the redistribution layer 1422 does not have any alignment pattern aligned with the alignment mark 126. In some embodiments, the alignment pattern 1444 is electrically insulated from the conductive pad 1442. In some embodiments, the alignment pattern 1444 may have the same pattern as the alignment mark 126. In some embodiments, the alignment pattern 1444 may have a different pattern than the alignment mark 126.

[0092] Figure 23 Schematic cross-sectional views and partial enlarged views of semiconductor packages according to some embodiments of the present invention are shown. It should be noted that... Figure 23 The semiconductor package shown includes many components that are the same as or similar to those disclosed in the previous embodiments. For clarity and simplicity, detailed descriptions of the same or similar components may be omitted, and the same or similar reference numerals denote the same or similar components.

[0093] refer to Figure 23 In some embodiments, the material filling the opening OP of the alignment mark 126 may be a composite layer. That is, the alignment mark 126 may include multiple layers filling the opening OP of the alignment mark 126. In some embodiments, the alignment mark 126 may include a barrier layer 1266 (such as a titanium nitride (TiN) layer, covering the sidewalls of the opening OP) and a conductive layer 1265 (such as a copper (Cu) layer, filling the remainder of the opening OP). In some embodiments, the formation of the alignment mark 126 may include the following steps. First, an etching process is performed through a mask layer (e.g., etched through the top surface of the second die 120 (e.g., the isolation layer 125) above the mask layer) Figure 5The mask layer PR shown forms multiple openings OP. Therefore, the pattern of the mask layer PR is transferred to the isolation layer 125 (which may be the substrate 121 of the second die 120) via an etching process. A barrier layer 1266 can then be formed over the isolation layer 125, covering the sidewalls of the openings OP. In some embodiments, the barrier layer 1266 may be formed of a material including TaN, TiN, etc. The barrier layer 1266 may have a thickness ranging from about 500 angstroms to about 750 angstroms. The barrier layer 1266 can be formed using various deposition techniques such as ALD, PVD, CVD, or other suitable techniques. A conductive layer 1265 can then be formed over the barrier layer 1266 to fill the remaining portion of the openings OP. For example, the conductive layer 1265 may include a conductive material such as copper, tungsten, other conductive metals, etc., and can be formed by, for example, electroplating, electroless plating, etc. The conductive layer 1265 may have a thickness ranging from about 1 μm to about 2 μm. The conductive material of alignment mark 126 can be the same as the conductive material of through hole 124. In some embodiments, the conductive material of alignment mark 126 can be different from the conductive material of through hole 124 because they are formed by different processes in separate steps. The mask layer can then be removed using a suitable removal process, such as an ashing process. Thereafter, a planarization process, such as a CMP process, can be performed to remove excess portions of conductive layer 1265 and barrier layer 1266 until the isolation layer 125 is exposed. For illustrative purposes, Figure 23 The use of composite layers is illustrated in the context of alignment marks. In some embodiments, Figure 23 The composite layer shown can be used for other alignment mark configurations, including those referenced above. Figures 17 to 19 Those that were discussed.

[0094] Figure 24 Schematic cross-sectional views and partial enlarged views of semiconductor packages according to some embodiments of the present invention are shown. It should be noted that... Figure 24 The semiconductor package shown includes many components that are the same as or similar to those disclosed in the previous embodiments. For clarity and simplicity, detailed descriptions of the same or similar components may be omitted, and the same or similar reference numerals denote the same or similar components.

[0095] refer to Figure 24 According to some embodiments of the present invention, the material filling the opening OP of the alignment mark 126 may be a dielectric material. In some embodiments, the dielectric material of the redistribution structure 140 fills the opening OP of the alignment mark 126. For example, the dielectric layer 1423 may fill the opening OP to form the alignment mark 126, such as... Figure 24The enlarged view on the left is shown in the figure. The dielectric material of the redistribution structure 140 may include silicon nitride (SiN), HDP OX (SiO2), TEOS OX (SiO2), silicon oxide, silicon carbide (SiC), silicon carbide oxycarbonate (SiOC), silicon oxynitride (SiON), oxygen-doped silicon carbide, nitrogen-doped silicon carbide, USG, etc. It should be noted that the dielectric material filling the opening OP is different from the material of the isolation layer 125. In some embodiments, the formation of the alignment mark 126 may include the following steps. First, an etching process is performed through a mask layer (e.g., ) above the top surface of the second die 120 (e.g., isolation layer 125). Figure 5 The mask layer PR (as shown) forms multiple openings OP. Therefore, the pattern of the mask layer PR is transferred to the isolation layer 125 (and may be the substrate 121 of the second die 120) via an etching process. The mask layer can then be removed using a suitable removal process (such as an ashing process). A dielectric layer 1423 can then be formed over the second die 120 and the sealing material 130 to cover the top surfaces of the second die 120 (e.g., isolation layer 125) and the sealing material 130, and fill the openings OP to form alignment marks 126. The dielectric layer 1423 can be formed using a suitable deposition process (such as CVD).

[0096] In some embodiments, the dielectric material filling the opening OP of the alignment mark 126 may be a composite layer. That is, multiple dielectric layers may be filled in the opening OP of the alignment mark 126, such as... Figure 24 The enlarged view on the right is shown in the middle. In some embodiments, alignment mark 126 may include a waterproof layer 1267 (such as a silicon nitride (SiN) layer covering the sidewalls of the opening OP) and a dielectric material (e.g., dielectric layer 1423) of the redistribution structure 140 filling the remainder of the opening OP. In some embodiments, waterproof layer 1267 may cover the entire top surface of the second die (e.g., the top surface of the insulating layer 125 and the sidewalls of the opening OP) and the top surface of the sealant 130 to provide waterproof properties to the second die 120 and the sealant 130. For example, waterproof layer 1267 may have a thickness in the range of about 500 angstroms to about 750 angstroms. Waterproof layer 1267 may be formed by CVD technology. The dielectric material of redistribution structure 140 may include silicon oxide (SiO2). X The silicon oxide layer may include tetraethoxysilane (TEOS) or quartz glass. The silicon oxide layer may have a thickness ranging from about 1 μm to about 2 μm. It should be noted that the dielectric material filling the opening OP may be different from the material of the insulating layer 125. In some embodiments, the formation of the alignment mark 126 may include the following steps. First, an etching process is performed through a mask layer (e.g., etched through the top surface of the second die 120 (e.g., insulating layer 125) above the mask layer. Figure 5The mask layer PR shown forms multiple openings OP. Therefore, the pattern of the mask layer PR is transferred to the isolation layer 125 (and may be the substrate 121 of the second die 120) via an etching process. The mask layer can then be removed using a suitable removal process (such as an ashing process). A waterproof layer 1267 can then be formed over the top surface of the isolation layer 125 (and the top surface of the sealing material 130), and the waterproof layer 1267 covers the sidewalls of the openings OP. In some embodiments, the waterproof layer 1267 may be formed of a material including silicon nitride (SiN). The thickness of the waterproof layer 1267 can range from about 500 angstroms to about 750 angstroms. The waterproof layer 1267 can be formed using various deposition techniques such as ALD, PVD, CVD, or other suitable techniques. Then, dielectric layer 1423 can be formed over second die 120 and sealing material 130 to cover the top surface of second die 120 (e.g., isolation layer 125) and sealing material 130, and fill the remainder of opening OP to form alignment mark 126. Dielectric layer 1423 can be formed by a suitable deposition process (such as CVD).

[0097] Figures 25 to 26 A cross-sectional view is shown of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present invention. It should be noted that... Figures 25 to 26 The manufacturing method and semiconductor package shown include many components that are the same as or similar to those disclosed in the previous embodiments. For clarity and simplicity, detailed descriptions of the same or similar components may be omitted, and the same or similar reference numerals denote the same or similar components.

[0098] refer to Figure 25 In some embodiments, the redistribution layer 1422' may contact the through-hole 124 without a dielectric via (e.g., Figure 24 The dielectric via 1421 shown connects them. For example, a dielectric layer 1423 may be formed over the second die 120 and the sealing material 130 to cover the top surface of the second die 120 (e.g., the insulating layer 125) and the sealing material 130. The dielectric layer 1423 may include oxides (such as silicon oxide), nitrides (such as silicon nitride), USG, or combinations thereof. The dielectric layer 1423 may be formed by a suitable deposition process (such as CVD). A redistribution layer (trace) 1422' is then formed in the dielectric layer 1423 by, for example, an damascene process. In some embodiments, when viewed from a top view, the alignment mark 126 does not overlap with the redistribution layer (trace) 1422', so the alignment mark 126 is not blocked during the alignment process. However, the invention is not limited thereto.

[0099] In some embodiments, a patterning process is performed to form a plurality of trenches in the dielectric layer 1423. In some embodiments, the trenches extend through the dielectric layer 1423. The patterning process removes a portion of the dielectric layer 1423 to expose the top surface of the through-hole 124 of the second die 120. The patterning process may include multiple photolithography and / or etching processes. The sidewalls of the trenches may be straight or sloping. The trenches are then filled with a conductive material to form Figure 25 The redistribution layer 1422' is shown. The conductive material includes a suitable metallic material, such as copper or a copper alloy. In some embodiments, the method of forming the conductive material may include a plating process (such as electroplating or electrochemical plating) or a suitable deposition process (such as CVD, PVD, etc.). Thereafter, a planarization process, such as CMP, may be performed to remove excess portions of the conductive material until the dielectric layer 1423 is exposed. In some embodiments, after the planarization process, the top surface of the redistribution layer 1422' is substantially coplanar with the top surface of the dielectric layer 1423.

[0100] Then, refer to Figure 26 In some embodiments, a passivation layer 1443 is formed over a dielectric layer 1423, and a via 1441 is formed in the passivation layer 1443 to electrically connect to the redistribution layer 1422'. A redistribution layer (or conductive pad) 1442 is then formed over the passivation layer 1443 and the via 1441, and is electrically coupled to the redistribution layer 1422'. The materials of the redistribution layer (or conductive pad) 1442 and the via 1441 may each comprise suitable metallic materials, such as aluminum, copper, alloys thereof, or combinations thereof. In some embodiments, the conductive pad 1442 may be an aluminum pad or an aluminum-copper pad, and other metallic materials may be used. The via 1441 and the redistribution layer 1442 may be formed separately with an interface between them, or formed simultaneously without an interface between them. In some embodiments, the alignment mark 126 does not overlap with the redistribution layer 1442 when viewed from a top view, so that the alignment mark 126 is not obstructed during the alignment process. However, the invention is not limited thereto.

[0101] In some embodiments, passivation layer 1445 may be formed over passivation layer 1443 to at least laterally seal conductive pad 1442. Passivation layers 1443 and 1445 may be monolayers or composite layers, and may be formed of non-porous materials. In some embodiments, each of passivation layers 1443 and 1445 may include silicon oxide, silicon nitride, or a combination thereof. In some embodiments, one or both of passivation layers 1443 and 1445 are composite layers comprising a silicon oxide layer (not shown separately) and a silicon nitride layer (not shown separately) situated above the silicon oxide layer. Passivation layers 1443 and 1445 may also be formed of other non-porous dielectric materials, such as undoped silicate glass (USG), silicon oxynitride, or a combination thereof. A planarization process, such as a CMP process, may then be performed to remove excess portions of passivation layer 1445 until conductive pad 1442 is exposed. In some embodiments, after performing a planarization process, the top surface of the conductive pad 1442 is substantially coplanar with the top surface of the passivation layer 1445.

[0102] Figures 27 to 28 A cross-sectional view is shown of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present invention. It should be noted that... Figures 27 to 28 The manufacturing method and semiconductor package shown include many components that are the same as or similar to those disclosed in the previous embodiments. For clarity and simplicity, detailed descriptions of the same or similar components may be omitted, and the same or similar reference numerals denote the same or similar components.

[0103] refer to Figure 27 According to some embodiments of the present invention, the material filling the opening OP of the alignment mark 126 may be a dielectric material. In some embodiments, the dielectric material of the redistribution structure 140 fills the opening OP of the alignment mark 126. For example, the dielectric layer 1423 may fill the opening OP to form such a Figure 27 Alignment mark 126 is shown. Furthermore, in some embodiments, the redistribution layer 1422' may be in direct contact with the through-hole 124 without a dielectric via (e.g., Figure 24The dielectric via 1421 shown connects them. For example, after forming the opening of alignment mark 126 by an etching process, a dielectric layer 1423 can be formed over the second die 120 and the sealing material 130 to cover the top surface of the second die 120 (e.g., isolation layer 125) and the sealing material 130, and fill the opening of alignment mark 126. The dielectric layer 1423 can be formed by a suitable deposition process (such as CVD). Then, a redistribution layer (trace) 1422' is formed in the dielectric layer 1423 by, for example, an damascene process. In some embodiments, the alignment mark 126 does not overlap with the redistribution layer (trace) 1422' when viewed from a top view, so that the alignment mark 126 is not blocked during the alignment process. However, the invention is not limited thereto. In other embodiments, the redistribution layer (trace) 1422' may also include an alignment pattern that overlaps (aligns) with the alignment mark 126.

[0104] In some embodiments, a patterning process is performed to form a plurality of trenches in the dielectric layer 1423. In some embodiments, the trenches extend through the dielectric layer 1423. The trenches are then filled with a conductive material to form Figure 27 The redistribution layer 1422' shown is illustrated. The conductive material includes a suitable metallic material, such as copper or a copper alloy. In some embodiments, the method of forming the conductive material may include a plating process (such as electroplating or electrochemical plating) or a suitable deposition process (such as CVD, PVD, etc.). Subsequently, a planarization process, such as CMP, may be performed to remove excess portions of the conductive material until the dielectric layer 1423 is exposed.

[0105] Then, refer to Figure 28 In some embodiments, a passivation layer 1443 is formed over a dielectric layer 1423, and a via 1441 is formed in the passivation layer 1443 to electrically connect to the redistribution layer 1422'. A redistribution layer (or conductive pad) 1442 is then formed over the passivation layer 1443 and the via 1441, and is electrically coupled to the redistribution layer 1422'. In some embodiments, alignment marks 126 do not overlap with the redistribution layer 1442 when viewed from a top view, so that the alignment marks 126 are not blocked during the alignment process. However, the invention is not limited thereto. In other embodiments, the redistribution layer 1442 may also include an alignment pattern that overlaps (aligns) with the alignment marks 126.

[0106] In some embodiments, a passivation layer 1445 may be formed over a passivation layer 1443 to at least laterally seal the conductive pads 1442. A planarization process (such as a CMP process) may then be performed to remove excess portions of the passivation layer 1445 until the conductive pads 1442 are exposed. In some embodiments, after the planarization process, the top surface of the conductive pads 1442 is substantially coplanar with the top surface of the passivation layer 1445 within a process variation. The present invention does not limit the process and sequence of steps for manufacturing the redistributed structure 140.

[0107] Figures 29 to 32 A cross-sectional view is shown of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present invention. It should be noted that... Figures 29 to 32 The manufacturing method and semiconductor package shown include many components that are the same as or similar to those disclosed in the previous embodiments. For clarity and simplicity, detailed descriptions of the same or similar components may be omitted, and the same or similar reference numerals denote the same or similar components.

[0108] refer to Figure 29 In some embodiments, the isolation layer 125 may be a composite layer. For example, the isolation layer 125 may include a waterproof layer 1251 and an insulating layer 1252. Figures 29 to 32 An example of the process for forming the composite insulating layer 125 is shown, and Figures 29 to 32 The process shown in the diagram can be performed in... Figure 3 The process shown will be performed afterward. Figure 3 The process shown removes the back side portion of the substrate 121 of the second die 120. After removing the back side portion of the substrate 121, a through-hole 124 protrudes from the back side of the substrate 121 and forms as shown. Figure 3 The groove RC spanning the substrate 121 is shown. Then, as... Figure 29 As shown, a waterproof layer 1251 is formed over the back side of substrate 121. In some embodiments, the waterproof layer 1251 may also cover the exposed surfaces of the through-hole 124 (e.g., the top surface and part of the side surface) and the top surface of the sealant 130. In some embodiments, the waterproof layer 1251 is a conformal layer, i.e., the waterproof layer 1251 has substantially equal thickness along a region (on which the waterproof layer 1251 is formed). The waterproof layer 1251 may include silicon nitride (SiN) and the like. In some embodiments, the waterproof layer 1251 may cover the back side of substrate 121, the exposed surfaces of through-hole 124, and the exposed surfaces of sealant 130 to provide waterproof properties to the second die 120 and sealant 130. In one example, the thickness of the waterproof layer 1251 may range from about 500 angstroms to about 750 angstroms. The waterproof layer 1251 can be formed using various deposition techniques such as ALD, PVD, CVD, or other suitable techniques. Then, as... Figure 30As shown, an insulating layer 1252 can be formed over the waterproof layer 1251 to fill the remaining portion of the groove. The insulating layer 1252 can be formed by a suitable deposition process (such as CVD). Thereafter, a planarization process (such as CMP) can be performed to remove excess portions of the waterproof layer 1251 and the insulating layer 1252 until the through-hole 124 and the sealant 130 are exposed. In some embodiments, after the planarization process, the top surfaces of the waterproof layer 1251 and the insulating layer 1252 are substantially coplanar with the top surfaces of the through-hole 124 and the sealant 130 within a process variation, and the waterproof layer 1251 laterally seals a portion of the side surface of the through-hole protruding from the substrate 121 of the second die 120.

[0109] refer to Figure 31 Then, multiple openings OP are formed by an etching process. Specifically, the openings OP can be formed by transferring the pattern of the mask layer to the waterproof layer 1251 and the insulating layer 1252 (and may be the substrate 121 of the second die 120) using an etching process. In some embodiments, the openings OP extend at least through the waterproof layer 1251 and the insulating layer 1252.

[0110] Then, refer to Figure 32 Alignment marks 126 are formed by filling openings OP with, for example, conductive or dielectric materials. In this embodiment, alignment marks 126 are formed by filling openings OP with conductive materials. For example, alignment marks 126 may include one or more conductive materials, such as copper, tungsten, other conductive metals, etc., and may be formed, for example, by electroplating, electroless plating, etc. The conductive material of alignment marks 126 may be the same as the conductive material of through-holes 124. In some embodiments, the conductive material of alignment marks 126 may be different from the conductive material of through-holes 124 because they are formed by different processes in separate steps. In other embodiments, alignment marks 126 are formed by filling openings OP with dielectric materials, such as dielectric layers of redistributed structures. Therefore, since the composite isolation layer 125 (including the waterproof layer 1251 and the insulating layer 1252) is formed after the through hole 124 is formed and before the alignment mark 126 is formed, the insulating layer 1252 and the through hole 124 are isolated from each other by the waterproof layer 1251, and both the insulating layer 1252 and the waterproof layer 1251 are in partial contact with the side surface of the alignment mark 126.

[0111] Figure 33 A partial top view of a die for a semiconductor package according to some embodiments of the present invention is shown. It should be noted that... Figure 33 The semiconductor package shown includes many components that are the same as or similar to those disclosed in the previous embodiments. For clarity and simplicity, detailed descriptions of the same or similar components may be omitted, and the same or similar reference numerals denote the same or similar components.

[0112] According to some embodiments of the present invention, Figure 33 A top view of the die corner is shown; the die corner may also be referred to as the die corner circuit disable (DCCF) area. In some embodiments, Figure 33 The die corner region shown is located at the corner of the second die 120. The integrated circuit is excluded from the die corner region because it is an area that may experience greater stress during and after back-end processing such as die sawing and packaging. The die corner region may include pseudo-metal patterns 127, 129 for stress relief. The pseudo-metal patterns may include a first pseudo-metal pattern 127 and a second pseudo-metal pattern 129. The first pseudo-metal pattern 127 and the second pseudo-metal pattern 129 may be located within the die corner region close to each other and configured such that the first pseudo-metal pattern 127 is within and / or closer to the active region (integrated circuit region) AR, and the second pseudo-metal pattern 129 is closer to the outline of the die corner region (e.g., along a scribing line), such as... Figure 33 As shown. The die corner region may also include a portion of a sealing ring 128 surrounding the active region AR, and an alignment mark 126 may be provided outside the active region AR and may be located inside the sealing ring 128.

[0113] In some embodiments, alignment mark 126 is disposed in at least one corner of the second die 120. For example, alignment mark 126 is disposed in... Figure 33 The die corner region shown. This combined structure (e.g., die corner region) with alignment marks 126 co-located with the first pseudo-metal pattern 127, the second pseudo-metal pattern 129, and the sealing ring 128 can utilize the die area more efficiently and save more die area for integrated circuit layout. According to some embodiments of the invention, the alignment marks 126 may be disposed within the sealing ring 128 (e.g., Figure 33 (as shown), within the first dummy metal pattern 127, the second dummy metal pattern 129, or a combination thereof. The alignment mark 126 may be isolated from the sealing ring 128, the first dummy metal pattern 127, and / or the second dummy metal pattern 129.

[0114] Figure 34 A schematic top view and a partial enlarged view of a die for a semiconductor package according to some embodiments of the present invention are shown. It should be noted that... Figure 34 The semiconductor package shown includes many components that are the same as or similar to those disclosed in the previous embodiments. For clarity and simplicity, detailed descriptions of the same or similar components may be omitted, and the same or similar reference numerals denote the same or similar components.

[0115] refer to Figure 34According to some embodiments of the present invention, the second die 120 may include more than one set of alignment marks 126 and 126'. In some embodiments, the multiple sets of alignment marks may be respectively disposed at multiple corners of the second die 120. For example, the alignment marks may include a first set of alignment marks 126 and a second set of alignment marks 126', which are respectively disposed at different corners, such as two opposite corners of the second die 120, such as... Figure 34 As shown. In some embodiments, two sets of alignment marks 126 and 126' may be arranged adjacent to opposite corners of the second die 120. In some embodiments, two sets of alignment marks 126 and 126' may be formed adjacent to two corners of the second die 120, wherein the two corners are adjacent corners formed by the same edge of the second die 120. It should be noted that although two sets of alignment marks 126 and 126' are shown herein, more or fewer sets of alignment marks may be provided. The invention is not limited thereto. In some embodiments, multiple sets of alignment marks may be arranged adjacent to each corner of the second die 120. Alignment marks 126 and 126' may be disposed within a sealing ring 128 surrounding the active region AR.

[0116] In some embodiments, each set of alignment marks 126 / 126' may have the same pattern. For example, each of the first set of alignment marks 126 and the second set of alignment marks 126' may have... Figure 34 The same pattern shown in the enlarged partial view comprises multiple subsets of alignment marks 1261, 1262, 1263, 1264, and the respective pitches of the subsets of alignment marks 1261, 1262, 1263, 1264 may be different from each other. In other embodiments, the pattern of each set of alignment marks may be different from each other.

[0117] Figure 35 A schematic top view and a partial enlarged view of a die for a semiconductor package according to some embodiments of the present invention are shown. It should be noted that... Figure 35 The semiconductor package shown includes many components that are the same as or similar to those disclosed in the previous embodiments. For clarity and simplicity, detailed descriptions of the same or similar components may be omitted, and the same or similar reference numerals denote the same or similar components.

[0118] refer to Figure 35According to some embodiments of the present invention, the second die 120 may include more than one set of alignment marks (e.g., two sets of alignment marks 126” and 126”'). In some embodiments, the multiple sets of alignment marks may be respectively disposed on multiple sides of the second die 120. For example, the alignment marks may include two sets of alignment marks 126” and 126”', which are respectively disposed on two adjacent sides of the second die 120, such as... Figure 35 As shown. Two sets of alignment marks 126” and 126”' can be formed adjacent to both sides of the second die 120, wherein these two sides are adjacent sides forming the same corner of the second die 120. In some embodiments, the two sets of alignment marks 126” and 126”' can be set adjacent to two opposite sides of the second die 120. It should be noted that although two sets of alignment marks 126” and 126”' are shown herein, more or fewer sets of alignment marks may be provided. The invention is not limited thereto. In some embodiments, multiple sets of alignment marks may be provided adjacent to each side of the second die 120. Alignment marks 126” and 126”' can be disposed within a sealing ring 128 surrounding the active region AR.

[0119] In some embodiments, each set of alignment marks 126” / 126”’ may have the same pattern. For example, each of the two sets of alignment marks 126” and 126”’ may have Figure 35 The same pattern shown in the enlarged partial view comprises multiple subsets of alignment marks 1261, 1262, 1263, 1264, and the respective pitches of the subsets of alignment marks 1261, 1262, 1263, 1264 may be different from each other. In other embodiments, the pattern of each set of alignment marks may be different from each other.

[0120] Figures 36 to 37 A cross-sectional view is shown of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present invention. It should be noted that... Figure 36 and Figure 37 The semiconductor package shown includes many components that are the same as or similar to those disclosed in the previous embodiments. For clarity and simplicity, detailed descriptions of the same or similar components may be omitted, and the same or similar reference numerals denote the same or similar components.

[0121] refer to Figure 36 According to some embodiments of the present invention, the second die 120 may be coupled to the first die 110 in a face-to-back configuration. That is, the front (active) surface of the second die 120 faces the back surface of the first die 110. In some embodiments, at least one integrated circuit device 1131 is formed in the front side of the first die 110 facing away from the second die 120, such as... Figure 36As shown. In some embodiments, the integrated circuit device 1131 may be formed in a front-end process (FEOL) process.

[0122] In some embodiments, integrated circuit devices 1131 (such as transistors including gate structures) are formed in the front side of the first die 110, while no devices are formed in the back side of the first die 110 facing the second die 120. In addition, the back side of the first die 110 is bonded to the front side of the second die 120, and thus the resulting stacked structure is a front-to-back (face-to-back) stacked structure.

[0123] In some embodiments, a plurality of through-substrate vias (TSVs) 114 extend through the substrate 111 of the first die 110, such as Figure 36 As shown. A through-hole 114 is used to provide electrical connectivity. The through-hole 114 connects the integrated circuit device 1131 and a metal line formed on the front side (shown bottom side) of the substrate 111 to a conductive pad 112 on the back side. In some embodiments, the through-hole 114 may extend into the interconnect structure 113 to make physical and electrical contact with conductive components of the interconnect structure 113. In some embodiments, the interconnect structure 113 is formed on the front side of the first die 110, and the through-hole 114 directly contacts the conductive components of the interconnect structure 113 on the front side of the first die 110 and the conductive pad 112 on the back side of the first die 110. In some embodiments, the through-hole 114 may include a pad (not shown) for covering its surface. The pad is disposed between the through-hole 114 and the substrate 111 to separate the through-hole 114 from the substrate 111. The pad may surround the sidewalls and / or top surface of the through-hole 114. The through-hole 114 may include copper, copper alloy, aluminum, aluminum alloy, Ta, TaN, Ti, TiN, CoW, or combinations thereof. The pad may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0124] refer to Figure 37 In some embodiments, carrier C1 can be removed, and the above regarding Figure 9 and Figure 10 The described similar process can be applied to semiconductor package 100 to form Figure 37 The stacked packaging structure 10 is shown. For example, Figure 36The semiconductor package 100 and interlayer vias 500 shown can be provided on a carrier, and when placing the semiconductor package 100, alignment marks 126 on the second die 120 can be used to align the position of the semiconductor package 100 to ensure that the semiconductor package 100 is placed in the desired position and that the semiconductor package 100 does not shift or rotate from its intended position and orientation. Alignment is performed by determining the relative alignment of the semiconductor package 100 with respect to the alignment marks 126. The alignment marks 126 are formed using a different process than those of the vias 124 of the second die 120, such that the pitch and pattern of the alignment marks 126 can differ from those of the vias 124 to meet fine pitch requirements and provide better resolution.

[0125] Furthermore, the semiconductor package 100 and the interlayer via 500 are at least laterally sealed by the sealing material 200. A redistribution structure 300 is then formed over the semiconductor package 100, and electrical connections 310 are disposed on the redistribution structure 300 to form a package structure PK. In some embodiments, electrical terminals 610 are formed over the package structure PK to be electrically connected to the interlayer via 500, and another package structure 600 is disposed on the package structure PK and electrically connected to the interlayer via 500 via electrical terminals 610. The wafer-level package can then be sawn into a plurality of independent stacked package structures 10, wherein each stacked package structure 10 includes a package structure 600 bonded to a package structure PK.

[0126] Based on the above discussion, it can be seen that the present invention provides various advantages. However, it should be understood that not all advantages need to be discussed herein, and other embodiments may provide different advantages, and no particular advantage is required in all embodiments.

[0127] Other components and processes may also be included. For example, test structures may be included to assist in verification testing of 3D packaged or 3DIC devices. Test structures may include, for example, test pads formed in a redistribution layer or on a substrate, which allow testing of the 3D package or 3DIC using probes and / or probe cards. Verification tests can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with test methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0128] According to some embodiments of the present invention, a semiconductor package includes a first die, a second die, an encapsulating material, and a redistribution structure. The first die includes a first bonding pad. The second die is disposed above the first die and includes a second bonding pad. The first bonding pad is bonded to the second bonding pad. The second die includes a substrate, a plurality of through-holes extending through the substrate, and a plurality of alignment marks. The pitch between two adjacent alignment marks is different from the pitch between two adjacent through-holes. The encapsulating material is disposed above the first die. The encapsulating material laterally seals the second die. The redistribution structure is disposed above the second die and the encapsulating material. The redistribution structure includes conductive elements electrically connected to corresponding through-holes in the plurality of through-holes. In some embodiments, the depth of each of the plurality of alignment marks is different from the depth of each of the plurality of through-holes. In some embodiments, the second die further includes an isolation layer disposed between the substrate of the second die and the redistribution structure, wherein the plurality of through-holes extend through the isolation layer. In some embodiments, the plurality of alignment marks extend from an upper surface of the isolation layer facing the redistribution structure and toward the substrate. In some embodiments, viewed from a top view, the alignment marks do not overlap with the conductive elements of the redistribution structure. In some embodiments, the redistribution structure includes an alignment pattern overlapping a plurality of alignment marks when viewed from a top view, wherein the alignment pattern includes a conductive material. In some embodiments, the redistribution structure includes a dielectric material, wherein the dielectric material of the redistribution structure and the alignment marks comprise a single continuous layer. In some embodiments, the alignment marks include a conductive material. In some embodiments, the alignment marks are disposed at corners of the second die. In some embodiments, the alignment marks include a first set of alignment marks and a second set of alignment marks, wherein the first set of alignment marks and the second set of alignment marks are disposed at different corners of the second die or at different sides of the second die. In some embodiments, the second die includes an active region and a sealing ring structure surrounding the active region of the second die, wherein the alignment marks are disposed outside the active region. In some embodiments, the cross-sectional shape of one of the alignment marks differs from the cross-sectional shape of one of the through-holes.

[0129] According to some embodiments of the present invention, a semiconductor package includes a first die, a second die, a first sealing material, and a first redistribution structure. The second die is disposed above and bonded to the first die. The second die includes a substrate and a plurality of through-holes extending through the substrate. The second die includes a plurality of alignment marks. The depth of the alignment marks differs from the depth of the through-holes. The first sealing material laterally seals the first die and the second die. The first redistribution structure is disposed above the second die and the first sealing material. The first redistribution structure includes a first conductive member electrically connected to the first die and the second die. In some embodiments, the semiconductor package further includes a second sealing material disposed above the first die and laterally sealing the second die, and the first sealing material laterally seals the first die and the second sealing material. In some embodiments, the semiconductor package further includes a second redistribution structure disposed above the second die and the second sealing material. The second redistribution structure includes a second conductive member electrically connected to the plurality of through-holes. The first sealing material laterally seals the second redistribution structure. The first redistribution structure is disposed above the second redistribution structure and the first sealing material. In some embodiments, the semiconductor package further includes a plurality of interlayer vias extending through the first sealing material.

[0130] According to some embodiments of the present invention, a method includes bonding a first die to a second die, the first die including a plurality of first bonding pads, the second die including a plurality of second bonding pads bonded to corresponding first bonding pads among the first bonding pads, the second die including a plurality of through-holes electrically connected to corresponding second bonding pads among the plurality of second bonding pads; forming a sealing material over the first die, the sealing material laterally sealing the second die; forming a plurality of alignment marks on the second die, the pitch between two adjacent alignment marks being different from the pitch between two adjacent through-holes among the plurality of through-holes; and forming a redistribution structure over the second die and the sealing material. In some embodiments, the method further includes removing a back-side portion of a substrate of the second die such that the plurality of through-holes protrude from the substrate; and providing an isolation layer over the substrate. The isolation layer laterally seals the through-holes protruding from the substrate, and the alignment marks are formed on the isolation layer. In some embodiments, forming the alignment marks on the second die further includes forming the alignment marks in the isolation layer. In some embodiments, forming alignment marks and forming a redistribution structure over the second die and the sealing material includes forming a groove in the back of the second die; and forming a dielectric layer over the second die and the sealing material. The dielectric layer fills the groove, and portions of the dielectric layer in the groove form a plurality of alignment marks.

[0131] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a base to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor package, comprising: A first die, wherein the first die includes a first bonding pad; A second die is disposed above the first die, wherein the second die includes a second bonding pad, wherein the first bonding pad is bonded to the second bonding pad, wherein the second die includes a substrate and a plurality of through holes extending through the substrate, wherein the second die includes a plurality of alignment marks, wherein the pitch between two adjacent alignment marks is different from the pitch between two adjacent through holes. A sealing material is disposed above the first core, and the sealing material laterally seals the second core; and A redistribution structure is disposed above the second die and the sealing material, wherein the redistribution structure includes a conductive component, wherein the conductive component is electrically connected to a corresponding through hole among the plurality of through holes; The second die further includes an isolation layer disposed between the substrate and the redistribution structure of the second die, wherein the plurality of alignment marks are disposed in the isolation layer and extend from the upper surface of the second die opposite to the first die, and the plurality of alignment marks directly contact the redistribution structure.

2. The semiconductor package according to claim 1, wherein, The depth of each of the plurality of alignment marks is different from the depth of each of the plurality of through holes.

3. The semiconductor package according to claim 1, wherein, The plurality of through holes extend through the isolation layer.

4. The semiconductor package according to claim 3, wherein, The plurality of alignment marks extend from the upper surface of the isolation layer facing the redistribution structure and toward the substrate.

5. The semiconductor package according to claim 1, wherein, Viewed from the top view, the plurality of alignment marks do not overlap with the conductive components of the redistributed structure.

6. The semiconductor package according to claim 1, wherein, The redistribution structure includes an alignment pattern that overlaps with the plurality of alignment marks when viewed from a top view, wherein the alignment pattern includes a conductive material.

7. The semiconductor package according to claim 1, wherein, The redistribution structure includes a dielectric material, wherein the dielectric material and the plurality of alignment marks of the redistribution structure comprise a single continuous layer.

8. The semiconductor package according to claim 1, wherein, The plurality of alignment marks comprise conductive material.

9. The semiconductor package according to claim 1, wherein, The plurality of alignment marks are located at the corners of the second die.

10. The semiconductor package according to claim 1, wherein, The plurality of alignment marks includes a first set of alignment marks and a second set of alignment marks, wherein the first set of alignment marks and the second set of alignment marks are disposed at different corners of the second die or at different sides of the second die.

11. The semiconductor package according to claim 1, wherein, The second die includes an active region and a sealing ring structure surrounding the active region of the second die, wherein the plurality of alignment marks are disposed on the outside of the active region.

12. The semiconductor package according to claim 1, wherein, The cross-sectional shape of one of the plurality of alignment marks is different from the cross-sectional shape of one of the plurality of through holes.

13. A semiconductor package, comprising: First die; A second die is disposed above and coupled to the first die, wherein the second die includes a substrate and a plurality of through holes extending through the substrate, wherein the second die includes a plurality of alignment marks, wherein the depth of the plurality of alignment marks is different from the depth of the plurality of through holes; A first sealing material is used to laterally seal the first core and the second core; and A first redistribution structure is disposed above the second die and the first sealing material, wherein the first redistribution structure includes a first conductive component electrically connected to the first die and the second die; The second die further includes an isolation layer disposed between the substrate of the second die and the first redistribution structure, wherein the plurality of alignment marks are disposed in the isolation layer and extend from the upper surface of the second die opposite to the first die, and the plurality of alignment marks directly contact the first redistribution structure.

14. The semiconductor package of claim 13, further comprising a second sealing material disposed above the first die and laterally sealing the second die, wherein the first sealing material laterally seals the first die and the second sealing material.

15. The semiconductor package of claim 14, further comprising a second redistribution structure disposed above the second die and the second sealing material, wherein, The second redistribution structure includes a second conductive component electrically connected to the plurality of through holes, wherein the first sealing material laterally seals the second redistribution structure, and wherein the first redistribution structure is disposed above the second redistribution structure and the first sealing material.

16. The semiconductor package of claim 13, further comprising a plurality of interlayer vias extending through the first sealing material.

17. A method of forming a semiconductor package, comprising: A first die is bonded to a second die, wherein the first die includes a plurality of first bonding pads, wherein the second die includes a plurality of second bonding pads bonded to corresponding first bonding pads among the plurality of first bonding pads, and wherein the second die includes a plurality of through holes electrically connected to corresponding second bonding pads among the plurality of second bonding pads. A sealing material is formed above the first die, wherein the sealing material laterally seals the second die; After the first die is joined to the second die, a plurality of alignment marks are formed on the second die, wherein the pitch between two adjacent alignment marks is different from the pitch between two adjacent through holes; and A redistribution structure is formed above the second core and the sealing material.

18. The method of claim 17, further comprising: Remove the back side portion of the substrate of the second die, so that the plurality of through holes protrude from the substrate; as well as An isolation layer is provided above the substrate, wherein the isolation layer laterally seals the plurality of through holes protruding from the substrate, and the plurality of alignment marks are formed on the isolation layer.

19. The method according to claim 18, wherein, Forming the plurality of alignment marks on the second die also includes: The plurality of alignment marks are formed in the isolation layer.

20. The method of claim 17, wherein, Forming the plurality of alignment marks and the redistribution structure above the second die and the sealing material includes: A groove is formed on the back side of the second die; and A dielectric layer is formed over the second die and the sealing material, wherein the dielectric layer fills the groove, and portions of the dielectric layer in the groove form the plurality of alignment marks.

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