Semiconductor element structure and manufacturing method thereof

Abstract

The present disclosure provides a semiconductor device structure and a method for fabricating the same. The semiconductor device structure includes a substrate having a densely patterned region and a sparsely patterned region; a first conductive layer disposed on the substrate; a first dielectric layer disposed on the first conductive layer; a first conductive stud and a second conductive stud disposed in the first dielectric layer, wherein the first conductive stud and the second conductive stud comprise copper and are separated from the first dielectric layer by a first liner layer comprising manganese; and wherein the first conductive stud and the second conductive stud have different aspect ratios.

Description

[0001] This application claims priority to and the benefit of U.S. application No. 17 / 093,977, filed on November 10, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a semiconductor device structure and a method for manufacturing the same, and more particularly to a semiconductor device structure having a manganese-containing liner layer and a method for manufacturing the same. Background Art

[0003] Semiconductor components are indispensable for many modern applications. With advancements in electronics technology, semiconductor components are becoming increasingly smaller, while simultaneously providing improved functionality and incorporating a greater number of integrated circuits. This miniaturization has led to the integration and packaging of various semiconductor components of varying types and sizes, each fulfilling a specific function, into a single module. Furthermore, numerous manufacturing steps are required to integrate these various semiconductor devices.

[0004] However, the fabrication and integration of multiple semiconductor devices involves numerous complex steps and operations. Integration of multiple semiconductor devices is becoming increasingly complex. This increased complexity in the fabrication and integration of multiple semiconductor devices can lead to defects, such as voids in conductive structures caused by the difficulty in filling high-aspect-ratio openings. Consequently, there is a need for continuous improvements in the fabrication process for multiple semiconductor devices to address these defects.

[0005] The above description of “prior art” only provides background technology, does not admit that the above description of “prior art” discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of “prior art” above should not be regarded as any part of the present invention. Summary of the Invention

[0006] The present disclosure aims to provide a semiconductor device structure and a method for manufacturing the same to solve at least one of the above problems.

[0007] One embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed on a semiconductor substrate; a second conductive layer disposed on the first conductive layer; a first conductive stud disposed between the first conductive layer and the second conductive layer and electrically connecting the first conductive layer and the second conductive layer, wherein the first conductive stud comprises copper; and a first liner layer disposed around the first conductive stud, wherein the first liner layer comprises manganese.

[0008] In some embodiments, the first conductive layer and the second conductive layer both include copper, and the first conductive plug further includes tungsten.

[0009] In some embodiments, the first liner layer comprises copper manganese silicon.

[0010] In some embodiments, the semiconductor device structure further includes a first dielectric layer and an air gap, wherein the first dielectric layer is disposed around the first liner layer, and the air gap is located between the first liner layer and the first dielectric layer.

[0011] In some embodiments, the semiconductor device structure further includes: a third conductive layer disposed on the second conductive layer; a second conductive stud disposed between the second conductive layer and the third conductive layer and electrically connecting the second conductive layer and the third conductive layer, wherein the second conductive stud comprises copper; and a second liner layer disposed around the second conductive stud, wherein a portion of the second liner layer is sandwiched between the second conductive stud and the second conductive layer, and wherein the second liner layer comprises manganese.

[0012] In some embodiments, the second liner layer includes: a first liner sublayer disposed on the second conductive layer and directly contacting the second conductive layer, wherein the first liner sublayer contains manganese silicon; a second liner sublayer disposed on the first liner sublayer, wherein the second liner sublayer contains manganese; and a third liner sublayer disposed on the second liner sublayer, wherein the third liner sublayer directly contacts the second conductive plug, and wherein the third liner sublayer contains copper manganese.

[0013] In some embodiments, the second liner layer comprises copper manganese silicon.

[0014] Another embodiment of the present disclosure provides a semiconductor device structure, comprising: a first conductive layer disposed on a semiconductor substrate; a first dielectric layer disposed on the first conductive layer; a second conductive layer disposed on the first dielectric layer; a second dielectric layer disposed on the second conductive layer; a third conductive layer disposed on the second dielectric layer; a first conductive stud passing through the first dielectric layer and electrically connecting the first conductive layer to the second conductive layer, wherein the first conductive stud comprises copper; a first liner layer disposed between the first conductive stud and the first dielectric layer, wherein the first liner layer comprises manganese; a second conductive stud disposed in the second dielectric layer, wherein the second conductive stud electrically connects the second conductive layer to the third conductive layer, and wherein the second conductive stud comprises copper; and a second liner layer disposed between the second conductive stud and the second dielectric layer, wherein the second liner layer comprises manganese.

[0015] In some embodiments, one of the first conductive stud and the second conductive stud further comprises tungsten.

[0016] In some embodiments, the first conductive stud and the second conductive stud are disposed in a pattern-dense area, and an air gap is disposed between the first liner layer and the first dielectric layer.

[0017] In some embodiments, the semiconductor device structure further includes: a third conductive stud disposed in the second dielectric layer and in a pattern sparse area, wherein the third conductive stud electrically connects the second conductive layer to the third conductive layer, and the third conductive stud comprises copper; and wherein the third conductive stud is separated from the second dielectric layer by the second liner layer, and a height of the third conductive stud is greater than a height of the second conductive stud.

[0018] In some embodiments, a width of the third conductive stud is greater than a width of the second conductive stud.

[0019] In some embodiments, the second liner layer includes: a first liner sublayer disposed on the second conductive layer and directly contacting the second conductive layer, wherein the first liner sublayer contains manganese or manganese silicon; and a second liner sublayer disposed on the first liner sublayer, wherein the second liner sublayer directly contacts the second conductive plug, the third conductive plug and the third conductive layer, wherein the second liner sublayer contains copper manganese.

[0020] Another embodiment of the present disclosure provides a method for fabricating a semiconductor device structure, comprising: forming a first conductive layer on a semiconductor substrate, wherein the first conductive layer comprises copper; forming a first dielectric layer on the first conductive layer; etching the first dielectric layer to form a first opening, thereby exposing the first conductive layer; forming a first liner layer and a first conductive liner in the first opening, wherein the first liner layer comprises manganese, the first conductive stud comprises copper, and the first conductive stud is surrounded by the first liner layer; and forming a second conductive layer on the first dielectric layer, on the first liner layer, and on the first conductive layer, wherein the second conductive layer comprises copper.

[0021] In some embodiments, the method for preparing the semiconductor device structure further includes: forming an energy-removable layer to line the first opening before forming the first liner layer and the first conductive plug, wherein after the energy-removable layer is formed, the first conductive layer is partially exposed.

[0022] In some embodiments, the method for fabricating the semiconductor device structure further includes: after forming the second conductive layer, performing a thermal treatment process to transform the energy removable layer into an air gap.

[0023] In some embodiments, the method for preparing the semiconductor device structure further includes: forming a second dielectric layer on the second conductive layer; etching the second dielectric layer to form a second opening to expose the second conductive layer; forming a second liner layer and a second conductive plug in the second opening, wherein the second conductive plug is surrounded by the second liner layer, the second liner layer contains manganese, and the second conductive plug contains copper; and forming a third conductive layer to cover the second liner layer and the second conductive plug.

[0024] In some embodiments, the first conductive stud and the second conductive stud further comprise tungsten.

[0025] In some embodiments, the third conductive layer is separated from the second dielectric layer by the second liner layer, and a portion of the second liner layer is sandwiched between the second conductive stud and the second conductive layer.

[0026] In some embodiments, forming the second liner layer includes: forming a first liner sublayer on an upper surface of the second dielectric layer, wherein the sidewalls and a lower surface of the second opening are covered by the first liner sublayer, and wherein the first liner sublayer contains manganese silicon; forming a second liner sublayer on the first liner sublayer, wherein the second liner sublayer contains manganese; and forming a third liner sublayer on the second liner sublayer, wherein the third liner sublayer contains copper manganese.

[0027] Some embodiments of the present disclosure provide semiconductor device structures. In some embodiments, the semiconductor device structure has a conductive stud and a liner layer. The conductive stud is located between two conductive layers and electrically connects the two conductive layers, and the two conductive layers are arranged in a vertical direction. The liner layer is arranged around the conductive stud. The conductive stud comprises copper, and the liner layer comprises manganese. The manganese-containing liner layer is configured to reduce or prevent the formation of multiple voids in the conductive stud, thereby reducing the contact resistance of the conductive stud. As a result, the operating speed of the semiconductor device structure can be increased, which significantly improves the overall device performance.

[0028] The above has been a fairly broad overview of the technical features and advantages of the present disclosure so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art of the present disclosure that the concepts and specific embodiments disclosed below can be readily utilized to modify or design other structures or processes to achieve the same purposes as those of the present disclosure. It should also be understood by those skilled in the art of the present disclosure that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] A more complete understanding of the disclosure of the present invention may be obtained by referring to the detailed description and claims in conjunction with the accompanying drawings, in which like reference numerals refer to like elements.

[0030] Figure 1 A schematic cross-sectional view illustrating a semiconductor device structure according to some embodiments of the present disclosure.

[0031] Figure 2 A schematic cross-sectional view illustrating an improved semiconductor device structure according to some embodiments of the present disclosure.

[0032] Figure 3 A schematic cross-sectional view illustrating an improved semiconductor device structure according to some embodiments of the present disclosure.

[0033] Figure 4 A schematic cross-sectional view illustrating an improved semiconductor device structure according to some embodiments of the present disclosure.

[0034] Figure 5 A schematic flow chart illustrating a method for preparing a semiconductor device structure according to some embodiments of the present disclosure.

[0035] Figure 6 A cross-sectional schematic diagram illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage comprises sequentially forming a first conductive layer and a first dielectric layer on a semiconductor substrate during the formation of the semiconductor device structure.

[0036] Figure 7 A schematic cross-sectional view illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage is etching the first dielectric layer to expose a portion of the first conductive layer during the formation of the semiconductor device structure.

[0037] Figure 8 A schematic cross-sectional view illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage comprises forming an energy-removable material on the first dielectric layer during formation of the semiconductor device structure.

[0038] Figure 9 A schematic cross-sectional view illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage is etching the energy removable material to form an energy removable layer in the first dielectric layer during formation of the semiconductor device structure.

[0039] Figure 10 A schematic cross-sectional view illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage comprises forming a liner material on the energy removable layer during formation of the semiconductor device structure.

[0040] Figure 11A cross-sectional view illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage is etching the liner material to form a liner layer in the first dielectric layer and surrounded by the energy removable layer during formation of the semiconductor device structure.

[0041] Figure 12 A cross-sectional view illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage comprises forming a conductive stud in the first dielectric layer and surrounded by the liner layer during the formation of the semiconductor device structure.

[0042] Figure 13 A cross-sectional schematic diagram illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage comprises forming a second conductive layer on the first dielectric layer during the formation of the semiconductor device structure.

[0043] Figure 14 A cross-sectional schematic diagram illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage comprises forming a second dielectric layer having an opening during the formation of the semiconductor device structure to expose the second conductive layer through the opening.

[0044] Figure 15 A schematic cross-sectional view illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage comprises forming a liner layer on the second dielectric layer during the formation of the semiconductor device structure.

[0045] Figure 16 A cross-sectional view illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage comprises forming a conductive stud in the second dielectric layer and surrounded by the liner layer during the formation of the semiconductor device structure.

[0046] Figure 17 A cross-sectional schematic diagram illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage comprises forming a third conductive layer on the second dielectric layer during the formation of the semiconductor device structure.

[0047] Figure 18 A cross-sectional view illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage comprises forming a liner layer on the second dielectric layer during the formation of an improved semiconductor device structure.

[0048] Figure 19 A schematic cross-sectional view of a semiconductor device structure according to some embodiments of the present disclosure is provided, wherein the semiconductor device structure has a pattern-dense region and a pattern-sparse region.

[0049] Figure 20 A schematic flow chart illustrating a method for fabricating a semiconductor device structure according to some embodiments of the present disclosure is provided, wherein the semiconductor device structure has a pattern-dense region and a pattern-sparse region.

[0050] Figure 21 A cross-sectional schematic diagram illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage comprises sequentially forming a first conductive layer and a first dielectric layer having a first opening on a semiconductor substrate during formation of the semiconductor device structure.

[0051] Figure 22 A cross-sectional schematic diagram illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage comprises forming an energy-removable layer in the first opening in the pattern-dense area during the formation of the semiconductor device structure.

[0052] Figure 23 A cross-sectional view illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage comprises forming a plurality of liner layers in a plurality of first openings during the formation of the semiconductor device structure.

[0053] Figure 24 A cross-sectional view illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage comprises forming a plurality of conductive plugs in a plurality of first openings and forming a second conductive layer on the first dielectric layer during formation of the semiconductor device structure.

[0054] Figure 25 A cross-sectional schematic diagram illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage comprises forming a second dielectric layer having a plurality of second openings on the second conductive layer during the formation of the semiconductor device structure.

[0055] Figure 26 A cross-sectional schematic diagram illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage comprises forming a plurality of liner layers in a plurality of second openings during the formation of the semiconductor device structure.

[0056] Figure 27 A cross-sectional schematic diagram illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage comprises forming a plurality of conductive plugs in a plurality of second openings and forming a third conductive layer on the second dielectric layer during formation of the semiconductor device structure.

[0057] Figure 28 A partial schematic diagram of an exemplary integrated circuit having an array of multiple memory cells illustrating some embodiments of the present disclosure is shown.

[0058] The reference numerals are as follows:

[0059] 10: Preparation method

[0060] 100a: semiconductor device structure

[0061] 100b: semiconductor device structure

[0062] 1000: memory element

[0063] 101:Semiconductor substrate

[0064] 103: first conductive layer

[0065] 105: first dielectric layer

[0066] 110: First opening

[0067] 110': First opening

[0068] 110”: First opening

[0069] 113: Energy Removable Materials

[0070] 113': Energy Removable Structure

[0071] 113”: Energy Removable Structure

[0072] 123: Gasket material

[0073] 123': cushion layer

[0074] 133: Conductive bolt

[0075] 143: second conductive layer

[0076] 145: second dielectric layer

[0077] 145T: Upper surface

[0078] 150: Second opening

[0079] 150': Second opening

[0080] 150B: bottom surface

[0081] 150S: Sidewall

[0082] 153: cushioning layer

[0083] 155: first cushion sublayer

[0084] 157: Second cushion sublayer

[0085] 159: third cushion sublayer

[0086] 163: Conductive bolt

[0087] 173: third conductive layer

[0088] 180: Air Gap

[0089] 200a: semiconductor device structure

[0090] 200b: semiconductor device structure

[0091] 250: Second opening

[0092] 253: cushioning layer

[0093] 30: Preparation method

[0094] 300:Semiconductor component structure

[0095] 301: semiconductor substrate

[0096] 303: first conductive layer

[0097] 305: first dielectric layer

[0098] 310a: first opening

[0099] 310a': first opening

[0100] 310a": first opening

[0101] 310b: first opening

[0102] 310b': first opening

[0103] 313: Energy removable layer

[0104] 313': Energy Removable Structure

[0105] 323a: cushion layer

[0106] 323b: cushioning layer

[0107] 333a: Conductive bolt

[0108] 333b: Conductive bolt

[0109] 343: second conductive layer

[0110] 345: second dielectric layer

[0111] 350a: Second opening

[0112] 350a': second opening

[0113] 350b: Second opening

[0114] 350b': Second opening

[0115] 353: cushioning layer

[0116] 355: first cushion sublayer

[0117] 357: Second cushion sublayer

[0118] 363a: Conductive bolt

[0119] 363b: Conductive bolt

[0120] 373: third conductive layer

[0121] 380: Air Gap

[0122] 50: Memory Cell

[0123] 51: Field Effect Transistor

[0124] 53:Capacitor

[0125] 55: Drain

[0126] 57: Source

[0127] 59: Gate

[0128] A: Pattern-dense area

[0129] B: Sparse pattern area

[0130] BL: Bit Line

[0131] D1: Depth

[0132] D2: Depth

[0133] H1: Height

[0134] H2: Height

[0135] S11: Step

[0136] S13: Step

[0137] S15: Step

[0138] S17: Step

[0139] S19: Steps

[0140] S21: Step

[0141] S23: Step

[0142] S31: Step

[0143] S33: Step

[0144] S35: Step

[0145] S37: Steps

[0146] S39: Step

[0147] S41: Step

[0148] S43: Step

[0149] W1: width

[0150] W2: width

[0151] W3: Width

[0152] W4: Width

[0153] WL: character line DETAILED DESCRIPTION

[0154] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, the description of a first component formed on a second component may include embodiments in which the first and second components are in direct contact, and may also include embodiments in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. These repetitions are for the purpose of simplicity and clarity and do not, in themselves, represent a specific relationship between the various embodiments and / or configurations discussed unless otherwise specified in the text.

[0155] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature illustrated in the figures to another element or feature. These spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0156] Figure 1 A cross-sectional view of a semiconductor device structure 100a is shown in FIG. Figure 1 As shown, the semiconductor device structure 100a has a first conductive layer 103, a first dielectric layer 105, a second conductive layer 143, a second dielectric layer 145 and a third conductive layer 173; the first conductive layer 103 is arranged on a semiconductor substrate 101; the first dielectric layer 105 is arranged on the first conductive layer 103; the second conductive layer 143 is arranged on the first dielectric layer 105; the second dielectric layer 145 is arranged on the second conductive layer 143; and the third conductive layer 173 is arranged on the second dielectric layer 145.

[0157] The semiconductor device structure 100a also includes a liner layer 123' (which may be considered a first liner layer) and a conductive stud 133 (which may be considered a conductive stud) disposed within the first dielectric layer 105. In some embodiments, the conductive stud 133 is surrounded by the liner layer 123', and the liner layer 123' is surrounded by the first dielectric layer 105. It should be understood that the first conductive layer 103 is electrically connected to the second conductive layer 143 via the conductive stud 143.

[0158] Furthermore, the semiconductor device structure 100a includes an energy-removable structure 113' disposed within the first dielectric layer 105 and between the liner layer 123' and the first dielectric layer 105. In some embodiments, an air gap 180 is surrounded by the energy-removable structure 113'. In other words, the air gap 180 is disposed between the liner layer 123' and the first dielectric layer 105. In some embodiments, the liner layer 123' is surrounded by the energy-removable structure 113' and the air gap 180. In other embodiments, the energy-removable structure 113' is not formed. In these examples, the liner layer 123' is separated from the first dielectric layer 105 by the air gap 180.

[0159] The semiconductor device structure 100a further includes a liner layer 153 (which may be considered a second liner layer) and a conductive stud 163 (which may be considered a second conductive stud) disposed between the second conductive layer 143 and the third conductive layer 1732. In some embodiments, the conductive stud 163 is surrounded by the liner layer 153. It should be understood that the second conductive layer 143 is electrically connected to the third conductive layer 173 via the conductive stud 163 and the liner layer 153.

[0160] In some embodiments, the liner layer 153 is disposed between the second dielectric layer 145 and the third conductive layer 173, and extends between the conductive studs 163 and the second dielectric layer 145, and between the conductive studs 163 and the second conductive layer 143. In some embodiments, the sidewalls and lower surface of the conductive studs 163 are covered by the liner layer 153. In some embodiments, a portion of the liner layer 153 is sandwiched between the conductive studs 163 and the second conductive layer 143.

[0161] In some embodiments, the liner layer 153 is a laminated multilayer structure. Figure 1As shown, the liner layer 153 includes a first liner sublayer 155, a second liner sublayer 157, and a third liner sublayer 159. The second liner sublayer 157 is disposed on the first liner sublayer 155, and the third liner sublayer 159 is disposed on the second liner sublayer 157. In some embodiments, the first liner sublayer 155 directly contacts the second conductive layer 143 and the second dielectric layer 145. In some embodiments, the third liner sublayer 159 directly contacts the conductive studs 163 and the third conductive layer 173.

[0162] In some embodiments, the semiconductor cell structure 100a is a dynamic random access memory (DRAM). In these examples, the plurality of conductive layers (including the first conductive layer 103, the second conductive layer 143, and the third conductive layer 173) can function as bit lines (BLs), storage nodes, and / or wiring layers of the DRAM, and the plurality of conductive studs (including the conductive studs 133 and 163) can function as bit line contact studs, capacitor contact studs, and / or interconnect structures of the DRAM.

[0163] In some embodiments, the first conductive layer 103, the second conductive layer 143, the third conductive layer 173, and the conductive plugs 133 and 163 all include copper (Cu), and the liner layers 123' and 153 all include manganese (Mn). In some other embodiments, the conductive plugs 133 and 163 also include tungsten (W). In particular, according to some embodiments, the liner layer 123' includes copper-manganese-silicon (CuMnSi), the first liner sublayer 155 of the liner layer 153 includes manganese silicon (MnSi), the second liner sublayer 157 of the liner layer 153 includes manganese (Mn), and the third liner sublayer 159 of the liner layer 153 includes copper-manganese (CuMn).

[0164] The manganese-containing liner layers 123' and 153 are configured to reduce or prevent voids from forming in the conductive plugs 133 and 163, thereby reducing the contact resistance of the conductive plugs 133 and 163. Consequently, the operating speed of the semiconductor device structure 100a can be increased, significantly improving overall device performance.

[0165] Figure 2 A cross-sectional view of an improved semiconductor device structure 100b illustrating some embodiments of the present disclosure is another embodiment of the semiconductor device structure 100a. Figure 1 and Figure 2 Similar components in the diagram are marked with the same component number.

[0166] Similar to semiconductor device structure 100a, semiconductor device structure 100b includes a conductive stud 133 and a liner layer 123′ disposed within a first dielectric layer 105, with conductive stud 133 surrounded by liner layer 123′. However, the difference is that energy-removable structure 113″ and air gap 180 are not formed within the first dielectric layer 105 of semiconductor device structure 100b. That is, liner layer 123′ directly contacts the first dielectric layer 105.

[0167] Furthermore, similar to the semiconductor device structure 100a, the manganese-containing liner layers 123′ and 153 of the semiconductor device structure 100b are configured to reduce or prevent the formation of multiple voids in the conductive plugs 133 and 163, thereby reducing the contact resistance of the conductive plugs 133 and 163. Consequently, the operating speed of the semiconductor device structure 100b can be increased, significantly improving overall device performance.

[0168] Figure 3 A schematic cross-sectional view of an improved semiconductor device structure 200a illustrating some embodiments of the present disclosure is another embodiment of the semiconductor device structure 100a. For consistency and clarity, the Figure 1 and Figure 3 Similar components in the diagram are marked with the same component number.

[0169] Similar to semiconductor device structure 100a, semiconductor device structure 200a includes a liner layer 253 (referred to as a second liner layer) disposed between second conductive layer 143 and third conductive layer 1723, and conductive studs 163. The difference is that liner layer 253 in semiconductor device structure 200a is a single layer. In some embodiments, liner layer 253 comprises copper-manganese-silicon.

[0170] Furthermore, similar to the semiconductor device structure 100a, the liner layers 123' and 253 of the semiconductor device structure 200a are configured to reduce or prevent the formation of multiple voids in the conductive plugs 133 and 163, thereby reducing the contact resistance of the conductive plugs 133 and 163. Consequently, the operating speed of the semiconductor device structure 200a can be increased, significantly improving the performance of the entire device.

[0171] Figure 4 A cross-sectional view of an improved semiconductor device structure 200b illustrating some embodiments of the present disclosure is another embodiment of the semiconductor device structure 200a. Figure 3 and Figure 4 Similar components in the diagram are marked with the same component number.

[0172] Similar to semiconductor device structure 200a, semiconductor device structure 200b includes a conductive stud 133 and a liner layer 123' disposed within first dielectric layer 105, with conductive stud 133 surrounded by liner layer 123'. However, the difference is that energy-removable structure 113" and air gap 180 are not formed within first dielectric layer 105 of semiconductor device structure 200b. In other words, liner layer 123' directly contacts first dielectric layer 105.

[0173] Furthermore, similar to the semiconductor device structure 200a, the manganese-containing liner layers 123′ and 253 of the semiconductor device structure 200b are configured to reduce or prevent the formation of multiple voids in the conductive plugs 133 and 263, thereby reducing the contact resistance of the conductive plugs 133 and 263. Consequently, the operating speed of the semiconductor device structure 200b can be increased, significantly improving the performance of the overall device.

[0174] Figure 5 A flow chart illustrating a method 10 for fabricating a semiconductor device structure (including the semiconductor device structure 100 and improved semiconductor device structures 100b, 200a, 200b) according to some embodiments of the present disclosure is provided. The method 10 includes steps S11, S13, S15, S17, S19, S21, and S23. Figure 5 Steps S11 to S23 are described in detail with reference to the following drawings.

[0175] Figures 6 to 17 Schematic cross-sectional views illustrating various intermediate stages during the formation of a semiconductor device structure 100a according to some embodiments of the present disclosure. Figure 6 As shown, a semiconductor substrate 101 is provided. The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer.

[0176] Alternatively or additionally, the semiconductor substrate 101 may include an elementary semiconductor material, a compound semiconductor material, and / or an alloy semiconductor material. Examples of elemental semiconductor materials may include, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and gallium indium arsenide phosphide (GaInAsP).

[0177] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 includes an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator (SIO) substrate, which may include a substrate, a buried oxide layer, and a semiconductor layer, wherein the buried oxide layer is located on the substrate, and the semiconductor layer is located on the buried oxide layer. The SIO substrate may be, for example, a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The SIO substrate may be fabricated using separation by implanted oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0178] Please still refer to Figure 6 According to some embodiments, a first conductive layer 103 is formed on the semiconductor substrate 101, and a first dielectric layer 105 is formed on the first conductive layer 103. The individual steps are shown in FIG. Figure 5Step S11 in method 10 is shown.

[0179] In some embodiments, the first conductive layer 103 comprises copper, and the fabrication technique for the first conductive layer 103 comprises a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a metal organic chemical vapor deposition (MOCVD) process, a sputtering process, a plating process, or other applicable processes. In some embodiments, the first dielectric layer 105 comprises silicon oxide, silicon nitride, silicon oxynitride, or other applicable dielectric materials, and the fabrication technique for the first dielectric layer 105 comprises a deposition process, such as a CVD process, a PVD process, an ALD process, a spin coating process, or other applicable processes.

[0180] Then, according to some embodiments, such as Figure 7 As shown, an etching process is performed on the first dielectric layer 105 to form a first opening 110, thereby exposing the first conductive layer 103. The individual steps are shown in FIG. Figure 5 The formation of the first opening 110 may include forming a patterned mask (not shown) on the first dielectric layer 105 and etching the first dielectric layer 105 using the patterned mask as a mask. In addition, the etching process used to form the first opening 110 may be a wet etching process, a dry etching process, or a combination thereof.

[0181] Next, according to some embodiments, such as Figure 8 As shown, an energy removable material 113 is conformally formed on the first dielectric layer 105. In some embodiments, the sidewalls and the bottom surface of the first opening 110 are covered by the energy removable material 113. Then, according to some embodiments, Figure 9 As shown, an anisotropic etching process is performed on the energy removable material 113 to vertically remove the same amount of the energy removable material 113 at all locations, leaving an energy removable layer 113 ′ on each sidewall of the first opening 110 .

[0182] In some embodiments, the material of the energy-removable layer 113' includes a base material and a decomposable porogen material, wherein the decomposable porogen material is substantially removed upon exposure to an energy source (i.e., heat). In some embodiments, the base material comprises hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ), porous polyarylether (PAE), porous SiLK, or porous SiO2, and the decomposable porogen material comprises a porogen organic compound, which provides porosity to the space originally occupied by the energy-removable layer 113' in subsequent processing.

[0183] Furthermore, the energy-removable material 113 is deposited by CVD, PVD, ALD, spin coating, or other suitable processes. Furthermore, the anisotropic etching process performed on the energy-removable material 113 may be a dry etching process. According to some embodiments, after the anisotropic etching process, a remaining portion of the first opening 110' is obtained, which is surrounded by the energy-removable layer 113', and the first conductive layer 103 is partially exposed through the remaining portion of the first opening 110'.

[0184] It should be understood that the formation of the energy removable layer 113' is optional. In some embodiments, the energy removable layer 113' is not performed. Figure 8 ) and the deposition process for forming the energy removable layer 113 '( Figure 9 In these examples, the air gap 180 and the energy removable structure 113" are not formed, and the resulting structure can be similar to that in Figure 2 The semiconductor device structure 100b in Figure 4 The semiconductor device structure 200b in FIG.

[0185] Then, according to some embodiments, such as Figure 10 As shown, a liner material 123 is conformally deposited on the first dielectric layer 105. In some embodiments, the sidewalls and the bottom surface of the remaining portion of the first opening 110' are covered by the liner material 113. Then, according to some embodiments, as shown in FIG. Figure 11 As shown, an anisotropic etching process is performed on the liner material 123 to vertically remove the same amount of the liner material 123 at all locations, leaving a liner layer 123 ′ on each sidewall of the energy removable layer 113 ′.

[0186] In some embodiments, the material of the liner layer 123' includes manganese (Mn), such as copper-manganese-silicon (CuMnSi). In some embodiments, the liner material 123 is deposited by a CVD process, a PVD process, an ALD process, a sputtering process, or other applicable processes. In addition, the anisotropic etching process performed on the liner material 123 can be a dry etching process. According to some embodiments, after the anisotropic etching process is performed, a remaining portion of the first opening 110" surrounded by the liner layer 123' is obtained, and the first conductive layer 103 is partially exposed through the remaining portion of the first opening 110".

[0187] According to some embodiments, Figure 12 As shown, after the liner layer 123' is formed, the conductive stud 133 is formed in the remaining portion of the first opening 110". The individual steps are shown in FIG. Figure 5 This is step S15 of method 10. In some embodiments, the conductive stud 133 is surrounded by the liner layer 123'.

[0188] In some embodiments, the conductive studs 133 include copper. In some embodiments, the conductive studs 133 include copper and tungsten (W). Forming the conductive studs 133 may include conformally depositing a conductive material (not shown) on the first dielectric layer 105 to fill the remaining portion of the first opening 110", and performing a planarization process to remove excess portions of the conductive material on the upper surface of the first dielectric layer 105. In some embodiments, the planarization process used to form the conductive studs 133 is a chemical mechanical polishing (CMP) process.

[0189] Then, according to some embodiments, such as Figure 13 As shown, the second conductive layer 143 is formed on the first dielectric layer 105. The individual steps are shown in FIG. Figure 5 10 . In some embodiments, the second conductive layer 143 comprises copper. The processes used to form the second conductive layer 143 are similar or identical to those used to form the first conductive layer 103 , and detailed descriptions thereof are not repeated herein. In some embodiments, the energy-removable layer 113 ′, the liner layer 123 ′, and the conductive studs 133 are covered by the second conductive layer 143 .

[0190] In some embodiments, the second conductive layer 143 and the conductive plugs 133 include the same material and are formed simultaneously. For example, the planarization process does not remove excess conductive material on the upper surface of the first dielectric layer 105, and the conductive material on the upper surface of the first dielectric layer 105 forms the second conductive layer 143 without performing an additional deposition process.

[0191] Next, according to some embodiments, such as Figure 14 As shown, a second dielectric layer 145 is formed on the second conductive layer 143, and an etching process is performed on the second dielectric layer 145 to form a second opening 150, thereby exposing the second conductive layer 143. The individual steps are shown in FIG. Figure 5 The materials and processes used to form the second dielectric layer 145 are similar or identical to those used to form the first dielectric layer 105, and their detailed descriptions are not repeated herein. Furthermore, the fabrication technique for the second opening 150 includes the use of a patterned mask. The processes used to form the second opening 150 are similar or identical to those used to form the first opening 110, and their detailed descriptions are not repeated herein.

[0192] According to some embodiments, Figure 15 As shown, after the second opening 150 is formed, a liner layer 153 is formed on the second dielectric layer 145. In some embodiments, the second opening 150 is lined with the liner layer 153. In particular, according to some embodiments, the upper surface 145T of the second dielectric layer 145, each sidewall 150S of the second opening 150, and the lower surface 150B (refer to FIG. Figure 14 ) is covered by the pad layer 153.

[0193] In some embodiments, the liner layer 153 is a multi-layer structure including a first liner sublayer 155, a second liner sublayer 157, and a third liner sublayer 159. In some embodiments, the first liner sublayer 155 comprises manganese silicon, the second liner sublayer 157 comprises manganese, and the third liner sublayer 159 comprises copper manganese. In some embodiments, the first liner sublayer 155, the second liner sublayer 157, and the third liner sublayer 159 are fabricated using a variety of deposition techniques, such as CVD, PVD, MOCVD, sputtering, and plating. After the liner layer 153 is formed, a remaining portion of the second opening 150' is obtained, which is surrounded by the liner layer 153.

[0194] Then, according to some embodiments, such as Figure 16 As shown, the conductive stud 163 is formed in the remaining portion of the second opening 150'. The individual steps are shown in FIG. Figure 5 This is step S21 of method 10 . In some embodiments, the conductive stud 163 is surrounded by the liner layer 153 .

[0195] In some embodiments, the conductive studs 163 comprise copper. In some embodiments, the conductive studs 163 comprise copper and tungsten. Forming the conductive studs 163 may include conformally depositing a conductive material (not shown) on the liner layer 153 to fill the remaining portion of the second opening 150', and performing a planarization process to remove excess conductive material on the upper surface of the liner layer 153. In some embodiments, the planarization process used to form the conductive studs 163 is a CMP process.

[0196] According to some embodiments, Figure 17 As shown, after the conductive studs 163 are formed, a third conductive layer 173 is formed on the second dielectric layer 145. The individual steps are shown in FIG. Figure 5 10 . In some embodiments, third conductive layer 173 comprises copper. Some processes used for third conductive layer 173 are similar or identical to those used to form first conductive layer 103, and detailed descriptions thereof are not repeated herein. In some embodiments, liner layer 153 and conductive studs 153 are covered by third conductive layer 173. Similar to second conductive layer 143 and conductive studs 133, third conductive layer 173 and conductive studs 163 comprise the same material and can be formed simultaneously.

[0197] Please refer back Figure 1 ,exist Figure 17 A heat treatment process is performed on the structure in order to convert the energy removable layer 113' into the air gap 180. In some embodiments, the air gap 180 is surrounded by the energy removable structure 113", which is the remaining portion of the energy removable layer 113'.

[0198] More specifically, according to some embodiments, a thermal treatment process is used to remove the decomposable porogen material of the energy-removable layer 113' to generate pores. After the decomposable porogen material is removed, the pores are filled with air to form air gaps 180. In some other embodiments, the thermal treatment process may be replaced by a phototreatment process, an electron beam treatment process, a combination thereof, or other applicable energy treatment processes. For example, ultraviolet light (UV light) or laser light may be used to remove the decomposable porogen material of the energy-removable layer 113' to form air gaps 180. After the air gaps 180 are formed, the semiconductor device structure 100a is obtained.

[0199] Figure 18 A cross-sectional view illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage is a step of forming a liner layer 253 on the second dielectric layer 145 during the formation of the improved semiconductor device structure 200a. Figure 18As shown, after the second opening 150 is formed (eg Figure 14 ), a liner layer 253 is formed on the second dielectric layer 145 .

[0200] In some embodiments, the liner layer 253 is a single layer that covers the upper surface 145T of the second dielectric layer 145, the sidewalls 150S and the lower surface 150B of the second opening 150 (see FIG. Figure 14 In some embodiments, the liner layer 253 comprises copper manganese silicon. After the liner layer 253 is formed, a remaining portion of the second opening 250 is obtained, which is surrounded by the liner layer 253.

[0201] Next, the remaining portion of the second opening 250 is filled with the conductive stud 163, and a third conductive layer 173 is formed to cover the liner layer 253 and the conductive stud 163. After the third conductive layer 173 is formed, a heat treatment process is performed to convert the energy removable layer 113' into an air gap 180. In some embodiments, the air gap 180 is surrounded by the energy removable structure 113", and the energy removable structure 113" is the remaining portion of the energy removable layer 113'. After the air gap 180 is formed, Figure 3 An improved semiconductor device structure 200a is provided.

[0202] Figure 19 The cross-sectional view of a semiconductor device structure 300 illustrating some embodiments of the present disclosure includes a pattern-dense region A and a pattern-sparse region B. The semiconductor device structure 300 may be similar to the semiconductor device structure 100 a , and similar element numbers represent similar elements.

[0203] The semiconductor device structure 300 includes a first conductive layer 303, a first dielectric layer 305, a second conductive layer 343, a second dielectric layer 345, and a third conductive layer 373. The first conductive layer 303 is disposed on a semiconductor substrate 301; the first dielectric layer 305 is disposed on the first conductive layer 303; the second conductive layer 343 is disposed on the first dielectric layer 305; the second dielectric layer 345 is disposed on the second conductive layer 343; and the third conductive layer 373 is disposed on the second dielectric layer 345. The detailed description of this embodiment is similar to that of the aforementioned embodiments and will not be repeated herein.

[0204] In the densely populated area A, the semiconductor device structure 300 includes a liner layer 323a (which may be considered a first liner layer) and a conductive stud 333a (which may be considered a first conductive stud) disposed in the first dielectric layer 305, and a liner layer 353 (which may be considered a second liner layer) and a conductive stud 363a (which may be considered a second conductive stud) disposed in the second dielectric layer 345. In some embodiments, the conductive stud 333a is surrounded by the liner layer 323a, and the conductive stud 363a is surrounded by the liner layer 353. Furthermore, the semiconductor device structure 300 includes an energy-removable structure 313' and an air gap 380, and the air gap 380 is surrounded by the energy-removable structure 313' in the densely populated area A.

[0205] In the pattern-sparse region B, the semiconductor device structure 300 includes a liner layer 323b and a conductive stud 333b disposed in the first dielectric layer 305, and a conductive stud 363b (which can be considered a third conductive stud) disposed in the second dielectric layer 345. In some embodiments, the conductive stud 333b is surrounded by the liner layer 323b. It should be understood that the liner layer 353 extends from the pattern-dense region A to the pattern-sparse region B, and the conductive stud 363b is surrounded by the liner layer 353.

[0206] In some embodiments, the liner layer 353 is a multi-layer structure including a first liner sublayer 355 and a second liner sublayer 357, wherein the second liner sublayer 357 is disposed on the first liner sublayer 355. In some embodiments, the first liner sublayer 355 directly contacts the second conductive layer 343 and the second dielectric layer 345. In some embodiments, the second liner sublayer 357 directly contacts the conductive studs 363a and 363b, and the third conductive layer 373. In some embodiments, the conductive studs 363a and 363b are considered a first conductive stud and a second conductive stud, respectively, having different aspect ratios.

[0207] In some embodiments, the first conductive layer 303, the second conductive layer 343, the third conductive layer 373, and the conductive studs 333a, 333b, 363a, and 363b all comprise copper, and the liner layers 323a, 323b, and 353 all comprise manganese. In some other embodiments, the conductive studs 333a, 333b, 363a, and 363b also comprise tungsten. In particular, according to some embodiments, the liner layers 323a and 323b each comprise copper-manganese-silicon, the first liner sublayer 355 of the liner layer 353 comprises manganese-rich manganese-silicon or manganese, and the second liner sublayer 357 of the liner layer 353 comprises copper-manganese.

[0208] Figure 20A flow chart illustrating a method 30 for manufacturing a semiconductor device structure 300 according to some embodiments of the present disclosure is provided. The method 30 includes steps S31 , S33 , S35 , S37 , S39 , S41 and S43 . Figure 20 Steps S31 to S43 are described in detail with reference to the following drawings.

[0209] Figures 21 to 27 Schematic cross-sectional views illustrating various intermediate stages during the formation of a semiconductor device structure 300 according to some embodiments of the present disclosure. Figure 21 As shown, a first conductive layer 303 is formed on a semiconductor substrate 301, and a first dielectric layer 305 is formed on the first conductive layer 303. The individual steps are shown in FIG. Figure 20 Step S31 in the preparation method 30 shown.

[0210] Some of the materials and processes used to form semiconductor substrate 301 are similar or identical to those used to form semiconductor substrate 101, and their detailed descriptions are not repeated herein. The fabrication techniques for first conductive layer 303 and first dielectric layer 305 include a variety of deposition processes, such as CVD, PVD, ALD, sputtering, and spin coating.

[0211] Please still refer to Figure 21 According to some embodiments, the first dielectric layer 301 is etched to form a first opening 310a in the pattern dense area A and a first opening 310b in the pattern sparse area B. In some embodiments, the first openings 310a and 310b both expose a portion of the first conductive layer 303. The respective steps are shown in FIG. Figure 20 The step S33 in the manufacturing method 30 is shown. The etching process for forming the first openings 310a and 310b can be a wet etching process, a dry etching process, or a combination thereof.

[0212] After the first openings 310a and 310b are formed in the first dielectric layer 305, a patterned mask (not shown) may be formed to cover the structure in the pattern sparse region B, and an energy removable material (not shown) may be conformally deposited on the first dielectric layer 305. Then, according to some embodiments, as Figure 22 As shown, an anisotropic etching process may be performed on the energy removable material to vertically remove the same amount of energy removable material everywhere, leaving an energy removable layer 313 on each sidewall of the first opening 310a in the pattern sparse region B.

[0213] After the energy removable layer 313 is formed, a remaining portion of the first opening 310a' is surrounded by the energy removable layer 313. Some materials used to form the energy removable layer 313 may be similar to or the same as those used in the energy removable layer 113' (see Figure 9) material, and its detailed description will not be repeated herein. Furthermore, after performing the anisotropic etching process for forming the energy removable layer 313, the patterned mask used to protect the first opening 310b in the pattern sparse area B can be removed.

[0214] Then, according to some embodiments, such as Figure 23 As shown, the liner layer 323a is formed in the remaining portion of the first opening 310a', and the liner layer 323b is formed in the first opening 310b. The liner layers 323a and 323b may be formed simultaneously.

[0215] In some embodiments, the formation of the liner layers 323a and 323b includes conformally depositing a liner material (not shown) on the first dielectric layer 305 to cover the sidewalls and bottom surfaces of the openings 310a′ and 310b, and performing an anisotropic etching process to vertically remove the same amount of liner material at all locations, leaving the liner layer 323a on the sidewalls of the energy-removable layer 313 in the pattern-dense area A, and leaving the liner layer 323b on the sidewalls of the first opening 310b in the pattern-sparse area B. After the anisotropic etching process, a remaining portion of the first opening 310a″ is surrounded by the liner layer 323a, and a remaining portion of the first opening 310b′ is surrounded by the liner layer 323b.

[0216] like Figure 24 As shown, according to some embodiments, after the liner layers 323a and 323b are formed, the conductive studs 333a are formed in the pattern-dense area A, and the conductive studs 333b are formed in the pattern-sparse area B. In some embodiments, the remaining portions of the first openings 310a' are filled with the conductive studs 333a, and the remaining portions of the first openings 310b' are filled with the conductive studs 333b. The individual steps are shown in FIG. Figure 20 Step S35 in the preparation method 30 shown.

[0217] Conductive studs 333a and 333b can be formed simultaneously. In some embodiments, the formation of conductive studs 333a and 333b includes a deposition process followed by a planarization process. It should be understood that, in some embodiments, the liner layer 323b and conductive studs 333b in the pattern-sparse region B are not surrounded by any energy-removable layer.

[0218] Please still refer to Figure 24 According to some embodiments, a second conductive layer 343 is formed on the first dielectric layer 305. The individual steps are shown in FIG. Figure 20In step S37 of the manufacturing method 30 shown, some materials and processes used to form the second conductive layer 343 are similar to or the same as those used to form the first conductive layer 303 , and their detailed descriptions are not repeated herein.

[0219] Next, if Figure 25 As shown, according to some embodiments, a second dielectric layer 345 is formed on the second conductive layer 343, and the second dielectric layer 345 is etched to form a second opening 350a in the pattern-dense area A and a second opening 350b in the pattern-sparse area B. In some embodiments, the second openings 350a and 350b both expose a portion of the second conductive layer 343. The respective steps are shown in FIG. Figure 20 Step S39 in the preparation method 30 shown.

[0220] Some materials and processes used to form the second dielectric layer 345 are similar to or the same as those used to form the first dielectric layer 305, and their detailed descriptions are not repeated herein. In addition, the etching process used to form the second openings 350a and 350b can be a wet etching process, a dry etching process, or a combination thereof. Figure 25 As shown, the second opening 350a in the pattern-dense area A has a width W3, and the second opening 350b in the pattern-sparse area B has a width W4. It should be understood that according to some embodiments, the width W4 is greater than the width W3.

[0221] like Figure 26 As shown, according to some embodiments, after the second openings 350a and 350b are formed, a first liner sublayer 355 of the liner layer 353 is conformally deposited on the second dielectric layer 345 and covers the sidewalls and bottom surfaces of the second openings 350a and 350b, and a second liner sublayer 357 of the liner layer 353 is conformally deposited on the first liner sublayer 355. The fabrication techniques for the first liner sublayer 355 and the second liner sublayer 357 of the liner layer 353 include a variety of deposition processes, such as CVD, PVD, ALD, MOCVD, sputtering, and plating. After the liner layer 353 is formed, a remaining portion of the second opening 350a' in the densely patterned area A and a remaining portion of the second opening 350b' in the sparsely patterned area B are surrounded by the liner layer 353.

[0222] like Figure 26 As shown, according to some embodiments, the width W2 of the remaining portion of the second opening 350b' is greater than the width W1 of the remaining portion of the second opening 350a'. Furthermore, according to some embodiments, the depth D2 of the remaining portion of the second opening 350b' is greater than the depth D1 of the remaining portion of the second opening 350a'.

[0223] Then, if Figure 27 As shown, according to some embodiments, the conductive studs 363a are formed in the pattern-dense area A, and the conductive studs 363b are formed in the pattern-sparse area B. In some embodiments, the remaining portion of the second opening 350a' is filled with the conductive studs 363a, and the remaining portion of the second opening 350b' is filled with the conductive studs 363b. The individual steps are shown in FIG. Figure 20 Step S41 in method 30 is shown.

[0224] The conductive plugs 363a and 363b may be formed simultaneously. Similar to the conductive plugs 333a and 333b, the formation of the conductive plugs 363a and 363b may include a deposition process followed by a planarization process.

[0225] Please still refer to Figure 27 , a third conductive layer 373 is formed on the second dielectric layer 345. In some embodiments, the liner layer 353 and the conductive studs 363a and 363b are covered by the third conductive layer 373. Some processes used to form the third conductive layer 373 are similar to or the same as those used to form the first conductive layer 303, and their detailed descriptions are not repeated herein. The individual steps are shown in FIG. Figure 20 Step S43 in method 30 is shown.

[0226] In some embodiments, the second opening 350b in the pattern sparse area B is wider than the second opening 350a in the pattern dense area A (refer to FIG. Figure 25 , the width W4 is greater than the width W3). Therefore, after the liner layer 353 is formed, the depth D2 of the remaining portion of the second opening 350b' located in the pattern sparse area B is greater than the depth D1 of the remaining portion of the second opening 350a' located in the pattern dense area A (refer to Figure 26 ). Therefore, if Figure 27 As shown, according to some embodiments, the width W2 of the conductive plug 363b located in the pattern sparse area B is greater than the width W1 of the conductive plug 363a located in the pattern dense area A, and the height H2 of the conductive plug 363b located in the pattern sparse area B is greater than the height H1 of the conductive plug 363a located in the pattern dense area A.

[0227] A thermal treatment process is performed to convert the energy-removable layer 313 into an air gap 380. In some other embodiments, the thermal treatment process may be replaced by a photoprocessing process, an electron beam treatment process, a combination thereof, or other applicable energy treatment processes. In some embodiments, the air gap 380 is surrounded by an energy-removable structure 313', which is the remaining portion of the energy-removable layer 313. After the air gap 380 is formed, the semiconductor device structure 300 is obtained. It should be understood that, according to some embodiments, the liner layer 323b and the conductive plug 333b located in the pattern sparse area B are not surrounded by any air gap.

[0228] Figure 28 A partial block diagram of an exemplary integrated circuit having an array of multiple memory cells 50, such as a memory device 1000, is provided to illustrate some embodiments of the present disclosure. In some embodiments, the memory device 1000 comprises a dynamic random access memory (DRAM) device. In some embodiments, the memory device 1000 comprises multiple memory cells 50 arranged in a grid pattern with multiple rows and columns. The number of memory cells 50 may vary depending on system requirements and fabrication technology.

[0229] In some embodiments, each memory cell 50 has an access element and a storage element. The access element is configured to provide controlled access to the storage element. In particular, according to some embodiments, the access element is a field-effect transistor (FET) 51, and the storage element is a capacitor 53. In each memory cell 50, the FET 51 has a drain 55, a source 57, and a gate 59. One terminal of the capacitor 53 is electrically connected to the source 57 of the FET 51, while the other terminal of the capacitor 53 can be electrically connected to ground. In addition, in each memory cell 50, the gate 59 of the FET 51 is electrically connected to a word line WL, and the drain 55 of the FET 51 is electrically connected to a bit line BL.

[0230] The above description refers to the terminal of FET 51 electrically connected to capacitor 53 as source 57, and the terminal of FET 51 electrically connected to bit line BL as drain 55. However, during read and write operations, the terminal of FET 51 electrically connected to capacitor 53 can be the drain, and the terminal of FET 51 electrically connected to bit line BL can be the source. That is, either terminal of FET 51 can be a source or a drain, depending on how FET 51 is controlled by the voltages applied to the source, drain, and gate.

[0231] By controlling the voltage at gate 59 via word line WL, a voltage potential is generated across field effect transistor 51, causing electrical charge to flow from source 55 to capacitor 53. Thus, the charge stored in capacitor 53 can represent a two-bit data in memory cell 50. For example, a positive charge above a threshold voltage stored in capacitor 53 represents a two-bit "1." If the charge in capacitor 53 is below the threshold, a two-bit "0" is stored in memory cell 50.

[0232] The plurality of bit lines BL are configured to read or write data from and to the plurality of memory cells 50. The plurality of word lines WL are configured to activate field effect transistors 51 to access a specific row of the plurality of memory cells 50. Accordingly, the memory device 1000 also has a peripheral circuit area that may include an address buffer, a row decoder, and a column decoder. The row decoder and the column decoder selectively access the plurality of memory cells 50 in response to a plurality of address signals, and the plurality of address signals are provided to the address buffer during read, write, and refresh operations. The plurality of address signals are typically provided by an external controller, such as a microprocessor or other type of memory controller.

[0233] Please refer back Figure 19, air gaps 380 are formed in the densely patterned region A of the semiconductor device structure 300, while no air gaps are formed in the sparsely patterned region B of the semiconductor device structure 300. Furthermore, conductive studs 363a having a smaller width W1 and a smaller height H1 are formed in the densely patterned region A, while conductive studs 363b having a larger width W2 and a larger height H2 are formed in the sparsely patterned region B. The densely patterned region A may be any region of the plurality of memory cells 50 in the memory device 1000, and the sparsely patterned region B may be any region of the address buffer, column decoder, or row decoder in the memory device 1000.

[0234] The present disclosure provides multiple embodiments of semiconductor device structures 100a, 100b, 200a, 200b, and 300. In some embodiments, each of the semiconductor device structures 100a, 100b, 200a, 200b, and 300 includes a conductive stud and a liner layer. The conductive stud is disposed between two conductive layers that are electrically connected in a vertical direction, and the liner layer surrounds the conductive stud. The conductive stud comprises copper, and the liner layer comprises manganese. The manganese-containing liner layer is configured to reduce or prevent the formation of multiple voids in the conductive stud, thereby reducing the contact resistance of the conductive stud. Consequently, the operating speed of the semiconductor device structures 100a, 100b, 200a, 200b, and 300 can be increased, significantly improving overall device performance.

[0235] One embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes: a first conductive layer disposed on a semiconductor substrate; a second conductive layer disposed on the first conductive layer; a first conductive stud disposed between the first conductive layer and the second conductive layer and electrically connecting the first conductive layer and the second conductive layer, wherein the first conductive stud comprises copper; and a first liner layer disposed around the first conductive stud, wherein the first liner layer comprises manganese.

[0236] Another embodiment of the present disclosure provides a semiconductor device structure, comprising: a first conductive layer disposed on a semiconductor substrate; a first dielectric layer disposed on the first conductive layer; a second conductive layer disposed on the first dielectric layer; a second dielectric layer disposed on the second conductive layer; a third conductive layer disposed on the second dielectric layer; a first conductive stud passing through the first dielectric layer and electrically connecting the first conductive layer to the second conductive layer, wherein the first conductive stud comprises copper; a first liner layer disposed between the first conductive stud and the first dielectric layer, wherein the first liner layer comprises manganese; a second conductive stud disposed in the second dielectric layer, wherein the second conductive stud electrically connects the second conductive layer to the third conductive layer, and wherein the second conductive stud comprises copper; and a second liner layer disposed between the second conductive stud and the second dielectric layer, wherein the second liner layer comprises manganese.

[0237] Another embodiment of the present disclosure provides a method for fabricating a semiconductor device structure, comprising: forming a first conductive layer on a semiconductor substrate, wherein the first conductive layer comprises copper; forming a first dielectric layer on the first conductive layer; etching the first dielectric layer to form a first opening, thereby exposing the first conductive layer; forming a first liner layer and a first conductive liner in the first opening, wherein the first liner layer comprises manganese, the first conductive stud comprises copper, and the first conductive stud is surrounded by the first liner layer; and forming a second conductive layer on the first dielectric layer, on the first liner layer, and on the first conductive layer, wherein the second conductive layer comprises copper.

[0238] The various embodiments disclosed herein have several advantages. By forming a manganese-containing liner layer, the resistance of the conductive studs surrounded by the manganese-containing liner layer can be reduced. Consequently, the operating speed of the semiconductor device structure can be increased, significantly improving overall device performance.

[0239] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes can be implemented in different ways, and many of the above processes can be replaced by other processes or combinations thereof.

[0240] Furthermore, the scope of the present invention is not limited to the specific embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future developed processes, machines, manufacture, compositions of matter, means, methods, or steps that function the same as or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps are intended to be encompassed by the claims of the present invention.

Claims

1. A semiconductor device structure comprising: a first conductive layer disposed on a semiconductor substrate; a second conductive layer disposed on the first conductive layer; a first conductive stud disposed between the first conductive layer and the second conductive layer and electrically connecting the first conductive layer and the second conductive layer, wherein the first conductive stud comprises copper; and a first liner layer disposed around the first conductive stud, wherein the first liner layer comprises manganese; a third conductive layer disposed on the second conductive layer; a second conductive stud disposed between the second conductive layer and the third conductive layer and electrically connecting the second conductive layer and the third conductive layer, wherein the second conductive stud comprises copper; and a second liner layer disposed around the second conductive stud, wherein a portion of the second liner layer is sandwiched between the second conductive stud and the second conductive layer; and The second liner layer comprises: a first liner sublayer disposed on the second conductive layer and directly contacting the second conductive layer, wherein the first liner sublayer comprises manganese silicon; a second liner sublayer disposed on the first liner sublayer, wherein the second liner sublayer comprises manganese; and A third liner sublayer is disposed on the second liner sublayer, wherein the third liner sublayer directly contacts the second conductive stud, and wherein the third liner sublayer comprises copper-manganese. 2 . The semiconductor device structure as claimed in claim 1 , wherein the first conductive layer and the second conductive layer both comprise copper, and the first conductive plug further comprises tungsten. The semiconductor device structure as claimed in claim 1 , wherein the first liner layer comprises copper manganese silicon. 4 . The semiconductor device structure as claimed in claim 1 , further comprising a first dielectric layer and an air gap, wherein the first dielectric layer is disposed around the first liner layer, and the air gap is located between the first liner layer and the first dielectric layer. The semiconductor device structure as claimed in claim 1 , wherein the second liner layer comprises copper manganese silicon.

6. A semiconductor device structure comprising: a first conductive layer disposed on a semiconductor substrate; a first dielectric layer disposed on the first conductive layer; a second conductive layer disposed on the first dielectric layer; a second dielectric layer disposed on the second conductive layer; a third conductive layer disposed on the second dielectric layer; a first conductive stud passing through the first dielectric layer and electrically connecting the first conductive layer to the second conductive layer, wherein the first conductive stud comprises copper; a first liner layer disposed between the first conductive stud and the first dielectric layer, wherein the first liner layer comprises manganese; a second conductive stud disposed in the second dielectric layer, wherein the second conductive stud electrically connects the second conductive layer to the third conductive layer, and wherein the second conductive stud comprises copper; and a second liner layer disposed between the second conductive stud and the second dielectric layer, wherein the second liner layer comprises manganese; a third conductive stud disposed in the second dielectric layer and in a sparsely patterned region, wherein the third conductive stud electrically connects the second conductive layer to the third conductive layer, and the third conductive stud comprises copper; and The third conductive stud is separated from the second dielectric layer by the second liner layer, and a height of the third conductive stud is greater than a height of the second conductive stud. 7 . The semiconductor device structure as claimed in claim 6 , wherein one of the first conductive stud and the second conductive stud further comprises tungsten. 8 . The semiconductor device structure as claimed in claim 6 , wherein the first conductive stud and the second conductive stud are disposed in a pattern-dense area, and an air gap is disposed between the first liner layer and the first dielectric layer. 9 . The semiconductor device structure as claimed in claim 6 , wherein a width of the third conductive stud is greater than a width of the second conductive stud.

10. The semiconductor device structure according to claim 6, wherein the second liner layer comprises: a first liner sublayer disposed on the second conductive layer and directly contacting the second conductive layer, wherein the first liner sublayer comprises manganese or manganese silicon; as well as A second liner sublayer is disposed on the first liner sublayer, wherein the second liner sublayer directly contacts the second conductive stud, the third conductive stud and the third conductive layer, and wherein the second liner sublayer contains copper and manganese.

11. A method for preparing a semiconductor device structure, comprising: forming a first conductive layer on a semiconductor substrate, wherein the first conductive layer comprises copper; forming a first dielectric layer on the first conductive layer; Etching the first dielectric layer to form a first opening, thereby exposing the first conductive layer; forming a first liner layer and a first conductive liner in the first opening, wherein the first liner layer comprises manganese, the first conductive stud comprises copper, and the first conductive stud is surrounded by the first liner layer; and forming a second conductive layer on the first dielectric layer, on the first liner layer, and on the first conductive layer, wherein the second conductive layer comprises copper; Before the first liner layer and the first conductive stud are formed, an energy removable layer is formed to line the first opening. After the energy removable layer is formed, the first conductive layer is partially exposed. 12 . The method for fabricating a semiconductor device structure as claimed in claim 11 , further comprising performing a thermal treatment process to transform the energy removable layer into an air gap after forming the second conductive layer.

13. The method for preparing a semiconductor device structure according to claim 11, further comprising: forming a second dielectric layer on the second conductive layer; Etching the second dielectric layer to form a second opening, thereby exposing the second conductive layer; forming a second liner layer and a second conductive stud in the second opening, wherein the second conductive stud is surrounded by the second liner layer, the second liner layer comprises manganese, and the second conductive stud comprises copper; and A third conductive layer is formed to cover the second liner layer and the second conductive stud. 14 . The method for fabricating a semiconductor device structure as claimed in claim 13 , wherein the first conductive plug and the second conductive plug further comprise tungsten. 15 . The method for fabricating a semiconductor device structure as claimed in claim 13 , wherein the third conductive layer is separated from the second dielectric layer by the second liner layer, and a portion of the second liner layer is sandwiched between the second conductive stud and the second conductive layer.

16. The method for fabricating a semiconductor device structure according to claim 13, wherein forming the second liner layer comprises: forming a first liner sublayer on an upper surface of the second dielectric layer, wherein each sidewall and a lower surface of the second opening are covered by the first liner sublayer, and wherein the first liner sublayer comprises manganese silicon; forming a second liner sublayer on the first liner sublayer, wherein the second liner sublayer comprises manganese; as well as A third liner sublayer is formed on the second liner sublayer, wherein the third liner sublayer comprises copper and manganese.

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