A Shield-Gate Trench MOSFET Structure for Optimizing the Terminal Electric Field and Its Manufacturing Method

Abstract

The present invention discloses a shielded-gate trench MOSFET structure capable of optimizing the terminal electric field and a manufacturing method thereof. The structure includes two epitaxial layers with low resistance and high resistance, and the high-resistance epitaxial layer is placed in the lower layer. The structure includes an active region and a terminal region divided by the epitaxial layer. An active region trench is arranged in the active region, and at least five terminal region trenches close to the active region trench in the terminal region are isolation rings, and at least one terminal region trench close to the dicing slot is a cutoff ring; a low-doped polysilicon layer deposited in the isolation ring is floating, and the cutoff ring is short-circuited with the cutoff ring metal and is floating. And a certain energy and dose of implantation opposite to the epitaxial type are performed at the bottom of the trenches in the terminal isolation region and the cutoff region to form an inversion layer. The present invention can better extend the depletion line, increase the curvature radius, reduce the electric field concentration, and finally achieve the effect of improving the terminal breakdown voltage, without increasing the process difficulty and reducing the production cost of the mask plate.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor power devices, and in particular relates to a shielded gate trench MOSFET structure capable of optimizing a terminal electric field and a manufacturing method thereof. Background Art

[0002] For traditional shielded gate trench power MOSFET devices, the mainstream process can already achieve 100~150V. However, structures above 150V require a process solution that etches a trench larger than 9um and grows an oxide layer larger than 1um in the deep trench. Most foundry processes and equipment are no longer able to meet this requirement. In order to reduce the difficulty of process technology, it is necessary to use double-layer or multi-layer epitaxy on voltage platforms less than 150V and lower to increase the breakdown voltage. However, the original ordinary shielded gate trench terminal cannot meet this requirement. The higher the device voltage, the greater the voltage drop below the trench, and the more concentrated the terminal electric field. Fig.16 , which makes the actual terminal breakdown voltage relatively low, which in turn leads to problems such as avalanche withstand abnormality, making the development and stable mass production of 150V300V shielded gate trench devices face huge challenges.

[0003] In addition to the good electrical performance parameters of the device itself, the market competitiveness of the device also requires a stable terminal window to cover the parameter and yield losses caused by process fluctuations.

[0004] During the manufacturing of shielded gate trench MOSFETs below 150V, the terminal design usually uses multiple trenches of equal width and spacing as terminal field rings, supplemented by bottom implantation with appropriate dose energy. This design may require multiple implantations, and it is cumbersome to find the optimal implantation and well-pushing design. Summary of the invention

[0005] In view of this, the main object of the present invention is to provide a shielded gate trench MOSFET structure capable of optimizing the terminal electric field and a manufacturing method thereof.

[0006] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0007] A shielded gate trench MOSFET structure capable of optimizing the terminal electric field comprises two layers of epitaxy, low resistance and high resistance, the high resistance epitaxy is placed in the lower layer, the structure comprises an active area and a terminal area divided by the epitaxial layer, an active area trench is arranged in the active area, and at least six terminal area trenches surrounding the active area trench are arranged in the terminal area, wherein at least five terminal area trenches close to the active area trenches are isolation rings, and the widths of the isolation ring trenches are inconsistent, and at least one terminal area trench close to the scribe groove is a cut-off ring; a low-doped polysilicon layer is deposited in the isolation ring and is floating, and the cut-off ring is short-circuited with the cut-off ring metal and is floating. In addition, a certain energy and dosage opposite to the epitaxy type are implanted at the bottom of the trenches in the terminal isolation area and the cut-off area to form an inversion layer.

[0008] The spacing between the trenches in the terminal area is 0.7um or more.

[0009] The spacings between the grooves in the preferred terminal area are mostly unequal.

[0010] The distance between the two grooves of the isolation ring and the cut-off ring close to each other is 5um or more.

[0011] The width of the termination region trench is equal to or greater than the width of the active region trench.

[0012] The widths of the trenches in the termination area are not uniform, and the widths have various arrangements.

[0013] The bottoms of the trenches with different widths in the terminal area have implanted inversion layers of different sizes.

[0014] A method for manufacturing a shielded gate trench MOSFET structure capable of optimizing a terminal electric field is implemented by the following steps:

[0015] Step 1: providing an n+ substrate heavily doped with n-type, and forming two n-type epitaxial layers of high resistance and low resistance on the n+ substrate;

[0016] Step 2: forming deep trenches on the n-type epitaxy by photolithography and dry etching, wherein the deep trenches include active area deep trenches and terminal area deep trenches, wherein the terminal area deep trenches surround the active area deep trenches, and retaining a hard mask;

[0017] Step 3: Perform bottom implantation on the deep trench in the terminal area through photolithography and implantation, and remove the photoresist and hard mask;

[0018] Step 4: growing a field oxide layer at the bottom and sidewalls of the deep trench by a wet thermal oxidation process;

[0019] Step 5: Perform the first highly doped source polysilicon deposition by a polysilicon deposition process; perform polysilicon back etching by a dry etching process until the polysilicon is flush with the upper surface of the epitaxial layer;

[0020] Step 6: Completely etch the polysilicon in the terminal area trench by photolithography and isotropic etching process;

[0021] Step 7: performing a second low-doped polysilicon deposition process through a polysilicon deposition process; performing polysilicon back etching through a dry etching process until the polysilicon is flush with the upper surface of the epitaxial layer;

[0022] Step 8: removing the surface field oxide layer by dry and wet etching process;

[0023] Step nine: growing a gate oxide layer through a dry thermal oxidation process to form a MOSFET device gate oxide;

[0024] Step 10: deposit polysilicon for the third time and etch it back into the trench to form a shallow trench MOSFET device gate;

[0025] Step 11: P-BODY injection to form a P well;

[0026] Step 12: N+ implantation to form the device source;

[0027] Step 13: dielectric layer deposition, contact hole lithography and hole etching; complete contact hole tungsten filling, and surface metal process to form the device front structure; finally, complete the back metal process to form the device drain terminal and complete the low-voltage super junction MOSFET terminal structure.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] The present invention can achieve a better terminal by using 6 mask layers. The electric field can pass through the low-doped polysilicon, which can better extend the depletion line, increase the radius of curvature, and reduce the electric field concentration, thereby ultimately achieving the effect of improving the terminal breakdown voltage, so that the shielded gate trench MOSFET can be developed to more than 150V with high yield and stable parameters, and can be implemented using traditional semiconductor manufacturing processes without increasing the difficulty of the process. In addition, the same set of masks can be used for 155~300V to derive new resistance and voltage products, thereby reducing the production cost of the mask. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a cross-sectional view of the device of the present invention.

[0031] Figure 2 This is a schematic diagram of step one of the present invention.

[0032] Figure 3 It is a schematic diagram of step 2 of the present invention.

[0033] Figure 4 It is a schematic diagram of step three of the present invention.

[0034] Figure 5 It is a schematic diagram of step four of the present invention.

[0035] Figure 6 It is a schematic diagram of step five of the present invention.

[0036] Figure 7 This is a schematic diagram of step six of the present invention.

[0037] Figure 8 It is a schematic diagram of step seven of the present invention.

[0038] Fig. 9 It is a schematic diagram of step eight of the present invention.

[0039] Fig.10 It is a schematic diagram of step nine of the present invention.

[0040] Fig.11 This is a schematic diagram of step ten of the present invention.

[0041] Fig.12 This is a schematic diagram of step eleven of the present invention.

[0042] Fig.13 This is a schematic diagram of step twelve of the present invention.

[0043] Fig.14 It is a schematic diagram of the depletion line when the drain of the complete structure of the present invention is broken down.

[0044] Fig.15 This is a schematic diagram of the depletion line when the drain of the more optimized structure of the present invention is broken down.

[0045] Fig.16 Schematic diagram of the depletion line when the drain of the non-optimized structure breaks down. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0047] The embodiment of the present invention provides a shielded gate trench MOSFET structure capable of optimizing the terminal electric field, wherein the terminal comprises two layers of epitaxy, low resistance and high resistance, the high resistance epitaxy is placed in the lower layer, the structure comprises an active area and a terminal area divided by the epitaxial layer, an active area trench is arranged in the active area, and at least six terminal area trenches surrounding the active area trench are arranged in the terminal area, wherein at least five terminal area trenches close to the active area trenches are isolation rings, and the widths of the isolation ring trenches are inconsistent, and at least one terminal area trench close to the scribe groove is a cut-off ring; the low-doped polysilicon layer deposited in the isolation ring is floating, and the cut-off ring is short-circuited with the cut-off ring metal and is floating. In addition, a certain energy and dosage opposite to the epitaxial type are implanted at the bottom of the trenches in the terminal isolation area and the cut-off area to form an inversion layer. The present invention optimizes the filling material in the terminal trench under the premise of minimizing the number of mask layers and not increasing the process difficulty. If the trench etching process can achieve a larger width and a deeper depth, it is better, and combined with the trench bottom injection, the terminal electric field can be optimized in the complete structure and the terminal voltage can be increased. Fig.15 .

[0048] Considering the process implementation problem, as a preferred solution of the present invention:

[0049] The spacing between the active area trenches is 0.75um or more;

[0050] The active area trench width is 2.0um or more;

[0051] The spacing between the grooves in the terminal area is less than 0.50um; less than 0.65um; less than 0.75um, less than 0.75um, and greater than 0.75um;

[0052] The widths of the terminal area grooves are respectively greater than 2.4 um; greater than 2.2 um; greater than 2.2 um; greater than 2.0 um; greater than 2.0 um; greater than 2.0 um;

[0053] The distance between the two grooves of the isolation ring and the cut-off ring close to each other is 5um or more;

[0054] The embodiment of the present invention provides a method for manufacturing a shielded gate trench MOSFET structure capable of optimizing the terminal electric field, such as Figure 1-11 As shown, the method is implemented by the following steps:

[0055] Step 1: Provide an n+ substrate with heavy n-type doping, and form two n-type epitaxial layers with high resistance and low resistance on the n+ substrate, such as Figure 2 As shown;

[0056] Step 2: forming deep trenches on the n-type epitaxy by photolithography and dry etching, wherein the deep trenches include active area deep trenches and terminal area deep trenches, wherein the terminal area deep trenches surround the active area deep trenches, and retaining the hard mask, such as Figure 3 As shown;

[0057] Step 3: Perform bottom implantation on the deep trench in the terminal area through photolithography and implantation, and remove the photoresist and hard mask, such as Figure 4 As shown;

[0058] Step 4: grow a field oxide layer at the bottom and sidewalls of the deep trench by a wet thermal oxidation process, and activate the trench bottom implantation, such as Figure 5 As shown;

[0059] Step 5: Perform the first highly doped source polysilicon deposition through a polysilicon deposition process; perform polysilicon back etching through a dry etching process until the polysilicon is flush with the upper surface of the epitaxial layer, such as Figure 6 As shown;

[0060] Step 6: Completely etch the polysilicon in the terminal area trench by photolithography and isotropic etching process, such as Figure 7 As shown;

[0061] Step 7: Perform a second low-doped polysilicon deposition process through a polysilicon deposition process; perform polysilicon back etching through a dry etching process until the polysilicon is flush with the upper surface of the epitaxial layer, such as Figure 8 As shown;

[0062] Step 8: Remove the surface field oxide layer by dry and wet etching process, such as Fig. 9 As shown;

[0063] Step 9: Grow the gate oxide layer through dry thermal oxidation process to form the gate oxide of MOSFET device, such as Fig.10 As shown;

[0064] Step 10: The third polysilicon deposition is carried out and then etched back into the trench to form a shallow trench MOSFET device gate. Fig.11 As shown;

[0065] Step 11: P-BODY injection to form a P well, such as Fig.12 As shown;

[0066] Step 12: N+ implantation to form the device source, such as Fig.13 As shown;

[0067] Step 13: dielectric layer deposition, contact hole lithography and hole etching; complete contact hole tungsten filling, and surface metal process to form the device front structure; finally complete the back metal process to form the device drain terminal and complete the low voltage super junction MOSFET terminal structure, such as Figure 1shown.

[0068] The trench terminal structure and manufacturing method of the power MOSFET described in the present invention optimizes the filling material in the terminal trench under the premise of minimizing the number of mask layers and not increasing the process difficulty. If the trench etching process can achieve a larger width and a deeper depth, it is better, and combined with the bottom injection of the trench, the terminal electric field can be optimized in the complete structure, the terminal voltage can be increased, and the development difficulty of 155V~300V can be greatly reduced. And it makes it possible for 155~300V to use the same set of masks to derive new resistance and voltage products, reducing the production cost of the mask.

[0069] The step 2 is specifically as follows:

[0070] Solution 1: The trench dry etching atmosphere is not optimized, and the depth of all trenches of different widths is consistent, such as Fig.14 ;

[0071] Solution 2: Optimize the trench dry etching atmosphere, wide trenches form deep trenches, and narrow trenches form normal depth trenches, such as Fig.15 .

[0072] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention.

Claims

1. A manufacturing method of a shielded-gate trench MOSFET structure capable of optimizing the terminal electric field, characterized in that, this method is implemented through the following steps: Step 1: Provide an n+-type substrate with heavy n-type doping, and form two epitaxial layers with high resistance and low resistance of n-type on the n+-type substrate; Step 2: Form deep trenches on the n-type epitaxy through photolithography and dry etching. The deep trenches include active region deep trenches and terminal region deep trenches. The terminal region deep trenches surround the active region deep trenches. In the terminal region deep trenches, the terminal region deep trenches close to the active region deep trenches are isolation ring trenches, and the terminal region deep trenches close to the dicing slot are cutoff ring trenches, and the hard mask plate is reserved; Step 3: Through photolithography and implantation, perform bottom implantation on the deep trenches in the terminal region, and remove the photoresist and the hard mask plate; Step 4: Grow a field oxide layer on the bottom and side walls of the deep trenches through a wet thermal oxidation process; Step 5: Perform the first high-doped source polysilicon deposition through a polysilicon deposition process; perform polysilicon back-etching through a dry etching process, and etch until the polysilicon is flush with the upper surface of the epitaxial layer; Step 6: Completely etch the polysilicon in the isolation ring trenches through photolithography and isotropic etching processes; Step 7: Perform the second low-doped polysilicon deposition through a polysilicon deposition process; perform polysilicon back-etching through a dry etching process, and etch until the polysilicon is flush with the upper surface of the epitaxial layer; Step 8: Remove the surface field oxide layer through a dry and wet etching process; Step 9: Grow a gate oxide layer through a dry thermal oxidation process to form the gate oxide of the MOSFET device; Step 10: Perform the third polysilicon deposition and back-etch it into the trenches to form the gate of the shallow trench MOSFET device; Step 11: Perform P-BODY implantation to form a P-well; Step 12: Perform N+ implantation to form the source of the device; Step 13: Deposit a dielectric layer, perform contact hole photolithography and hole etching; Complete the tungsten filling of the contact holes and the surface metal process to form the front structure of the device; finally complete the back metal process to form the drain end of the device, and complete the low-voltage superjunction MOSFET terminal structure.

2. A shielded-gate trench MOSFET structure capable of optimizing the terminal electric field prepared by the manufacturing method according to claim 1, characterized in that: It includes two epitaxial layers of low resistance and high resistance, and the high-resistance epitaxy is placed in the lower layer. The structure includes an active region and a terminal region divided by the epitaxial layer. Active region trenches are arranged in the active region, and there are at least six terminal region trenches in the terminal region and surrounding the active region trenches. Among them, at least five terminal region trenches close to the active region trenches are isolation rings, and the widths of the isolation ring trenches are inconsistent. At least one terminal region trench close to the dicing slot is a cutoff ring; the low-doped polysilicon layer deposited in the isolation ring is floating, and the cutoff ring is short-circuited with the cutoff ring metal and floating; and an inversion layer is formed by injecting a certain energy and dose opposite to the epitaxial type at the bottom of the isolation ring trench.

3. A shielded-gate trench MOSFET structure capable of optimizing the terminal electric field according to claim 2, characterized in that: The distance between the terminal region trenches is 0.7 μm or more.

4. A shielded-gate trench MOSFET structure capable of optimizing the terminal electric field according to claim 3, characterized in that: the spacings between the trenches in the terminal region are mostly arranged unevenly.

5. A shielded-gate trench MOSFET structure capable of optimizing the terminal electric field according to claim 4, characterized in that: the spacing between two trenches where the isolation ring and the cutoff ring are close to each other is 5 μm or more.

6. A shielded-gate trench MOSFET structure capable of optimizing the terminal electric field according to claim 4, characterized in that: the width of the trenches in the terminal region is equal to or greater than the width of the trenches in the active region.

7. A shielded-gate trench MOSFET structure capable of optimizing the terminal electric field according to claim 6, characterized in that: the widths of the trenches in the terminal region are inconsistent and there are multiple arrangements of the widths.

8. A shielded-gate trench MOSFET structure capable of optimizing the terminal electric field according to claim 7, characterized in that: inversion layers with different sizes are implanted at the bottoms of the trenches with different widths in the terminal region.

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