Buck-boost converter and hybrid control method

Abstract

An apparatus comprising: a buck converter portion of a buck-boost converter configured to operate under a constant on-time control scheme, wherein an on-time of a high-side switch of the buck converter portion is determined by a buck on-time timer; and a boost converter portion of the buck-boost converter configured to operate under a constant off-time control scheme, wherein an off-time of a low-side switch of the boost converter portion is determined by a boost off-time timer.

Description

Technical Field

[0001] This invention relates to control schemes for power converters, and in certain embodiments, to power converters employing a hybrid control scheme with a constant switching frequency under various operating conditions. Background Technology

[0002] With further technological advancements, various electronic devices, such as mobile phones, tablet PCs, digital cameras, MP3 players, and / or similar devices, have become ubiquitous. Each electronic device requires DC power at a substantially constant voltage, which can be regulated within specified tolerances even when the current drawn by the device varies over a wide range. To maintain the voltage within these tolerances, power converters coupled to the electronic devices (e.g., switching DC / DC converters) provide very fast transient response while maintaining a stable output voltage under various load transients.

[0003] Hysteresis-based power converter control schemes, such as constant on-time or constant off-time schemes, enable the power converter to provide fast transient response. A power converter employing a constant on-time control scheme may consist only of a feedback comparator and a turn-on timer. In operation, the power converter's feedback circuit directly compares the feedback signal with an internal reference. When the feedback signal drops below the internal reference, the high-side switch of the power converter opens and remains on for the duration of the turn-on timer. As a result of opening the high-side switch, the inductor current of the power converter increases. When the turn-on timer expires, the high-side switch of the power converter closes and remains on until the feedback signal drops below the internal reference again. In summary, when using a constant on-time control scheme in a power converter, the on-time of the high-side switch is terminated by the turn-on timer, and the off-time of the high-side switch is terminated by the feedback comparator.

[0004] As electronic devices become increasingly portable and mobile, many rely on rechargeable batteries for their power. However, due to the characteristics of rechargeable batteries, the output voltage of a battery pack can vary widely between a fully charged and a completely depleted state. Furthermore, with the emergence of Type-C Universal Serial Bus (USB) as a new standard for charging and data transfer, the output voltage of a USB port is no longer fixed (e.g., 5V). Instead, the output voltage can vary widely from approximately 3.5V to approximately 20V. Meanwhile, downstream power converters connected to newer USB ports (e.g., Type-C USB) may still require a voltage approximately equal to 5V. In response to this wide input voltage range, four-switch buck-boost converters have become commonplace for Type-C USB applications.

[0005] In a conventional four-switch buck-boost converter, all four switches are turned on and off once per switching cycle. Furthermore, energy from the input power supply is never directly transferred to the output of the four-switch buck-boost converter. Instead, the energy from the input power supply is first stored in the inductor of the buck-boost converter before being transferred to the output. Therefore, conventional four-switch buck-boost converters are not very efficient.

[0006] It is desirable to provide devices and / or methods for enabling a conventional four-switch buck-boost converter employing a combination of constant on-time control and constant off-time control to operate in buck mode, boost mode, and buck-boost mode at different input voltages. Furthermore, it is desirable to have a smooth transition between any two of the above operating modes in response to changes in input voltage. Summary of the Invention

[0007] In a particular embodiment, a control scheme can achieve fast transient response and improve the performance of a four-switch buck-boost converter under various operating conditions.

[0008] According to one embodiment, an apparatus includes: a buck converter portion of a buck-boost converter configured to operate under a constant on-time control scheme, wherein the on-time of the high-side switch of the buck converter portion is determined by a buck on-time timer; and a boost converter portion of a buck-boost converter configured to operate under a constant off-time control scheme, wherein the off-time of the low-side switch of the boost converter portion is determined by a boost off-time timer.

[0009] According to another embodiment, a method includes: applying a constant on-time control scheme to the buck converter section of a buck-boost converter, wherein the on-time of the high-side switch of the buck converter section is determined by a buck on-time timer under the constant on-time control scheme; and applying a constant off-time control scheme to the boost converter section of a buck-boost converter, wherein the off-time of the low-side switch of the boost converter section is determined by a boost off-time timer under the constant off-time control scheme.

[0010] According to yet another embodiment, a controller includes: a first timer for setting the on-time of a first high-side switch of a buck-boost converter, wherein the on-time of the first high-side switch is determined by the input voltage of the buck-boost converter and the output voltage of the buck-boost converter; a second timer for setting the off-time of a second low-side switch of the buck-boost converter, wherein the off-time of the second low-side switch is determined by the input voltage of the buck-boost converter and the output voltage of the buck-boost converter; and a current-mode control device for setting the on-time of the first low-side switch and the off-time of the second high-side switch of the buck-boost converter.

[0011] The advantages of the preferred embodiments of this disclosure are improved performance of the buck-boost power converter. More specifically, the control mechanism of the buck-boost converter is based on a combination of a constant on-time control scheme and a constant off-time control scheme. The buck converter section of the buck-boost converter is configured to operate under the constant on-time control scheme. The boost converter section of the buck-boost converter is configured to operate under the constant off-time control mode. Furthermore, a combination of a valley current mode (VCM) control scheme and a peak current mode (PCM) control scheme is applied to the buck-boost power converter. Specifically, the VCM control scheme is used to terminate the on-time of the low-side switch of the buck converter section of the buck-boost converter. The PCM control scheme is used to terminate the on-time of the low-side switch of the boost converter section of the buck-boost converter.

[0012] The combination of constant on-time and constant off-time control schemes eliminates the need for a fixed clock signal. Furthermore, this combination allows for automatic transition from pulse width modulation (PWM) mode to pulse frequency modulation (PFM) mode. It also eliminates the slope compensation required for current-mode control. The combination of constant on-time and constant off-time control schemes significantly simplifies the control circuitry and associated current consumption. By combining VCM and PCM control, the bipolar output response formed by the inductor and output capacitor can be reduced to a unipolar response, thus greatly simplifying the control loop compensation design.

[0013] The features and technical advantages of the invention have been broadly outlined above to facilitate a better understanding of the following detailed description. Additional features and advantages of the invention, which form the subject matter of the claims, will be described below. Those skilled in the art will understand that the disclosed concepts and specific embodiments can be readily utilized as the basis for modifications or the design of other structures or processes to achieve the same purpose as the invention. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. Attached Figure Description

[0014] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, wherein:

[0015] Figure 1 A schematic diagram of a buck-boost converter and its associated hybrid control circuitry according to various embodiments of the present disclosure is shown.

[0016] Figure 2 Schematic diagrams of buck turn-on time timer and boost turn-off time timer according to various embodiments of the present disclosure are shown;

[0017] Figure 3 Various embodiments according to this disclosure are shown. Figure 1 The timing diagram shown above is associated with the buck operation mode of the buck-boost converter.

[0018] Figure 4 Various embodiments according to this disclosure are shown. Figure 1 The timing diagram shown above is associated with the buck-boost operation mode of the buck-boost converter; and

[0019] Figure 5 Various embodiments according to this disclosure are shown. Figure 1 The timing diagram shown is associated with the boost operation mode of the buck-boost converter.

[0020] Unless otherwise indicated, corresponding numbers and symbols in different figures generally refer to corresponding parts. The accompanying drawings are provided to clearly illustrate relevant aspects of various embodiments and are not necessarily drawn to scale. Detailed Implementation

[0021] The following describes in detail the making and use of the presently preferred embodiments. However, it should be understood that the present invention provides many applicable inventive concepts that can be implemented in a wide variety of specific situations. The specific embodiments described are merely illustrative of particular ways of making and using this disclosure and are not intended to limit the scope of this disclosure.

[0022] This disclosure will be described with reference to preferred embodiments in a specific context, namely, a hybrid control scheme applied to a buck-boost converter. This hybrid control scheme includes a constant on-time control scheme and a constant off-time control scheme. The constant on-time control scheme is applied to the buck converter portion of the buck-boost converter. The constant off-time control scheme is applied to the boost converter portion of the buck-boost converter. Under this hybrid control scheme, the buck-boost converter is configured to operate at a fixed or nearly fixed switching frequency under various operating conditions. Furthermore, under this hybrid control scheme, the buck-boost converter can have a smooth and autonomous transition between buck operating mode and boost operating mode. However, the invention is also applicable to various power converters. Various embodiments will be explained in detail below with reference to the accompanying drawings.

[0023] Figure 1 Schematic diagrams of buck-boost converters and their associated hybrid control circuitry according to various embodiments of the present disclosure are shown. Figure 1As shown, the buck-boost converter includes a first high-side switch Q1 (102), a first low-side switch Q2 (103), a second low-side switch Q3 (106), a second high-side switch Q4 (105), and an inductor 104. The first high-side switch Q1 and the first low-side switch Q2 are connected in series between the positive and negative terminals of the input capacitor 101. The input capacitor 101 is connected to the power supply VIN. The input capacitor 101 is used to provide a stable voltage for the buck-boost converter.

[0024] The second high-side switch Q4 and the second low-side switch Q3 are connected in series between the positive and negative terminals of the output capacitor 107. The inductor 104 is coupled between the common node of the first high-side switch Q1 and the first low-side switch Q2 and the common node of the second high-side switch Q4 and the second low-side switch Q3.

[0025] The buck-boost converter can be divided into two parts: a buck converter section and a boost converter section. The buck converter section may include a first high-side switch Q1 and a first low-side switch Q2. The buck converter section and inductor 104 can function as a buck converter. Conversely, the boost converter section may include a second high-side switch Q4 and a second low-side switch Q3. The boost converter section and inductor 104 can function as a boost converter. The buck converter section, inductor 104, and boost converter section are cascaded between input capacitor 101 and output capacitor 107.

[0026] Both the buck converter section and the boost converter section of the buck-boost converter are controlled by a hybrid control circuit. More specifically, the hybrid control circuit includes a constant on-time control circuit and a constant off-time control circuit. The constant on-time control circuit is configured to apply a constant on-time control scheme to the buck converter section of the buck-boost converter. The constant off-time control circuit is configured to apply a constant off-time control scheme to the boost converter section of the buck-boost converter.

[0027] like Figure 1 As shown, the hybrid control circuit includes an amplifier 118, a current comparator 114, a buck on-time timer 130, a boost off-time timer 140, a first latch 111, a second latch 119, a buck control logic unit 110, and a boost control logic unit 112. In some embodiments, the buck on-time timer 130 acts as a constant on-time control circuit. The buck on-time timer 130 is used to determine the on-time of the first high-side switch Q1. The boost off-time timer 140 acts as a constant off-time control circuit. The boost off-time timer 140 is used to determine the off-time of the second low-side switch Q3.

[0028] The output (CMPB) of current comparator 114 is fed to inverter 135 to generate signal CMP. For example... Figure 1 As shown, CMP is used to determine the on-time of the first low-side switch Q2 or the off-time of the first high-side switch Q1. CMPB is used to determine the on-time of the second low-side switch Q3 or the off-time of the second high-side switch Q4. Throughout this description, current comparator 114 may also be referred to as a comparator.

[0029] like Figure 1 As shown, the hybrid control circuit can detect the output voltage VOUT and the current flowing through the inductor 104, and generate multiple gate drive signals for driving switches Q1, Q2, Q3 and Q4 accordingly.

[0030] In some embodiments, amplifier 118 is a voltage error amplifier. For example... Figure 1 As shown, the output voltage VOUT is detected via a voltage divider formed by resistors 108 and 109 at the inverting input (FB) of amplifier 118. The non-inverting input of amplifier 118 is connected to a predetermined reference VREF. The output of amplifier 118 is connected to the inverting input of current comparator 114. A compensation network is connected between the output of amplifier 118 and ground. The compensation network includes resistor 115, capacitor 116, and capacitor 117. Resistor 115 and capacitor 116 are connected in series and further connected in parallel with capacitor 117. The compensation network helps stabilize the control loop and provides sufficient phase margin, thereby improving the transient response performance of the buck-boost converter.

[0031] The non-inverting input of current comparator 114 is configured to receive the detected current signal (CS). For example... Figure 1 As shown, the current flowing through inductor 104 is detected by a suitable current sensing device, such as a DC resistor (DCR) current sensing device. The sensed current signal is fed to the non-inverting input of current comparator 114 via current sensing amplifier 113. Current sensing amplifier 113 is used to provide a suitable current sensing gain.

[0032] A first latch 111 is used to generate gate drive signals for switches Q1 and Q2 respectively. For example... Figure 1 As shown, the reset input of the first latch 111 is configured to receive the output signal of the buck conduction timer 130. The set input of the first latch 111 is configured to receive the output signal of the current comparator 114 via the inverter 135. Figure 1As shown, the CMP signal is fed to the setting input of the first latch 111. The output of the first latch 111 is a PWM signal used to control the buck converter section of the buck-boost converter. The output of the first latch 111 is applied to the gates of switches Q1 and Q2 respectively by the buck control logic unit 110. The buck control logic unit 110 is used to generate a high-side gate drive signal and a low-side gate drive signal based on the PWM signal generated by the first latch 111. In addition, the buck control logic unit 110 adds an appropriate delay between the high-side gate drive signal and the low-side gate drive signal. The following will discuss... Figure 2 A detailed schematic diagram of the buck conduction timer 130 is provided.

[0033] A second latch 119 is used to generate gate drive signals for switches Q3 and Q4 respectively. For example... Figure 1 As shown, the set input of the second latch 119 is configured to receive the output signal of the boost shutdown timer 140. The reset input of the second latch 119 is configured to receive the output signal of the current comparator 114. Figure 1 As shown, the output of the second latch 119 is a PWM signal used to control the boost converter section of the buck-boost converter. For example... Figure 1 As shown, the output of the second latch 119 is applied to the gates of switches Q3 and Q4 respectively via the boost control logic unit 112. The boost control logic unit 112 is used to generate high-side gate drive signals and low-side gate drive signals based on the PWM signal generated by the second latch 119. Furthermore, the boost control logic unit 112 adds an appropriate delay between the high-side gate drive signal and the low-side gate drive signal. The following will discuss... Figure 2 A detailed schematic diagram of the boost shutdown timer 140.

[0034] It should be noted that although the examples throughout this description are based on buck-boost converters and configured as buck-boost converters (e.g., as...), Figure 1 The buck-boost converter shown has a mixed control circuit that generates the gate drive signal, but as... Figure 1 The buck-boost converter and hybrid control circuit illustrated can have many variations, substitutions, and modifications. For example, the hybrid control circuit can detect other necessary signals, such as the input voltage, input current, and / or output current of the buck-boost converter. Furthermore, one or more dedicated drivers can be coupled between the hybrid control circuit and switches Q1, Q2, Q3, and Q4. In summary, limiting the buck-boost converter and hybrid control circuit described herein is merely to clearly illustrate aspects of the invention in various embodiments. This disclosure is not limited to any particular power topology and system configuration.

[0035] Figure 1The switches shown (e.g., Q1) can be implemented as n-type metal-oxide-semiconductor (NMOS) transistors. Alternatively, these switches can be implemented as other suitable controllable devices, such as metal-oxide-semiconductor field-effect transistor (MOSFET) devices, bipolar junction transistor (BJT) devices, superjunction transistor (SJT) devices, insulated-gate bipolar transistor (IGBT) devices, gallium nitride (GaN)-based power devices, and / or similar devices.

[0036] It should also be noted that, although Figure 1 Four switches Q1, Q2, Q3, and Q4 are shown, but various embodiments of this disclosure may include other changes, modifications, and substitutions. For example, the low-side switch Q2 may be replaced by a freewheeling diode and / or similar components. The high-side switch Q4 may be replaced by a rectifier diode and / or similar components.

[0037] Depending on different design needs and applications, buck-boost converters can be configured to operate in three different modes: buck operation, boost operation, and buck-boost operation. The following sections will discuss these modes in detail. Figure 3-5 Describe the detailed operating principles of these three operating modes.

[0038] In some embodiments, the buck-boost converter is configured to operate in buck operation mode. In buck operation mode, switches Q1 and Q2 are controlled by complementary gate drive signals with appropriate switching dead times, in the same manner as in conventional buck converters. Switch Q3 is always off, and switch Q4 is always on. The following will discuss... Figure 3 Describe the detailed operating principle of the buck operation mode.

[0039] In some embodiments, the buck-boost converter is configured to operate in a buck-boost operating mode. In the buck-boost operating mode, the buck-boost converter operates in a complementary manner, using both buck and boost modes. In some embodiments, the buck-boost converter can operate based on the induced current signal CS and the error amplifier output voltage signal V. CTRL The relationship between these parameters enables a smooth and autonomous transition between buck and boost operating modes. More specifically, the buck-boost converter is configured such that the induced current signal CS is greater than the error amplifier output voltage signal V. CTRL It operates in buck mode. On the other hand, the buck-boost converter is configured such that the induced current signal CS is less than the error amplifier output voltage signal V. CTRL It operates in boost mode. The following will discuss... Figure 4 Describe the detailed operating principle of the buck-boost operation mode.

[0040] In some embodiments, the buck-boost converter is configured to operate in boost mode. In boost mode, switches Q3 and Q4 are controlled by complementary gate drive signals with appropriate switching dead times, in the same manner as in conventional boost converters. Switch Q2 is always off, and switch Q1 is always on. The following will discuss... Figure 5 Describe the detailed operating principle of the boost mode.

[0041] Figure 2 Schematic diagrams of buck on-time timers and boost on-time timers according to various embodiments of the present disclosure are shown. In some embodiments, the buck on-time timer 130 is configured to calculate the on-time of a buck converter section. The on-time of the buck converter section is the on-time of a first high-side switch Q1. The boost off-time timer 140 is configured to calculate the off-time of a boost converter section. The off-time of the boost converter section is the off-time of a second low-side switch Q3.

[0042] like Figure 2 As shown, the buck conduction timer 130 includes a current source 203, a capacitor 204, a switch 205, a comparator 201, an OR gate 206, and an inverter 207. Figure 2 As shown, the current level of current source 203 is proportional to the input voltage VIN. In some embodiments, k2 is a predetermined coefficient. Capacitor 204 is charged using current source 203. The voltage across capacitor 204 is a ramp voltage. Figure 2 As shown, the ramp voltage across capacitor 204 is represented as VR. BUCK Throughout this description, capacitor 204 can also be referred to as a ramp capacitor.

[0043] The ramp voltage across capacitor 204 is fed to the non-inverting input of comparator 201. The inverting input of comparator 201 is connected to a threshold voltage, which is proportional to the output voltage. In some embodiments, k1 is a predetermined coefficient. The gate of switch 205 is controlled by the output signal of OR gate 206. Figure 2 As shown, the OR gate 206 is configured to receive the PWM signal generated by the first latch 111 via the inverter 207. BUCK And receive CMP signals. For example... Figure 2 As shown, PWM BUCK The combination of the signal and the CMP signal determines the reset of capacitor 204.

[0044] like Figure 2 As shown, the ramp voltage VR is converted at comparator 201. BCUK Compare with the threshold voltage. At the ramp voltage VR BCUKAfter the threshold voltage is reached, the output of comparator 201 generates a termination signal TON for the conduction time of the buck converter section. BUCK (Termination signal used to turn off switch Q1).

[0045] via ramp voltage VR BCUK The comparison with the threshold voltage determines the on-time of high-side switch Q1 or the off-time of low-side switch Q2. The on-time of high-side switch Q1 (or the off-time of low-side switch Q2) satisfies the following equation:

[0046]

[0047] Where C BUCK It is a 204 capacitor, and k1 and k2 are predetermined parameters.

[0048] The boost turn-off timer 140 includes a current source 213, a capacitor 214, a switch 215, a comparator 211, and an OR gate 216. For example... Figure 2 As shown, the current level of current source 213 is proportional to the output voltage VOUT. In some embodiments, k4 is a predetermined coefficient. Capacitor 214 is charged using current source 213. The voltage across capacitor 214 is a ramp voltage. Figure 2 As shown, the ramp voltage across capacitor 214 is represented as VR. BOOST Throughout this description, capacitor 214 can also be referred to as a ramp capacitor.

[0049] The ramp voltage across capacitor 214 is fed to the non-inverting input of comparator 211. The inverting input of comparator 211 is connected to a threshold voltage proportional to the input voltage VIN. In some embodiments, k3 is a predetermined coefficient. The gate of switch 215 is controlled by the output signal of OR gate 216. Figure 2 As shown, the OR gate 216 is configured to receive the PWM signal generated by the second latch 119. BOOST And the CMPB signal. PWM BOOST The combination of the signal and the CMP signal determines the reset of capacitor 214.

[0050] The voltage across capacitor 214 is compared with a threshold voltage at comparator 211. Once the voltage across capacitor 214 reaches the threshold voltage, the output of comparator 211 generates a termination signal TOFF for the turn-off time of the boost converter section. BOOST .

[0051] The off-time of low-side switch Q3 or the on-time of high-side switch Q4 is determined by comparing the voltage across capacitor 214 with the threshold voltage. The off-time of low-side switch Q3 (or the on-time of high-side switch Q4) satisfies the following equation:

[0052]

[0053] Where C BOOST It is a capacitor of size 214, and k3 and k4 are predetermined parameters.

[0054] In the above equations, k1 and k3 are voltage scaling factors, and k2 and k4 are voltage-to-current scaling factors. By selecting different scaling factors, TON can be adjusted accordingly. BUCK / TOFF BOOST and the corresponding switching frequency.

[0055] Figure 3 Various embodiments according to this disclosure are shown. Figure 1 The timing diagram shown is associated with the buck operation mode of the buck-boost converter. Figure 3 The horizontal axis represents the time interval. There are 12 rows. The first row, 301, represents the PWM signal generated by the first latch 111. BUCK The second line, 302, represents the threshold voltage (k1·VOUT) and ramp signal (VR) fed into comparator 201. BUCK The third line, 303, represents the output voltage (TON) of comparator 201. BUCK The fourth line, 304, represents the PWM signal generated by the second latch 119. BOOST The fifth line, 305, represents the threshold voltage (k3·VIN) and ramp signal (VR) fed into comparator 211. BOOST The sixth line, 306, represents the output voltage (TOFF) of comparator 211. BOOST The seventh line, 307, represents the detected current signal (CS) and the error amplifier voltage (V) fed into the current comparator 114. CTRL The eighth line consists of two rows. Row 308 represents the output voltage (CMP) of inverter 135. Row 308B represents the output voltage (CMPB) of current comparator 114. Row 309 represents the gate drive signal of switch Q1. Row 310 represents the gate drive signal of switch Q2. Row 311 represents the gate drive signal of switch Q3. Row 312 represents the gate drive signal of switch Q4.

[0056] In operation, when the input voltage VIN of the buck-boost converter is much higher than the output voltage VOUT of the buck-boost converter, the output voltage V of the error amplifier will... CTRL The inductor current signal V is lower than the induced current signal. CS Response to V CTRL and V CS The relationship between them, such as Figure 3As shown, for most of the switching cycle (from t1 to t3), the CMPB signal is high, while the CMP signal is low. Figure 3 As shown, the CMPB signal is a pulse with logic high from t1' to t3. The CMP signal is a pulse with logic high from t1 to t1'. Return to Figure 2 From t1' to t3, a long pulse of the CMPB signal disables the boost shutdown timer 140. From t1' to t3, a logic low state of the CMP signal enables the buck on-time timer 130. Because the boost shutdown timer 140 is disabled from t1' to t3, VR is activated only during the short time period from t1 to t1'. BOOST In such a short period of time, VR BOOST It is always below k3·VIN. Therefore, the signal TOFF BOOST It is in a logic low state, thus in PWM BOOST Generates a logic low state. Responds to PWM. BOOST In this low-logic state, the high-side switch Q4 is always on, and the low-side switch Q3 is always off. The on-time of the buck converter section (the on-time of Q1) is determined by the buck on-time timer 130. The buck-boost converter operates in buck mode.

[0057] Return to reference Figure 1 In buck operation mode, current sensing amplifier 113 is configured to detect the current of Q1 (the current flowing through inductor 104). According to valley current mode control, at t1, when the output of current sensing amplifier 113 reaches the control voltage V of comparator 114... CTRL When Q1 is turned on, the buck on-time timer 130 starts counting. Once the buck on-time timer 130 triggers at t2, Q1 is turned off and Q2 is turned on. Once the output of the current sensing amplifier 113 reaches the control voltage V of the comparator 114 at t3... CTRL Then Q2 is closed and Q1 is reopened to start another loop.

[0058] At time t1, the output of current sensing amplifier 113 ( Figure 3 The CS in the middle drops and reaches the control voltage V of comparator 114. CTRL Return to reference. Figure 1 At time t1, the output of comparator 114 generates a logic level "0" (CMPB) and sends this logic level "0" to inverter 135. Inverter 135 generates a logic level "1" (CMP) and sends this logic level "1" to the setting input of the first latch 111. According to the operating principle of the RS latch, the output of comparator 114 determines the turn-on edge of the gate drive signal of Q1.

[0059] like Figure 3 As shown, at time t1, Q2 is already off, and Q1 is already on. Note that there is a suitable delay between turning on Q1 and turning off Q2. As a result of turning on Q1, the induced current CS increases linearly from time t1 to time t2. From time t1 to time t2, the control signal PWM... BUCK It has a logic high state, and CMP has a logic low state. PWM BUCK The combination of the CMP signal and the shutdown function is as follows: Figure 2 The switch 205 of the ramp signal generation circuit is shown. Therefore, from time t1 to time t2, the ramp capacitor 204 is charged, and the voltage across the ramp capacitor 204 (VR) BUCK The voltage increases linearly. During buck operation mode, the boost shutdown timer is never triggered. This is achieved through the output of comparator 114 ( Figure 3 CMPB in the middle to reset the boost ramp (VR) BOOST ).

[0060] At time t2, the ramp voltage VR BUCK The threshold voltage k1·VOUT is reached. The output of comparator 201 generates a logic level "1" (TON). BUCK The logic level "1" is sent to the reset input of the first latch 111. According to the operating principle of the RS latch, the output of comparator 201 determines the turn-off edge of the gate drive signal of Q1.

[0061] like Figure 3 As shown, at time t2, the buck control logic unit 210 applies logic level "1" and logic level "0" to the gates of Q2 and Q1, respectively. As a result of turning on Q2 and turning off Q1, from time t2 to time t3, the detected current signal CS decreases linearly, and the ramp capacitor 204 discharges.

[0062] At time t3, the output of current sensing amplifier 113 ( Figure 3 The CS in the circuit reaches the control voltage V of comparator 114 again. CTRL The buck-boost converter enters a new switching cycle.

[0063] Figure 4 Various embodiments according to this disclosure are shown. Figure 1 The timing diagram shown is associated with the buck-boost operation mode of the buck-boost converter. Figure 4 The horizontal axis represents time intervals. There are 12 rows, 421-432, which are... Figure 3 Lines 301-312 are similar and therefore will not be discussed further.

[0064] During operation, when the input voltage VIN drops to a level approximately equal to the output voltage VOUT, the buck-boost converter operates in a mode combining buck and boost operation modes. Error amplifier voltage V CTRL With the detected current signal V CS The relationship between these factors determines the mode in which the buck-boost converter operates. For example, when V... CS Higher than V CTRL When the buck-boost converter operates in buck mode, the buck-boost converter is active. Buck on-time timer 130 is an active timer that controls the on and off states of Q1 and Q2. Simultaneously, boost off-time timer 140 is disabled to keep Q4 on and Q3 off. When the input voltage VIN is lower than (or close to) the output voltage VOUT, the current operating mode (buck operation mode) cannot regulate the output voltage. The output voltage drops accordingly. In response to the drop in output voltage, the error amplifier increases V... CTRL When V CTRL Increase to greater than V CS When the boost off-time timer 140 is activated, it controls the on and off states of Q3 and Q4. Simultaneously, the buck on-time timer 130 is disabled, keeping Q1 on and Q2 off. In this configuration, the buck-boost converter operates in boost mode. (Depending on V) CTRL and V CS The buck-boost converter operates alternately in buck and boost modes to maintain regulation of its output.

[0065] Figure 4 The timing diagram illustrates the operating principle of the buck-boost mode. From time t1 to time t2, V CS Higher than V CTRL The output voltage (CMPB) of current comparator 114 is high. This high output disables the boost shutdown timer 140. The buck-boost converter operates in buck operation mode. At time t2, V CS Below V CTRL The output voltage (CMPB) of current comparator 114 is low, and the output voltage (CMP) of inverter 135 is high. This high output (CMP) disables the buck on-time timer 130. The buck-boost converter operates in boost mode. Figure 4 As shown, the buck-boost converter operates in a complementary manner, using both buck and boost operation modes. Specifically, Figure 4As shown, during the two consecutive switching cycles preceding t1, the buck-boost converter operates in boost mode. In t1, within one switching cycle, the buck-boost converter exits boost mode and operates in buck mode. In t2, the buck-boost converter returns to boost mode.

[0066] One advantage of this hybrid control scheme is that the buck-boost converter can achieve autonomous and smooth transitions between buck and boost operating modes, such as... Figure 4 As shown.

[0067] Figure 5 Various embodiments according to this disclosure are shown. Figure 1 The timing diagram shown is associated with the boost operation mode of the buck-boost converter. Figure 5 The horizontal axis represents time intervals. There are 12 rows, 541-552, which are... Figure 3 Lines 301-312 are similar and therefore will not be discussed further.

[0068] During operation, when the input voltage VIN drops below a predetermined level below the output voltage VOUT, the output voltage V of the error amplifier... CTR L is higher than the induced inductor current signal V. CS Response to V CTRL With V C The relationship between S, such as Figure 5 As shown, for most of the switching cycle (from t1 to t3), the CMP signal is high, while the CMPB signal is low. Figure 5 As shown, the CMP signal is a pulse with logic high from t1' to t3. The CMPB signal is a pulse with logic high from t1 to t1'. (Return to reference) Figure 2 From t1' to t3, a long pulse of the CMP signal disables the buck on-time timer 130. From t1' to t3, a logic low state of the CMPB signal enables the boost off-time timer 140. Because the buck on-time timer 130 is disabled from t1' to t3, VR is activated only during the short time period from t1 to t1'. BUCK In such a short period of time, VR BUC K is always lower than k1·VOUT. Therefore, the signal TON BUCK It is in a logic low state. A logic low state will not reset the first latch 111. Therefore, the first latch 111 is in the PWM state. UBUCK Generates a logic high state. Responds to PWM. BUCK In the logic high state, high-side switch Q1 is always on, and low-side switch Q2 is always off.

[0069] Figure 5The timing diagram illustrates the operating principle of the boost mode. At time t1, the output of the current sensing amplifier 113 ( Figure 5 The CS in the comparator reaches the control voltage V of the comparator 114. CTRL As mentioned above... Figure 1 As discussed, at time t1, the output of comparator 114 ( Figure 5 The CMPB in the second latch generates a logic level "1" and sends this logic level "1" to the reset input of the second latch 119 (e.g., ...). Figure 1 (As shown). According to the operating principle of the RS latch, the output of comparator 114 determines the turn-off edge of the gate drive signal of Q3.

[0070] like Figure 5 As shown, at time t1, Q3 is already off. After a suitable delay, Q4 is turned on. As a result of turning on Q4, the induced current CS decreases linearly from time t1 to time t2. From time t1 to time t2, the control signal PWM... BOOST It has a logic low state. Additionally, CMPB has a logic low state. PWM BOOST The combination of CMPB and shutdown, such as Figure 2 The switch 215 of the ramp signal generation circuit is shown. Therefore, from time t1 to time t2, the ramp capacitor 214 is charged, and the voltage across the capacitor 214 (VR) BOOST It increases in a linear manner.

[0071] At time t2, the ramp voltage VR BOOST The threshold voltage has been reached. The output of comparator 211 (TON) BOOST The comparator generates a logic level "1" and sends this logic level "1" to the reset input of the second latch 119. According to the operating principle of the RS latch, the output of comparator 211 (TON) BOOST Determine the turn-off edge of the gate drive signal for Q3.

[0072] like Figure 5 As shown, logic level "0" and logic level "1" are applied to the gates of Q3 and Q4 respectively by the boost control logic unit 112. As a result of turning off Q3 and turning on Q4, the induced current CS increases linearly from time t2 to time t3. At time t2, the ramp capacitor 214 discharges. At time t3, the output of the current sensing amplifier 113 ( Figure 3 The CS in the circuit reaches the control voltage V of comparator 114 again. CTRL The buck-boost converter enters a new switching cycle.

[0073] Although embodiments of the invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations may be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

[0074] Furthermore, it is not intended that the scope of this application be limited to specific embodiments of the processes, machines, manufactures, compositions of matter, methods, and steps described herein. Those skilled in the art will readily understand from the disclosure of this invention that, according to the present invention, currently existing or later-developed processes, machines, manufactures, compositions of matter, methods, or steps that perform substantially the same function or achieve substantially the same results as the corresponding embodiments described herein can be utilized. Therefore, it is intended that the appended claims encompass such processes, machines, manufactures, compositions of matter, methods, or steps within their scope.

Claims

1. A voltage conversion device, comprising: A buck converter section of a buck-boost converter configured to operate under a constant on-time control scheme, wherein the on-time of the high-side switch of the buck converter section is determined by a buck on-time timer; and The buck-boost converter section of the buck-boost converter is configured to operate under a constant off-time control scheme, wherein the off-time of the low-side switch of the boost converter section is determined by a boost off-time timer. The buck on-time timer is configured to determine the off edge of the gate drive signal of the high-side switch of the buck converter portion of the buck-boost converter, wherein the buck on-time timer includes a first input configured to receive a first ramp signal and a second input configured to receive a first threshold voltage. The first ramp signal is generated by a first current source having a current level proportional to the input voltage of the buck-boost converter, and the first threshold voltage is proportional to the output voltage of the buck-boost converter; The boost turn-off timer is configured to determine the turn-off edge of the gate drive signal applied to the high-side switch of the boost converter portion of the buck-boost converter, wherein the boost turn-off timer includes a first input configured to receive a second ramp signal and a second input configured to receive a second threshold voltage. The second ramp signal is generated by a second current source having a current level proportional to the output voltage of the buck-boost converter, and the second threshold voltage is proportional to the input voltage of the buck-boost converter.

2. The device as claimed in claim 1, wherein, The buck converter section includes a first high-side switch and a first low-side switch connected in series between the two input terminals of the buck-boost converter; The boost converter section includes a second high-side switch and a second low-side switch connected in series between the two output terminals of the buck-boost converter; and An inductor is connected between the common node of the first high-side switch and the first low-side switch and the common node of the second high-side switch and the second low-side switch.

3. The device as claimed in claim 1, wherein, The shut-off edge of the gate drive signal applied to the low-side switch of the buck converter section of the buck-boost converter and the shut-off edge of the gate drive signal applied to the low-side switch of the boost converter section of the buck-boost converter are determined by a comparator, and The comparator has a first input configured to receive the output voltage of the error amplifier and a second input configured to receive a signal proportional to the current flowing through the inductor of the buck-boost converter.

4. The device as described in claim 3, wherein, The error amplifier has a first input connected to a predetermined reference and a second input configured to detect the output voltage of the buck-boost converter.

5. The device as claimed in claim 1, wherein, The buck-boost converter is configured to operate in buck mode in response to an input voltage greater than the output voltage, and In the buck mode, the low-side switch of the boost converter section is always off, and the high-side switch of the boost converter section is always on.

6. The device as claimed in claim 1, wherein, The buck-boost converter is configured to operate in boost mode in response to an input voltage being less than the output voltage, and In the boost mode, the low-side switch of the buck converter section is always off, and the high-side switch of the buck converter section is always on.

7. The device as claimed in claim 1, wherein, The buck-boost converter is configured to operate in buck-boost mode in response to the input voltage of the buck-boost converter being equal to the output voltage of the buck-boost converter, and In the buck-boost mode, the buck-boost converter operates in a complementary manner, using both buck and boost modes.

8. The device as claimed in claim 7, wherein, In the buck-boost mode, the buck-boost converter automatically switches between buck mode and boost mode based on the relationship between the induced current signal and the error amplifier output voltage signal.

9. The device as claimed in claim 8, wherein, The buck-boost converter is configured to operate in buck mode when the induced current signal is greater than the output voltage signal of the error amplifier; and The buck-boost converter is configured to operate in boost mode when the induced current signal is less than the output voltage signal of the error amplifier.

10. A control method for a voltage conversion device, comprising: A constant on-time control scheme is applied to the buck converter section of the buck-boost converter, wherein, under this scheme, the on-time of the high-side switch in the buck converter section is determined by a buck on-time timer; and A constant off-time control scheme is applied to the boost converter section of the buck-boost converter, wherein the off-time of the low-side switch of the boost converter section is determined by the boost off-time timer under the constant off-time control scheme. In the buck-boost timer, a first ramp signal is generated using a first current source having a current level proportional to the input voltage of the buck-boost converter, a first threshold voltage proportional to the output voltage of the buck-boost converter is generated, the first threshold voltage is compared with the first ramp signal using a first comparator, and the gate drive signal of the high-side switch of the buck converter section of the buck-boost converter is terminated based on the comparison result generated by the first comparator. In the boost turn-off timer, a second current source having a current level proportional to the output voltage of the buck-boost converter generates a second ramp signal, generates a second threshold voltage proportional to the input voltage of the buck-boost converter, compares the second threshold voltage with the second ramp signal using a second comparator, and terminates the gate drive signal of the high-side switch of the boost converter portion of the buck-boost converter based on the comparison result generated by the second comparator.

11. The method of claim 10, further comprising: A current sensing signal is generated that is proportional to the current flowing through the inductor of the buck-boost converter. The detected output voltage of the buck-boost converter is compared with a predetermined reference using an error voltage amplifier; The current sensing signal is compared with the output voltage of the error voltage amplifier using a comparator; as well as Based on the comparison result generated by the comparator, the on-state of the low-side switch of the buck converter section of the buck-boost converter and the on-state of the low-side switch of the boost converter section of the buck-boost converter are terminated.

12. The method of claim 11, further comprising: The buck-boost converter is configured to operate in buck mode when the input voltage of the buck-boost converter is greater than the output voltage of the buck-boost converter, wherein in the buck operation mode, the boost shutdown timer is disabled based on the comparison result generated by the comparator.

13. The method of claim 12, further comprising: The buck-boost converter is configured to operate in boost mode when the input voltage of the buck-boost converter is less than the output voltage of the buck-boost converter, wherein in boost mode, the buck on-time timer is disabled based on the comparison result generated by the comparator.

14. The method of claim 12, further comprising: The buck-boost converter is configured to operate in buck-boost mode when the input voltage of the buck-boost converter is equal to the output voltage of the buck-boost converter, wherein In the buck-boost operation mode, the buck on-time timer and the boost off-time timer are enabled / disabled in a complementary manner based on the comparison result generated by the comparator.

15. A controller for a voltage conversion device, comprising: A first timer is used to set the opening time of the first high-side switch of a buck-boost converter, wherein the opening time of the first high-side switch is determined by the input voltage and the output voltage of the buck-boost converter; A second timer is used to set the off time of the second low-side switch of the buck-boost converter, wherein the off time of the second low-side switch is determined by the input voltage of the buck-boost converter and the output voltage of the buck-boost converter; as well as A current-mode control device for setting the on-time of the first low-side switch and the off-time of the second high-side switch of the buck-boost converter; The first timer includes a first input configured to receive a first ramp signal and a second input configured to receive a first threshold voltage. The first ramp signal is generated by a first current source having a current level proportional to the input voltage of the buck-boost converter, and the first threshold voltage is proportional to the output voltage of the buck-boost converter; The second timer includes a first input configured to receive a second ramp signal and a second input configured to receive a second threshold voltage, wherein The second ramp signal is generated by a second current source having a current level proportional to the output voltage of the buck-boost converter, and the second threshold voltage is proportional to the input voltage of the buck-boost converter.

16. The controller of claim 15, wherein, The turn-off edge of the gate drive signal applied to the first low-side switch of the buck-boost converter and the turn-off edge of the gate drive signal applied to the second high-side switch of the buck-boost converter are determined by the output of the comparator, and The comparator has a first input configured to receive the output voltage of the error amplifier and a second input configured to receive a signal proportional to the current flowing through the inductor of the buck-boost converter.

17. The controller of claim 15, wherein the buck-boost converter comprises: The first high-side switch and the first low-side switch are connected in series between the two input terminals of the buck-boost converter; The second high-side switch and the second low-side switch are connected in series between the two output terminals of the buck-boost converter; as well as An inductor is connected between the common node of the first high-side switch and the first low-side switch and the common node of the second high-side switch and the second low-side switch.

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