Impedance matching method of dual-frequency matching device and dual-frequency matching device

Abstract

The application provides an impedance matching method of a dual-frequency matching device and the dual-frequency matching device. The method comprises the following steps: obtaining a first standing wave ratio of a low-frequency input end and a second standing wave ratio of a high-frequency input end; if the first standing wave ratio does not satisfy a first condition and / or the second standing wave ratio does not satisfy a second condition, obtaining a first impedance of the low-frequency input end and a second impedance of the high-frequency input end; obtaining a load impedance of the dual-frequency matching device; calculating first data for adjusting a capacitance in the dual-frequency matching device according to the first impedance, the second impedance and the load impedance; adjusting the capacitance in a low-frequency impedance matching network in a low-frequency part according to the first data, so as to realize impedance matching of the low-frequency part; and adjusting the capacitance in a high-frequency impedance matching network in a high-frequency part according to the first data, so as to realize impedance matching of the high-frequency part. The application realizes automatic impedance matching.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronics, and particularly relates to an impedance matching method of a dual-frequency matching device and the dual-frequency matching device. BACKGROUND

[0002] The traditional dual-frequency matching device is divided into a high-frequency part and a low-frequency part. The high-frequency part can adopt an L-shaped matching network, and the input end detection adopts an analog mode. The low-frequency part can adopt a T-shaped matching network composed of an array of capacitors and transformers, and a manual gear shifting mode is adopted to change the array of capacitors and transformers to achieve impedance matching. The traditional dual-frequency matching device adopts an analog port mode to communicate with the outside in the communication mode, and a user sets the matching device by inputting a voltage to the analog port pin and reads the matching device state by reading the array pin voltage.

[0003] In the prior art, in order to achieve impedance matching, the low-frequency part generally adopts a manual gear shifting mode. For a process with relatively large impedance variation, the adjustment is relatively complex and troublesome, and the gear position needs to be frequently adjusted. Moreover, the input end of the low-frequency part does not have a power impedance detector, and a user cannot read these parameters, which affects the accurate debugging of the process. Neither the high-frequency part nor the low-frequency part has a detector at the output end, and a user cannot read the output end parameters such as power, impedance, current and voltage, which also affects the accurate debugging of the process. SUMMARY

[0004] In order to solve the problems in the prior art, the present application provides an impedance matching method of a dual-frequency matching device and the dual-frequency matching device, and the main purpose is to achieve automatic impedance matching.

[0005] To achieve the above purpose, the present application provides an impedance matching method of a dual-frequency matching device, which comprises the following steps:

[0006] obtaining a first standing wave ratio of a low-frequency input end and a second standing wave ratio of a high-frequency input end, wherein the low-frequency input end is an input end of a low-frequency part, and the high-frequency input end is an input end of a high-frequency part;

[0007] if the first standing wave ratio does not satisfy a first condition and / or the second standing wave ratio does not satisfy a second condition, obtaining a first impedance of the low-frequency input end and a second impedance of the high-frequency input end;

[0008] obtaining a load impedance of the dual-frequency matching device;

[0009] calculating first data for adjusting a capacitor in the dual-frequency matching device according to the first impedance, the second impedance and the load impedance;

[0010] adjusting the capacitor in the low-frequency impedance matching network in the low-frequency part according to the first data to achieve impedance matching of the low-frequency part;

[0011] The capacitance in the high-frequency impedance matching network in the high-frequency part is adjusted according to the first data to realize impedance matching of the high-frequency part.

[0012] In addition, the application also provides a dual-frequency matching device, which comprises a control module, a low-frequency part and a high-frequency part, the low-frequency part comprises a low-frequency impedance matching network, and the high-frequency part comprises a high-frequency impedance matching network.

[0013] The control module is used for obtaining a first standing wave ratio of a low-frequency input end and a second standing wave ratio of a high-frequency input end, wherein the low-frequency input end is an input end of the low-frequency part, and the high-frequency input end is an input end of the high-frequency part; if the first standing wave ratio does not satisfy a first condition and / or the second standing wave ratio does not satisfy a second condition, a first impedance of the low-frequency input end and a second impedance of the high-frequency input end are obtained, a load impedance of the dual-frequency matching device is obtained, first data for adjusting the capacitance in the dual-frequency matching device is calculated according to the first impedance, the second impedance and the load impedance, the capacitance in the low-frequency impedance matching network in the low-frequency part is adjusted according to the first data to realize impedance matching of the low-frequency part, and the capacitance in the high-frequency impedance matching network in the high-frequency part is adjusted according to the first data to realize impedance matching of the high-frequency part.

[0014] The dual-frequency matching device and the impedance matching method thereof provided by the application can determine whether impedance matching is achieved by using a standing wave ratio, obtain the impedance of the input end and the load impedance in the case where it is determined that impedance matching is not achieved, calculate first data for adjusting the capacitance in the impedance matching network according to the impedance of the input end and the load impedance, and adjust the capacitance in the impedance matching network according to the first data, thereby achieving the purpose of automatically realizing impedance matching. In addition, the application can realize an automatic matching device by using the low-frequency part, and various parameters of the high-frequency input and output end can be read and communicated with a field bus master station. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 The figure is a structural block diagram of the dual-frequency matching device in an embodiment of the application.

[0016] Figure 2 The figure is a flowchart of the impedance matching method of the dual-frequency matching device in an embodiment of the application.

[0017] Figure 3 The figure is a structural block diagram of a T-shaped impedance matching network in an embodiment of the application.

[0018] Figure 4 The figures are structural block diagrams of two L-shaped impedance matching networks in an embodiment of the application.

[0019] Figure 5 The figures are structural block diagrams of six other T-shaped impedance matching networks in an embodiment of the application.

[0020] Figure 6 Structure block diagram of another four L-type impedance matching networks in an embodiment of the present application;

[0021] Figure 7 Equivalent schematic diagram of the variable capacitor in an embodiment of the present application.

[0022] The object, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0023] To make the object, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0024] Figure 1 Structure block diagram of a dual-frequency matching device in an embodiment of the present application; the dual-frequency matching device comprises a control module, a low-frequency part and a high-frequency part, the low-frequency part comprises a low-frequency impedance matching network, and the high-frequency part comprises a high-frequency impedance matching network;

[0025] The control module is configured to acquire a first standing wave ratio of a low-frequency input end and a second standing wave ratio of a high-frequency input end, wherein the low-frequency input end is an input end of the low-frequency part, and the high-frequency input end is an input end of the high-frequency part; if the first standing wave ratio does not satisfy a first condition and / or the second standing wave ratio does not satisfy a second condition, the control module is configured to acquire a first impedance of the low-frequency input end and a second impedance of the high-frequency input end, acquire a load impedance of the dual-frequency matching device, calculate first data for adjusting a capacitor in the dual-frequency matching device according to the first impedance, the second impedance and the load impedance, adjust the capacitor in the low-frequency impedance matching network in the low-frequency part according to the first data, so as to realize impedance matching of the low-frequency part, and adjust the capacitor in the high-frequency impedance matching network in the high-frequency part according to the first data, so as to realize impedance matching of the high-frequency part.

[0026] Figure 2 Flowchart of the impedance matching method of the dual-frequency matching device in an embodiment of the present application. Refer to Figure 2 The control module in the dual-frequency matching device is taken as an example for description. The impedance matching method of the dual-frequency matching device comprises the following steps S100-S600. Figure 1

[0027] ​S100: obtaining a first standing wave ratio of a low-frequency input end and a second standing wave ratio of a high-frequency input end, wherein the low-frequency input end is an input end of a low-frequency part, and the high-frequency input end is an input end of a high-frequency part.

[0028] Specifically, the dual-frequency matching device comprises a high-frequency part and a low-frequency part, the high-frequency part comprises a high-frequency impedance matching network and a low-frequency impedance matching network, the low-frequency input end is an input end of the low-frequency part, and the high-frequency input end is an input end of the high-frequency part.

[0029] The signal input by the low-frequency input end is a low-frequency power signal, and the first detector of the low-frequency input end obtains the low-frequency power signal of the low-frequency input end and then calculates a first impedance of the low-frequency input end, which is the input impedance of the low-frequency input end.

[0030] The signal input by the high-frequency input end is a high-frequency power signal, and the second detector of the high-frequency input end obtains the high-frequency power signal of the high-frequency input end and then calculates a second impedance of the high-frequency input end, which is the input impedance of the high-frequency input end.

[0031] S200: if the first standing wave ratio does not satisfy a first condition and / or the second standing wave ratio does not satisfy a second condition, obtaining the first impedance of the low-frequency input end and the second impedance of the high-frequency input end.

[0032] Specifically, if at least one of the first standing wave ratio is not equal to 1 and the second standing wave ratio is not equal to 1 occurs, the control module will adjust the capacitance in the impedance matching network.

[0033] How to adjust the capacitance specifically needs to obtain the first impedance of the low-frequency input end and the second impedance of the high-frequency input end.

[0034] S300: obtaining a load impedance of the dual-frequency matching device.

[0035] Specifically, the load impedance of the dual-frequency matching device can be detected by an impedance meter. The impedance data can also be obtained by a vector network analyzer.

[0036] S400: calculating first data for adjusting the capacitance in the dual-frequency matching device according to the first impedance, the second impedance and the load impedance.

[0037] Specifically, the low-frequency impedance matching network and the high-frequency impedance matching network in the dual-frequency matching device can only one of them need to be adjusted, and the other one does not need to be adjusted, or both of them need to be adjusted, or neither of them needs to be adjusted.

[0038] Therefore, the first data comprises a first expected value of the capacitance in the low-frequency impedance matching network and / or a second expected value of the capacitance in the high-frequency impedance matching network.

[0039] The control module calculates a first expected value of the variable capacitor in the low-frequency impedance matching network according to a first calculation formula corresponding to the low-frequency impedance network, the first impedance and the load impedance, and then adjusts the capacitor in the low-frequency impedance matching network to the first expected value.

[0040] The control module calculates a second expected value of the variable capacitor in the high-frequency impedance matching network according to a second calculation formula corresponding to the high-frequency impedance network, the second impedance and the load impedance, and then adjusts the capacitor in the high-frequency impedance matching network to the second expected value.

[0041] S500: Adjusting the capacitor in the low-frequency impedance matching network in the low-frequency part according to the first data to realize impedance matching of the low-frequency part.

[0042] S600: Adjusting the capacitor in the high-frequency impedance matching network in the high-frequency part according to the first data to realize impedance matching of the high-frequency part.

[0043] Specifically, the capacitance value of the capacitor in the first calculation formula and the second calculation formula is adjustable and the load impedance is a variable. When the load impedance changes, in order to make the equation hold, the capacitor also needs to change accordingly, therefore, adjusting the capacitor can maintain impedance matching.

[0044] The embodiment realizes automatic matching of the low-frequency impedance matching network and the high-frequency impedance matching network, and uses the method of adjusting the vacuum adjustable capacitor to achieve automatic matching. Both the input end and the output end use digital detectors, and a field bus module is added in communication, which can adapt to Profibus, Devicenet, EtherCAT and other bus modules. Various parameters of the high-frequency input and output ends can be read, and communication with the field bus master station can be realized.

[0045] In one embodiment, the low-frequency impedance matching network is a T-type impedance matching network, and the high-frequency impedance matching network is an L-type impedance matching network.

[0046] The step S400 specifically includes: calculating first sub-data for adjusting the capacitor in the T-type impedance matching network in the dual-frequency matching device according to the first impedance and the load impedance, and calculating second sub-data for adjusting the capacitor in the L-type impedance matching network in the dual-frequency matching device according to the second impedance and the load impedance.

[0047] The step S500 specifically includes: adjusting the capacitor to be adjusted in the T-type impedance matching network according to the first sub-data to realize impedance matching of the low-frequency impedance matching network.

[0048] The step S600 specifically includes: adjusting the capacitor to be adjusted in the L-type impedance matching network according to the second sub-data to realize impedance matching of the high-frequency impedance matching network.

[0049] Specifically, the first calculation formula is an identity equation, which includes the relationship among the first impedance, the load impedance and the capacitances in the low-frequency impedance matching network. If the load impedance changes, the control module needs to calculate the first expected value of the capacitances in the low-frequency impedance matching network, i.e., the first sub-data, and generate a corresponding first adjustment signal according to the first sub-data, and control the capacitance values of the capacitances in the low-frequency impedance matching network by the first adjustment signal.

[0050] The second calculation formula is an identity equation, which includes the relationship among the second impedance, the load impedance and the capacitances in the high-frequency impedance matching network. If the load impedance changes, the control module needs to calculate the second expected value of the capacitances in the high-frequency impedance matching network, i.e., the second sub-data, and generate a corresponding second adjustment signal according to the second sub-data, and control the capacitance values of the capacitances in the high-frequency impedance matching network by the second adjustment signal.

[0051] In an embodiment, the T-type impedance matching network includes a first capacitance, a second capacitance and a third capacitance, the first capacitance is connected in series with the second capacitance and the third capacitance respectively, the first loop includes the first capacitance, the second capacitance and the load, and the second loop includes the first capacitance and the third capacitance.

[0052] The first calculation formula of the first sub-data is:

[0053]

[0054] Wherein, C1 is the capacitance value of the first capacitance, C2 is the capacitance value of the second capacitance, C3 is the capacitance value of the third capacitance, Z LOAD is the load impedance, Z in1 is the first impedance.

[0055] The first sub-data includes at least one of C1, C2 and C3.

[0056] Specifically, Figure 3 is a structure block diagram of a T-type impedance matching network in an embodiment of the application; refer to Figure 3 , the capacitance C1 and the capacitance C3 are connected in series on the second loop, and the capacitance C1, the capacitance C2 and the load Z LOAD are connected in series on the first loop. The capacitances C1, C2 and C3 are all variable capacitances with variable capacitance values. The first impedance Z in1 is the input impedance, and its imaginary part is 0.

[0057] If the load impedance Z LOAD changes, in order to make the first calculation formula (1) hold, the values of at least one of C1, C2 and C3 need to be changed accordingly.

[0058] In one embodiment, if the values of C2 and C3 remain unchanged, the value of C1 is changed, and the first sub-data is the first expected value of C1. The control module changes the capacitance value of the capacitor C1 to the first sub-data.

[0059] If the values of C1 and C3 remain unchanged, the value of C2 is changed, and the first sub-data is the first expected value of C2. The control module changes the capacitance value of the capacitor C2 to the first sub-data.

[0060] If the values of C1 and C2 remain unchanged, the value of C3 is changed, and the first sub-data is the first expected value of C3. The control module changes the capacitance value of the capacitor C3 to the first sub-data.

[0061] If the value of C3 remains unchanged, the values of C1 and C2 are changed, and the first sub-data is the first expected value of C1 and C2. The control module changes the capacitance value of the capacitor C1 and the capacitance value of the capacitor C2 to the corresponding first sub-data, respectively.

[0062] If the value of C2 remains unchanged, the values of C1 and C3 are changed, and the first sub-data is the first expected value of C1 and C3. The control module changes the capacitance value of the capacitor C1 and the capacitance value of the capacitor C3 to the corresponding first sub-data, respectively.

[0063] If the value of C1 remains unchanged, the values of C2 and C3 are changed, and the first sub-data is the first expected value of C2 and C3. The control module changes the capacitance value of the capacitor C2 and the capacitance value of the capacitor C3 to the corresponding first sub-data, respectively.

[0064] If the values of C1, C2 and C3 are changed at the same time, the first sub-data is the first expected value of C1, C2 and C3. The control module changes the capacitance value of the capacitor C1, the capacitance value of the capacitor C2 and the capacitance value of the capacitor C3 to the corresponding first sub-data, respectively.

[0065] When there are at least two variables, the capacitor has multiple candidate values, but because the value range of the capacitors C1, C2 and C3 is limited, the actual capacitance value is also limited.

[0066] In one embodiment, the L-type impedance matching network includes a fourth capacitor and a fifth capacitor in series, the third loop includes the fourth capacitor and the load, and the fourth loop includes the fourth capacitor and the fifth capacitor.

[0067] The calculation formula of the second sub-data is:

[0068]

[0069] wherein C4 is the capacitance value of the fourth capacitor, C5 is the capacitance value of the fifth capacitor, and ZLOAD Z is a load impedance, in2 Z is a second impedance;

[0070] The second sub-data includes at least one of C4 and C5.

[0071] Specifically, Figure 4 FIG. 1 is a structural block diagram of two L-type impedance matching networks in an embodiment of the present application; refer to Figure 4 In the L1 corresponding L-type impedance matching network, the capacitor C4 and the capacitor C5 are connected in series on the fourth loop, and the capacitor C4 and the load Z LOAD are connected in series on the third loop. The capacitors C4 and C5 are both variable capacitors with variable capacitance values. The second impedance Z in2 is an input impedance, and its imaginary part is 0.

[0072] If the load impedance Z LOAD changes, in order to make the second calculation formula (2) hold, it is necessary to change the value of at least one of C4 and C5.

[0073] In one specific embodiment, if the value of C4 is kept unchanged, the value of C5 is changed, and at this time the second sub-data is the second expected value of C5. The control module will change the capacitance value of the capacitor C5 to the corresponding second sub-data.

[0074] If the value of C5 is kept unchanged, the value of C4 is changed, and at this time the second sub-data is the second expected value of C4. The control module will change the capacitance value of the capacitor C4 to the corresponding second sub-data.

[0075] If the values of C4 and C5 are changed at the same time, at this time the second sub-data is the second expected value of C4 and C5. The control module will change the capacitance value of the capacitor C4 and the capacitance value of the capacitor C5 to the corresponding second sub-data.

[0076] When there are at least two variables, the capacitor has multiple candidate values, but because the value range of the capacitors C4 and C5 is limited, the actual value of the capacitor that can be selected is also limited.

[0077] In one embodiment, the L-type impedance matching network includes a fourth capacitor and a fifth capacitor, the third loop includes the fifth capacitor and the load, and the fourth loop includes the fourth capacitor;

[0078] The second calculation formula of the second sub-data is:

[0079]

[0080] Wherein, C4 is the capacitance value of the fourth capacitor, C5 is the capacitance value of the fifth capacitor, Z LOAD is a load impedance, in2 Z is a second impedance;

[0081] The second sub-data includes at least one of C4 and C5.

[0082] Specifically, Figure 4 is a structure block diagram of two L-shaped impedance matching networks in an embodiment of the present application. Referring to Figure 4 The L-shaped impedance matching network corresponding to L2 in the middle, the capacitor C4 is connected in series on the fourth loop, and the capacitor C5 is connected in series with the load Z LOAD on the third loop. The capacitors C4 and C5 are both variable capacitors with variable capacitance values. The second impedance Z in2 is the input impedance, and its imaginary part is 0.

[0083] If the load impedance Z LOAD changes, in order to make the second calculation formula (3) hold, it is necessary to change the value of at least one of C4 and C5 accordingly.

[0084] In a specific embodiment, if the value of C4 is kept unchanged, the value of C5 is changed, and at this time the second sub-data is the second expected value of C5. The control module will change the capacitance value of the capacitor C5 to the corresponding second sub-data.

[0085] If the value of C5 is kept unchanged, the value of C4 is changed, and at this time the second sub-data is the second expected value of C4. The control module will change the capacitance value of the capacitor C4 to the corresponding second sub-data.

[0086] If the values of C4 and C5 are changed at the same time, at this time the second sub-data is the second expected value of C4 and C5. The control module will change the capacitance value of the capacitor C4 and the capacitance value of the capacitor C5 to the corresponding second sub-data.

[0087] When there are at least two variables, the capacitor has multiple candidate values, but because the value range of the capacitors C4 and C5 is limited, the actual value of the capacitor that can be selected is also limited.

[0088] In an embodiment, the T-shaped impedance matching network includes a first capacitor, a second capacitor, and a first inductor;

[0089] The first capacitor is connected in series with the second capacitor and the first inductor, respectively, the first loop includes the first capacitor, the second capacitor, and the load, and the second loop includes the first capacitor and the first inductor;

[0090] Or, the first capacitor is connected in series with the second capacitor and the first inductor, respectively, the first loop includes the first capacitor, the first inductor, and the load, and the second loop includes the first capacitor and the second capacitor;

[0091] Or, the first inductor is connected in series with the first capacitor and the second capacitor, respectively, the first loop includes the first inductor, the first capacitor, and the load, and the second loop includes the first inductor and the second capacitor;

[0092] The capacitance values of the first capacitor and the second capacitor are adjustable, and the inductance value of the first inductor is not adjustable.

[0093] Specifically, Figure 5 is a structural block diagram of another six T-type impedance matching networks in an embodiment of the present application. Referring to Figure 5 The T-type impedance matching network corresponding to T2 in FIG. 2, the capacitor C1 and the inductor L1 are connected in series on the second loop, and the capacitor C1, the capacitor C2 and the load Z LOAD are connected in series on the first loop. The capacitors C1 and C2 are both variable capacitors with variable capacitance values. The first impedance Z in1 is the input impedance, and the imaginary part thereof is 0. The inductance value of the first inductor L1 is constant. In this case, the inductance value of the first inductor L1 is also included in the first calculation formula. If the load impedance Z LOAD changes, changing the capacitance values of the capacitors C1 and / or C2 can make the corresponding first calculation formula still hold.

[0094] Figure 5 The first calculation formula corresponding to the T-type impedance matching network corresponding to T2 in FIG. 2 is shown in the following formula (6):

[0095]

[0096] wherein C1 is the capacitance value of the first capacitor, C2 is the capacitance value of the second capacitor, L1 is the inductance value of the first inductor, Z LOAD is the load impedance, and Z in1 is the first impedance.

[0097] The first sub-data includes at least one of C1 and C2.

[0098] Referring to Figure 5 The T-type impedance matching network corresponding to T3 in FIG. 3, the capacitor C1 and the capacitor C2 are connected in series on the second loop, and the capacitor C1, the inductor L1 and the load Z LOAD are connected in series on the first loop. The capacitors C1 and C2 are both variable capacitors with variable capacitance values. The first impedance Z in1 is the input impedance, and the imaginary part thereof is 0. The inductance value of the first inductor L1 is constant. In this case, the inductance value of the first inductor L1 is also included in the first calculation formula. If the load impedance Z LOAD changes, changing the capacitance values of the capacitors C1 and / or C2 can make the corresponding first calculation formula still hold.

[0099] Figure 5 The first calculation formula corresponding to the T-type impedance matching network corresponding to T3 in FIG. 3 is shown in the following formula (7):

[0100]

[0101] wherein C1 is a capacitance value of the first capacitor, C2 is a capacitance value of the second capacitor, L1 is an inductance value of the first inductor, Z LOAD is the load impedance, Z in1 is the first impedance;

[0102] The first sub-data includes at least one of C1 and C2.

[0103] Referring to Figure 5 the T-type impedance matching network corresponding to T4 in FIG. 4, the inductor L1 and the capacitor C2 are connected in series on the second loop, the inductor L1 and the capacitor C1 are connected in series on the first loop, and the load Z LOAD is connected in parallel to the first loop. The capacitors C1 and C2 are both variable capacitors with variable capacitance values. The first impedance Z in1 is the input impedance, and the imaginary part thereof is 0. The inductance value of the first inductor L1 is constant. In this case, the inductance value of the first inductor L1 is also included in the first calculation formula. If the load impedance Z LOAD changes, changing the capacitance values of the capacitors C1 and / or C2 can make the corresponding first calculation formula still hold.

[0104] Figure 5 The first calculation formula corresponding to the T-type impedance matching network corresponding to T4 in FIG. 4 is shown in the following formula (8):

[0105]

[0106] wherein C1 is a capacitance value of the first capacitor, C2 is a capacitance value of the second capacitor, L1 is an inductance value of the first inductor, Z LOAD is the load impedance, Z in1 is the first impedance;

[0107] The first sub-data includes at least one of C1 and C2.

[0108] In one embodiment, the T-type impedance matching network includes a first capacitor, a first inductor, and a second inductor;

[0109] The first capacitor is connected in series with the first inductor and the second inductor, respectively, the first loop includes the first capacitor, the second inductor, and the load, and the second loop includes the first capacitor and the first inductor;

[0110] Alternatively, the first inductor is connected in series with the first capacitor and the second inductor, respectively, the first loop includes the first inductor, the second inductor, and the load, and the second loop includes the first inductor and the first capacitor;

[0111] Alternatively, the first inductor is connected in series with the first capacitor and the second inductor, respectively, the first loop includes the first inductor, the first capacitor, and the load, and the second loop includes the first inductor and the second inductor;

[0112] The capacitance of the first capacitor is adjustable, while the inductance values ​​of the first and second inductors are not adjustable.

[0113] Specifically, refer to Figure 5 The T-type impedance matching network corresponding to T5 has capacitor C1 and inductor L1 connected in series in the second circuit. Capacitor C1, inductor L2, and load Z are connected in series. LOAD It is connected in series in the first circuit. Capacitor C1 is a variable capacitor with a variable capacitance. First impedance Z in1 Let Z be the input impedance, and its imaginary part be 0. The inductance values ​​of the first inductor L1 and inductor L2 remain unchanged. In this case, the first calculation formula also includes the inductance values ​​of the first inductor L1 and inductor L2. If the load impedance Z LOAD If the value of capacitor C1 changes, then changing the capacitance value of capacitor C1 will still make the corresponding first calculation formula still valid.

[0114] Figure 5 The first calculation formula for the T-type impedance matching network corresponding to T5 is shown in the following formula (9):

[0115]

[0116] Where C1 is the capacitance of the first capacitor, L1 is the inductance of the first inductor, L2 is the inductance of the second inductor, and Z... LOAD Z is the load impedance. in1 The first impedance;

[0117] The first sub-data includes C1.

[0118] refer to Figure 5 The T-type impedance matching network corresponding to T6 has capacitor C1 and inductor L1 connected in series in the second circuit, and inductors L1 and L2 are connected to the load Z. LOAD It is connected in series in the first circuit. Capacitor C1 is a variable capacitor with a variable capacitance. First impedance Z in1 Let Z be the input impedance, and its imaginary part be 0. The inductance values ​​of the first inductor L1 and inductor L2 remain unchanged. In this case, the first calculation formula also includes the inductance values ​​of the first inductor L1 and inductor L2. If the load impedance Z LOAD If the values ​​of capacitors C1 and C2 change, the corresponding first calculation formula can still be valid.

[0119] Figure 5 The first calculation formula for the T-type impedance matching network corresponding to T6 is shown in the following formula (10):

[0120]

[0121] Where C1 is the capacitance of the first capacitor, L1 is the inductance of the first inductor, L2 is the inductance of the second inductor, and Z...LOAD Z is a load impedance, in1 Z is a first impedance;

[0122] The first sub-data includes C1.

[0123] Referring to Figure 5 The T-shaped impedance matching network corresponding to T7 has inductance L1 and inductance L2 in series on the second loop, and capacitor C1, inductance L1 and load Z LOAD are in series on the first loop. Capacitor C1 is a variable capacitor with a variable capacitance. The first impedance Z in1 is an input impedance, and its imaginary part is 0. The inductance values of the first inductance L1 and the second inductance L2 are constant. In this case, the inductance values of the first inductance L1 and the second inductance L2 are also included in the first calculation formula. If the load impedance Z LOAD changes, changing the capacitance of capacitor C1 can make the corresponding first calculation formula still hold.

[0124] Figure 6 The first calculation formula corresponding to the T-shaped impedance matching network corresponding to T7 is shown in the following formula (11):

[0125]

[0126] Where C1 is the capacitance of the first capacitor, L1 is the inductance of the first inductor, L2 is the inductance of the second inductor, and Z LOAD is a load impedance, in1 Z is a first impedance;

[0127] The first sub-data includes C1.

[0128] In one embodiment, the L-shaped impedance matching network includes a fourth capacitor and a third inductor in series;

[0129] The third inductor is in series with the fourth capacitor and the load, respectively, the third loop includes the third inductor and the load, and the fourth loop includes the third inductor and the fourth capacitor;

[0130] Or, the third loop includes the third inductor and the load, and the fourth loop includes the fourth capacitor;

[0131] Or, the fourth capacitor is in series with the third inductor and the load, respectively, the third loop includes the fourth capacitor and the load, and the fourth loop includes the fourth capacitor and the third inductor;

[0132] Or, the third loop includes the fourth capacitor and the load, and the fourth loop includes the third inductor;

[0133] Wherein the capacitance of the fourth capacitor is adjustable, and the inductance of the third inductor is not adjustable.

[0134] Specifically, Figure 6Figure 2 is a structural block diagram of another L-type impedance matching network in an embodiment of the present application; refer to Figure 6 The L-type impedance matching network corresponding to L3 in Figure 2 has inductance L3 and capacitance C4 in series on the fourth loop, and inductance L3 and load impedance Z LOAD are in series on the third loop. Capacitance C4 is a variable capacitance with a variable capacitance value. The second impedance Z in2 is the input impedance, and the imaginary part thereof is 0. The inductance value of inductance L3 is constant. In this case, the inductance value of inductance L3 is also included in the second calculation formula. If the load impedance Z LOAD changes, changing the capacitance value of capacitance C4 can make the corresponding second calculation formula still hold.

[0135] Figure 6 The second calculation formula corresponding to the L-type impedance matching network corresponding to L3 in Figure 2 is shown in the following formula (12):

[0136]

[0137] wherein C4 is the capacitance value of the fourth capacitance, L3 is the inductance value of the third inductance, Z LOAD is the load impedance, Z in2 is the second impedance;

[0138] The second sub-data includes C4.

[0139] Refer to Figure 6 The L-type impedance matching network corresponding to L4 in Figure 3 has capacitance C4 in series on the fourth loop, and inductance L3 and load impedance Z LOAD are in series on the third loop. Capacitance C4 is a variable capacitance with a variable capacitance value. The second impedance Z in2 is the input impedance, and the imaginary part thereof is 0. The inductance value of inductance L3 is constant. In this case, the inductance value of inductance L3 is also included in the second calculation formula. If the load impedance Z LOAD changes, changing the capacitance value of capacitance C4 can make the corresponding second calculation formula still hold.

[0140] Figure 6 The second calculation formula corresponding to the L-type impedance matching network corresponding to L4 in Figure 3 is shown in the following formula (13):

[0141]

[0142] wherein C4 is the capacitance value of the fourth capacitance, L3 is the inductance value of the third inductance, Z LOAD is the load impedance, Z in2 is the second impedance;

[0143] The second sub-data includes C4.

[0144] Refer toFigure 6 The L-type impedance matching network corresponding to L5 has the fourth capacitor C4 in series with the third inductor L3 on the fourth loop, and the fourth capacitor C4 is in series with the load Z LOAD on the third loop. The fourth capacitor C4 is a variable capacitor with a variable capacitance. The second impedance Z in2 is the input impedance, and the imaginary part thereof is 0. The inductance value of the third inductor L3 is constant. In this case, the inductance value of the third inductor L3 is also included in the second calculation formula. If the load impedance Z LOAD changes, changing the capacitance value of the fourth capacitor C4 can make the corresponding second calculation formula still hold.

[0145] Figure 6 The second calculation formula corresponding to the L-type impedance matching network corresponding to L5 is shown in the following formula (14):

[0146]

[0147] wherein C4 is the capacitance value of the fourth capacitor, L3 is the inductance value of the third inductor, Z LOAD is the load impedance, Z in2 is the second impedance;

[0148] The second sub-data includes C4.

[0149] Reference Figure 7 The L-type impedance matching network corresponding to L6 has the third inductor L3 in series on the fourth loop, and the fourth capacitor C4 is in series with the load Z LOAD on the third loop. The fourth capacitor C4 is a variable capacitor with a variable capacitance. The second impedance Z in2 is the input impedance, and the imaginary part thereof is 0. The inductance value of the third inductor L3 is constant. In this case, the inductance value of the third inductor L3 is also included in the second calculation formula. If the load impedance Z LOAD changes, changing the capacitance value of the fourth capacitor C4 can make the corresponding second calculation formula still hold.

[0150] Figure 7 The second calculation formula corresponding to the L-type impedance matching network corresponding to L6 is shown in the following formula (15):

[0151]

[0152] wherein C4 is the capacitance value of the fourth capacitor, L3 is the inductance value of the third inductor, Z LOAD is the load impedance, Z in2 is the second impedance;

[0153] The second sub-data includes C4.

[0154] In one embodiment, the first standing wave ratio of the low-frequency input end is calculated by a first detector of the low-frequency input end collecting a low-frequency power signal of the low-frequency input end;

[0155] The second standing wave ratio of the high-frequency input end is calculated by a second detector of the high-frequency input end collecting a high-frequency power signal of the high-frequency input end;

[0156] The low-frequency power signal flows into the filter plate after passing through the low-frequency impedance matching network, and the high-frequency power signal flows into the filter plate after passing through the high-frequency impedance matching network;

[0157] The filter plate separates the high-frequency power signal and the low-frequency power signal and outputs them to the external cavity respectively;

[0158] The method further comprises:

[0159] The third standing wave ratio of the output end of the dual-frequency matching device is obtained, wherein the third standing wave ratio is calculated by a third detector of the output end of the dual-frequency matching device collecting an output signal of the output end;

[0160] If the third standing wave ratio does not satisfy the third condition, the capacitance in the dual-frequency matching device is readjusted.

[0161] Specifically, the high-frequency and low-frequency power after matching are converged into the filter plate, the filter plate separates the two power signals with different frequencies, and ensures that the high-frequency and low-frequency power can be output to the external cavity. The filter plate outputs the integrated high-frequency and low-frequency power to the external cavity, and the third detector collects impedance data and transmits them to the control module.

[0162] The third detector arranged at the output end can verify whether the low-frequency impedance matching network and the high-frequency impedance matching network in the dual-frequency matching device have reached impedance matching. When the verification result is that the third standing wave ratio does not satisfy the third condition, the control module can readjust the value of the capacitance in the matching network to achieve impedance matching, thereby further ensuring the accuracy of impedance matching.

[0163] The first detector, the second detector and the third detector of the application are all digital detectors.

[0164] In one embodiment, the capacitance value of the capacitance is changed by changing the voltage of the capacitance. ​ The equivalent schematic diagram of the variable capacitance in one embodiment of the application is shown in FIG. 2. ​ The specific principle of changing the capacitance is described as follows: the capacitance is composed of two parts AB and BC, the capacitance value C is the capacitance value of AC, and the equivalent capacitance value C AB of AB and the capacitance value C BC of BC are connected in series. The capacitance value is changed by changing the voltage U BCThat is, the capacitance control voltage V is used to change the capacitance value C. The relationship between C and V is shown in equation (4). In equation (4), the AB part and the BC part use dielectrics with different dielectric constants, and C AB The ratio C BC is much greater, and because of the parallel relationship, as shown in equation (5), C is mainly determined by the smaller C BC , so by changing V to change C BC , the value of C is changed.

[0165]

[0166] C=C AB / / C BC (5)

[0167] The input end and the output end of the novel dual-frequency matching device both use digital detectors, and a field bus module is added in communication, which can adapt to Profibus, Devicenet, EtherCAT and other bus modules, various parameters of the high-frequency input end and the low-frequency input end can be read, and communication with the field bus master station end can be realized.

[0168] The low-frequency matching network is in an automatic matching mode, and a vacuum adjustable capacitor is used to achieve automatic matching.

[0169] The novel dual-frequency matching device uses digital detectors for the input end and the output end of the high-frequency matching network and the low-frequency matching network, the low-frequency matching network is modified to an automatic matching mode, and a vacuum adjustable capacitor is used to achieve automatic matching. A field bus module is added in communication, which can adapt to Profibus, Devicenet, EtherCAT and other bus modules. The module continuously exchanges data with the high-frequency master controller and the low-frequency master controller and the output end detector controller, realizes that the instructions received by the field bus are transmitted to the controllers, and the state data of the matching device is uploaded to the field bus master station end.

[0170] The power of the high-frequency part and the low-frequency part is all input into the filter plate and then input into the cavity. The filter plate blocks the power of the high-frequency part from flowing into the low-frequency part, so that the high-frequency power and the low-frequency power can both enter the cavity.

[0171] The output end of the novel dual-frequency matching device is provided with an output end detector. The detector transmits the collected signals to the output end detector controller, and the controller calculates the power, impedance, voltage and current of the input end high-frequency signal and the input end low-frequency signal. Reading of these parameters is beneficial to monitoring of the process by the user.

[0172] It should be understood that the size of the serial number of each step in the above embodiments does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0173] The "first" and "second" in the above modules / units are only used to distinguish different modules / units, and are not used to limit the priority of which module / unit is higher or other limiting meanings. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or modules does not have to be limited to those steps or modules clearly listed, but can include other steps or modules that are not clearly listed or inherent to these processes, methods, products or devices. The division of modules in the present application is only a logical division, and other division methods can be used in actual application.

[0174] The processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor and the like. The processor is the control center of the computer device, and connects all parts of the computer device through various interfaces and lines.

[0175] The memory can be used to store computer readable instructions and / or modules, and the processor realizes various functions of the computer device by running or executing the computer readable instructions and / or modules stored in the memory, and calling the data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application required by a function (such as a sound playing function, an image playing function, etc.), etc.; and the data storage area can store data created according to the use of the mobile phone (such as audio data, video data, etc.), etc.

[0176] The memory can be integrated in the processor, or can be arranged separately from the processor.

[0177] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through computer readable instructions, and the computer readable instructions can be stored in a computer readable storage medium. When the computer readable instructions are executed, the processes of the above-mentioned embodiments of the method can be included. Any reference to memory, storage, database or other medium used in the embodiments provided in the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM) and the like.

[0178] It should be noted that in this paper, the term "include", "contain" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, device, article or method including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or includes elements inherent to such process, device, article or method. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, device, article or method including the element.

[0179] The above-mentioned serial numbers of the embodiments of the present application are only for description, not representing the advantages and disadvantages of the embodiments. Through the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be realized by software and necessary general hardware platform, of course, also can be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of software product, which is stored in a storage medium (such as ROM / RAM, magnetic disc, optical disc) as described above, including a plurality of instructions for making a terminal device (which can be a mobile phone, computer, server or network device) execute the method described in each embodiment of the present application.

[0180] The above merely preferred embodiments of the present application and are not intended to limit the patent scope of the present application, any equivalent structure or equivalent process transformation using the content of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An impedance matching method of a dual-frequency matching device, applied to a control module of the dual-frequency matching device, characterized in that, The method comprises: obtaining a first standing wave ratio of a low-frequency input end and a second standing wave ratio of a high-frequency input end, wherein the low-frequency input end is an input end of a low-frequency part, and the high-frequency input end is an input end of a high-frequency part; if the first standing wave ratio does not satisfy a first condition and / or the second standing wave ratio does not satisfy a second condition, obtaining a first impedance of the low-frequency input end and a second impedance of the high-frequency input end; obtaining a load impedance of the dual-frequency matching device; calculating first data for adjusting capacitances in the dual-frequency matching device according to the first impedance, the second impedance and the load impedance; adjusting the capacitances in a low-frequency impedance matching network in the low-frequency part according to the first data to achieve impedance matching of the low-frequency part; adjusting the capacitances in a high-frequency impedance matching network in the high-frequency part according to the first data to achieve impedance matching of the high-frequency part; the low-frequency impedance matching network is a T-type impedance matching network, and the high-frequency impedance matching network is an L-type impedance matching network; the calculating first data for adjusting capacitances in the dual-frequency matching device according to the first impedance, the second impedance and the load impedance comprises: calculating first sub-data for adjusting capacitances in a T-type impedance matching network in the dual-frequency matching device according to the first impedance and the load impedance, and calculating second sub-data for adjusting capacitances in an L-type impedance matching network in the dual-frequency matching device according to the second impedance and the load impedance; the adjusting the capacitances in a low-frequency impedance matching network in the low-frequency part according to the first data to achieve impedance matching of the low-frequency part comprises: adjusting to-be-adjusted capacitances in the T-type impedance matching network according to the first sub-data to achieve impedance matching of the low-frequency impedance matching network; the adjusting the capacitances in a high-frequency impedance matching network in the high-frequency part according to the first data to achieve impedance matching of the high-frequency part comprises: adjusting to-be-adjusted capacitances in the L-type impedance matching network according to the second sub-data to achieve impedance matching of the high-frequency impedance matching network.

2. The method of claim 1, wherein, The T-type impedance matching network comprises a first capacitance, a second capacitance and a third capacitance, the first capacitance is connected in series with the second capacitance and the third capacitance respectively, a first loop comprises the first capacitance, the second capacitance and a load, and a second loop comprises the first capacitance and the third capacitance. A first calculation formula of the first sub-data is: wherein C1 is a capacitance value of the first capacitor, C2 is a capacitance value of the second capacitor, C3 is a capacitance value of the third capacitor, Z LOAD is the load impedance, Z in1 is the first impedance; The first sub-data comprises at least one of C1, C2 and C3.

3. The method of claim 1, wherein, The L-type impedance matching network comprises a fourth capacitance and a fifth capacitance connected in series, a third loop comprises the fourth capacitance and a load, and a fourth loop comprises the fourth capacitance and the fifth capacitance. A second calculation formula of the second sub-data is: wherein C4 is a capacitance value of the fourth capacitor, C5 is a capacitance value of the fifth capacitor, Z LOAD is the load impedance, Z in2 is the second impedance; The second sub-data comprises at least one of C4 and C5.

4. The method of claim 1, wherein, The L-type impedance matching network comprises a fourth capacitance and a fifth capacitance, a third loop comprises the fifth capacitance and a load, and a fourth loop comprises the fourth capacitance. A second calculation formula of the second sub-data is: wherein C4 is a capacitance value of the fourth capacitor, C5 is a capacitance value of the fifth capacitor, Z LOAD is the load impedance, Z in2 is the second impedance; The second sub-data comprises at least one of C4 and C5.

5. The method of claim 1, wherein the T-type impedance matching network comprises a first capacitor, a second capacitor and a first inductor; the first capacitor is connected in series with the second capacitor and the first inductor respectively, a first loop comprises the first capacitor, the second capacitor and the load, and a second loop comprises the first capacitor and the first inductor; or, the first capacitor is connected in series with the second capacitor and the first inductor respectively, a first loop comprises the first capacitor, the first inductor and the load, and a second loop comprises the first capacitor and the second capacitor; or, the first inductor is connected in series with the first capacitor and the second capacitor respectively, a first loop comprises the first inductor, the first capacitor and the load, and a second loop comprises the first inductor and the second capacitor; wherein the capacitance of the first capacitor and the second capacitor is adjustable, and the inductance of the first inductor is not adjustable.

6. The method of claim 1, wherein the T-type impedance matching network comprises a first capacitor, a first inductor and a second inductor; the first capacitor is connected in series with the first inductor and the second inductor respectively, a first loop comprises the first capacitor, the second inductor and the load, and a second loop comprises the first capacitor and the first inductor; or, the first inductor is connected in series with the first capacitor and the second inductor respectively, a first loop comprises the first inductor, the second inductor and the load, and a second loop comprises the first inductor and the first capacitor; or, the first inductor is connected in series with the first capacitor and the second inductor respectively, a first loop comprises the first inductor, the first capacitor and the load, and a second loop comprises the first inductor and the second inductor; wherein the capacitance of the first capacitor is adjustable, and the inductance of the first inductor and the second inductor is not adjustable.

7. The method of claim 1, wherein the L-type impedance matching network comprises a fourth capacitor and a third inductor connected in series; the third inductor is connected in series with the fourth capacitor and the load respectively, a third loop comprises the third inductor and the load, and a fourth loop comprises the third inductor and the fourth capacitor; or, a third loop comprises the third inductor and the load, and a fourth loop comprises the fourth capacitor; or, the fourth capacitor is connected in series with the third inductor and the load respectively, a third loop comprises the fourth capacitor and the load, and a fourth loop comprises the fourth capacitor and the third inductor; or, a third loop comprises the fourth capacitor and the load, and a fourth loop comprises the third inductor; wherein the capacitance of the fourth capacitor is adjustable, and the inductance of the third inductor is not adjustable.

8. The method of claim 1, wherein the first standing wave ratio of the low-frequency input end is calculated by a first detector of the low-frequency input end collecting a low-frequency power signal of the low-frequency input end; the second standing wave ratio of the high-frequency input end is calculated by a second detector of the high-frequency input end collecting a high-frequency power signal of the high-frequency input end; the low-frequency power signal flows into a filter plate after passing through the low-frequency impedance matching network, and the high-frequency power signal flows into the filter plate after passing through the high-frequency impedance matching network; ​ ​ ​ ​ The filter plate separates the high-frequency power signal and the low-frequency power signal and outputs them to an external cavity respectively; The method further comprises: acquiring a third standing wave ratio of an output end of the dual-frequency matcher, wherein the third standing wave ratio is calculated by an output signal of the output end collected by a third detector of the output end of the dual-frequency matcher; if the third standing wave ratio does not satisfy a third condition, readjusting a capacitance in the dual-frequency matcher.

9. A dual frequency matching network, characterized by, An impedance matching method for implementing a dual-frequency matcher as claimed in any one of claims 1-8, the dual-frequency matcher comprising a control module, a low-frequency part and a high-frequency part, the low-frequency part comprising a low-frequency impedance matching network, and the high-frequency part comprising a high-frequency impedance matching network; The control module is configured to acquire a first standing wave ratio of a low-frequency input end and a second standing wave ratio of a high-frequency input end, wherein the low-frequency input end is an input end of the low-frequency part, and the high-frequency input end is an input end of the high-frequency part; if the first standing wave ratio does not satisfy a first condition and / or the second standing wave ratio does not satisfy a second condition, acquire a first impedance of the low-frequency input end and a second impedance of the high-frequency input end, acquire a load impedance of the dual-frequency matcher, calculate first data for adjusting a capacitance in the dual-frequency matcher according to the first impedance, the second impedance and the load impedance, adjust the capacitance in the low-frequency impedance matching network in the low-frequency part according to the first data to achieve impedance matching of the low-frequency part, and adjust the capacitance in the high-frequency impedance matching network in the high-frequency part according to the first data to achieve impedance matching of the high-frequency part. The low-frequency impedance matching network is a T-type impedance matching network, and the high-frequency impedance matching network is an L-type impedance matching network. The calculation of the first data for adjusting the capacitance in the dual-frequency matcher according to the first impedance, the second impedance and the load impedance comprises: calculating first sub-data for adjusting the capacitance in the T-type impedance matching network in the dual-frequency matcher according to the first impedance and the load impedance, and calculating second sub-data for adjusting the capacitance in the L-type impedance matching network in the dual-frequency matcher according to the second impedance and the load impedance. The adjustment of the capacitance in the low-frequency impedance matching network in the low-frequency part according to the first data to achieve impedance matching of the low-frequency part comprises: adjusting the to-be-adjusted capacitance in the T-type impedance matching network according to the first sub-data to achieve impedance matching of the low-frequency impedance matching network. The adjustment of the capacitance in the high-frequency impedance matching network in the high-frequency part according to the first data to achieve impedance matching of the high-frequency part comprises: adjusting the to-be-adjusted capacitance in the L-type impedance matching network according to the second sub-data to achieve impedance matching of the high-frequency impedance matching network.

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