Integrated chip and method of manufacturing the same

Abstract

The application discloses an integrated chip and a preparation method thereof, wherein the integrated chip comprises a device wafer, a bulk acoustic resonator and a resonant circuit unit; the bulk acoustic resonator is arranged on one side surface of the device wafer; the resonant circuit unit is arranged on the one side surface of the device wafer in parallel with the bulk acoustic resonator, or the resonant circuit unit is arranged on the side of the bulk acoustic resonator away from the device wafer; the bulk acoustic resonator is electrically connected with the resonant circuit unit; the bulk acoustic resonator and the resonant circuit unit are integrated on the same chip, so that the integration degree of the device is improved, the communication bandwidth is increased, the system efficiency is improved, the chip area is reduced and the cost is lowered.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication equipment, and particularly relates to an integrated chip and a preparation method thereof. BACKGROUND

[0002] 5G communication drives the rapid development of the radio frequency front-end market. Compared with 4G, various devices of the radio frequency front-end in the 5G mobile phone will be greatly increased. The deployment of the 5G network is divided into two stages, the first stage is Sub-6GHz, and the second stage is the millimeter wave frequency band. Specifically, four frequency bands are added in the first stage, namely n41 (frequency range 2.496-2.69GHz, bandwidth 196MHz), n77 (frequency range 3.3-4.2GHz, bandwidth 900MHz), n78 (frequency range 3.3-3.8GHz, bandwidth 500MHz), and n79 (frequency range 4.4-5.0GHz, bandwidth 600MHz). The frequency used by 5G and future communication will be higher and higher to meet the demand of mobile communication for larger bandwidth. SUMMARY

[0003] In order to meet the requirement of bandwidth of 5G and future communication, the existing filter usually assembles discrete inductors, capacitors and electrical components together to form a matching circuit at the packaging stage to increase the bandwidth. As a result, the device area is large, the circuit loss is large, and the manufacturing cost is high.

[0004] The main purpose of the present application is to provide an integrated chip and a preparation method thereof, which aims to solve the problems of complex manufacturing process and high cost of the existing bulk acoustic wave filter suitable for high frequency bands.

[0005] To achieve the above purpose, the present application provides an integrated chip, which comprises:

[0006] a device wafer;

[0007] a bulk acoustic wave resonator arranged on one side surface of the device wafer; and

[0008] a resonant circuit unit arranged on one side surface of the device wafer in parallel with the bulk acoustic wave resonator, or arranged on a side of the bulk acoustic wave resonator away from the device wafer;

[0009] The bulk acoustic wave resonator and the resonant circuit unit are electrically connected.

[0010] Optionally, a cavity with an opening is formed on one side surface of the device wafer;

[0011] The bulk acoustic wave resonator comprises:

[0012] a lower electrode layer arranged on the opening, and the lower electrode layer is provided with a signal output part;

[0013] a piezoelectric layer formed on a side of the lower electrode layer away from the device wafer; and

[0014] an upper electrode layer formed on a side of the piezoelectric layer away from the lower electrode layer, the upper electrode layer being provided with a signal input part;

[0015] The signal input part or the signal output part is electrically connected to the resonant circuit unit.

[0016] Optionally, a side surface of the device wafer has a plurality of layout areas arranged side by side and spaced apart;

[0017] The resonant circuit unit includes an inductor, a capacitor and a resistor electrically connected to each other, and the bulk acoustic wave resonator, the inductor, the capacitor and the resistor are sequentially arranged on a plurality of layout areas;

[0018] The bulk acoustic wave resonator is electrically connected to at least one of the inductor, the capacitor and the resistor.

[0019] Optionally, the integrated chip further includes a cap wafer, the cap wafer is erected on a side of the bulk acoustic wave resonator away from the device wafer to form an upper cavity with the bulk acoustic wave resonator, and the cap wafer is provided with a conductive through hole in the thickness direction thereof;

[0020] The resonant circuit unit is arranged on a side of the cap wafer away from the bulk acoustic wave resonator and is electrically connected to the bulk acoustic wave resonator through the conductive through hole.

[0021] Optionally, the resonant circuit unit includes:

[0022] a first dielectric layer formed on a side surface of the cap wafer away from the bulk acoustic wave resonator; and

[0023] a component group formed on the first dielectric layer, the component group including an inductor, a capacitor and a resistor arranged side by side and spaced apart and electrically connected to each other;

[0024] The bulk acoustic wave resonator is electrically connected to at least one of the inductor, the capacitor and the resistor.

[0025] Optionally, the resonant circuit unit includes:

[0026] a second dielectric layer formed on a side surface of the cap wafer away from the bulk acoustic wave resonator;

[0027] a component layer group including an inductor layer, a capacitor layer and a resistor layer arranged in sequence and electrically connected to each other;

[0028] Wherein, the bulk acoustic wave resonator is electrically connected with at least one of the inductance layer, the capacitance layer and the resistance layer.

[0029] The application further provides an integrated chip preparation method based on the above integrated chip, which comprises:

[0030] providing a device wafer;

[0031] providing a bulk acoustic wave resonator on one side surface of the device wafer;

[0032] providing a resonant circuit unit on the bulk acoustic wave resonator, or side by side on one side surface of the device wafer;

[0033] making an interconnection structure to electrically connect at least the bulk acoustic wave resonator with the resonant circuit unit.

[0034] Optionally, the step of providing a bulk acoustic wave resonator on one side surface of the device wafer comprises:

[0035] forming a first dielectric layer on one side surface of the device wafer;

[0036] forming an intermetal dielectric layer on the side of the first dielectric layer away from the device wafer;

[0037] respectively providing an inductive metal line, a capacitive metal line and a resistive metal line in the intermetal dielectric layer to form an inductor, a capacitor and a resistor respectively;

[0038] In the step of making an interconnection structure, the interconnection structure is further provided between the inductor, the capacitor and the resistor.

[0039] Optionally, the step of providing a resonant circuit unit on the bulk acoustic wave resonator comprises:

[0040] mounting a cap wafer on the side of the bulk acoustic wave resonator away from the device wafer to form an upper cavity together with the bulk acoustic wave resonator;

[0041] forming a second dielectric layer on the side of the cap wafer away from the bulk acoustic wave resonator;

[0042] forming an intermetal dielectric layer on the side of the second dielectric layer away from the cap wafer;

[0043] respectively providing an inductive metal line, a capacitive metal line and a resistive metal line in the intermetal dielectric layer to form an inductor, a capacitor and a resistor respectively;

[0044] In the step of fabricating the interconnection structure, the interconnection structure is further arranged between the inductor, the capacitor and the resistor.

[0045] Optionally, the step of arranging the resonant circuit unit on the bulk acoustic wave resonator comprises:

[0046] A cap wafer is arranged on the side of the bulk acoustic wave resonator away from the device wafer to form an upper cavity together with the bulk acoustic wave resonator;

[0047] A second dielectric layer is formed on the side of the cap wafer away from the bulk acoustic wave resonator;

[0048] A first intermetallic dielectric layer is formed on the side of the second dielectric layer away from the cap wafer;

[0049] An inductor metal line is arranged in the first intermetallic dielectric layer to form an inductor;

[0050] A capacitor dielectric layer is formed on the first intermetallic dielectric layer;

[0051] A second intermetallic dielectric layer is formed on the capacitor dielectric layer;

[0052] A capacitor metal line is arranged in the second intermetallic dielectric layer to form a capacitor;

[0053] A third metal dielectric layer is formed on the second intermetallic dielectric layer;

[0054] A resistor metal line is arranged on the third metal dielectric layer to form a resistor;

[0055] A passivation layer is formed on the third metal dielectric layer to cover the resistor;

[0056] In the step of fabricating the interconnection structure, the interconnection structure is further arranged between the inductor layer, the capacitor layer and the resistor layer.

[0057] In the technical solution of the present application, a device wafer is provided, a bulk acoustic wave resonator is arranged on one side surface of the device wafer, and the resonant circuit unit is arranged side by side with the bulk acoustic wave resonator on the one side surface of the device wafer or on the side of the bulk acoustic wave resonator away from the device wafer; that is, the resonant circuit unit and the bulk acoustic wave resonator are integrated on the same chip, so as to improve the integration degree of the device, increase the communication bandwidth, improve the system efficiency, reduce the chip area and reduce the cost. BRIEF DESCRIPTION OF DRAWINGS

[0058] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0059] Figure 1 A schematic diagram of the structure of the first embodiment of the integrated chip provided by the present invention;

[0060] Figure 2 A schematic diagram of the structure of the second embodiment of the integrated chip provided by the present invention;

[0061] Figure 3 A schematic diagram of the structure of the third embodiment of the integrated chip provided by the present invention;

[0062] Figure 4 A flowchart illustrating an embodiment of the integrated chip fabrication method provided by the present invention;

[0063] Figure 5 for Figure 4 A flowchart of the first embodiment of step S30 in the process;

[0064] Figure 6 for Figure 4 A flowchart of the second embodiment of step S30 in the process;

[0065] Figure 7 for Figure 4 The flowchart of the third embodiment of step S30 in the process.

[0066] Explanation of reference numerals in the accompanying drawings of the embodiments provided in this invention:

[0067]

[0068]

[0069] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0070] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0071] It should be noted that if the embodiments of the present application involve directionality indication (such as up, down, left, right, front, back, etc.), the directionality indication is only used to explain the relative position relationship, motion condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directionality indication also changes accordingly.

[0072] In addition, if the embodiments of the present application involve descriptions such as "first", "second", etc., the descriptions of "first", "second", etc. are only for description purposes and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features. In addition, the meaning of "and / or" appearing throughout the text includes three parallel schemes. For example, "A and / or B" includes A scheme, or B scheme, or A and B simultaneously meet the scheme. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the realization of ordinary skilled in the art, when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, nor within the scope of protection claimed by the present application.

[0073] In the communication of 4G and before, the main radio frequency filter is BAW filter, that is, bulk acoustic wave filter. The existing ordinary bulk acoustic wave filter has a lower application frequency band. The bulk acoustic wave filter applicable to a high frequency band has a complex manufacturing process and a high cost.

[0074] In view of this, the present application provides an integrated chip and a preparation method thereof. Figures 1 to 3 The present application provides a specific embodiment of the integrated chip; Figures 4 to 7 The present application provides a specific embodiment of the preparation method of the integrated chip.

[0075] Please refer to Figures 1 to 3 The integrated chip 100 includes a device wafer 1, a bulk acoustic wave resonator 2, and a resonant circuit unit 3. The bulk acoustic wave resonator 2 is arranged on one side surface of the device wafer 1. The resonant circuit unit 3 is arranged on one side surface of the device wafer 1 in parallel with the bulk acoustic wave resonator 2, or the resonant circuit unit 3 is arranged on the side of the bulk acoustic wave resonator 2 away from the device wafer 1. The bulk acoustic wave resonator 2 and the resonant circuit unit 3 are electrically connected.

[0076] In the technical scheme of the present application, a device wafer 1 is provided, a bulk acoustic resonator 2 is arranged on one side surface of the device wafer 1, and a resonant circuit unit 3 is arranged on the one side surface of the device wafer 1 in parallel with the bulk acoustic resonator 2 or is arranged on the side of the bulk acoustic resonator 2 away from the device wafer 1; that is, the resonant circuit unit 3 and the bulk acoustic resonator 2 are integrated on the same chip, so as to improve the integration of the device, increase the communication bandwidth, improve the system efficiency, and reduce the chip area and cost.

[0077] Specifically, further referring to Figure 1 A cavity 11 with an opening is formed on the one side surface of the device wafer 1; the bulk acoustic resonator 2 comprises a lower electrode layer 21, a piezoelectric layer 22 and an upper electrode layer 23, the lower electrode layer 21 is arranged on the opening, and the lower electrode layer 21 is provided with a signal output part 5; the piezoelectric layer 22 is formed on the side of the lower electrode layer 21 away from the device wafer 1; the upper electrode layer 23 is formed on the side of the piezoelectric layer 22 away from the lower electrode layer 21, and the upper electrode layer 23 is provided with a signal input part 4; wherein the signal input part 4 or the signal output part 5 is electrically connected with the resonant circuit unit 3; it should be noted that the basic structure of the bulk acoustic resonator 2 is a sandwich structure, in which the piezoelectric thin film is arranged between the upper and lower metal electrodes; the acoustic wave oscillates in the piezoelectric thin film to form a standing wave. In order to keep the acoustic wave oscillating in the piezoelectric thin film, sufficient isolation between the oscillation structure and the external environment is required to obtain minimum loss and maximum quality factor (Q value). For example, in a thin film bulk acoustic resonator (FBAR), cavities are arranged on the two sides away from the upper and lower electrode layers 21 to form a suspended thin film and a cavity. Since the acoustic impedance of air is much lower than that of the piezoelectric layer 22, most of the acoustic waves will be reflected back to make the acoustic wave oscillate in the piezoelectric thin film, thereby improving the working efficiency of the bulk acoustic resonator 2.

[0078] It should be noted that the material of the device wafer 1 can be selected from insulating silicon (such as SOI), silicon carbide, sapphire, glass and the like, so as to have good insulation performance; at the same time, in order to adapt to the existing filter, the size of the device wafer 1 is generally set to 2-6 inches; when the material of the device wafer 1 is silicon (including insulating silicon), the size of the device wafer 1 can be set to 4-12 inches, so as to be suitable for more specifications of filters.

[0079] The material of the piezoelectric layer 22 is not limited, and can be selected from one of zinc oxide, lead zirconate titanate (PZT), gallium nitride, lithium tantalate, and lithium niobate. In this embodiment, the piezoelectric layer 22 is an aluminum nitride film, which is used as the piezoelectric layer 22 to improve the piezoelectric coefficient of the piezoelectric layer 22, thereby improving the electromechanical coupling coefficient of the bulk acoustic wave resonator 2, and further improving the performance of the filter.

[0080] Specifically, in the first embodiment, one side surface of the device wafer 1 has a plurality of layout areas arranged side by side and spaced apart; the resonant circuit unit 3 includes an inductor 31, a capacitor 32, and a resistor 33 electrically connected to each other, and the bulk acoustic wave resonator 2, the inductor 31, the capacitor 32, and the resistor 33 are sequentially arranged on the plurality of layout areas; the bulk acoustic wave resonator 2 is electrically connected to at least one of the inductor 31, the capacitor 32, and the resistor 33; sequentially arranging the bulk acoustic wave resonator 2, the inductor 31, the capacitor 32, and the resistor 33 on the plurality of layout areas not only realizes the integration of the bulk acoustic wave resonator 2 and the resonant circuit unit 3, but also makes the manufacturing of the integrated chip 100 simpler.

[0081] For further reference Figure 2 and Figure 3 In the second and third embodiments, the integrated chip 100 further includes a cap wafer 6, which is arranged on the side of the bulk acoustic wave resonator 2 away from the device wafer 1 to form an upper cavity with the bulk acoustic wave resonator 1, and the cap wafer 6 is provided with a conductive through hole in the thickness direction thereof; wherein the resonant circuit unit 3 is arranged on the side of the cap wafer 6 away from the bulk acoustic wave resonator 2, and is electrically connected to the bulk acoustic wave resonator 2 through the conductive through hole; it should be noted that when manufacturing the integrated chip 100, if all the components are arranged on the same plane, the area of the integrated chip 100 is approximately the sum of the areas of the components. In a complex circuit, ten or even dozens of components may be used, so the area of the integrated chip 100 becomes very large, resulting in an increase in product cost; by adding the cap wafer 6 on the bulk acoustic wave resonator 2 and arranging the resonant circuit unit 3 on the side of the cap wafer 6 away from the device wafer 1, not only the integration of the bulk acoustic wave resonator 2 and the resonant circuit unit 3 is realized, but also the area of the integrated chip 100 is greatly reduced, which not only simplifies the manufacturing process, but also reduces the production cost.

[0082] It should be noted that in the second embodiment and the third embodiment, the device wafer 1 has a cavity 11 with an opening formed on one side surface thereof, the bulk acoustic resonator 2 includes a lower electrode layer 21, a piezoelectric layer 22, and an upper electrode layer 23; the lower electrode layer 21 covers the opening, the piezoelectric layer 22 is formed on the one side surface of the device wafer 1 and covers the lower electrode layer 21, the upper electrode layer 23 is formed on the side of the piezoelectric layer 22 away from the lower electrode layer 21, and the upper electrode layer 23 is arranged corresponding to the position where the opening is located and extends towards the side of the piezoelectric layer 22; the signal input part 4 of the bulk acoustic resonator 2 is connected to the upper electrode layer 23 and the piezoelectric layer 22, and the signal output part 5 of the bulk acoustic resonator 2 is connected to the lower electrode layer 21 and the piezoelectric layer 22; wherein the signal input part 4 or the signal output part 5 is electrically connected to the resonant circuit unit 3, so as to realize the formation of the bulk acoustic resonator 2.

[0083] In the second embodiment, the resonant circuit unit 3 includes a first dielectric layer 37 and a component group; the first dielectric layer 37 is formed on the side surface of the cap wafer 6 away from the bulk acoustic resonator 2; the component group is formed on the first dielectric layer 37, and the component group includes an inductor 31, a capacitor 32, and a resistor 33 arranged side by side and spaced apart and electrically connected to each other; wherein the bulk acoustic resonator 2 is electrically connected to at least one of the inductor 31, the capacitor 32, and the resistor 33; by arranging the inductor 31, the capacitor 32, and the resistor 33 side by side and spaced apart on the first dielectric layer 37, the structure of the resonant circuit unit 3 is simple and easy to manufacture.

[0084] Specifically, in the present embodiment, an intermetallic dielectric layer 39 is formed on the first dielectric layer 37, and an inductor metal line, a capacitor metal line, and a resistor metal line are respectively formed on the intermetallic dielectric layer 39 to respectively form the inductor 31, the capacitor 32, and the resistor 33.

[0085] In the third embodiment, the resonant circuit unit 3 includes a second dielectric layer 38 and a component layer group; the second dielectric layer 38 is formed on the surface of the cap wafer 6 facing away from the bulk acoustic wave resonator 2; the component layer group includes an inductor layer 34, a capacitor layer 35, and a resistor layer 36 stacked sequentially, and the inductor layer 34, the capacitor layer 35, and the resistor layer 36 are electrically connected to each other; wherein, the bulk acoustic wave resonator 2 is electrically connected to at least one of the inductor layer 34, the capacitor layer 35, and the resistor layer 36; it should be noted that, due to the resonant circuit unit 3... The area occupied by circuit unit 3 is greater than the sum of the areas occupied by capacitor 32, resistor 33 and inductor 31. Therefore, arranging capacitor 32, resistor 33 and inductor 31 side by side will increase the area occupied by resonant circuit unit 3, thereby increasing the area of ​​integrated chip 100 and thus increasing product cost. By setting capacitor 32, resistor 33 and inductor 31 as an inductor layer 34, capacitor layer 35 and resistor layer 36 stacked in sequence, the area of ​​integrated chip 100 can be further reduced and production cost can be reduced.

[0086] Specifically, in this embodiment, a first intermetallic dielectric layer 391 is formed on the second dielectric layer 38; an inductor metal line is disposed within the first intermetallic dielectric layer 391 to form the inductor layer 34; a capacitor dielectric layer is formed on the first intermetallic dielectric layer 391; a second intermetallic dielectric layer 392 is formed on the capacitor dielectric layer; a capacitor metal line is disposed within the second intermetallic dielectric layer 392 to form the capacitor layer 35; a third intermetallic dielectric layer 393 is formed on the second intermetallic dielectric layer 392; a resistor metal line is disposed on the third intermetallic dielectric layer 393 to form a resistor layer 36; and a passivation layer is formed on the third intermetallic dielectric layer 393 to cover the resistor layer 36.

[0087] In this invention, the integrated chip 100 further includes an interconnection structure 7; wherein the bulk acoustic wave resonator 2 and the resonant circuit unit 3 are electrically connected through the interconnection structure 7; using the interconnection structure 7 to replace traditional wiring not only simplifies the manufacturing steps, but also simplifies the internal structure of the integrated chip 100.

[0088] In this invention, the integrated chip 100 further includes an interconnection structure 7; wherein the inductor 31, the capacitor 32 and the resistor 33 are electrically connected through the interconnection structure 7; the interconnection structure 7 realizes the electrical connection between the components inside the resonant circuit unit 3.

[0089] It should be noted that the above two technical features can be set alternatively or simultaneously. Specifically, in the embodiment, the above two technical features are set simultaneously, that is, the integrated chip 100 further comprises an interconnection structure 7; the bulk acoustic resonator 2 and the resonant circuit unit 3 are electrically connected through the interconnection structure 7; the inductor 31, the capacitor 32 and the resistor 33 are electrically connected through the interconnection structure 7; the electrical connection between the internal components of the integrated chip 100 is realized through the interconnection structure 7, which not only simplifies the manufacturing steps, but also simplifies the internal structure of the integrated chip 100.

[0090] Specifically, the interconnection structure 7 is set as one of a metal interconnection structure or an air bridge structure.

[0091] Based on the above integrated chip, the preparation method of the integrated chip is described.

[0092] Please refer to Figure 4 , the first embodiment of the preparation method of the integrated chip provided by the present application.

[0093] The preparation method of the integrated chip comprises:

[0094] S10: providing a device wafer;

[0095] S20: disposing a bulk acoustic resonator on one side surface of the device wafer;

[0096] S30: disposing a resonant circuit unit side by side on one side surface of the device wafer, or disposing a resonant circuit unit on the bulk acoustic resonator;

[0097] S40: manufacturing an interconnection structure to electrically connect at least the bulk acoustic resonator and the resonant circuit unit.

[0098] In the embodiment, by disposing a bulk acoustic resonator on the shaped surface of the device wafer, and simultaneously integrating a resonant circuit unit on the device wafer, the resonant circuit unit is disposed side by side with the bulk acoustic resonator on the shaped surface, or is disposed on the side of the bulk acoustic resonator away from the shaped surface, so as to integrate the resonant circuit unit and the bulk acoustic resonator on the same chip, thereby improving the integration degree of the device, increasing the communication bandwidth, improving the system efficiency, reducing the chip area and reducing the cost; and using the interconnection structure can not only realize the electrical connection between the units and elements, but also simplify the manufacturing process and the internal structure of the integrated chip.

[0099] Specifically, please refer to Figure 5 , the step S30 of "disposing a bulk acoustic resonator on one side surface of the device wafer" comprises:

[0100] S31: forming a first dielectric layer on one side surface of the device wafer;

[0101] S32: forming an intermetal dielectric layer on the side of the first dielectric layer away from the device wafer;

[0102] S33: disposing an inductor metal line, a capacitor metal line and a resistor metal line in the intermetal dielectric layer respectively to form an inductor, a capacitor and a resistor respectively;

[0103] In the step S40 of fabricating the interconnection structure, the interconnection structure is further arranged between the inductor, the capacitor and the resistor.

[0104] In this embodiment, the first dielectric layer and the intermetal dielectric layer are formed on the device wafer, and the inductor, the capacitor and the resistor are sequentially arranged on the intermetal dielectric layer to realize the arrangement of the resonant circuit unit on the device wafer, which is simple in structure and easy to fabricate.

[0105] Specifically, referring to Figure 6 , the step S30 of arranging a resonant circuit unit on the bulk acoustic wave resonator comprises:

[0106] S31': erecting a cap wafer on the side of the bulk acoustic wave resonator away from the device wafer to form an upper cavity together with the bulk acoustic wave resonator;

[0107] S32': forming a second dielectric layer on the side of the cap wafer away from the bulk acoustic wave resonator;

[0108] S33': forming an intermetal dielectric layer on the side of the second dielectric layer away from the cap wafer;

[0109] S34': forming an inductor metal line, a capacitor metal line and a resistor metal line in the intermetal dielectric layer respectively to form an inductor, a capacitor and a resistor respectively;

[0110] In the step S40 of fabricating the interconnection structure, the interconnection structure is further arranged between the inductor, the capacitor and the resistor.

[0111] In this embodiment, the cap wafer is added on the bulk acoustic wave resonator, the second dielectric layer and the intermetal dielectric layer are formed on the cap wafer, and the inductor, the capacitor and the resistor are sequentially arranged on the intermetal dielectric layer, so that the integration of each component in the resonant circuit unit is realized, the area of the integrated chip is greatly reduced, the fabrication process is simplified, and the production cost is reduced.

[0112] Specifically, referring to Figure 7 , the step S30 of "arranging a resonant circuit unit on the bulk acoustic resonator" comprises:

[0113] S31": a cap wafer is arranged on the side of the bulk acoustic resonator away from the device wafer to form an upper cavity together with the bulk acoustic resonator;

[0114] S32": a second dielectric layer is formed on the side of the cap wafer away from the bulk acoustic resonator;

[0115] S33": a first intermetallic dielectric layer is formed on the second dielectric layer;

[0116] S34": an inductive metal line is arranged in the first intermetallic dielectric layer to form an inductor;

[0117] S35": a capacitive dielectric layer is formed on the first intermetallic dielectric layer;

[0118] S36": a second intermetallic dielectric layer is formed on the capacitive dielectric layer;

[0119] S37": a capacitive metal line is arranged in the second intermetallic dielectric layer to form a capacitor;

[0120] S38": a third metal dielectric layer is formed on the second intermetallic dielectric layer;

[0121] S39": a resistive metal line is arranged on the third metal dielectric layer to form a resistor;

[0122] S310": a passivation layer is formed on the third metal dielectric layer to cover the resistor;

[0123] In the step S40 of "making an interconnection structure", the interconnection structure is further arranged between the inductive layer, the capacitive layer and the resistive layer.

[0124] In the embodiment, the cap wafer is added on the bulk acoustic resonator, the second dielectric layer and the intermetallic dielectric layer are formed on the cap wafer, and the inductive layer, the capacitive layer and the resistive layer are sequentially stacked on the intermetallic dielectric layer, so as to further reduce the area of the integrated chip and reduce the production cost.

[0125] The above only describes the preferred embodiments of the present application, and does not limit the patent scope of the present application. Any equivalent structural transformation made according to the content of the present application specification and drawings, or direct / indirect application in other related technical fields is included in the patent protection scope of the present application.

Claims

1. An integrated chip, characterized in that, include: Device wafers; A bulk acoustic resonator is disposed on one side surface of the device wafer; as well as, The resonant circuit unit includes an inductor layer, a capacitor layer and a resistor layer stacked sequentially, and the resonant circuit unit is located on the side of the bulk acoustic wave resonator away from the device wafer. The bulk acoustic resonator is electrically connected to the resonant circuit unit. A cavity with an opening is formed on one side surface of the device wafer; The bulk acoustic resonator includes: A lower electrode layer is disposed over the opening, and the lower electrode layer is provided with a signal output section; A piezoelectric layer is formed on the side of the lower electrode layer opposite to the device wafer; and, An upper electrode layer is formed on the side of the piezoelectric layer opposite to the lower electrode layer, and the upper electrode layer is provided with a signal input section; The signal input section or the signal output section is electrically connected to the resonant circuit unit; The capacitor layer is located between the inductor layer and the resistor layer, and the inductor layer is positioned close to the bulk acoustic resonator.

2. The integrated chip according to claim 1, characterized in that, The inductor layer includes an inductor, the capacitor layer includes a capacitor, the resistor layer includes a resistor, the inductor, the capacitor, and the resistor are electrically connected to each other, and the bulk acoustic wave resonator is electrically connected to at least one of the inductor, the capacitor, and the resistor.

3. The integrated chip according to claim 1, characterized in that, The integrated chip also includes a cap wafer, which is mounted on the side of the bulk acoustic wave resonator away from the device wafer to form an upper cavity with the bulk acoustic wave resonator. The cap wafer has conductive vias in its thickness direction. The resonant circuit unit is located on the side of the cap wafer away from the bulk acoustic wave resonator, and is electrically connected to the bulk acoustic wave resonator through the conductive via.

4. The integrated chip according to claim 3, characterized in that, The resonant circuit unit includes: A second dielectric layer is formed on the surface of the cap wafer facing away from the bulk acoustic resonator; The component layer group includes an inductor layer, a capacitor layer and a resistor layer stacked in sequence, and the inductor layer, the capacitor layer and the resistor layer are electrically connected to each other; The bulk acoustic resonator is electrically connected to at least one of the inductor layer, the capacitor layer, and the resistor layer.

5. A method for fabricating an integrated chip based on the integrated chip according to any one of claims 1-4, characterized in that, include: Provide a device wafer; A bulk acoustic resonator is disposed on one side surface of the device wafer; A resonant circuit unit is provided on the bulk acoustic resonator; An interconnection structure is fabricated to electrically connect at least the bulk acoustic resonator to the resonant circuit unit.

6. The integrated chip fabrication method according to claim 5, characterized in that, The step of "setting a resonant circuit unit on the bulk acoustic resonator" includes: A cap wafer is mounted on the side of the bulk acoustic wave resonator away from the device wafer to form an upper cavity together with the bulk acoustic wave resonator. A second dielectric layer is formed on the side of the cap wafer opposite to the bulk acoustic resonator; A first intermetallic dielectric layer is formed on the side of the second dielectric layer opposite to the cap wafer; An inductor metal line is disposed within the first intermetallic dielectric layer to form an inductor layer; A capacitor dielectric layer is formed on the first intermetallic dielectric layer; A second intermetallic dielectric layer is formed on the capacitor dielectric layer; Capacitor metal lines are disposed within the second intermetallic dielectric layer to form a capacitor layer; A third metal dielectric layer is formed on the second intermetallic dielectric layer; A resistive metal line is disposed on the third metal dielectric layer to form a resistive layer; A passivation layer is formed on the third metal dielectric layer to cover the resistive layer; In the step of "fabricating the interconnect structure": the interconnect structure is further disposed between the inductor layer, the capacitor layer and the resistor layer.

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