Solutions for enabling die reuse in 3D stacked products

By using partially through-hole TSV interconnects and bonding pad vias in 3D integrated circuits, the interconnect alignment problem of different types of dies is solved, reducing costs and improving signal routing efficiency, and enhancing the space utilization of active devices.

CN114467174BActive Publication Date: 2026-07-03ADVANCED MICRO DEVICES INC
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
ADVANCED MICRO DEVICES INC
Filing Date
2020-09-25
Publication Date
2026-07-03

AI Technical Summary

Technical Problem

In existing technologies for 3D integrated circuits, interconnects cannot be aligned with different types of dies, resulting in high manufacturing costs and limited interconnect locations, especially when memory dies are stacked with other dies, making it impossible to effectively route traffic.

Method used

The system employs through-silicon via (TSV) interconnects that do not completely penetrate the first semiconductor die, and provides bonding pad vias and bonding pad interconnects on the top of the die. Vertical and horizontal signal routing is achieved through the metal layer extension, avoiding space occupation in the TSV and blocking regions, and providing flexible mask design.

Benefits of technology

It enables flexible interconnection between different types of dies, reduces manufacturing costs, increases space for active devices, and improves the flexibility and efficiency of signal routing.

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Abstract

Systems, apparatus, and methods for routing traffic through vertically stacked semiconductor dies are disclosed. In a three-dimensional integrated circuit, a first semiconductor die has a second die vertically stacked on top of it. The first die includes through-silicon via (TSV) interconnects that do not penetrate the first die. The first die includes one or more metal layers above the TSVs, said one or more metal layers being connected to a bonding pad interface via bonding pad vias. If signals transmitted through the TSVs of the first die are shared by the second die, the second die includes TSVs aligned with the bonding pad interfaces of the first die. If the second die does not share these signals, the second die includes an insulating portion on the wafer backside aligned with the bonding pad interfaces.
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