A test connection device for mass production testing of fA class currents

Abstract

The application discloses a test connecting device for mass production test of fA-level current, which is characterized by comprising a test golden finger and an electromagnetic shielding body wrapped around the test golden finger, the test golden finger being electrically connected with device end feet of a chip to be tested and a current measuring device respectively, the electromagnetic shielding body comprising a first insulating ring, a shielding inner ring, a second insulating ring, a voltage fast stabilization shielding ring, a third insulating ring and a grounding shielding ring arranged in sequence from inside to outside, and the electromagnetic shielding body being electrically connected with a shielding control circuit, the shielding control circuit being used to control the potential of the voltage fast stabilization shielding ring to be the same as the potential of the test golden finger, then control the potential of the shielding inner ring to be the same as the potential of the test golden finger, and finally control the potential of the shielding inner ring to be the same as the potential of the test golden finger until the measurement is finished; the test connecting device can reduce or avoid the influence of external environment on the test golden finger, improve the measurement precision, shorten the measurement time of the current measuring device on fA-level leakage current and improve the measurement efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to a test connection device for current, in particular to a test connection device for mass production test of fA level current. BACKGROUND

[0002] At present, according to the requirements of working application scene and the like, only a very small leakage current is allowed to exist at the device end pin of the chip such as operational amplifier during work, and the leakage current is generally fA level. For the fA level leakage current, at present, it is usually measured in experimental environment by technical means, and in actual mass production test, due to the extremely weak leakage current and the long distance between the chip to be measured and the current measuring device, the measurement precision of the current measuring device to the leakage current of the chip to be measured is deteriorated due to the influence of the environment, so that the leakage current cannot be effectively detected, and it is difficult to meet the requirements of mass production test. SUMMARY

[0003] The technical problem to be solved by the present application is to provide a test connection device for mass production test of fA level current, which can reduce or even avoid the influence of external environment on the test connection gold finger during detection, meet the measurement requirements of fA level leakage current during mass production, and improve the efficiency and reliability of mass production test.

[0004] The technical scheme adopted by the present application to solve the above technical problem is: a test connection device for mass production test of fA level current, used for connecting a chip to be measured and a current measuring device, comprising a test gold finger and an electromagnetic shielding body wrapped around the test gold finger, one end of the test gold finger is electrically connected to a device end pin of the chip to be measured, the other end of the test gold finger is electrically connected to the current measuring device, the electromagnetic shielding body comprises a first insulating ring, a shielding inner ring, a second insulating ring, a voltage fast stabilization shielding ring, a third insulating ring and a grounding shielding ring arranged in sequence from inside to outside, a shielding control circuit is electrically connected to the electromagnetic shielding body, the shielding control circuit makes the grounding shielding ring always in a grounded state, and during test, the shielding control circuit first controls the potential of the voltage fast stabilization shielding ring to be the same as the potential of the test gold finger, then controls the potential of the shielding inner ring to be the same as the potential of the test gold finger, and until the measurement is completed.

[0005] Further, the first insulating ring, the shielding inner ring, the second insulating ring, the voltage fast stabilization shielding ring, the third insulating ring and the grounding shielding ring are concentrically distributed with the test gold finger.

[0006] Further, the shielding control circuit comprises a sample-and-hold circuit, a shielding inner ring control circuit and a stable shielding ring control circuit, the sample-and-hold circuit is used for sampling and holding a shielding drive signal, the shielding inner ring control circuit is electrically connected with the shielding inner ring and is used for controlling the potential of the shielding inner ring to be the same as that of the test golden finger, and the stable shielding ring control circuit is electrically connected with the voltage fast stable shielding ring and is used for controlling the potential of the voltage fast stable shielding ring to be fast stabilized at the same potential of the test golden finger.

[0007] Further, the sample-and-hold circuit comprises a first NMOS tube, a second NMOS tube and a fifth capacitor, the drain of the first NMOS tube is electrically connected with a shielding drive signal, the source of the first NMOS tube is electrically connected with the source of the second NMOS tube, the first end of the fifth capacitor, the shielding inner ring control circuit and the stable shielding ring control circuit respectively, and the drain of the second NMOS tube and the second end of the fifth capacitor are grounded.

[0008] Further, the stable shielding ring control circuit comprises a first operational amplifier, a first capacitor, a second capacitor, a third capacitor, a first resistor and a second resistor, the non-inverting terminal of the first operational amplifier is electrically connected with the first end of the fifth capacitor, the source of the first NMOS tube and the source of the second NMOS tube, the positive power supply terminal of the first operational amplifier is grounded through the second capacitor, the negative power supply terminal of the first operational amplifier is grounded through the first capacitor, the inverting terminal of the first operational amplifier is electrically connected with one end of the second resistor, the other end of the second resistor is electrically connected with the output of the first operational amplifier and one end of the first resistor respectively, the other end of the first resistor is electrically connected with one end of the third capacitor to form a stable shielding ring control output, the stable shielding ring control output is electrically connected with the voltage fast stable shielding ring, and the other end of the third capacitor is grounded.

[0009] Further, the shielding inner ring control circuit comprises a square wave signal generating circuit and a constant voltage generating circuit, and the constant voltage generating circuit is electrically connected with the square wave signal generating circuit and the sample-and-hold circuit respectively.

[0010] Further, the square wave signal generating circuit comprises a second operational amplifier, a fourth capacitor, a third resistor, a first variable resistor, a second variable resistor and a third NMOS tube, the non-inverting terminal of the second operational amplifier is electrically connected with one end of the third resistor and one end of the first variable resistor, the other end of the third resistor is grounded, the other end of the first variable resistor is electrically connected with the output terminal of the second operational amplifier and the drain terminal of the third NMOS tube, the inverting terminal of the second operational amplifier is electrically connected with one end of the second variable resistor and one end of the fourth capacitor, the other end of the fourth capacitor is grounded, the other end of the second variable resistor is electrically connected with the output terminal of the second operational amplifier and the drain terminal of the third NMOS tube, and the source terminal of the third NMOS tube is electrically connected with the constant voltage generating circuit.

[0011] Further, the constant voltage generating circuit comprises a third operational amplifier, a fourth NMOS tube, a sixth capacitor, a seventh capacitor, an eighth capacitor, a fifth resistor and a sixth resistor, the non-inverting terminal of the third operational amplifier is electrically connected with the first end of the fifth capacitor, the source terminal of the first NMOS tube and the source terminal of the second NMOS tube, the inverting terminal of the third operational amplifier is electrically connected with one end of the fifth resistor, the other end of the fifth resistor is electrically connected with the output terminal of the third operational amplifier and one end of the sixth resistor, the negative power supply terminal of the third operational amplifier is grounded through the sixth capacitor, the positive power supply terminal of the third operational amplifier is grounded through the seventh capacitor, the other end of the sixth resistor is electrically connected with one end of the eighth capacitor and the drain terminal of the fourth NMOS tube, the other end of the eighth capacitor is grounded, and the source terminal of the fourth NMOS tube is electrically connected with the source terminal of the third NMOS tube to form a shielded inner ring control output terminal, the shielded inner ring control output terminal is electrically connected with the shielded inner ring.

[0012] Further, the second operational amplifier and the third operational amplifier adopt high-bandwidth operational amplifiers, the high-bandwidth operational amplifier comprises a voltage comparator, a CMOS input operational amplifier, a JFET input operational amplifier, an inverter, a push-pull output circuit and a ninth capacitor, the noninverting terminal of the JFET input operational amplifier, the noninverting terminal of the CMOS input operational amplifier and the first voltage negative terminal of the voltage comparator are connected to form the noninverting terminal of the high-bandwidth operational amplifier, the inverting terminal of the JFET input operational amplifier, the inverting terminal of the CMOS input operational amplifier and the second voltage negative terminal of the voltage comparator are connected to form the inverting terminal of the high-bandwidth operational amplifier, the voltage positive terminal of the voltage comparator is connected to a reference voltage, the output terminal of the voltage comparator is connected to the enable terminal of the JFET input operational amplifier and the input terminal of the inverter, the output terminal of the inverter is connected to the enable terminal of the CMOS input operational amplifier, the output terminal of the JFET input operational amplifier and the output terminal of the CMOS input operational amplifier are connected to the input terminal of the push-pull output circuit and one end of the ninth capacitor, and the output terminal of the push-pull output circuit and the other end of the ninth capacitor are connected to form the output terminal of the high-bandwidth operational amplifier.

[0013] Further, the shielding drive signal is a voltage signal of an input protection pin of the chip to be measured or a voltage signal sampled by the test finger.

[0014] Compared with the prior art, the application has the advantages that the test finger is wrapped with the electromagnetic shielding body, the influence of the external environment on the test finger is reduced or avoided, and the measurement accuracy is improved; the shielding control circuit is electrically connected to the electromagnetic shielding body, when the test finger measures the leakage current flowing through the device pin of the chip to be measured, the shielding control circuit makes the voltage of the shielding ring quickly and stably reach the same potential as the test finger, after the voltage of the shielding ring is kept at the same potential as the test finger, the shielding control circuit controls the potential of the shielding inner ring to be consistent with the potential of the test finger until the leakage current measurement is completed, which greatly shortens the steady state time during the whole measurement, thereby shortening the time for the current measurement device to measure the fA-level leakage current through the test finger and improving the measurement efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 The connection diagram for measuring the chip to be measured by using the application;

[0016] Figure 2 The top view of the electromagnetic shielding body and the test finger of the application;

[0017] Figure 3 is a sectional view; Figure 2

[0018] Figure 4 is a circuit schematic diagram of a shielding control circuit of the present application;

[0019] Figure 5 is a schematic diagram of a timing control signal generated by a timing control circuit of the present application;

[0020] Figure 6 is a schematic diagram of a timing control signal of the present application;

[0021] Figure 7 is a circuit block diagram of a high-bandwidth operational amplifier of the present application. DETAILED DESCRIPTION

[0022] The present application will be further described in detail below with reference to the accompanying drawings.

[0023] As shown in the drawings, a test connecting device for mass production testing of fA-level current is used to connect a chip under test 1 and a current measuring device 2, the chip under test 1 can be a commonly used chip such as an operational amplifier, and the current measuring device 2 is an existing device. The test connecting device comprises a test pin 3 and an electromagnetic shield 4 wrapped around the test pin 3. One end of the test pin 3 is electrically connected to a device pin 5 of the chip under test 1, and the other end of the test pin 3 is electrically connected to the current measuring device 2. The chip under test 1 generally has a plurality of device pins 5, and the number of test pins 3 is generally equal to the number of device pins 5 on the chip under test 1. During mass production testing, the chip under test 1 is placed in a test station, and the chip under test 1 is electrically connected to the test pins 3 on the test connecting device one by one through the device pins 5. If only part of the device pins 5 on the chip under test 1 needs to be measured for leakage current, the electromagnetic shield 4 can be set on the test pins 3 corresponding to the part of the device pins 5. For other test pins 3, the existing common form can be used. Of course, the electromagnetic shield 4 can also be set on all test pins 3.

[0024] The electromagnetic shield 4 comprises a first insulating ring 41, a shield inner ring 42, a second insulating ring 43, a voltage fast stabilization shield ring 44, a third insulating ring 45 and a ground shield ring 46 arranged from inside to outside, as shown in the drawings. Figure 3 ​As shown, the first insulating ring 41, the shielding inner ring 42, the second insulating ring 43, the voltage fast stabilization shielding ring 44, the third insulating ring 45 and the grounding shielding ring 46 are concentrically distributed with the test pin 3, the shielding inner ring 42, the voltage fast stabilization shielding ring 44 and the grounding shielding ring 46 can adopt the shielding materials commonly used at present, the first insulating ring 41, the second insulating ring 43 and the third insulating ring 45 can adopt the insulating isolation materials commonly used at present, the shielding inner ring 42 is insulated and isolated from the test pin 3 through the first insulating ring 41, the shielding inner ring 42 is insulated and isolated from the voltage fast stabilization shielding ring 44 through the second insulating ring 43, and the grounding shielding ring 46 is insulated and isolated from the voltage fast stabilization shielding ring 44 through the third insulating ring 45; in addition, the electromagnetic shielding body 4 can also be set to be flat to reduce the protruding height of the electromagnetic shielding body 4 on the circuit board, and for the test pin 3, the width of one end connected with the device end pin 5 of the chip 1 to be tested is small, and the width gradually increases in the direction pointing to the other end of the test pin 3, as shown. Figure 2

[0025] By setting the electromagnetic shielding body 4 on the test pin 3, the influence of the environment on the test pin 3 in the test can be reduced to meet the measurement needs of the fA level leakage current in mass production. In order to improve the measurement efficiency in mass production, the shielding control circuit is also electrically connected to the electromagnetic shielding body 4, and the grounding shielding ring 46 is grounded. The shielding control circuit makes the grounding shielding ring 46 always in a grounded state, and during the test, the shielding control circuit first controls the potential of the voltage fast stabilization shielding ring 44 to be quickly stabilized to the same potential as the test pin 3, and then controls the potential of the shielding inner ring 42 to be the same as the potential of the test pin 3 until the end of the leakage current measurement. Specifically, after the potential of the voltage fast stabilization shielding ring 44 is the same as the potential of the test pin 3 surrounded by the ring, the shielding control circuit makes the potential of the voltage fast stabilization shielding ring 44 stable at the same potential as the test pin 3, and then the shielding control circuit makes the potential of the shielding inner ring 42 the same as the potential of the test pin 3. When the potentials of the shielding inner ring 42 and the voltage fast stabilization shielding ring 44 are the same as the potential of the test pin 3 surrounded by the ring, stable and accurate measurement of the fA level leakage current of the device end pin 5 can be realized. The electromagnetic shielding body 4 can quickly enter a shielding steady state, that is, the steady state time during the entire measurement can be greatly shortened, thereby shortening the time for the current measurement device 2 to measure the corresponding fA level leakage current through the test pin 3 and improving the measurement efficiency.

[0026] ​The shielding control circuit comprises a sample-and-hold circuit 6, a shielding inner ring control circuit electrically connected to the sample-and-hold circuit 6, and a stable shielding ring control circuit 7 electrically connected to the voltage fast stable shielding ring 44 and used to control the potential of the voltage fast stable shielding ring 44 to be fast stabilized at the same potential of the test golden finger 3. The shielding inner ring control circuit is electrically connected to the shielding inner ring 42, and a square wave signal output by the shielding inner ring control circuit is used to charge a capacitor formed by the shielding inner ring 42, the first insulating ring 41 and the test golden finger 3. After the charging is completed, the shielding inner ring control circuit stops outputting the square wave signal and loads a constant shielding inner ring control voltage onto the shielding inner ring 42, so that the potential of the shielding inner ring 42 is the same as that of the test golden finger 3 until the leakage current measurement is completed. The sample-and-hold circuit 6 is used to sample a shielding drive signal and control the working states of the shielding inner ring control circuit and the stable shielding ring control circuit 7 according to the sampling state of the shielding drive signal. Specifically, the shielding drive signal can be a voltage signal of an input protection pin of the chip under test 1 or a voltage signal sampled from the test golden finger 3. When the chip under test 1 has an input protection pin, the shielding drive signal is the voltage signal of the input protection pin of the chip under test 1. Specifically, the voltage of the input protection pin is configured to be consistent with the voltage of the test golden finger 3 in the chip under test 1. When the chip under test 1 does not have an input protection pin, the voltage signal of the test golden finger 3 can be obtained by using an existing method (such as a buffer circuit). The specific method can be determined according to the actual situation. Therefore, the sample-and-hold circuit 6 obtains the shielding drive signal in different ways according to the specific packaging form of the chip under test 1, but can control the potential of the shielding inner ring 42 and the voltage fast stable shielding ring 44 to be the same as that of the test golden finger 3 according to the obtained shielding drive signal, so as to meet the measurement requirement of the fA-level leakage current.

[0027] Specifically, as Figure 4As shown, the sample and hold circuit 6 comprises a first NMOS tube Q1, a second NMOS tube Q2 and a fifth capacitor C5, the drain terminal of the first NMOS tube Q1 is electrically connected with the shield driving signal, the source terminal of the first NMOS tube Q1 is electrically connected with the source terminal of the second NMOS tube Q2, the first terminal of the fifth capacitor C5, the shield inner ring control circuit and the stable shield ring control circuit respectively, the drain terminal of the second NMOS tube Q2 and the second terminal of the fifth capacitor C5 are grounded; when the first NMOS tube Q1 is turned on and the second NMOS tube Q2 is turned off, the shield driving signal charges the fifth capacitor C5; when the first NMOS tube Q1 and the second NMOS tube Q2 are both turned off, at this time, the capacitor voltage of the fifth capacitor C5 is used to drive the shield inner ring control circuit and the stable shield ring control circuit 7 to be in the corresponding working state; when the first NMOS tube Q1 is turned off and the second NMOS tube Q2 is turned on, the fifth capacitor C5 is discharged, and after the discharge of the fifth capacitor C5 is completed, the working state of the shield inner ring control circuit and the stable shield ring control circuit 7 is turned off, and the corresponding potential on the shield inner ring 42 and the voltage fast stable shield ring 44 is also zero.

[0028] The stable shield ring control circuit 7 comprises a first operational amplifier U1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first resistor R1 and a second resistor R2, the non-inverting terminal of the first operational amplifier U1 is electrically connected with the first terminal of the fifth capacitor C5, the source terminal of the first NMOS tube Q1 and the source terminal of the second NMOS tube Q2, the positive power supply terminal of the first operational amplifier U1 is grounded through the second capacitor C2, the negative power supply terminal of the first operational amplifier U1 is grounded through the first capacitor C1, the inverting terminal of the first operational amplifier U1 is electrically connected with one end of the second resistor R2, the other end of the second resistor R2 is electrically connected with the output terminal of the first operational amplifier U1 and one end of the first resistor R1 respectively, the other end of the first resistor R1 is electrically connected with one end of the third capacitor C3 to form a stable shield ring control output terminal Vout1, the stable shield ring control output terminal Vout1 is electrically connected with the voltage fast stable shield ring 44, and the other end of the third capacitor C3 is grounded.

[0029] The first operational amplifier U1 can adopt a commonly used high-precision operational amplifier or a high-bandwidth operational amplifier. When the first NMOS tube Q1 and the second NMOS tube Q2 in the sample and hold circuit 6 are both in the off state, the capacitor voltage of the fifth capacitor C5 is loaded to the non-inverting terminal of the first operational amplifier U1, at this time, the voltage of the voltage fast stable shield ring 44 is the same as the voltage of the test golden finger 3; when the fifth capacitor C5 is in the discharge state, the stable shield ring control circuit is in the non-working state. Figure 4 It can be known that the first operational amplifier U1 works in the voltage follower state, therefore, the voltage consistent with the shield driving signal can be obtained through the stable shield ring control output terminal Vout1.

[0030] The shielded inner ring control circuit includes a square wave signal generating circuit 8 and a constant voltage generating circuit 9, and the constant voltage generating circuit 9 is electrically connected with the square wave signal generating circuit 8 and the sample and hold circuit 6, in particular:

[0031] The square wave signal generating circuit 8 includes a second operational amplifier U2, a fourth capacitor C4, a third resistor R3, a first variable resistor R9, a second variable resistor R10 and a third NMOS tube Q3, the same phase end of the second operational amplifier U2 is electrically connected with one end of the third resistor R3 and one end of the first variable resistor R9, the other end of the third resistor R3 is grounded, the other end of the first variable resistor R9 is electrically connected with the output end of the second operational amplifier U2 and the drain end of the third NMOS tube Q3, the opposite phase end of the second operational amplifier U2 is electrically connected with one end of the second variable resistor R10 and one end of the fourth capacitor C4, the other end of the fourth capacitor C4 is grounded, the other end of the second variable resistor R10 is electrically connected with the output end of the second operational amplifier U2 and the drain end of the third NMOS tube Q3, and the source end of the third NMOS tube Q3 is electrically connected with the constant voltage generating circuit;

[0032] The constant voltage generating circuit 9 includes a third operational amplifier U3, a fourth NMOS tube Q4, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a fifth resistor R5 and a sixth resistor R6, the same phase end of the third operational amplifier U3 is electrically connected with the first end of the fifth capacitor C5, the source end of the first NMOS tube Q1 and the source end of the second NMOS tube Q2, the opposite phase end of the third operational amplifier U3 is electrically connected with one end of the fifth resistor R5, the other end of the fifth resistor R5 is electrically connected with the output end of the third operational amplifier U3 and one end of the sixth resistor R6, the negative power supply end of the third operational amplifier U3 is grounded through the sixth capacitor C6, the positive power supply end of the third operational amplifier U3 is grounded through the seventh capacitor C7, the other end of the sixth resistor R6 is electrically connected with one end of the eighth capacitor C8 and the drain end of the fourth NMOS tube Q4, the other end of the eighth capacitor C8 is grounded, and the source end of the fourth NMOS tube Q4 is electrically connected with the source end of the third NMOS tube Q3 to form a shielded inner ring control output end Vout2, and the shielded inner ring control output end Vout2 is electrically connected with the shielded inner ring 42.

[0033] The second operational amplifier U2 and the third operational amplifier U3 in the shielded inner loop control circuit use the same high-bandwidth operational amplifier. The square wave generated by the square wave signal generation circuit 8 can be adjusted through the first variable resistor R9 and the second variable resistor R10. The output state of the square wave signal generation circuit 8 can be controlled through the third NMOS transistor Q3. When the third NMOS transistor Q3 is on and the fourth NMOS transistor Q4 is off, the square wave signal generated by the square wave signal generation circuit 8 can be loaded onto the shielded inner loop 42 through the shielded inner loop control output terminal Vout2. When the third NMOS transistor Q3 is off and the fourth NMOS transistor Q4 is on, the voltage generated by the constant voltage generation circuit 9 is loaded onto the shielded inner loop 42 through the shielded inner loop control output terminal Vout2. Furthermore, the constant voltage generation circuit 9, through the third operational amplifier U3, can quickly make the shielded inner loop 42 obtain the corresponding voltage through the shielded inner loop control output terminal Vout2, thus rapidly raising the potential of the shielded inner loop 42 to the same potential as the test gold finger 3. Figure 4 As can be seen, the third operational amplifier U3 operates in voltage follower mode. Therefore, the voltage consistent with the shielded drive signal can be obtained by controlling the output terminal Vout2 through the shielded inner loop.

[0034] In practice, the operating states of the first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3, and the fourth NMOS transistor Q4 are all controlled by corresponding timing control signals, such as... Figure 5 The diagram shows a sequence control circuit generating timing control signals. The timing control circuit can use a commonly used circuit configuration. The timing signals Q1, Q2, Q3, and Q4 generated by the timing control circuit correspond one-to-one with the first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3, and the fourth NMOS transistor Q4, respectively. The specific details of the timing signals Q1, Q2, Q3, and Q4 are as follows: Figure 6 As shown, when timing signal Q1 is high, the first NMOS transistor Q1 is turned on; when timing signal Q2 is high, the second NMOS transistor Q2 is turned on; when timing signal Q3 is high, the third NMOS transistor Q3 is turned on; and when timing signal Q4 is high, the fourth NMOS transistor Q4 is turned on. Figure 6 The diagram shows a complete cycle of measuring fA-level leakage current. By controlling the operation of the entire shielding control circuit through timing control signals, the measurement time under stable conditions can be significantly shortened and the measurement efficiency improved while meeting the requirements of mass production testing of fA-level leakage current.

[0035] like Figure 7As shown, the high-bandwidth operational amplifier comprises a voltage comparator U4, a CMOS input operational amplifier U5, a JFET input operational amplifier U6, an inverter U7, a push-pull output circuit U8 and a ninth capacitor C9, the non-inverting terminal of the JFET input operational amplifier U6, the non-inverting terminal of the CMOS input operational amplifier U5 and the first voltage negative terminal of the voltage comparator U4 are connected to each other to form the non-inverting terminal of the high-bandwidth operational amplifier, the inverting terminal of the JFET input operational amplifier U6, the inverting terminal of the CMOS input operational amplifier U5 and the second voltage negative terminal of the voltage comparator U4 are connected to each other to form the inverting terminal of the high-bandwidth operational amplifier, the voltage positive terminal of the voltage comparator U4 is connected to a reference voltage Vref, the output terminal of the voltage comparator U4 is electrically connected to the enable terminal of the JFET input operational amplifier U6 and the input terminal of the inverter U7, the output terminal of the inverter U7 is electrically connected to the enable terminal of the CMOS input operational amplifier U5; the output terminal of the JFET input operational amplifier U6 and the output terminal of the CMOS input operational amplifier U5 are both electrically connected to the input terminal of the push-pull output circuit U8 and one end of the ninth capacitor C9, and the output terminal of the push-pull output circuit U8 and the other end of the ninth capacitor C9 are connected to each other to form the output terminal of the high-bandwidth operational amplifier.

[0036] Among them: the voltage comparator U4, the CMOS input operational amplifier U5 and the JFET input operational amplifier U6 can all adopt the existing common circuit form, and the size of the reference voltage Vref can be selected as needed. The first voltage negative terminal and the second voltage negative terminal of the voltage comparator U4 are the common-mode voltage signals of the entire high-bandwidth operational amplifier, when the common-mode voltage signal is lower than the reference voltage Vref, the JFET input operational amplifier U6 is in working state, and when the common-mode voltage signal is higher than the reference voltage Vref, the CMOS input operational amplifier U5 is in working state. In the working interval of the high-bandwidth operational amplifier, the working of the JFET input operational amplifier U6 is taken as the standard, therefore, according to the working characteristics of the JFET input operational amplifier U6, the high-bandwidth operational amplifier has the characteristics of high bandwidth and high slew rate. The push-pull output circuit U8 forms a push-pull output stage, and the push-pull output circuit U8 can adopt the existing common push-pull output form.

[0037] In addition, when the first operational amplifier U1 adopts the high-bandwidth operational amplifier, the circuit form of the above high-bandwidth operational amplifier can also be adopted.

[0038] The protection scope of the present application includes but is not limited to the above embodiments, and the protection scope is subject to the claims, any replacement, deformation and improvement of the present technology which is easily thought by the skilled in the art falls within the protection scope of the present application.

Claims

1. A test connection device for mass production testing of fA-level current, used to connect a chip under test (DUT) and a current measuring device, comprising a test gold finger and an electromagnetic shield surrounding the test gold finger, wherein one end of the test gold finger is electrically connected to a pin of the DUT, and the other end of the test gold finger is electrically connected to the current measuring device, characterized in that: The electromagnetic shielding body comprises, from the inside out, a first insulating ring, an inner shielding ring, a second insulating ring, a voltage fast stabilization shielding ring, a third insulating ring, and a grounding shielding ring. A shielding control circuit is electrically connected to the electromagnetic shielding body, ensuring that the grounding shielding ring is always grounded. The shielding control circuit includes a sample-and-hold circuit and an inner shielding ring control circuit and a stabilizing shielding ring control circuit, both electrically connected to the sample-and-hold circuit. The sample-and-hold circuit samples and holds the shielding drive signal. The inner shielding ring control circuit is electrically connected to the inner shielding ring and controls the potential of the inner shielding ring relative to the voltage of the test gold finger. The voltage fast stabilization shielding ring control circuit is electrically connected to the voltage fast stabilization shielding ring, and is used to control the potential of the voltage fast stabilization shielding ring to quickly stabilize at the same potential as the test gold finger. During testing, the shielding control circuit first controls the potential of the voltage fast stabilization shielding ring to be the same as the potential of the test gold finger, and then controls the potential of the inner shielding ring to be the same as the potential of the test gold finger, until the measurement ends. This allows the electromagnetic shielding body to quickly enter the shielding steady state, greatly shortening the steady-state time during the entire measurement, thereby shortening the time for the current measuring device to measure the corresponding fA level leakage current through the test gold finger, and improving measurement efficiency.

2. The test connection device for mass production testing of fA-level current as described in claim 1, characterized in that: The first insulating ring, inner shielding ring, second insulating ring, voltage fast stabilization shielding ring, third insulating ring, and grounding shielding ring are all concentrically distributed with the test gold fingers.

3. The test connection device for mass production testing of fA-level current as described in claim 1, characterized in that: The sample-and-hold circuit includes a first NMOS transistor (Q1), a second NMOS transistor (Q2), and a fifth capacitor (C5). The drain of the first NMOS transistor (Q1) is electrically connected to the shielding drive signal. The source of the first NMOS transistor (Q1) is electrically connected to the source of the second NMOS transistor (Q2), the first terminal of the fifth capacitor (C5), the shielding inner loop control circuit, and the stable shielding loop control circuit. The drain of the second NMOS transistor (Q2) and the second terminal of the fifth capacitor (C5) are both grounded.

4. The test connection device for mass production testing of fA-level current as described in claim 3, characterized in that: The stable shielding ring control circuit includes a first operational amplifier (U1), a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a first resistor (R1), and a second resistor (R2). The non-inverting input of the first operational amplifier (U1) is electrically connected to the first terminal of the fifth capacitor (C5), the source terminal of the first NMOS transistor (Q1), and the source terminal of the second NMOS transistor (Q2). The positive power supply terminal of the first operational amplifier (U1) is grounded through the second capacitor (C2), and the negative power supply terminal of the first operational amplifier (U1) is grounded through the first capacitor. (C1) is grounded. The inverting input of the first operational amplifier (U1) is electrically connected to one end of the second resistor (R2). The other end of the second resistor (R2) is electrically connected to the output terminal of the first operational amplifier (U1) and one end of the first resistor (R1). The other end of the first resistor (R1) is electrically connected to one end of the third capacitor (C3) to form a stable shielding ring control output terminal (Vout1). The stable shielding ring control output terminal (Vout1) is electrically connected to the voltage fast stabilization shielding ring. The other end of the third capacitor (C3) is grounded.

5. A test connection device for mass production testing of fA-level current as described in claim 3, characterized in that: The shielded inner loop control circuit includes a square wave signal generation circuit and a constant voltage generation circuit, wherein the constant voltage generation circuit is electrically connected to the square wave signal generation circuit and the sample-and-hold circuit, respectively.

6. The test connection device for mass production testing of fA-level current as described in claim 5, characterized in that: The square wave signal generation circuit includes a second operational amplifier (U2), a fourth capacitor (C4), a third resistor (R3), a first variable resistor (R9), a second variable resistor (R10), and a third NMOS transistor (Q3). The non-inverting input of the second operational amplifier (U2) is electrically connected to one end of the third resistor (R3) and one end of the first variable resistor (R9), respectively. The other end of the third resistor (R3) is grounded. The other end of the first variable resistor (R9) is electrically connected to the output terminal of the second operational amplifier (U2) and the drain terminal of the third NMOS transistor (Q3). The inverting input of the second operational amplifier (U2) is electrically connected to one end of the second variable resistor (R10) and one end of the fourth capacitor (C4), respectively. The other end of the fourth capacitor (C4) is grounded. The other end of the second variable resistor (R10) is electrically connected to the output terminal of the second operational amplifier (U2) and the drain terminal of the third NMOS transistor (Q3). The source terminal of the third NMOS transistor (Q3) is electrically connected to the constant voltage generation circuit.

7. A test connection device for mass production testing of fA-level current as described in claim 6, characterized in that: The constant voltage generation circuit includes a third operational amplifier (U3), a fourth NMOS transistor (Q4), a sixth capacitor (C6), a seventh capacitor (C7), an eighth capacitor (C8), a fifth resistor (R5), and a sixth resistor (R6). The non-inverting input of the third operational amplifier (U3) is electrically connected to the first terminal of the fifth capacitor (C5), the source terminal of the first NMOS transistor (Q1), and the source terminal of the second NMOS transistor (Q2). The inverting input of the third operational amplifier (U3) is electrically connected to one end of the fifth resistor (R5), and the other end of the fifth resistor (R5) is connected to the output terminal of the third operational amplifier (U3) and the sixth resistor (R6). One end of the resistor (R6) is electrically connected. The negative power supply terminal of the third operational amplifier (U3) is grounded through the sixth capacitor (C6). The positive power supply terminal of the third operational amplifier (U3) is grounded through the seventh capacitor (C7). The other end of the sixth resistor (R6) is electrically connected to one end of the eighth capacitor (C8) and the drain terminal of the fourth NMOS transistor (Q4). The other end of the eighth capacitor (C8) is grounded. The source terminal of the fourth NMOS transistor (Q4) is electrically connected to the source terminal of the third NMOS transistor (Q3) to form the shielded inner loop control output terminal (Vout2). The shielded inner loop control output terminal (Vout2) is electrically connected to the shielded inner loop.

8. A test connection device for mass production testing of fA-level current as described in claim 7, characterized in that: Both the second operational amplifier (U2) and the third operational amplifier (U3) are high-bandwidth operational amplifiers. The high-bandwidth operational amplifier includes a voltage comparator (U4), a CMOS input operational amplifier (U5), a JFET input operational amplifier (U6), an inverter (U7), a push-pull output circuit (U8), and a ninth capacitor (C9). The non-inverting input of the JFET input operational amplifier (U6), the non-inverting input of the CMOS input operational amplifier (U5), and the first negative voltage terminal of the voltage comparator (U4) are interconnected to form the non-inverting input of the high-bandwidth operational amplifier. The inverting input of the JFET input operational amplifier (U6), the inverting input of the CMOS input operational amplifier (U5), and the second negative voltage terminal of the voltage comparator (U4) are interconnected to form... The high-bandwidth operational amplifier's inverting input and the voltage comparator (U4)'s positive voltage terminal are connected to a reference voltage (Vref). The output of the voltage comparator (U4) is electrically connected to the enable terminal of the JFET input operational amplifier (U6) and the input terminal of the inverter (U7). The output of the inverter (U7) is electrically connected to the enable terminal of the CMOS input operational amplifier (U5). The outputs of the JFET input operational amplifier (U6) and the CMOS input operational amplifier (U5) are both electrically connected to the input of the push-pull output circuit (U8) and one end of the ninth capacitor (C9). The output of the push-pull output circuit (U8) and the other end of the ninth capacitor (C9) are interconnected to form the output of the high-bandwidth operational amplifier.

9. A test connection device for mass production testing of fA-level currents as described in claim 1, characterized in that: The shielding drive signal is the voltage signal of the input protection pin of the chip under test, or the voltage signal sampled by the test gold finger.

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