A digital correction and compensation circuit for oscilloscope

Abstract

The invention discloses a digital correction and compensation circuit for an oscilloscope, belonging to the field of digital technology. The invention adopts a digital correction and compensation method inside an FPGA to replace the traditional analog device and software compensation and correction; the automatic calibration of the gain and bias of the data acquisition module ADC can be realized, the calibration accuracy is high, the calibration speed is fast, and the accuracy and effectiveness of the calibration are improved; the amplitude compensation of the oscilloscope is realized in a digital way, the bandwidth of the oscilloscope can be improved, the amplitude-frequency response optimization is optimized, and the amplitude flatness reaches ±1dB; the noise reduction filtering is realized in a digital way, and six digital filtering gears such as 20MHz, 250MHz, 500MHz, 1GHz, 1.5GHz, and 2GHz can be realized; the waveform reconstruction is realized in a digital way, and the minimum time base of the oscilloscope can reach 5ps / div, and the digital interpolation multiple is up to 2000 times; the invention can be extended and applied to oscilloscopes with higher bandwidth and higher sampling rate.

Description

Technical Field

[0001] The invention belongs to the field of digital technology, and in particular relates to a digital correction and compensation circuit for an oscilloscope. Background Art

[0002] In order to solve the various errors caused by the hardware circuit limitations of the oscilloscope, domestic oscilloscopes mainly implement the waveform reconstruction module in the CPU-side software mode to solve the problem of insufficient sampling rate of the fast time base gear resulting in a small number of sampling points and inability to fill the display area. The bandwidth and flatness optimization module is implemented in the CPU-side software mode to solve the frequency response flatness problem of the oscilloscope. The analog noise reduction and filtering module is used to reduce the background noise of the oscilloscope through relay switches and analog filters.

[0003] In order to solve the problem that the sampling rate of the fast time base gear is insufficient and the sampling points cannot fill the display area, the existing technical solution uses the CPU-side software to perform software interpolation on the sampled data. The oscilloscope stores the sampled raw data in the memory, and transmits the sampled data to the CPU memory under the control of the clock and trigger signal. The CPU calculates the interpolation point through the software interpolation algorithm on the CPU side according to the screen display area and the number of sampling points in the memory, and then sends it to the screen for display.

[0004] In view of the problem that the flatness of the frequency response tends to deteriorate when approaching the bandwidth limit of the oscilloscope, the oscilloscope has amplitude attenuation at certain frequency points and amplitude amplification at certain frequency points, the existing technical solution uses CPU-side software to compensate the sampled data. The oscilloscope stores the sampled raw data in the memory, and transmits the actual sampled data to the CPU memory under the control of the clock and trigger signal. The CPU compares the data in the memory with the data output by the standard source, and calibrates the actual sampled data in the memory to the ideal value of the standard source through compensation processing.

[0005] In order to solve the problem of high background noise of broadband oscilloscopes, when testing signals with lower bandwidth or signals with relatively slow edge rates, the existing technical solution uses a relay switch combined with analog filters of different bandwidths to reduce the background noise. The existing analog filter noise reduction technology generally has only two gears: 20MHz and 200MHz.

[0006] The existing oscilloscope correction circuit and method are mainly implemented by analog circuit and CPU-side software post-processing. The existing technical solutions use more analog filters and relays for development, which occupy a large circuit area, consume a lot of power and are costly. At the same time, the CPU-side software post-processing method requires that all the sampling data of the oscilloscope be transferred to the memory of the CPU before data compensation and correction can be performed. The entire data processing process adopts a serial method, which has a slow processing speed and low efficiency, reduces the screen waveform refresh speed of the oscilloscope, increases the dead time of acquisition, and reduces the real-time performance of the oscilloscope. Summary of the invention

[0007] In view of the above technical problems existing in the prior art, the present invention proposes a digital correction and compensation circuit for an oscilloscope, which has a reasonable design, overcomes the shortcomings of the prior art, and has good effects.

[0008] In order to achieve the above object, the present invention adopts the following technical solution:

[0009] A digital correction and compensation circuit for an oscilloscope comprises a calibration signal generation module, an analog front-end conditioning module, a data acquisition module, a digital signal processing module and an embedded CPU module; wherein the digital signal processing module is a core module;

[0010] The calibration signal generation module is configured to generate the fast edge and sine wave signals required for oscilloscope calibration, with a signal amplitude of 500mVpp, a fast edge signal frequency of a fixed 1kHz, a sine wave frequency of 10MHz to 2.5GHz, and a frequency adjustment step of 10MHz;

[0011] The analog front-end conditioning module is configured to condition the oscilloscope channel input signal CH and the calibration signal; the input frequency range of the analog front-end conditioning module is DC to 2.5 GHz, the amplitude range is 4 mVpp to 8 Vpp, the output frequency range is DC to 2.5 GHz, and the amplitude range is 2.35 mV to 600 mVpp;

[0012] A data acquisition module is configured to acquire a signal output by the analog front-end conditioning module;

[0013] A digital signal processing module, configured to process a digital signal;

[0014] The embedded CPU module is configured to communicate with the CPU interactive control unit interface of the digital signal processing module through the PCIe2.0 interface to achieve the interaction and transmission of control commands and collected data.

[0015] Preferably, the calibration signal generating module comprises a fast edge signal generating unit, a sinusoidal signal generating unit and a first switch selecting unit;

[0016] A fast edge signal generating unit is configured to generate a fast edge signal required for gain and phase calibration of an ADC in a data acquisition module;

[0017] The sine signal generating unit is configured to generate a sine wave signal required by the bandwidth and flatness optimizing unit in the digital signal processing module, the maximum frequency of which is 1 / 4 of the ADC sampling rate in the back-end data acquisition module;

[0018] The first switch selection unit is configured to switch the output of the fast edge signal and the sinusoidal signal, and outputs a calibration signal JZ with an amplitude of 500mVpp.

[0019] Preferably, the analog front-end conditioning module comprises a second switch selection unit, an attenuator unit and an amplifier unit;

[0020] The second switch selection unit is configured to realize the selection of the oscilloscope channel input signal CH and the calibration signal ZJ generated by the calibration signal generation module; when the oscilloscope selects the calibration signal ZJ, the oscilloscope is in the automatic calibration mode, realizing the self-calibration of the ADC in the data acquisition module and the automatic generation of the correction filter coefficient in the bandwidth and flatness optimization unit in the digital signal processing module, the ZJ signal comes from the calibration signal generation module inside the oscilloscope, and the amplitude is 500mVpp; when the oscilloscope selects the channel signal CH, the oscilloscope can realize the normal measurement of the object under test, the amplitude of the CH signal is 4mVpp~8Vpp, and the signal frequency is the bandwidth of the oscilloscope, that is, DC~2.5GHz;

[0021] The attenuator unit is configured to attenuate the CH signal. If the input channel signal amplitude is 600mVpp to 8Vpp, it exceeds the full-scale range of the ADC in the data acquisition module. The full-scale voltage of the ADC is 600mVpp, and the attenuator module performs attenuation, and the attenuation multiple is CH / 600mV.

[0022] The amplifier unit is configured to amplify the CH signal. If the input channel signal amplitude is 4mVpp to 600mVpp, which is lower than the full-scale range of the ADC in the data acquisition module, and the full-scale voltage of the ADC is 600mVpp, the amplifier unit amplifies the signal with an amplification factor of 600mV / CH.

[0023] Preferably, the data acquisition module comprises a clock generation unit and an ADC unit;

[0024] A clock generating unit, configured to generate a 5 GHz clock for the ADC unit;

[0025] The ADC unit is configured to convert the analog signal CH of the channel into a digital signal, and then send it to the back-end digital signal processing unit for data post-processing.

[0026] Preferably, the clock generation unit uses the digital integrated phase-locked loop LMX2952 frequency synthesizer; the ADC unit uses the AAD08S010GA chip, which realizes the conversion of analog to digital signals with a sampling rate of 10GSa / s and a vertical resolution of 8bit, and outputs an 80Gbps data stream. In order to realize the reception of the back-end digital signal processing unit, the data stream generates a 2.5Gbps*32 low-speed data stream inside the ADC. When the ADC outputs, it adopts a double-edge output mode, the output clock is 1.25GHz, and the data stream bit is 32-bit wide D[31:0], which is sent to the back-end digital signal processing module.

[0027] Preferably, the digital signal processing module adopts an FPGA of model XCKU060-2FFVA1517I, including a data preprocessing unit, a bandwidth and frequency response optimization unit, a noise reduction filter unit, a data selector, a data storage control unit, a waveform reconstruction unit and a CPU interaction control unit;

[0028] A data preprocessing unit, configured to process the data;

[0029] The bandwidth and frequency response optimization unit is configured to improve the voltage characteristics of the oscilloscope waveform in the vertical direction. The user can choose to turn on or off the bandwidth and frequency response optimization unit. When it is turned off, the front-end data preprocessing unit directly sends the 312.5MHz 256-bit data stream DZ[255:0] to the back-end for subsequent processing. When it is turned on, the front-end data preprocessing unit directly sends the 312.5MHz 256-bit data stream DZ[255:0] to the bandwidth and frequency response optimization unit for processing.

[0030] The noise reduction filter unit includes a noise reduction filter coefficient RAM, a CIC extraction filter, a FIR filter and a CIC interpolation filter; the user can choose to turn the noise reduction filter unit on or off; when the option is turned off, the front-end 312.5MHz 256-bit data stream DZ[255:0] is directly sent to the back-end for subsequent processing; when the option is turned on, the front-end 312.5MHz 256-bit data stream DZ[255:0] is sent to the noise reduction filter unit for processing; the user can select six digital low-pass filters including 20MHz, 250MHz, 500MHz, 1GHz, 1.5GHz and 2GHz. The six digital filters are realized by using different CIC+FIR cascade combinations and filter coefficient selections; when the user selects a bandwidth limit with a larger passband range of 1.5GHz or 2GHz, The oscilloscope enables some CIC extraction, FIR filtering and CIC interpolation filters according to the selection and delays the data to achieve signal synchronization with the channel that does not enable bandwidth limitation. When the user selects a lower passband range of 20MHz or 250MHz, the oscilloscope will enable the back-end CIC extraction + FIR filtering + CIC interpolation cascade module. First, the sampled signal is extracted by a power of 2 to reduce the data flow rate to an acceptable operating frequency for the FIR filter. The FIR filter multiplies and adds the input signal with the preset filter coefficient. Finally, the interpolation CIC module completes the interpolation processing of the filtered signal to generate data with the same total bit width, that is, the 312.5MHz 256-bit data stream DZ[255:0] passes through the noise reduction filter unit and outputs a new 312.5MHz 256-bit data stream DJZ[255:0].

[0031] The waveform reconstruction unit is configured to improve the time characteristics of the oscilloscope waveform in the horizontal direction. The user can choose to turn on or off the waveform reconstruction unit. When it is turned off, the front-end noise reduction filter unit directly stores the 312.5MHz 256-bit data stream DJZ[255:0] in the RAM memory inside the FPGA under the control of the data storage control unit; when it is turned on, the front-end noise reduction filter unit directly sends the 312.5MHz 256-bit data stream DJZ[255:0] to the waveform reconstruction unit for processing;

[0032] The data storage control unit is configured to store the 312.5MHz 256-bit data stream DCJ[255:0] output by the waveform reconstruction unit into the memory RAM inside the FPGA; the embedded CPU module sends the sampled data DCJ[255:0] to the display screen for display via the CPU interface interaction control unit in the digital signal processing module;

[0033] A CPU interaction control unit is configured for use with an embedded CPU module and a digital.

[0034] Preferably, the data preprocessing unit comprises a data receiving unit, a speed reduction processing unit and a data reassembly unit;

[0035] The data receiving unit is configured to receive the 1.25 GHz dual clock edge and 32-bit data stream D[31:0] output by the data acquisition module, and convert the differential input signal into a single-ended signal output, and convert the single-ended signal into a 1.25 GHz single clock edge 64-bit data stream DY[63:0];

[0036] The speed reduction processing unit is configured to convert the 64-bit data stream DY[63:0] of 1.25 GHz into a 256-bit data stream DJ[255:0] of a lower rate of 312.5 MHz to meet the clock requirement of the internal data processing of the FPGA;

[0037] The data reassembly unit is configured to realize the re-combination and arrangement of the 256-bit data stream DJ[255:0] of 312.5MHz, and arranges and reassembles it according to the sampling sequence of the sampling clock to form a new 256-bit data stream DZ[255:0] of 312.5MHz.

[0038] Preferably, the bandwidth and frequency response have an optimization unit, including an amplitude correction filter coefficient RAM and a FIR filter unit;

[0039] The FIR filter unit includes a multiplier and adder, a delay device and a lookup table of the MAC; the 312.5MHz 256-bit data stream DZ[255:0] is multiplied by the correction coefficient in the amplitude correction filter coefficient RAM, added to the MAC of the previous stage, and finally output to the lower-level MAC structure. After multi-stage FIR filtering, the corrected DYH[255:0] is output and sent to the back end for subsequent processing; wherein, the specific value of the correction filter coefficient in the amplitude correction filter coefficient RAM is automatically generated by the amplitude correction filter coefficient calculation unit of the embedded CPU module.

[0040] Preferably, the waveform reconstruction unit comprises a waveform reconstruction filter coefficient RAM and a FIR interpolation filter unit;

[0041] The FIR interpolation filter unit includes a MAC multiplier and adder, a delay device and a lookup table; the 312.5MHz 256-bit data stream DJZ[255:0] is multiplied by the correction coefficient in the waveform reconstruction filter coefficient RAM, added to the MAC of the previous stage, and finally output to the next-level MAC structure, and after multi-stage FIR interpolation filtering, the waveform reconstructed DCJ[255:0] is output and stored in the RAM memory inside the FPGA under the control of the data storage control unit; wherein, the specific value of the waveform reconstruction filter coefficient in the waveform reconstruction filter coefficient RAM is generated by the waveform reconstruction filter coefficient calculation unit of the embedded CPU module.

[0042] Preferably, the embedded CPU module includes an amplitude correction filter coefficient calculation unit, a noise reduction filter coefficient calculation unit, and a waveform reconstruction filter coefficient calculation unit;

[0043] The amplitude correction filter coefficient calculation unit is required to automatically generate the correction coefficient before the oscilloscope leaves the factory. It is configured to realize automatic compensation of the amplitude of the oscilloscope, thereby improving the bandwidth and optimizing the frequency response. Due to the differences in the hardware chips in the analog front-end conditioning module and the data acquisition module of the oscilloscope, the amplitude correction filter coefficients of each oscilloscope are different. Therefore, the amplitude correction filter coefficients of each oscilloscope must be automatically calculated before leaving the factory and saved in the hard disk of the oscilloscope.

[0044] The embedded CPU module controls the calibration signal generation module to output a sine wave signal with a frequency of 10MHz and an amplitude of 500mVpp, which is sent to the digital signal processing module for digital signal processing after passing through the analog front-end conditioning module and the data acquisition module; in the digital signal processing module, the data preprocessing unit works normally, while the bandwidth and frequency response optimization unit, the noise reduction filter unit, and the waveform reconstruction unit are all closed, and the oscilloscope stores the original sampling data of the data acquisition module in the memory of the CPU; in the same way, the calibration signal output is kept fixed at a sine wave signal of 500mVpp, and the frequency is stepped by 10MHz to 2.5GHz in turn. After multiple measurements, the collected original data records are organized into a curve Hy, and the ideal frequency response curve of the oscilloscope is Hj, then the amplitude correction filter coefficient is Hj / Hy, and the embedded CPU module stores the amplitude correction filter coefficient in the amplitude correction filter coefficient RAM of the digital signal processing module, and the bandwidth and frequency response optimization unit can achieve an amplitude flatness of ±1dB;

[0045] The noise reduction filter coefficient calculation unit is configured to realize the bandwidth limiting function of the oscilloscope. The noise reduction filter coefficient of each oscilloscope is fixed and is only related to the digital low-pass filter of the six gears of 20MHz, 250MHz, 500MHz, 1GHz, 1.5GHz and 2GHz selected by the user; the embedded CPU module stores the noise reduction filter coefficient calculated by the noise reduction filter coefficient calculation unit into the noise reduction filter coefficient RAM of the digital signal processing module; if the gear of the noise reduction filter changes and is not 20MHz, 250MHz, 500MHz, 1GHz, 1.5GHz, 2GHz, the noise reduction filter coefficient calculation unit of the embedded CPU module needs to recalculate it once and then store it into the noise reduction filter coefficient RAM of the digital signal processing module;

[0046] The waveform reconstruction filter coefficient calculation unit is configured to realize the digital interpolation function of the oscilloscope. The waveform reconstruction filter coefficient of each oscilloscope is fixed and is only related to the horizontal resolution of the LCD screen and the time base gear of the oscilloscope. The embedded CPU module stores the waveform reconstruction filter coefficient calculated by the waveform reconstruction filter coefficient calculation unit in the waveform reconstruction filter coefficient RAM of the digital signal processing module. If the horizontal resolution or the time base gear of the oscilloscope LCD screen changes, the waveform reconstruction filter coefficient calculation unit of the embedded CPU module needs to recalculate it once and then store it in the waveform reconstruction filter coefficient RAM of the digital signal processing module.

[0047] Beneficial technical effects brought by the present invention:

[0048] 1) Use digital correction and compensation inside FPGA to replace traditional analog devices and software compensation and correction;

[0049] 2) It can realize automatic calibration of the gain and bias of the ADC of the data acquisition module, with high calibration accuracy and fast calibration speed, thus improving the accuracy and effectiveness of calibration;

[0050] 3) Digitally realize the amplitude compensation of the oscilloscope, which can improve the bandwidth of the oscilloscope and optimize the amplitude-frequency response, and the amplitude flatness reaches ±1dB;

[0051] 4) Digital noise reduction filtering can be achieved, and six digital filtering gears including 20MHz, 250MHz, 500MHz, 1GHz, 1.5GHz, and 2GHz can be realized;

[0052] 5) Waveform reconstruction is realized by digital method. The minimum time base of the oscilloscope can reach 5ps / div, and the maximum digital interpolation multiple is 2000 times;

[0053] 6) The digital correction and compensation circuit and method can be extended to be applied to oscilloscopes with higher bandwidth and higher sampling rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 The present invention is a circuit principle block diagram for digital correction and compensation of an oscilloscope. DETAILED DESCRIPTION

[0055] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0056] Figure 1 This is a system composition block diagram of an oscilloscope digital correction and compensation circuit and method. The invention consists of five major parts, namely a calibration signal generation module, an analog front-end conditioning module, a data acquisition module, a digital signal processing module, and an embedded CPU module. The digital signal processing module includes a data preprocessing unit, a bandwidth and frequency response optimization unit, a noise reduction filter unit, a data storage control unit, a waveform reconstruction unit, a CPU control interaction unit, etc., and is the core module of the present invention.

[0057] 1. Calibration signal generation module

[0058] In the scheme, the calibration signal production module is mainly composed of three parts: a fast edge signal generation unit, a sinusoidal signal generation unit and a switch selection unit. The fast edge signal generation unit mainly generates the fast edge signal required for the gain and phase calibration of the ADC (AAD08S010GA) in the data acquisition module. The amplitude of the fast edge signal is generally 5 / 6 of the full scale of the back-end ADC. In this invention, the full scale of ADC is 600mVpp, and the amplitude of the fast edge signal is 500mVpp. The sinusoidal signal generation unit mainly generates the maximum frequency of the sinusoidal wave signal required by the bandwidth and flatness optimization unit in the digital signal processing module, which is 1 / 4 of the ADC sampling rate in the back-end data acquisition module. In this invention, the ADC sampling rate is 10GSa / s, and the maximum frequency of the sinusoidal signal is 2.5GHz, and the frequency stepping of the present invention is 1kHz. The amplitude of the sinusoidal signal is generally 5 / 6 of the full scale of the back-end ADC. In this invention, the full scale of ADC is 600mVpp, and the amplitude of the sinusoidal signal is 500mVpp. The switch selection is mainly used to switch the output of fast edge signal and sinusoidal signal, and the output amplitude is 500mVpp calibration signal JZ.

[0059] 2. Analog front-end conditioning module

[0060] In the scheme, the analog front-end conditioning module is mainly composed of three parts: the switch selection unit, the attenuator unit and the amplifier unit. The switch selection unit mainly realizes the selection of the oscilloscope channel input signal CH and the calibration signal ZJ generated by the calibration signal generation module. When the oscilloscope selects the calibration signal ZJ, the oscilloscope is in automatic calibration mode, realizing the self-calibration of the ADC in the data acquisition module and the automatic generation of the correction filter coefficient in the bandwidth and flatness optimization unit in the digital signal processing module. In this scheme, the ZJ signal comes from the calibration signal generation module inside the oscilloscope, with an amplitude of 500mVpp. When the oscilloscope selects the channel signal CH, the oscilloscope can realize normal measurement of the object under test. In this sub-scheme, the amplitude of the CH signal is 4mVpp~8Vpp, and the signal frequency is the bandwidth of the oscilloscope, that is, DC~2.5GHz. The attenuator unit mainly realizes the attenuation of the CH signal. If the input channel signal amplitude is 600mVpp~8Vpp, it exceeds the full-scale range of the ADC in the data acquisition module. In this solution, the full-scale range of the ADC is 600mVpp, so the attenuator module performs attenuation, and the attenuation multiple is CH / 600mV. The amplifier unit mainly realizes the amplification of the CH signal. If the input channel signal amplitude is 4mVpp~600mVpp, it is lower than the full-scale range of the ADC in the data acquisition module. In this solution, the full-scale range of the ADC is 600mVpp, so the amplifier unit performs amplification, and the amplification multiple is 600mV / CH.

[0061] 3. Data acquisition module

[0062] In the scheme, the data acquisition module mainly consists of two parts: the clock generation unit and the ADC unit. The clock generation unit mainly generates the 5GHz clock required by the back-end ADC. The digital integrated phase-locked loop LMX2952 frequency synthesizer is selected in the scheme to implement it. The ADC unit is called an analog-to-digital converter, which mainly converts the analog signal CH of the channel into a digital signal, and then sends it to the back-end digital signal processing unit for data post-processing. In the scheme, the ADC unit uses the AAD08S010GA chip, which realizes the conversion of analog to digital signals with a sampling rate of 10GSa / s and a vertical resolution of 8bit, and outputs an 80Gbps data stream. In order to realize the reception of the back-end digital signal processing unit, the data stream generates a low-speed data stream of 2.5Gbps*32 inside the ADC. When the ADC outputs, the double-edge output mode is adopted. Because the output clock is 1.25GHz, the data stream is 32-bit wide D[31:0] and sent to the back-end digital signal processing module.

[0063] 4. Digital signal processing module

[0064] In the scheme, the digital signal processing module is mainly composed of a data preprocessing unit, a bandwidth and frequency response optimization unit, a noise reduction filter unit, a data selector, a data storage control unit, a waveform reconstruction unit, and a CPU interaction control unit. The digital signal processing module is implemented using FPGA (XCKU060-2FFVA1517I).

[0065] The data preprocessing unit is mainly composed of data receiving, speed reduction processing and data reorganization units. In the scheme, the data receiving unit is mainly used to receive the 1.25GHz dual clock edge and 32-bit data stream D[31:0] output by the data acquisition module, and convert the differential input signal into a single-ended signal output, and convert the single-ended signal into a 1.25GHz single clock edge 64-bit data stream DY[63:0]. The speed reduction processing unit mainly converts the 1.25GHz 64-bit data stream DY[63:0] into a 312.5MHz 256-bit data stream DJ[255:0] with a lower rate to meet the clock requirements of the internal data processing of the FPGA. The data reorganization unit mainly realizes the recombination and arrangement of the 312.5MHz 256-bit data stream DJ[255:0]. It arranges and reorganizes according to the sampling order of the sampling clock to form a new 312.5MHz 256-bit data stream DZ[255:0].

[0066] The bandwidth and frequency response optimization unit is mainly composed of the amplitude correction filter coefficient RAM and the FIR filter unit. In the solution, the bandwidth and frequency response optimization unit is a software function of the oscilloscope, which mainly improves the voltage characteristics of the oscilloscope waveform in the vertical direction. The user can choose to turn on or off the bandwidth and frequency response optimization unit. When it is turned off, the front-end data preprocessing unit sends the 312.5MHz 256-bit data stream DZ[255:0] directly to the back-end for subsequent processing. When it is turned on, the front-end data preprocessing unit sends the 312.5MHz 256-bit data stream DZ[255:0] directly to the bandwidth and frequency response optimization unit for processing. This unit is mainly implemented using FIR digital filters, and the FIR filter is mainly composed of MAC multipliers and adders, delay devices, and lookup tables. The 312.5MHz 256-bit data stream DZ[255:0] is multiplied by the correction coefficient in the amplitude correction filter coefficient RAM, added to the MAC of the previous stage, and finally output to the lower-level MAC structure. After multi-stage FIR filtering, the corrected DYH[255:0] is output and sent to the back end for subsequent processing. The specific value of the correction filter coefficient in the amplitude correction filter coefficient RAM is automatically generated by the amplitude correction filter coefficient calculation unit of the embedded CPU module.

[0067] The noise reduction filter unit is mainly composed of noise reduction filter coefficient RAM, CIC extraction filter, FIR filter and CIC interpolation filter. In the scheme, the noise reduction filter unit is a software function of the oscilloscope, and the user can choose to turn on or off the noise reduction filter unit. When it is turned off, the 256-bit data stream DZ[255:0] of the front end 312.5MHz is directly sent to the back end for subsequent processing. When it is turned on, the 256-bit data stream DZ[255:0] of the front end 312.5MHz is sent to the noise reduction filter unit for processing. The noise reduction filter unit is a software function. The user can choose a digital low-pass filter with six gears, such as 20MHz, 250MHz, 500MHz, 1GHz, 1.5GHz, and 2GHz. The six gears of digital filters are realized by using different CIC+FIR cascade combinations and filter coefficient selection. When the user selects a bandwidth limit with a larger passband range such as 1.5GHz, 2GHz, etc., the oscilloscope will enable some CIC extraction, FIR filtering and CIC interpolation filters according to the selection and delay the data to achieve signal synchronization with the channel without bandwidth limitation. When the user selects a lower passband range such as 20MHz, 250MHz, etc., this solution will enable the back-end CIC extraction + FIR filtering + CIC interpolation cascade module, first extract the sampled signal by a power of 2 to reduce the data stream rate to an acceptable operating frequency for the FIR filter, and the FIR filter multiplies and adds the input signal with the preset filter coefficients. Finally, the interpolation CIC module completes the interpolation processing of the filtered signal to generate data with the same total bit width, that is, the 312.5MHz 256-bit data stream DZ[255:0] passes through the noise reduction filter unit and outputs a new 312.5MHz 256-bit data stream DJZ[255:0]. The specific value of the noise reduction filter coefficient in the noise reduction filter coefficient RAM is automatically generated by the noise reduction filter coefficient calculation unit of the embedded CPU module.

[0068] The waveform reconstruction unit is mainly composed of waveform reconstruction filter coefficient RAM and FIR interpolation filter unit. In the scheme, the waveform reconstruction unit is a software function of the oscilloscope, which mainly improves the time characteristics of the oscilloscope waveform in the horizontal direction. The user can choose to turn on or off the waveform reconstruction unit. When it is turned off, the front-end noise reduction filter unit directly stores the 312.5MHz 256-bit data stream DJZ[255:0] in the RAM memory inside the FPGA under the control of the data storage control unit. When it is turned on, the front-end noise reduction filter unit directly sends the 312.5MHz 256-bit data stream DJZ[255:0] to the waveform reconstruction unit for processing. This unit is mainly implemented by FIR interpolation filter, and the FIR interpolation filter is mainly composed of MAC multipliers and adders, delays, and lookup tables. The 312.5MHz 256-bit data stream DJZ[255:0] is multiplied by the correction coefficient in the waveform reconstruction filter coefficient RAM, added to the MAC of the previous stage, and finally output to the next-level MAC structure. After multi-stage FIR interpolation filtering, the waveform reconstruction DCJ[255:0] is output and stored in the RAM memory inside the FPGA under the control of the data storage control unit. The specific values ​​of the waveform reconstruction filter coefficients in the waveform reconstruction filter coefficient RAM are generated by the waveform reconstruction filter coefficient calculation unit of the embedded CPU module.

[0069] The data storage control unit mainly stores the 312.5MHz 256-bit data stream DCJ[255:0] output by the waveform reconstruction unit into the memory RAM inside the FPGA. The embedded CPU module sends the sampled data DCJ[255:0] to the display screen for display through the CPU interface interaction control unit in the digital signal processing module.

[0070] The CPU interactive control unit is mainly the interface for interaction between the embedded CPU module and the digital signal processing module. Data interaction, command interaction, etc. between the two modules are all realized through this interface.

[0071] 5. Embedded CPU module

[0072] In the scheme, the embedded CPU module is the main controller of the oscilloscope and also the human-machine interface for the oscilloscope to interact with the user. In the invention of the digital correction and compensation circuit and method of the oscilloscope, the embedded CPU module mainly includes an amplitude correction filter coefficient calculation unit, a noise reduction filter coefficient calculation unit, a waveform reconstruction filter coefficient calculation unit, etc. The embedded CPU module communicates with the CPU interactive control unit interface of the digital signal processing module through the PCIe2.0 interface to realize the interaction and transmission of control commands and collected data.

[0073] The amplitude correction filter coefficient calculation unit needs to automatically generate the correction coefficient before the oscilloscope leaves the factory to realize the automatic compensation of the amplitude of the oscilloscope, thereby completing the improvement of bandwidth and optimization of frequency response. Due to the differences in the hardware chips in the analog front-end conditioning module and the data acquisition module of the oscilloscope, the amplitude correction filter coefficients of each oscilloscope are different. Therefore, the amplitude correction filter coefficients of each oscilloscope must be automatically calculated before leaving the factory and saved in the hard disk of the oscilloscope. The embedded CPU module controls the calibration signal generation module to output a sine wave signal with a frequency of 10MHz and an amplitude of 500mVpp. After passing through the analog front-end conditioning module and the data acquisition module, it is sent to the digital signal processing module for digital signal processing. In the digital signal processing module, the data preprocessing unit works normally, while the bandwidth and frequency response optimization unit, the noise reduction filter unit, and the waveform reconstruction unit are all selected to be closed. The oscilloscope stores the most original sampling data of the data acquisition module in the CPU memory. In the same way, the calibration signal output is kept fixed at a sine wave signal of 500mVpp, and the frequency is stepped by 10MHz to 2.5GHz. After multiple measurements, the collected raw data is recorded and organized into a curve Hy. The ideal frequency response curve of the oscilloscope is Hj, and the amplitude correction filter coefficient is Hj / Hy. The embedded CPU module stores the amplitude correction filter coefficient in the amplitude correction filter coefficient RAM of the digital signal processing module. The bandwidth and frequency response optimization unit can achieve an amplitude flatness of ±1dB.

[0074] The noise reduction filter coefficient calculation unit mainly realizes the bandwidth limitation function of the oscilloscope, which is a standard function of the oscilloscope. The noise reduction filter coefficient of each oscilloscope is fixed and is only related to the digital low-pass filter of the six gears selected by the user, namely 20MHz, 250MHz, 500MHz, 1GHz, 1.5GHz, and 2GHz. The embedded CPU module stores the noise reduction filter coefficient calculated by the noise reduction filter coefficient calculation unit into the noise reduction filter coefficient RAM of the digital signal processing module. If the gear of the noise reduction filter changes and is not 20MHz, 250MHz, 500MHz, 1GHz, 1.5GHz, or 2GHz, the noise reduction filter coefficient calculation unit of the embedded CPU module needs to recalculate it and then store it in the noise reduction filter coefficient RAM of the digital signal processing module.

[0075] The waveform reconstruction filter coefficient calculation unit mainly realizes the digital interpolation function of the oscilloscope, which is a standard function of the oscilloscope. The waveform reconstruction filter coefficient of each oscilloscope is fixed and is only related to the horizontal resolution of the LCD screen and the time base gear of the oscilloscope. In the present invention, the horizontal resolution of the LCD screen is 1000 points, and the time base gear is 5ps / div~1000s / div. The embedded CPU module stores the waveform reconstruction filter coefficient calculated by the waveform reconstruction filter coefficient calculation unit into the waveform reconstruction filter coefficient RAM of the digital signal processing module. If the horizontal resolution or time base gear of the oscilloscope LCD screen changes, the waveform reconstruction filter coefficient calculation unit of the embedded CPU module needs to be recalculated once and then stored in the waveform reconstruction filter coefficient RAM of the digital signal processing module. The minimum time base gear of the present invention is 5ps, and the maximum interpolation multiple of the waveform reconstruction filter is 2000 times.

[0076] The present invention is completely implemented in FPGA by adopting digital signal processing mode; a mathematical operation point is inserted between two real sampling points by using linear interpolation or SINC interpolation algorithm through a waveform reconstruction module, thereby improving the measurement resolution, measurement accuracy and display quality of the oscilloscope, and reconstructing the waveform more accurately; the bandwidth of the oscilloscope is expanded by a bandwidth and flatness optimization module, and the flatness of the frequency response of the oscilloscope is improved; the background noise of the oscilloscope is reduced by a noise reduction filter module, and the accuracy of amplitude measurement and time measurement is enhanced; since the digital signal processing mode is adopted in the FPGA to perform digital correction and compensation, each module adopts a parallel architecture, has fast processing speed and high efficiency, and while improving the waveform display quality and measurement accuracy of the oscilloscope, the waveform refresh rate of the oscilloscope is also increased, and the real-time performance of the oscilloscope is improved.

[0077] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by technicians in this technical field within the essential scope of the present invention should also fall within the protection scope of the present invention.

Claims

1. A digital correction and compensation circuit for an oscilloscope, characterized in that: It includes a calibration signal generation module, an analog front-end conditioning module, a data acquisition module, a digital signal processing module and an embedded CPU module; wherein the digital signal processing module is the core module; The calibration signal generation module is configured to generate the fast edge and sine wave signals required for oscilloscope calibration, with a signal amplitude of 500mVpp, a fixed fast edge signal frequency of 1kHz, a sine wave frequency of 10MHz~2.5GHz, and a frequency adjustment step of 10MHz; The analog front-end conditioning module is configured to condition the oscilloscope channel input signal CH and the calibration signal; the input frequency range of the analog front-end conditioning module is DC~2.5GHz, the amplitude range is 4mVpp~8Vpp, the output frequency range is DC~2.5GHz, and the amplitude range is 2.35mV~600mVpp; A data acquisition module is configured to acquire a signal output by the analog front-end conditioning module; A digital signal processing module, configured to process a digital signal; The embedded CPU module is configured to communicate with the CPU interactive control unit interface of the digital signal processing module through the PCIe2.0 interface to realize the interaction and transmission of control commands and collected data; The digital signal processing module uses an FPGA model XCKU060-2FFVA1517I, including a data preprocessing unit, a bandwidth and frequency response optimization unit, a noise reduction filter unit, a data selector, a data storage control unit, a waveform reconstruction unit, and a CPU interaction control unit; A data preprocessing unit, configured to process the data; The bandwidth and frequency response optimization unit is configured to improve the voltage characteristics of the oscilloscope waveform in the vertical direction. The user can choose to turn on or off the bandwidth and frequency response optimization unit. When it is turned off, the front-end data preprocessing unit directly sends the 312.5MHz 256-bit data stream DZ[255:0] to the back-end for subsequent processing. When it is turned on, the front-end data preprocessing unit directly sends the 312.5MHz 256-bit data stream DZ[255:0] to the bandwidth and frequency response optimization unit for processing. Noise reduction filter unit, including noise reduction filter coefficient RAM, CIC extraction filter, FIR filter and CIC interpolation filter; users can choose to turn on or off the noise reduction filter unit; when turned off, the 256-bit data stream DZ[255:0] of the front end 312.5MHz is directly sent to the back end for subsequent processing; when turned on, the 256-bit data stream DZ[255:0] of the front end 312.5MHz is sent to the noise reduction filter unit for processing; users can choose six gears of digital low-pass filters including 20MHz, 250MHz, 500MHz, 1GHz, 1.5GHz and 2GHz. The six gears of digital filters are realized by adopting different CIC+FIR cascade combinations and filter coefficient selection; when the user selects a bandwidth limit with a larger passband range of 1.5GHz or 2GHz, the oscilloscope turns on part of the CIC according to the selection The oscilloscope uses the decimation, FIR filtering and CIC interpolation filters and delays the data to achieve signal synchronization with the channel that does not enable bandwidth limitation. When the user selects a lower passband range of 20MHz or 250MHz, the oscilloscope will enable the back-end CIC decimation + FIR filtering + CIC interpolation cascade module. First, the sampled signal is decimate by a power of 2 to reduce the data stream rate to an acceptable operating frequency for the FIR filter. The FIR filter multiplies and adds the input signal with the preset filter coefficient. Finally, the interpolation CIC module completes the interpolation processing of the filtered signal to generate data with the same total bit width, that is, the 312.5MHz 256-bit data stream DZ[255:0] is output as a new 312.5MHz 256-bit data stream DJZ[255:0] after the noise reduction filter unit. The waveform reconstruction unit is configured to improve the time characteristics of the oscilloscope waveform in the horizontal direction. The user can choose to turn on or off the waveform reconstruction unit. When it is turned off, the front-end noise reduction filter unit directly stores the 312.5MHz 256-bit data stream DJZ[255:0] in the RAM memory inside the FPGA under the control of the data storage control unit; when it is turned on, the front-end noise reduction filter unit directly sends the 312.5MHz 256-bit data stream DJZ[255:0] to the waveform reconstruction unit for processing; The data storage control unit is configured to store the 312.5MHz 256-bit data stream DCJ[255:0] output by the waveform reconstruction unit into the memory RAM inside the FPGA; the embedded CPU module sends the sampled data DCJ[255:0] to the display screen for display via the CPU interface interaction control unit in the digital signal processing module; A CPU interaction control unit is configured for use with an embedded CPU module and a digital.

2. The digital correction and compensation circuit for an oscilloscope according to claim 1, characterized in that: A calibration signal generating module, comprising a fast edge signal generating unit, a sinusoidal signal generating unit and a first switch selecting unit; A fast edge signal generating unit is configured to generate a fast edge signal required for gain and phase calibration of an ADC in a data acquisition module; The sine signal generating unit is configured to generate a sine wave signal required by the bandwidth and flatness optimizing unit in the digital signal processing module, the maximum frequency of which is 1 / 4 of the ADC sampling rate in the back-end data acquisition module; The first switch selection unit is configured to switch the output of the fast edge signal and the sinusoidal signal, and outputs a calibration signal JZ with an amplitude of 500mVpp.

3. The digital correction and compensation circuit for an oscilloscope according to claim 1, characterized in that: An analog front-end conditioning module, comprising a second switch selection unit, an attenuator unit and an amplifier unit; The second switch selection unit is configured to realize the selection of the oscilloscope channel input signal CH and the calibration signal ZJ generated by the calibration signal generation module; when the oscilloscope selects the calibration signal ZJ, the oscilloscope is in the automatic calibration mode, realizing the self-calibration of the ADC in the data acquisition module and the automatic generation of the correction filter coefficient in the bandwidth and flatness optimization unit in the digital signal processing module, the ZJ signal comes from the calibration signal generation module inside the oscilloscope, and the amplitude is 500mVpp; when the oscilloscope selects the channel signal CH, the oscilloscope can realize the normal measurement of the object under test, the amplitude of the CH signal is 4mVpp~8Vpp, and the signal frequency is the bandwidth of the oscilloscope, that is, DC~2.5GHz; The attenuator unit is configured to attenuate the CH signal. If the input channel signal amplitude is 600mVpp~8Vpp, it exceeds the full-scale range of the ADC in the data acquisition module. The full-scale voltage of the ADC is 600mVpp, and the attenuator module performs attenuation, and the attenuation multiple is CH / 600mV. The amplifier unit is configured to amplify the CH signal. If the input channel signal amplitude is 4mVpp~600mVpp, it is lower than the full-scale range of the ADC in the data acquisition module. The full-scale voltage of the ADC is 600mVpp, and the amplifier unit amplifies it with an amplification factor of 600mV / CH.

4. The digital correction and compensation circuit for an oscilloscope according to claim 1, characterized in that: A data acquisition module, including a clock generation unit and an ADC unit; A clock generating unit, configured to generate a 5 GHz clock for the ADC unit; The ADC unit is configured to convert the analog signal CH of the channel into a digital signal, and then send it to the back-end digital signal processing unit for data post-processing.

5. The digital correction and compensation circuit for an oscilloscope according to claim 4, characterized in that: The clock generation unit uses the digital integrated phase-locked loop LMX2952 frequency synthesizer; the ADC unit uses the AAD08S010GA chip, which realizes the conversion of analog to digital signals with a sampling rate of 10GSa / s and a vertical resolution of 8bit, and outputs an 80Gbps data stream. In order to realize the reception of the back-end digital signal processing unit, the data stream generates a 2.5Gbps*32 low-speed data stream inside the ADC. When the ADC outputs, it adopts the double-edge output mode, the output clock is 1.25GHz, and the data stream bit is 32-bit wide D[31:0], which is sent to the back-end digital signal processing module.

6. The digital correction and compensation circuit for an oscilloscope according to claim 1, characterized in that: A data preprocessing unit, comprising a data receiving unit, a speed reduction processing unit and a data reassembly unit; The data receiving unit is configured to receive the 1.25 GHz dual clock edge and 32-bit data stream D[31:0] output by the data acquisition module, and convert the differential input signal into a single-ended signal output, and convert the single-ended signal into a 1.25 GHz single clock edge 64-bit data stream DY[63:0]; The speed reduction processing unit is configured to convert the 64-bit data stream DY[63:0] of 1.25 GHz into a 256-bit data stream DJ[255:0] of a lower rate of 312.5 MHz to meet the clock requirement of the internal data processing of the FPGA; The data reassembly unit is configured to realize the re-combination and arrangement of the 256-bit data stream DJ[255:0] of 312.5MHz, and arranges and reassembles it according to the sampling sequence of the sampling clock to form a new 256-bit data stream DZ[255:0] of 312.5MHz.

7. The digital correction and compensation circuit for an oscilloscope according to claim 1, characterized in that: Bandwidth and frequency response optimization unit, including amplitude correction filter coefficient RAM and FIR filter unit; The FIR filter unit includes a multiplier and adder, a delay device and a lookup table of the MAC; the 312.5MHz 256-bit data stream DZ[255:0] is multiplied by the correction coefficient in the amplitude correction filter coefficient RAM, added to the MAC of the previous stage, and finally output to the lower-level MAC structure. After multi-stage FIR filtering, the corrected DYH[255:0] is output and sent to the back end for subsequent processing; wherein, the specific value of the correction filter coefficient in the amplitude correction filter coefficient RAM is automatically generated by the amplitude correction filter coefficient calculation unit of the embedded CPU module.

8. The digital correction and compensation circuit for an oscilloscope according to claim 1, characterized in that: A waveform reconstruction unit, including a waveform reconstruction filter coefficient RAM and a FIR interpolation filter unit; The FIR interpolation filter unit includes a MAC multiplier and adder, a delay device and a lookup table; the 312.5MHz 256-bit data stream DJZ[255:0] is multiplied by the correction coefficient in the waveform reconstruction filter coefficient RAM, added to the MAC of the previous stage, and finally output to the next-level MAC structure, and after multi-stage FIR interpolation filtering, the waveform reconstructed DCJ[255:0] is output and stored in the RAM memory inside the FPGA under the control of the data storage control unit; wherein, the specific value of the waveform reconstruction filter coefficient in the waveform reconstruction filter coefficient RAM is generated by the waveform reconstruction filter coefficient calculation unit of the embedded CPU module.

9. The digital correction and compensation circuit for an oscilloscope according to claim 1, characterized in that: An embedded CPU module, including an amplitude correction filter coefficient calculation unit, a noise reduction filter coefficient calculation unit, and a waveform reconstruction filter coefficient calculation unit; The amplitude correction filter coefficient calculation unit is required to automatically generate the correction coefficient before the oscilloscope leaves the factory. It is configured to realize automatic compensation of the amplitude of the oscilloscope, thereby improving the bandwidth and optimizing the frequency response. Due to the differences in the hardware chips in the analog front-end conditioning module and the data acquisition module of the oscilloscope, the amplitude correction filter coefficients of each oscilloscope are different. Therefore, the amplitude correction filter coefficients of each oscilloscope must be automatically calculated before leaving the factory and saved in the hard disk of the oscilloscope. The embedded CPU module controls the calibration signal generation module to output a sine wave signal with a frequency of 10MHz and an amplitude of 500mVpp, which is sent to the digital signal processing module for digital signal processing after passing through the analog front-end conditioning module and the data acquisition module; in the digital signal processing module, the data preprocessing unit works normally, while the bandwidth and frequency response optimization unit, the noise reduction filter unit, and the waveform reconstruction unit are all closed, and the oscilloscope stores the original sampling data of the data acquisition module in the memory of the CPU; in the same way, the calibration signal output is kept fixed at a sine wave signal of 500mVpp, and the frequency is stepped by 10MHz to 2.5GHz in turn. After multiple measurements, the collected original data records are organized into a curve Hy, and the ideal frequency response curve of the oscilloscope is Hj, then the amplitude correction filter coefficient is Hj / Hy, and the embedded CPU module stores the amplitude correction filter coefficient in the amplitude correction filter coefficient RAM of the digital signal processing module, and the bandwidth and frequency response optimization unit can achieve an amplitude flatness of ±1dB; The noise reduction filter coefficient calculation unit is configured to realize the bandwidth limiting function of the oscilloscope. The noise reduction filter coefficient of each oscilloscope is fixed and is only related to the digital low-pass filter of the six gears of 20MHz, 250MHz, 500MHz, 1GHz, 1.5GHz and 2GHz selected by the user; the embedded CPU module stores the noise reduction filter coefficient calculated by the noise reduction filter coefficient calculation unit into the noise reduction filter coefficient RAM of the digital signal processing module; if the gear of the noise reduction filter changes and is not 20MHz, 250MHz, 500MHz, 1GHz, 1.5GHz, 2GHz, the noise reduction filter coefficient calculation unit of the embedded CPU module needs to recalculate it once and then store it into the noise reduction filter coefficient RAM of the digital signal processing module; The waveform reconstruction filter coefficient calculation unit is configured to realize the digital interpolation function of the oscilloscope. The waveform reconstruction filter coefficient of each oscilloscope is fixed and is only related to the horizontal resolution of the LCD screen and the time base gear of the oscilloscope. The embedded CPU module stores the waveform reconstruction filter coefficient calculated by the waveform reconstruction filter coefficient calculation unit into the waveform reconstruction filter coefficient RAM of the digital signal processing module. If the horizontal resolution or time base gear of the oscilloscope LCD screen changes, the waveform reconstruction filter coefficient calculation unit of the embedded CPU module needs to recalculate once and then store it in the waveform reconstruction filter coefficient RAM of the digital signal processing module.

Images