Digital oscilloscope variable sampling rate acquisition storage device

Abstract

The application discloses a digital oscilloscope variable sampling rate acquisition and storage device, which comprises a data acquisition module, an upper computer, a data preprocessing module and a data cache module. The data acquisition module acquires data and sends the data to the data preprocessing module. The upper computer sets a threshold start position, a threshold end position and a sampling rate increase multiple according to user needs, and sets parameters for the data preprocessing module and the data cache module. According to control signals of the upper computer and the data cache module, the data preprocessing module changes the data extraction multiple, thereby changing the data sampling rate, and sends the data after the extraction to the data cache module. The data cache module caches the data, and sends control signals to the data preprocessing module according to the data cache condition. The application can adopt the variable sampling rate in the same waveform data, so that the user can observe the waveform details without wasting the storage space.

Description

Digital oscilloscope variable sampling rate acquisition and storage device Technical Field

[0001] This invention belongs to the field of signal processing technology, and more specifically, relates to a variable sampling rate acquisition and storage device for a digital oscilloscope. Background Technology

[0002] With the development of electronic information technology, semiconductor integrated circuits, and computer technology, the bandwidth and complexity of signals are increasing. Extracting information of interest from signals has become a crucial task in modern signal measurement technology. Time-domain measurement technology based on real-time sampling and processing is the mainstream of modern signal measurement. Figure 1 is a flowchart of existing time-domain measurement technology. As shown in Figure 1, existing time-domain measurement technology mainly includes four steps: input signal acquisition, storage, processing, and display.

[0003] As the frequency and complexity of input analog signals continue to increase, according to the Nyquist sampling theorem, in order to improve the integrity of the captured signal, it is necessary to increase the sampling rate and measurement accuracy of the analog-to-digital converter (ADC). This leads to the ADC generating a large amount of sampled data. As shown in the time-domain test system in Figure 1, its signal acquisition capability depends on the data transmission, storage, and processing capabilities. A large amount of sampled data will put enormous pressure on data transmission, storage, and processing. To solve this problem and improve the signal acquisition capability of the time-domain test system, compressed acquisition schemes for time-domain signal waveforms have been proposed in published literature and registered patents.

[0004] Chinese patent CN111308147A discloses a data acquisition device based on information entropy. It divides the ADC-acquired data evenly, uses a peak detector to detect the maximum and minimum values ​​and performs differential processing. Then, it selects the original data and the maximum and minimum values ​​by comparing them with a set threshold. Under certain conditions, it discards a portion of the sampled data. While retaining valuable waveform information, it greatly compresses the number of acquisition points and reduces the pressure of data transmission and storage.

[0005] The aforementioned invention achieves waveform data compression through relatively simple logic, solving the problems of complex and time-consuming calculations, and realizing real-time waveform acquisition and processing. However, taking the maximum and minimum values ​​results in the loss of a large amount of information, which may include a lot of key information. In order to better display the detailed information of the waveforms that users are interested in, it is necessary to increase the sampling rate and acquire more information to ensure that key information in the signal can be acquired without loss. However, this puts a huge burden on data transmission and storage. It can be seen that the traditional real-time acquisition method can no longer meet the current needs. In order to alleviate the pressure on data transmission and storage while allowing users to obtain richer information on the waveforms they are interested in, it is necessary to expand and improve the real-time acquisition method, so as to more flexibly handle the acquisition needs of different users for different signals and maximize the utilization of memory resources. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a variable sampling rate acquisition and storage device for digital oscilloscopes. By using a variable sampling rate in the same waveform data, it is possible for users to observe waveform details without wasting storage space.

[0007] To achieve the above-mentioned objectives, the digital oscilloscope variable sampling rate acquisition and storage device of the present invention includes a data acquisition module, a host computer, a data preprocessing module, and a data buffer module, wherein:

[0008] The data acquisition module is used to acquire the signal after it has been conditioned by the analog channel using a preset sampling rate R, and send the acquired data data to the data preprocessing module;

[0009] The host computer receives the user-set time base, threshold start position L1, threshold end position L2, and sampling rate boosting factor m within the threshold area. The threshold start position L1 and threshold end position L2 are the grid numbers in the waveform display area on the digital oscilloscope screen, and must satisfy L2 - L1 < L / 2, where L represents the total number of grids in the displayed waveform. The sampling rate boosting factor m must also satisfy...

[0010] The host computer calculates the default decimation rate A = R / r for the collected data based on the sampling rate r determined by the time base.

[0011] The total number of display points P of the waveform displayed on the screen is calculated using the following formula:

[0012]

[0013] Where Q represents the number of display points in each small square in the waveform display area;

[0014] The starting storage location P1 and the ending storage location P2 are calculated using the following formula:

[0015]

[0016]

[0017] The host computer sends the default sampling rate A and the sampling rate enhancement rate m to the data preprocessing module, and sends the start storage position P1, end storage position P2 and total display points P to the data buffer module. During the operation of the digital oscilloscope, the host computer generates a variable sampling rate acquisition start signal S and a variable sampling rate acquisition end signal E according to the user's instructions and sends them to the data preprocessing module and the data buffer module.

[0018] The data preprocessing module is used to perform sampling rate sampling on the acquired data DATA based on the sampling rate increase factor m, the variable sampling rate acquisition start signal S, and the variable sampling rate acquisition end signal E received from the host computer, as well as the sampling rate increase factor start signal s and the sampling rate increase factor end signal e received from the data buffer module. The preprocessing module then sends the processed data DATA to the data buffer module. The data preprocessing module includes a variable sampling rate control module and a variable sampling rate processing module, wherein:

[0019] The variable sampling rate control module receives the default decimation rate A, the sampling rate increment m, the variable sampling rate acquisition start signal S, and the variable sampling rate acquisition end signal E from the host computer, and the sampling rate increment start signal s and the sampling rate increment end signal e from the data buffer module 4. It then generates the decimation rate C and sends it to the variable sampling rate processing module. The generation rule for the decimation rate is as follows:

[0020] 1) If the variable sampling rate control module has not yet received the variable sampling rate acquisition start signal S, or has received the variable sampling rate acquisition end signal E, then set the decimation rate C = A;

[0021] 2) If the variable sampling rate control module receives the variable sampling rate acquisition start signal S, or if the variable sampling rate control module receives the variable sampling rate acquisition start signal S and then receives the sampling rate multiplier increase end signal e, then set the decimation multiplier C = A × m;

[0022] 3) If the variable sampling rate control module receives the variable sampling rate acquisition start signal S and then receives the sampling rate multiplier increase start signal s, then set the decimation multiplier C = A / m;

[0023] The variable sampling rate processing module is used to extract data from the data acquired by the data acquisition module according to the extraction rate C received from the variable sampling rate control module, and then send the data to the data buffer module.

[0024] The data caching module is used to cache the data DATA after variable sampling rate processing. Based on the caching situation, it generates a sampling rate increase start signal s and a sampling rate increase end signal e and sends them to the data preprocessing module.

[0025] The data buffer module is used to buffer the data DATA processed at the variable sampling rate. Based on the buffering status, it generates a sampling rate increase start signal s and a sampling rate increase end signal e, and sends them to the data preprocessing module. The data buffer module includes a RAM address control module and a RAM memory, wherein:

[0026] The RAM address control module receives the sampling rate boosting factor m, the start storage location P1 and the end storage location P2, the variable sampling rate acquisition start signal S, and the variable sampling rate acquisition end signal E from the host computer. It sets a counter with modulus P. Whenever the variable sampling rate acquisition start signal S is received, the counter increments the address based on the valid data DATA signal. Whenever the counter value equals the start storage location P1, a sampling rate boosting start signal s is generated and sent to the data preprocessing module. Whenever the counter value equals the end storage location P2, a sampling rate boosting end signal e is generated and sent to the data preprocessing module. During address incrementing, the RAM address control module generates a write enable based on the valid data DATA signal and sends the address and write enable to the RAM memory for data caching.

[0027] The RAM memory is used to cache data DATA into RAM based on the write enable signal and address received from the RAM address control module.

[0028] The present invention relates to a digital oscilloscope variable sampling rate acquisition and storage device, comprising a data acquisition module, a host computer, a data preprocessing module, and a data buffer module. The data acquisition module acquires data and sends it to the data preprocessing module. The host computer sets the threshold start position, threshold end position, and sampling rate boosting factor according to user needs, and sets parameters for the data preprocessing module and the data buffer module. The data preprocessing module changes the data sampling factor according to the control signals from the host computer and the data buffer module, thereby changing the data sampling rate, and sends the sampled data to the data buffer module. The data buffer module buffers the data and sends control signals to the data preprocessing module according to the data buffering status.

[0029] The present invention has the following beneficial effects.

[0030] 1) This invention can perform variable sampling rate sampling on signals. A high sampling rate is used to acquire waveforms of interest in the same waveform data, while a low sampling rate is selected to acquire parts of no interest. This allows for more flexible adjustment of the sampling rate of the signal display in different time ranges, which helps to better analyze the signal and discover hidden features in the signal.

[0031] 2) This invention allows users to customize and adjust the variable sampling rate and its range according to their needs, achieving better human-computer interaction performance. For different waveform inputs, users can observe the waveform of interest in detail.

[0032] 3) This invention uses a high sampling rate only on the waveform of interest, which can effectively control the pressure on data transmission and storage. It can complete variable sampling rate acquisition under limited data transmission and storage resources, meet the needs of modern measurement technology for real-time acquisition technology, and has certain guiding significance for time-domain compression acquisition technology. Attached Figure Description

[0033] Figure 1 is a flowchart of existing time-domain measurement techniques;

[0034] Figure 2 is a structural diagram of a specific embodiment of the variable sampling rate acquisition and storage device for digital oscilloscopes of the present invention.

[0035] Figure 3 is a schematic diagram of the decimation rate change in the variable sampling rate control module of the present invention;

[0036] Figure 4 is a schematic diagram of the extraction multiplier generation state machine in this invention;

[0037] Figure 5 is a structural diagram of the FPGA-based digital oscilloscope in this embodiment;

[0038] Figure 6 is a flowchart of the variable sampling rate data acquisition process in this embodiment;

[0039] Figure 7 is an example diagram of waveform data display in this embodiment. Detailed Implementation

[0040] The specific embodiments of the present invention will now be described with reference to the accompanying drawings to enable those skilled in the art to better understand the invention. It should be particularly noted that in the following description, detailed descriptions of known functions and designs that might obscure the main content of the invention will be omitted here.

[0041] Example

[0042] Figure 2 is a structural diagram of a specific embodiment of the variable sampling rate acquisition and storage device for a digital oscilloscope according to the present invention. As shown in Figure 2, the variable sampling rate acquisition and storage device for a digital oscilloscope according to the present invention includes a data acquisition module 1, a host computer 2, a data preprocessing module 3, and a data buffer module 4. Each module will be described in detail below.

[0043] Data acquisition module 1 is used to acquire the signal after it has been conditioned by the analog channel at a preset sampling rate R, and then sends the acquired data (data) to data preprocessing module 3. The sampling rate R is determined by the hardware of data acquisition module 1.

[0044] The host computer 2 is used to receive the user-set time base, threshold start position L1, threshold end position L2, and sampling rate enhancement factor m within the threshold area. The threshold start position L1 and threshold end position L2 are the grid numbers in the waveform display area on the digital oscilloscope screen, and must satisfy L2 - L1 < L / 2, where L represents the total number of grids in the waveform displayed on the screen. The sampling rate enhancement factor m must satisfy...

[0045] The host computer 2 calculates the default sampling rate A = R / r for the collected data based on the sampling rate r determined by the time base.

[0046] The total number of display points P of the waveform displayed on the screen is calculated using the following formula:

[0047]

[0048] Where Q represents the number of display points in each small square in the waveform display area.

[0049] The starting storage location P1 and the ending storage location P2 are calculated using the following formula:

[0050]

[0051]

[0052] The host computer 2 sends the default decimation rate A and the sampling rate boosting rate m to the data preprocessing module 3, and sends the start storage position P1, end storage position P2, and total display points P to the data buffer module 4. During the operation of the digital oscilloscope, the host computer 2 generates a variable sampling rate acquisition start signal S and a variable sampling rate acquisition end signal E according to user instructions and sends them to the data preprocessing module 3 and the data buffer module 4.

[0053] The data preprocessing module 3 is used to perform sampling rate sampling on the acquired data DATA based on the sampling rate increase factor m, the variable sampling rate acquisition start signal S, and the variable sampling rate acquisition end signal E received from the host computer 2, and the sampling rate increase factor start signal s and the sampling rate increase factor end signal e received from the data buffer module 4. Then, the processed data DATA is sent to the data buffer module 4. As shown in Figure 2, the data preprocessing module 3 in this invention includes a variable sampling rate control module 31 and a variable sampling rate processing module 32, wherein:

[0054] The variable sampling rate control module 31 receives the default decimation rate A, the sampling rate increase rate m, the variable sampling rate acquisition start signal S, and the variable sampling rate acquisition end signal E from the host computer 2, and the sampling rate increase rate start signal s and the sampling rate increase rate end signal e from the data buffer module 4. It then generates the decimation rate C and sends it to the variable sampling rate processing module 32. Figure 3 is a schematic diagram of the decimation rate change in the variable sampling rate control module of this invention. As shown in Figure 3, the decimation rate generation rule is as follows:

[0055] 1) If the variable sampling rate control module 31 has not yet received the variable sampling rate acquisition start signal S, or has received the variable sampling rate acquisition end signal E, then the decimation factor C = A is set. At this time, the sampling rate change factor of data DATA relative to data data is A.

[0056] 2) If the variable sampling rate control module 31 receives the variable sampling rate acquisition start signal S, or if the variable sampling rate control module 31 receives the variable sampling rate acquisition start signal S and then receives the sampling rate multiplier increase end signal e, then the decimation multiplier C = A × m is set. At this time, the sampling rate change multiplier of data DATA relative to data data is A / m.

[0057] 3) If the variable sampling rate control module 31 receives the variable sampling rate acquisition start signal S and then receives the sampling rate multiplier increase start signal s, then the decimation multiplier C = A / m is set. At this time, the sampling rate change multiplier of data DATA relative to data data is A×m.

[0058] In this embodiment, the variable sampling rate control module 31 uses a state machine to adaptively generate the decimation rate. Figure 4 is a schematic diagram of the decimation rate generation state machine in this invention. As shown in Figure 4, the decimation rate generation state machine in this invention includes a default state, a downsampling state, and an upsampling state, wherein:

[0059] The default state is the initial state of the variable sampling rate control module 31, in which the decimation rate C = A is set. If the variable sampling rate acquisition start signal S is received in the default state, the module will switch to the downsampling state.

[0060] In downsampling mode, the decimation factor C = A × m is set. If a sampling rate increase start signal s is received in downsampling mode, the system switches to upsampling mode. If a variable sampling rate acquisition end signal E is received, the system switches to default mode.

[0061] In upsampling mode, the decimation rate C = A / m is set. If the sampling rate increase end signal e is received in upsampling mode, the system switches to downsampling mode. If the variable sampling rate acquisition end signal E is received, the system switches to default mode.

[0062] As described above, variable sampling rate control can be achieved using a state machine with only 3 states, which is simple and effective.

[0063] The variable sampling rate processing module 32 is used to extract data DATA from the data acquired by the data acquisition module 1 according to the extraction rate C received from the variable sampling rate control module 31, and then send the extracted data DATA to the data buffer module 4. Generally, data extraction is achieved through a counter, that is, the modulus of the counter is set to C, and the count value changes sequentially from 0 to C-1. Each time the count value reaches C-1, a valid data signal is output, and the current data and the valid data signal are output. Subsequently, the data buffer module 4 buffers the data using the valid signal. In this way, the signal acquired by the data acquisition module can be processed by the variable sampling rate.

[0064] The data caching module 4 is used to cache the data DATA processed by the variable sampling rate. Based on the caching status, it generates a sampling rate increase start signal s and a sampling rate increase end signal e, and sends them to the data preprocessing module 3. As shown in Figure 2, the data caching module in this invention includes a RAM address control module 41 and a RAM memory 42, wherein:

[0065] The RAM address control module 41 receives the sampling rate boosting factor m, the start storage location P1 and the end storage location P2, the variable sampling rate acquisition start signal S, and the variable sampling rate acquisition end signal E from the host computer 2. It sets a counter with modulus P. Whenever the variable sampling rate acquisition start signal S is received, the counter increments the address based on the valid data DATA signal. Whenever the counter value equals the start storage location P1, a sampling rate boosting start signal s is generated and sent to the data preprocessing module 3. Whenever the counter value equals the end storage location P2, a sampling rate boosting end signal e is generated and sent to the data preprocessing module 3. During address incrementing, the RAM address control module 41 generates a write enable based on the valid data DATA signal and sends the address and write enable to the RAM memory 42 for data caching.

[0066] RAM memory 42 is used to cache data DATA into RAM according to the write enable signal and address received from RAM address control module 41.

[0067] To better illustrate the technical effects of the present invention, specific examples are used to experimentally verify the invention. Figure 5 is a structural diagram of the FPGA-based digital oscilloscope in this embodiment. In this embodiment, the input signal is a sine wave signal with white noise, the frequency of the input signal is 1MHz, and the sampling rate r of the data acquisition module 1 is 100MHz. As shown in Figure 5, the basic principle of the digital oscilloscope display in this embodiment is: in the horizontal direction, the sampling points are displayed sequentially in different columns of the screen according to the sampling order; in the vertical direction, the display position is determined according to the size of the sampled value, with the larger sampled value displayed at the top of the screen. In this example, the time base setting has 10 horizontal divisions on the oscilloscope screen, with 100 points displayed in each division. The host computer 2 sets the threshold start point to 4.5 and the end point to 5.5. To observe the details of the intermediate waveform, the sampling rate increase factor m = 10 is set within the threshold area, that is, the waveform sampling rate within the threshold is increased by 10 times, and the waveform sampling rate outside the threshold is decreased by 10 times. It can be calculated that the starting storage position is 45 and the ending storage position is 1045.

[0068] Figure 6 is a flowchart of the variable sampling rate data acquisition process in this embodiment. As shown in Figure 5, the variable sampling rate function is first enabled, the variable sampling rate acquisition start signal S is pulled high, and the host computer 2 sends down various parameters and control signals. After receiving the variable sampling rate acquisition start signal S, the variable sampling rate control module 31 enables the variable sampling rate function, sets the decimation rate of the variable sampling rate processing module 32 to 10 times the default decimation rate, performs variable sampling rate processing through a counter, and waits for the RAM address control module 41 to generate the sampling rate increase start signal s.

[0069] Simultaneously, the RAM address control module 41 receives the variable sampling rate acquisition start signal S, the start storage position 45, the end storage position 1045, and the total number of display points 1095. After receiving the data DATA and valid signal output by the variable sampling rate processing module 32, the address begins to accumulate, and a write enable control signal and address are output to the RAM memory 5 to cache the data. After accumulating to the start storage position, a sampling rate multiplier increase start signal s is output. After receiving the sampling rate multiplier increase start signal s, the variable sampling rate control module 31 sets the decimation multiplier to 1 / 10 of the original decimation multiplier and inputs it to the variable sampling rate processing module 32. The variable sampling rate processing module 32 controls the output of a valid signal through a counter to perform point acquisition operation, inputting the data into the RAM memory 42, and inputting the valid signal into the RAM control module 41. At this time, the address of RAM control module 41 is continuously incremented until the end storage location 1045, and then the sampling rate multiplier increase end signal e is output to variable sampling rate control module 31. Variable sampling rate control module 31 sets the decimation multiplier of variable sampling rate processing module 32 to 10 times the default decimation multiplier. After that, the address of RAM control module 42 continues to increment until the address reaches the total number of display points 1095, and then the writing of data to RAM memory 5 ends, thereby obtaining a frame of waveform data.

[0070] Figure 7 is an example of waveform data display in this embodiment. As shown in Figure 6, it can be seen that the waveform sampling rate in the interval of grid 4.5 to 5.5 is significantly higher than the waveform sampling rate in other intervals, and the noise details in the sine wave can also be observed more clearly.

[0071] Although the illustrative specific embodiments of the present invention have been described above to enable those skilled in the art to understand the invention, it should be understood that the invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the invention as defined and determined by the appended claims, and all inventions utilizing the concept of the present invention are protected.

Claims

1. A variable sampling rate acquisition and storage device for a digital oscilloscope, characterized in that, It includes a data acquisition module, a host computer, a data preprocessing module, and a data caching module, wherein: the data acquisition module is used to use a preset sampling rate. The signal after being conditioned by the analog channel is acquired, and the acquired data is processed. The data is sent to the data preprocessing module; the host computer receives the user-defined time base and threshold start position. Threshold End Position And the sampling rate increase factor within the threshold region The threshold start position Threshold End Position These are the grid numbers in the waveform display area on the digital oscilloscope screen, and they need to meet certain requirements. ， This indicates the total number of frames in the waveform displayed on the screen, representing the sampling rate magnification factor. Need to meet The sampling rate determined by the host computer based on the time base. Calculation for collected data Default extraction rate The total number of display points of the waveform on the screen is calculated using the following formula. ： ,in, This indicates the number of display points in each small square within the waveform display area; the starting storage position is calculated using the following formula. and end storage location ： ， The host computer will default to extracting the multiplier. Sampling rate increase factor The data is sent to the data preprocessing module, where the storage location will begin. End storage location Total number of display points The data is sent to the data buffer module; during the operation of the digital oscilloscope, the host computer generates a variable sampling rate acquisition start signal according to the user's instructions. With the variable sampling rate acquisition end signal The data is then sent to the data preprocessing module and the data caching module; the data preprocessing module is used to increase the sampling rate based on the sampling rate received from the host computer. Variable sampling rate acquisition start signal Variable sampling rate acquisition end signal And the sampling rate increase start signal received from the data buffer module. and the end signal of sampling rate multiplication Changing the sampling rate affects the collected data. Perform sampling processing, and then process the data. The data is fed into the data buffer module; the data preprocessing module includes a variable sampling rate control module and a variable sampling rate processing module, wherein: the variable sampling rate control module is used to receive the default decimation rate from the host computer. Sampling rate increase factor Variable sampling rate acquisition start signal Variable sampling rate acquisition end signal The sampling rate is increased from the data buffer module to start the signal. and the end signal of sampling rate multiplication Then generate the extraction multiplier. Send to the variable sampling rate processing module; the generation rule for the decimation rate is: 1) If the variable sampling rate control module has not yet received the variable sampling rate acquisition start signal... Or receive a variable sampling rate acquisition end signal Then set the extraction multiplier. 2) If the variable sampling rate control module receives the variable sampling rate acquisition start signal Or the variable sampling rate control module receives the variable sampling rate acquisition start signal. Then receive the end signal of sampling rate increase. Then set the extraction multiplier. 3) If the variable sampling rate control module receives the variable sampling rate acquisition start signal Then receive the sampling rate increase start signal Then set the extraction multiplier. The variable sampling rate processing module is used to process the decimation rate received from the variable sampling rate control module. Data collected by the data acquisition module Data was obtained by sampling. And send it to the data caching module; the data caching module is used to cache the data after variable sampling rate processing. Generate a sampling rate increase start signal based on the buffer status. and the end signal of sampling rate multiplication The data is then sent to the data preprocessing module; the data caching module is used to cache the data processed by the variable sampling rate. Generate a sampling rate increase start signal based on the buffer status. and the end signal of sampling rate multiplication The data is then sent to the data preprocessing module; the data caching module includes a RAM address control module and a RAM memory, wherein the RAM address control module is used to receive the sampling rate from the host computer and increase the sampling rate by a factor of 1. Start storage location and end storage location Variable sampling rate acquisition start signal and variable sampling rate acquisition end signal Set a counter with a modulus of 1. Whenever a variable sampling rate acquisition start signal is received The counter is based on the data The valid signal is used to increment the address. Whenever the counter value equals the starting storage location... Then the sampling rate is increased to start signal. It is then sent to the data preprocessing module, whenever the counter value equals the end storage location. Then, the sampling rate is increased by a factor of 1 to generate an end signal. And send it to the data preprocessing module; during the address accumulation process, the RAM address control module determines the data... A valid write enable signal is generated, and the address and write enable are sent to the RAM memory for data caching; the RAM memory is used to store data according to the write enable signal and address received from the RAM address control module. Cache it in RAM.

2. The variable sampling rate acquisition and storage device for a digital oscilloscope according to claim 1, characterized in that, The variable sampling rate control module uses a state machine to adaptively generate the decimation rate. The state machine includes a default state, a downsampling state, and an upsampling state. The default state is the initial state of the variable sampling rate control module, and the decimation rate is set in this state. In the default state, if a variable sampling rate acquisition start signal is received... Then it switches to downsampling mode; in downsampling mode, the sampling rate is set. If a signal indicating a start of increased sampling rate is received during downsampling, Then it switches to upsampling mode if a variable sampling rate acquisition end signal is received. Then switch to the default state; in upsampling state, set the sampling rate. If a signal indicating an increase in the sampling rate is received during upsampling, the signal indicating an end to the upsampling rate increase is obtained. Then it switches to downsampling mode if a variable sampling rate acquisition end signal is received. Then it will switch to the default state.

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