A voltage-to-digital conversion circuit based on capacitive isolation

Abstract

The application discloses a voltage digital conversion circuit based on capacitive isolation, which modulates a bipolar analog signal into a digital signal through a voltage / digital conversion circuit, and enters an FPGA system for processing after passing through a capacitive digitizer, so that lossless analog signal transmission can be realized, the problem of analog signal isolation transmission in a traditional scheme is fundamentally eliminated, noise resistance is enhanced, and the measurement precision of the system is improved. On an interface, external bipolar positive and negative voltage can be directly input, and is converted into a single-bit digital signal, and different modulation clock paths can be multiplexed, so that the number of external interfaces is reduced, the complexity of the system is reduced, meanwhile, a series comb filter is constructed in the FPGA to perform low-pass filtering on the single-bit digital signal, high-frequency modulation signals introduced by the voltage / digital conversion circuit are filtered out, and finally, the analog voltage signal at the isolation end is restored.

Description

Technical Field

[0001] This invention belongs to the field of aerospace equipment, and specifically relates to a voltage-to-digital conversion circuit based on capacitor isolation. Background Technology

[0002] In the fields of aerospace and industrial control, in order to avoid the formation of loop currents between nodes, which could cause mutual interference between mechanisms, resulting in equipment performance degradation or other serious accidents, it is necessary to isolate each electrical node. At the same time, in order to monitor the working status of each electrical node, it is necessary to measure the analog voltage signals such as voltage, current, and temperature of the isolated electrical nodes.

[0003] Traditional analog signal isolation methods can be divided into two main categories. The first is based on linear optocouplers and their feedback circuits. The core idea of ​​this approach is that two identical optotransistors in the linear optocoupler can receive the same photocurrent. The op-amp negative feedback circuit controls the photocurrent of the optotransistor at the isolation end to be proportional to the current of the voltage-to-current converter. Therefore, the output voltage of the photocurrent at the measurement end after passing through the voltage-to-current converter is equal to the input voltage at the isolation end. However, this method is expensive, has low bandwidth, complex structure, low accuracy, and suffers significant degradation over time and with temperature. The second method is based on voltage-frequency and frequency-to-voltage conversion circuits. This converts the analog signal at the isolation end into a digital frequency signal related to the voltage magnitude. This digital frequency signal is then converted back to an analog voltage using a digital optocoupler and a frequency-to-voltage converter. However, this method is complex, consumes a lot of power, and has a dead zone in the measurement range. Meanwhile, after obtaining the restored analog voltage at the measurement end, both schemes require an analog switch to switch channels. The introduction of the analog switch causes impedance mismatch, necessitating the use of an operational amplifier-based follower after the analog switch to buffer its output signal. The buffered analog voltage signal is then fed into an analog-to-digital converter (ADC) for conversion. Finally, it communicates with the FPGA system via the ADC's bus interface, forming a complete isolated voltage measurement system. The system block diagram is shown below. Figure 1 As shown.

[0004] Meanwhile, in terms of the selection of isolation devices, both digital optocouplers and linear optocouplers are transmission devices based on optical media, which have disadvantages such as large size, high power consumption, low insulation withstand voltage, and severe decay with temperature and time, and cannot meet the requirements of the new generation of aerospace equipment.

[0005] Both of the above traditional solutions have their own drawbacks and high circuit complexity. The expansion of measurement channels depends on the number of analog switches, which greatly limits the development of new-generation aerospace equipment. Especially in telemetry systems, the number of channels for analog voltage isolation measurement can reach hundreds. Traditional measurement solutions cannot meet the actual needs. There is an urgent need for more integrated analog voltage isolation measurement technology to develop a miniaturized, multi-channel, high-precision, and stable analog voltage isolation measurement circuit. Summary of the Invention

[0006] The purpose of this invention is to overcome the measurement problem of multiple sets of non-common ground analog voltage signals and provide a voltage-to-digital conversion circuit based on capacitor isolation. This circuit eliminates the need for traditional analog switches, operational amplifier followers, and analog-to-digital converters. The digitalization of the external interface significantly reduces the number of wires and the area occupied by the components, enabling the isolation measurement of dozens or even hundreds of analog voltage signals in a smaller circuit area.

[0007] To achieve the above objectives, the present invention includes:

[0008] The signal conditioning circuit is used to receive bipolar voltage signals and output unipolar voltage signals to the voltage-to-digital conversion circuit.

[0009] A voltage-to-digital converter circuit is used to receive unipolar voltage signals and isolated clock signals, and output digital signals to a capacitive digital isolator.

[0010] A capacitive digital isolator is used to receive the clock signal from the FPGA system, output the isolated clock signal to the voltage-to-digital converter circuit, and output the isolated digital signal to the FPGA system.

[0011] The signal conditioning circuit is used to convert bipolar analog voltage signals into unipolar analog voltage signals, amplify or attenuate the signals, and perform noise reduction.

[0012] The voltage-to-digital converter circuit is used to quantize the input unipolar analog voltage signal according to the received clock signal, output a digital signal to the capacitive digital isolator, and then transmit it to the measurement terminal.

[0013] A capacitive digital isolator circuit is used to pass the input digital signal through an isolation capacitor, while simultaneously shaping the received digital signal and outputting a standard CMOS level to the FPGA system.

[0014] The FPGA system outputs a modulation clock CLK to a capacitive digital isolator and receives the digital signal DAT output by the capacitive digital isolator according to the edge of the modulation clock CLK. It implements a digital low-pass filter in the internal IP core and calculates the corresponding bipolar analog voltage value.

[0015] The signal conditioning circuit includes operational amplifier Op1 and operational amplifier Op2;

[0016] The positive input terminal of operational amplifier Op2 is connected to one end of resistor R1, one end of resistor R2, and one end of capacitor C1. The other end of resistor R1 is connected to the positive terminal of the signal. The other end of resistor R2 is connected to the other end of capacitor C1, the output terminal of operational amplifier Op2, and the output signal VOUT. The inverting input terminal of operational amplifier Op2 is connected to one end of resistor R3, one end of resistor R4, and one end of capacitor C2. The other end of resistor R3 is the negative terminal of the signal. The other end of resistor R4 is connected to the other end of capacitor C2, the output virtual ground signal VG, the inverting input terminal of operational amplifier Op1, and the output terminal of operational amplifier Op1. The positive input terminal of operational amplifier Op1 is connected to one end of capacitor C3, one end of resistor R5, and one end of resistor R6. The other end of resistor R5 is connected to the voltage reference VREF. The other end of resistor R6 is connected to the other end of capacitor C3 and the ground terminal.

[0017] The voltage-to-digital conversion circuit includes summation nodes SUM1 and SUM2, a hysteresis comparator CMP, and a D flip-flop FILP.

[0018] The summation node SUM1 subtracts the unipolar positive voltage VOUT and the output signal Q of the D flip-flop FILP, and integrates the result in continuous time through the integrator I1.

[0019] The summation node SUM2 subtracts the output of integrator I1 from the output signal Q of D flip-flop FILP, and then integrates the result through integrator I2 in continuous time.

[0020] The hysteresis comparator CMP compares the output of the integrator I2 with the VG signal in the signal conditioning circuit, and outputs the signal to the D flip-flop FILP.

[0021] Under the influence of the input clock CLK, the D flip-flop FILP, combined with the voltage reference VREF, latches the output signal of the comparator CMP according to the clock cycle, outputs a digital signal according to the clock cycle of CLK, and connects to the summing nodes SUM1 and SUM2 to become the system feedback signal.

[0022] The capacitive digital isolator includes hysteresis comparator CMP2 and hysteresis comparator CMP3;

[0023] The input of hysteresis comparator CMP2 is connected to one end of resistor R7, one end of capacitor C4, and one end of resistor R8. The other end of capacitor C4 is connected to the input clock signal. The other end of resistor R7 is connected to the isolation power supply VCC1. The other end of resistor R8 is connected to one end of capacitor C6 and the ground terminal. The other end of capacitor C6 is connected to one end of resistor R10 and the ground terminal. The other end of resistor R10 is connected to one end of capacitor C5, one end of resistor R9, and the input of hysteresis comparator CMP3. The other end of capacitor C5 is connected to the input of digital signal DAT. The other end of resistor R9 is connected to the digital power supply VCC2. The output of hysteresis comparator CMP2 outputs the clock signal, and the output of hysteresis comparator CMP3 outputs the digital signal.

[0024] Resistors R7, R8, R9, and R10 are all DC bias setting resistors.

[0025] Capacitors C4, C5, and C6 are all high-voltage isolation capacitors.

[0026] Compared with existing technologies, this invention modulates bipolar analog signals into digital signals through a voltage-to-digital converter circuit. After passing through a capacitive digitizer, the signals are processed by an FPGA system, enabling distortion-free analog signal transmission. This fundamentally eliminates the problem of isolated analog signal transmission in traditional solutions, enhances noise immunity, and improves system measurement accuracy. Externally, bipolar positive and negative voltages can be directly input and converted into single-bit digital signals. Modulation clocks for different paths can be multiplexed, reducing the number of external interfaces and lowering system complexity. Simultaneously, a series comb filter is constructed in the FPGA to perform low-pass filtering on the single-bit digital signals, filtering out high-frequency modulation signals introduced by the voltage-to-digital converter circuit, ultimately restoring the analog voltage signal at the isolated terminal. This invention solves the measurement problem of multiple sets of non-common-ground analog voltage signals. It offers high measurement accuracy, is independent of temperature and time, has a small circuit size, controllable cost, configurable and independent channel count, and can be output via various communication buses after FPGA processing. It features miniaturization, high integration, and high flexibility, and can be widely applied in aerospace, industrial control, and other fields. Attached Figure Description

[0027] Figure 1 This is a block diagram of a traditional isolated voltage acquisition system.

[0028] Figure 2 This is a circuit block diagram of the present invention;

[0029] Figure 3 This is a schematic diagram of the signal conditioning circuit in this invention;

[0030] Figure 4 This is a schematic diagram of the voltage / digital conversion circuit in this invention;

[0031] Figure 5 This is a schematic diagram of the capacitive digital isolation circuit in this invention;

[0032] Figure 6 This is a block diagram of the isolation voltage acquisition system of the present invention. Detailed Implementation

[0033] The invention will now be further described with reference to the accompanying drawings.

[0034] To ensure the accuracy of isolated measurements, only digital signals can be transmitted through the isolation channel, and only digital signals can be transmitted without loss. If the analog voltage signal can be digitally modulated at the isolation end, the modulated digital signal includes low-frequency analog signals and high-frequency digital carrier signals. This digital signal can then be isolated and transmitted using a digital isolator. A digital filter built in the FPGA can then filter out the high-frequency carrier signal, allowing the original analog signal to be recovered. Compared to linear optocouplers directly transmitting analog signals through the isolation channel, this design eliminates signal distortion and attenuation in the isolated transmission link. This not only reduces the design complexity of the isolation channel but also makes the digital signal easier to process after passing through it. Traditional multiplexers, analog switches, and analog-to-digital converters can be omitted, allowing direct connection to the FPGA for digital signal processing. This significantly simplifies the hardware circuitry, reducing costs and improving design reliability.

[0035] Meanwhile, the output of this voltage-to-digital conversion circuit contains only a clock input signal CLK and a converted data output signal DAT. Both signals are CMOS level standards and can be directly fed into an FPGA system. When processing multiple measurement channels, the clock input signal CLK can be multiplexed, and the only independent signal for different channels is the data conversion signal DAT. In short, this solution features high measurement accuracy, small size, good stability, and ease of digital integration.

[0036] In addition, when choosing digital isolators, traditional solutions would choose digital optocouplers or magnetic isolators. The disadvantages of digital optocouplers are similar to those of linear optocouplers. Their signal transmission medium is light, which is slow, consumes a lot of power, and suffers from light decay, making it difficult to guarantee long-term reliability. Magnetic isolators use magnetic fields as their signal transmission medium. This is a technology that integrates signals using standard semiconductor processes. The internal signal transformer is a coreless transformer, which has the characteristics of high speed and high reliability. Its disadvantages are that it is more expensive, and the transformer itself is a radiation source, which may cause EMI problems.

[0037] This invention selects a capacitive isolator as the digital isolator, which has high insulation strength, low power consumption, high speed, simple and reliable structure, no EMI problem, and can achieve highly efficient isolated transmission of digital signals, thereby further reducing the size and cost of the circuit.

[0038] See Figure 2 The present invention includes:

[0039] See Figure 3 The signal conditioning circuit is used to receive bipolar voltage signals and output unipolar voltage signals to the voltage / digital conversion circuit. Since the conversion circuit is powered by a single power supply, in order to measure negative voltage, the signal conditioning circuit is used to convert bipolar analog voltage signals into unipolar analog voltage signals, while amplifying or attenuating the signals, implementing a first-order analog low-pass filter, and denoising the input signals.

[0040] The signal conditioning circuit includes operational amplifiers Op1 and Op2. The positive input terminal of operational amplifier Op2 is connected to one end of resistor R1, one end of resistor R2, and one end of capacitor C1. The other end of resistor R1 is connected to the positive terminal of the signal. The other end of resistor R2 is connected to the other end of capacitor C1, the output terminal of operational amplifier Op2, and the output signal vout. The inverting input terminal of operational amplifier Op2 is connected to one end of resistor R3, one end of resistor R4, and one end of capacitor C2. The other end of resistor R3 is the negative terminal of the signal. The other end of resistor R4 is connected to the other end of capacitor C2, the output virtual ground signal VG, the inverting input terminal of operational amplifier Op1, and the output terminal of operational amplifier Op1. The positive input terminal of operational amplifier Op1 is connected to one end of capacitor C3, one end of resistor R5, and one end of resistor R6. The other end of resistor R5 is connected to the voltage reference VREF. The other end of resistor R6 is connected to the other end of capacitor C3 and the ground terminal.

[0041] Operational amplifier Op1 is designed as a follower input mode, featuring high input impedance and low output impedance. It buffers the input voltage and outputs a virtual ground signal VG, which can absorb or output current to maintain the virtual ground signal VG constant. Operational amplifier Op2 is designed as a differential input mode, capable of extracting the differential term (V0) from the input signal. IN+ -V IN- The input bipolar positive and negative voltage is converted into a unipolar positive voltage. The signal swing is adjusted to within the operational amplifier supply voltage by forming an amplification or attenuation network through resistors R1, R2, R3 and R4. At the same time, the signal is low-pass filtered by forming poles through capacitors C1 and C2.

[0042] See Figure 4The voltage-to-digital conversion circuit is used to receive unipolar voltage signals and isolated clock signals, and output digital signals to capacitive digital isolators. The voltage-to-digital conversion circuit is used to quantize the input unipolar analog voltage signals according to the received clock frequency, output digitized "1" or "0", and output digital signals to capacitive digital isolators to be transmitted to the measurement end.

[0043] The voltage-to-digital conversion circuit includes summation nodes SUM1 and SUM2, a hysteresis comparator CMP, and a D flip-flop FILP.

[0044] The summation node SUM1 subtracts the unipolar positive voltage VOUT and the output signal Q of the D flip-flop FILP, and integrates the result in continuous time through the integrator I1.

[0045] The summation node SUM2 subtracts the output of integrator I1 from the output signal Q of D flip-flop FILP, and then integrates the result through integrator I2 in continuous time.

[0046] The hysteresis comparator CMP compares the output of integrator I2 with the VG signal in the signal conditioning circuit and outputs a digital value "1" or "0". The comparator has a certain hysteresis range to reduce the influence of circuit noise and outputs the signal to the D flip-flop FILP.

[0047] Under the influence of the input clock CLK, the D flip-flop FILP, combined with the voltage reference VREF, latches the output signal of the comparator CMP according to the clock cycle, and outputs a digital signal, "1" or "0", according to the clock cycle of CLK. The corresponding analog voltage is "+VREF" or "0", and is connected to the summing nodes SUM1 and SUM2 to become the system feedback signal.

[0048] The voltage reference VREF is a bandgap voltage reference. This circuit is unaffected by input voltage, DC current, and temperature, and provides a reference value for analog voltage conversion at the isolation terminal.

[0049] See Figure 5 A capacitive digital isolator is used to receive the clock signal from the FPGA system and output an isolated clock signal value to a voltage-to-digital converter circuit, which then outputs an isolated digital signal to the FPGA system. The capacitive digital isolator circuit is used to send the input digital signal back to the FPGA system through an isolation capacitor, or to shape the received digital signal and output a standard CMOS level to the FPGA system.

[0050] A capacitive digital isolator consists of a resistor and a hysteresis comparator. It has a mirror structure, corresponding to one channel of digital isolated transmission and one channel of digital isolated reception, corresponding to digital signals CLK and DAT. The digital signal modulation strategy is unipolar voltage edge pulse modulation. By setting an appropriate DC bias voltage, the output signal of the hysteresis comparator is latched using the rising and falling edges of the input digital signal, thereby transmitting the input digital signal to the other side.

[0051] The capacitive digital isolator includes hysteresis comparators CMP2 and CMP3. The input of hysteresis comparator CMP2 is connected to one end of resistor R7, one end of capacitor C4, and one end of resistor R8. The other end of capacitor C4 is connected to the input clock signal. The other end of resistor R7 is connected to the isolation power supply VCC1. The other end of resistor R8 is connected to one end of capacitor C6 and ground. The other end of capacitor C6 is connected to one end of resistor R10 and ground. The other end of resistor R10 is connected to one end of capacitor C5, one end of resistor R9, and the input of hysteresis comparator CMP3. The other end of capacitor C5 is connected to the input of the digital signal DAT. The other end of resistor R9 is connected to the digital power supply VCC2. The output of hysteresis comparator CMP2 outputs the clock signal, and the output of hysteresis comparator CMP3 outputs the digital signal.

[0052] Resistors R7, R8, R9, and R10 are all DC bias setting resistors, providing DC bias for isolation capacitors C4 and C5. Capacitors C4, C5, and C6 are all high-voltage isolation capacitors, characterized by small capacitance, low leakage current, high withstand voltage, and strong stability. Hysteresis comparators CMP2 and CMP3 are hysteresis comparators that latch the signal after the isolation capacitors to restore the edge signal to the correct digital level signal.

[0053] The FPGA system outputs a modulation clock CLK to a capacitive digital isolator and receives the digital signal DAT output by the capacitive digital isolator according to the edge of the modulation clock CLK. It implements a digital low-pass filter in the internal IP core and calculates the corresponding bipolar analog voltage value.

[0054] Example:

[0055] See Figure 6 This invention realizes a voltage measurement system with 4-channel path isolation. The scheme uses 4 sets of capacitive digital voltage conversion circuits to convert the voltage signals of 4 different reference ground lines. At the same time, an FPGA is used to generate a clock signal for the 4 conversion circuits and to acquire 4 data signals DAT1 to DAT4. Finally, the analog signal is restored and measured through an internally constructed digital filter.

Claims

1. A voltage-to-digital conversion circuit based on capacitive isolation, characterized in that, include: The signal conditioning circuit is used to receive bipolar voltage signals and output unipolar voltage signals to the voltage-to-digital conversion circuit. The voltage-to-digital converter circuit is used to receive a unipolar voltage signal and an isolated clock signal, and output a digital signal to a capacitive digital isolator. The voltage-to-digital converter circuit includes a summing node SUM1, a summing node SUM2, a hysteresis comparator CMP, and a D flip-flop FILP. The summation node SUM1 subtracts the unipolar positive voltage VOUT and the output signal Q of the D flip-flop FILP, and integrates the result in continuous time through the integrator I1. The summation node SUM2 subtracts the output of integrator I1 from the output signal Q of D flip-flop FILP, and then integrates the result through integrator I2 in continuous time. The hysteresis comparator CMP compares the output of the integrator I2 with the VG signal in the signal conditioning circuit, and outputs the signal to the D flip-flop FILP. Under the influence of the input clock CLK, the D flip-flop FILP, combined with the voltage reference VREF, latches the output signal of the comparator CMP according to the clock cycle, outputs a digital signal according to the clock cycle of CLK, and connects to the summing nodes SUM1 and SUM2 to become the system feedback signal. A capacitive digital isolator is used to receive the clock signal from the FPGA system, output the isolated clock signal to the voltage-to-digital converter circuit, and output the isolated digital signal to the FPGA system. The capacitive digital isolator includes hysteresis comparator CMP2 and hysteresis comparator CMP3; The input of hysteresis comparator CMP2 is connected to one end of resistor R7, one end of capacitor C4, and one end of resistor R8. The other end of capacitor C4 is connected to the input clock signal. The other end of resistor R7 is connected to the isolation power supply VCC1. The other end of resistor R8 is connected to one end of capacitor C6 and the ground terminal. The other end of capacitor C6 is connected to one end of resistor R10 and the ground terminal. The other end of resistor R10 is connected to one end of capacitor C5, one end of resistor R9, and the input of hysteresis comparator CMP3. The other end of capacitor C5 is connected to the input of digital signal DAT. The other end of resistor R9 is connected to the digital power supply VCC2. The output of hysteresis comparator CMP2 outputs the clock signal, and the output of hysteresis comparator CMP3 outputs the digital signal. Resistors R7, R8, R9, and R10 are all DC bias setting resistors; The signal conditioning circuit includes operational amplifier Op1 and operational amplifier Op2; The positive input terminal of operational amplifier Op2 is connected to one end of resistor R1, one end of resistor R2, and one end of capacitor C1. The other end of resistor R1 is connected to the positive terminal of the signal. The other end of resistor R2 is connected to the other end of capacitor C1, the output terminal of operational amplifier Op2, and the output signal VOUT. The inverting input terminal of operational amplifier Op2 is connected to one end of resistor R3, one end of resistor R4, and one end of capacitor C2. The other end of resistor R3 is the negative terminal of the signal. The other end of resistor R4 is connected to the other end of capacitor C2, the output virtual ground signal VG, the inverting input terminal of operational amplifier Op1, and the output terminal of operational amplifier Op1. The positive input terminal of operational amplifier Op1 is connected to one end of capacitor C3, one end of resistor R5, and one end of resistor R6. The other end of resistor R5 is connected to the voltage reference VREF. The other end of resistor R6 is connected to the other end of capacitor C3 and the ground terminal.

2. The voltage-to-digital conversion circuit based on capacitive isolation according to claim 1, characterized in that, The signal conditioning circuit is used to convert bipolar analog voltage signals into unipolar analog voltage signals, amplify or attenuate the signals, and perform noise reduction.

3. The voltage-to-digital conversion circuit based on capacitive isolation according to claim 1, characterized in that, The voltage-to-digital converter circuit is used to quantize the input unipolar analog voltage signal according to the received clock signal, output a digital signal to the capacitive digital isolator, and then transmit it to the measurement terminal.

4. The voltage-to-digital conversion circuit based on capacitive isolation according to claim 1, characterized in that, A capacitive digital isolator circuit is used to pass the input digital signal through an isolation capacitor, while simultaneously shaping the received digital signal and outputting a standard CMOS level to the FPGA system.

5. The voltage-to-digital conversion circuit based on capacitive isolation according to claim 1, characterized in that, The FPGA system outputs a modulation clock CLK to a capacitive digital isolator and receives the digital signal DAT output by the capacitive digital isolator according to the edge of the modulation clock CLK. It implements a digital low-pass filter in the internal IP core and calculates the corresponding bipolar analog voltage value.

6. The voltage-to-digital conversion circuit based on capacitive isolation according to claim 1, characterized in that, Capacitors C4, C5, and C6 are all high-voltage isolation capacitors.

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