Method for managing operations and corresponding memory device

Abstract

Embodiments of the present disclosure relate to methods for managing operations and corresponding memory devices. An embodiment method for managing operations for modifying the contents of a memory plane of a memory device coupled to a processing unit includes: communicating control of the operation by the processor unit to the memory device, the operation performed by the memory device, and information indicating the end of the operation communicated by the memory device itself to the processing unit at the end of the operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of French Application No. 2011586, filed on November 12, 2020, which is incorporated herein by reference. Technical Field

[0003] Embodiments relate to microelectronics, in particular to memory devices, and more particularly to the management of modifications of the contents of their memory planes (eg, during write operations). Background Art

[0004] The embodiments are applicable to all types of memories, in particular but not limited to non-volatile memories of the electrically erasable and programmable type (EEPROM memories) or flash memories.

[0005] The modification of the contents of a memory plane usually involves a write operation in this memory plane, but also depends on the vocabulary used for the different types of memories, a write cycle of an EEPROM memory (an erase step followed by a programming step), or the programming of a Flash memory (a write-erase cycle).

[0006] Currently, when memory devices are used in applications connected to a processing unit (e.g. a microprocessor or a microcontroller), the only way to know whether the memory is available again after controlling an operation (write, erase or program) for modifying the contents of its memory plane is to use the resources of the microprocessor to check the state of the memory.

[0007] More specifically, according to the first solution, when the write control is transmitted, the microprocessor can internally trigger a time counter. The value of this counter depends on the characteristics of the memory. When the counter has reached its maximum count value, the write operation is then considered to have been completed.

[0008] According to a second solution, the microprocessor can perform an operation known as a "polling" operation, according to a name well known to those skilled in the art, consisting in interrogating the memory to find out the logical state of some control bits in order to determine when the write operation is finished and therefore when the memory is available again.

[0009] However, regardless of the solution considered, it requires the microprocessor to use internal resources, which cannot be used to perform other actions. In addition, using these internal resources can reduce the speed of the application and increase current consumption.

[0010] Furthermore, with respect to the first solution described above, by default, the maximum count value is typically greater than the time required to perform a write operation. Summary of the invention

[0011] Therefore, there is a need to overcome the above-mentioned disadvantages and to propose a solution that allows a processing unit (e.g. a microprocessor) to determine the end time of an operation for modifying the content of a memory plane of a memory device without excessively affecting its operation, in particular in terms of consumption.

[0012] It is also proposed to provide a solution which does not affect the volume requirements of the microprocessor and memory devices.

[0013] According to one implementation and embodiment, it is proposed that the memory device itself informs the processing unit of the end of an operation for modifying its memory content, such as in particular a write operation using already existing memory device pins.

[0014] According to one aspect, a method for managing operations for modifying (eg, writing, erasing, programming) contents of a memory plane of a memory device coupled to a processing unit is thus provided.

[0015] The method according to this aspect includes control of an operation communicated by a processing unit to a memory device, execution of the operation by the memory device, and, at the end of the operation, information communicated by the memory device itself to the processing unit indicating the end of the operation.

[0016] Thus, the processing unit (eg, a microprocessor) does not use its internal resources to determine the end of the modification operation, since it is the memory device itself that will inform the processing unit of the end of the operation.

[0017] Therefore, this will not slow down the application and will not affect the current consumption.

[0018] In practice, the memory device may include an auxiliary pin whose logic state is managed by the processing unit and can be interpreted by the memory device only during communications controlled by the processing unit.

[0019] In this case, the method advantageously comprises managing, by the memory device, the logic state of the auxiliary pin and the configuration of the processing unit in an interrupt detection mode on the auxiliary pin during the execution of the operation and during the communication of the stop information.

[0020] The communication of the stop information then comprises a modification of the logic state of the auxiliary pin by the memory device, which modification can be interpreted as an interrupt by the processing unit.

[0021] Thus, during communication between the processing unit and the memory device for control of the transmit operation, the auxiliary pin is in input mode and its logic state is managed by the processing unit. The logic state can be interpreted by the memory device.

[0022] On the other hand, from the end of the stored content modification operation control (which marks the actual start of the modification operation), the logic state of the auxiliary pin can no longer be interpreted by the memory device. Therefore, the auxiliary pin will switch to output mode and be used to indicate to the processing unit that the write operation has been completed.

[0023] More specifically, therefore, once a write operation (for example) is completed, the memory device itself will manage the logic state of the auxiliary pin and modify its logic state (for example, create a falling edge). The processing unit configured in interrupt mode will then detect this interrupt and conclude that the write operation is completed and the memory is available again.

[0024] It can therefore be seen here that, as mentioned above, no internal microprocessor resources are used. The microprocessor only has to manage interrupts on the line connecting the auxiliary pin to the processing unit.

[0025] Also, the proposed solution requires no additional bulk since existing memory device pins are used.

[0026] According to one implementation, the memory device is coupled to the processing unit via a communication medium that supports a serial communication protocol.

[0027] The serial communication protocol includes a clock signal line and at least one data signal line, and an auxiliary line connecting the processing unit to the auxiliary pin.

[0028] Furthermore, the auxiliary line is separated from the clock signal line and the at least one data line.

[0029] In practice, the clock signal lines and data lines should not be used as auxiliary lines, since the transitions on these lines may be interpreted as another event by another processing unit and / or another memory device connected to the communication medium.

[0030] For example, the communication medium may support the I2C communication protocol.

[0031] In this case, a pin that receives an auxiliary logic signal during communication controlled by the processing unit, which prohibits or authorizes the execution of an operation, may be selected as an auxiliary pin.

[0032] Thus, the auxiliary pin may be a pin that is commonly referred to by those skilled in the art by the acronym / WC that receives the logic signal of the same name.

[0033] The communication medium may also be a medium supporting the SPI communication protocol.

[0034] In this case, the auxiliary pin may be a pin that receives an auxiliary logic signal during communication controlled by the processing unit, the auxiliary logic signal causing or not causing a pause in the communication between the processing unit and the memory device.

[0035] In other words, for example, the auxiliary pin may be a pin that is commonly known by those skilled in the art under the name of "hold" and receives a logic signal of the same name.

[0036] Alternatively, still when the communication protocol is the SPI protocol, the auxiliary pin may be a pin that receives an auxiliary logic signal during communication controlled by the processing unit, the auxiliary logic signal activating or deactivating protection of the memory device from being affected by the operation.

[0037] In other words, in this case, the auxiliary pin may be a pin commonly known to those skilled in the art by the acronym WP for the logic signal receiving the same name.

[0038] The memory device may be a non-volatile memory device such as an EEPROM memory or a flash memory.

[0039] According to another aspect, a memory device is provided, the memory device comprising a memory plane, a control interface configured to be coupled to a processing unit and intended to receive from the processing unit controls for operations to modify the content of the memory plane.

[0040] The memory device also includes an auxiliary interface configured to be coupled to the processing unit.

[0041] The memory device further includes a processing circuit configured to perform the operation and, upon completion of the operation, communicate information indicating completion of the operation to the processing unit via the auxiliary interface.

[0042] According to one embodiment, the auxiliary interface comprises an auxiliary pin, the logic state of which is intended to be managed by the processing unit and can be interpreted by the processing circuit only during communications controlled by the processing unit.

[0043] Furthermore, the processing circuit is configured to manage a logic state of the auxiliary pin and to modify the logic state of the auxiliary pin during execution of the operation and during communication of the stop information so as to generate an interrupt that can be interpreted as the stop information by the processing unit.

[0044] According to one embodiment, the control interface and the auxiliary interface are configured to be coupled to the processing unit through a communication medium configured to support a serial communication protocol and including a clock signal line, at least one data signal line, and an auxiliary line connecting the processing unit to the auxiliary pin.

[0045] The auxiliary line is separated from the clock signal line and the at least one data line.

[0046] When the communication medium is configured to support the I2C communication protocol, the auxiliary pin may be a pin configured to receive an auxiliary logic signal during communication controlled by the processing unit, the auxiliary logic signal prohibiting or authorizing execution of an operation.

[0047] When the communication medium is configured to support the SPI communication protocol, the auxiliary pin may be a pin configured to receive an auxiliary logic signal during communication controlled by the processing unit, the auxiliary logic signal causing or not causing a pause in communication between the processing unit and the memory device.

[0048] Alternatively, still in the case of the SPI communication protocol, the auxiliary pin may be a pin that receives an auxiliary logic signal during communication controlled by the processing unit, which auxiliary logic signal activates or deactivates the protection of the memory device from the operation.

[0049] According to another aspect, a system is provided, the system comprising a processing unit (eg a microprocessor or a microcontroller), a memory device as defined above, and a communication medium coupling a control interface and an auxiliary interface of the device to the processing unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Other advantages and features of the present invention will become apparent upon reading the following detailed description and examining the non-limiting accompanying drawings, in which:

[0051] Figure 1 A processing unit is illustrated connected to a memory device via a communications medium;

[0052] Figure 2 A method for managing operations for modifying contents of a memory plane of a memory device is illustrated;

[0053] Figure 3 The diagram shows the ability to 2 An integrated non-volatile EEPROM memory device that communicates on the C bus;

[0054] Figure 4 The diagram shows 2 C bus signals for example communications performed;

[0055] Figure 5 A prior art example of writing in a memory device is illustrated;

[0056] Figure 6 An example embodiment of writing in a memory device is illustrated;

[0057] Figure 7illustrates circuitry that allows the logic state of a signal delivered to an auxiliary terminal to be managed by processing circuitry of a memory device;

[0058] Figure 8 The diagram illustrates a memory device connected to a processing unit via a bus supporting the SPI protocol;

[0059] Fig. 9 illustrates a prior art write operation in a memory device;

[0060] Fig.10 illustrates an embodiment write operation in a memory device; and

[0061] Fig.11 Circuitry is illustrated that allows auxiliary signals to be managed by processing circuitry of a memory device. DETAILED DESCRIPTION

[0062] exist Figure 1 In the drawings, reference numeral SYS denotes a system comprising a processing unit UT (eg a microprocessor or a microcontroller) connected to a memory device DM via a communication medium BS (eg a bus).

[0063] The memory device DM is here a non-volatile memory, for example an EEPROM memory or a flash memory, but these examples are not limiting.

[0064] The memory device includes a memory plane PM for storing data, as well as a control interface INTC and an auxiliary interface BRX.

[0065] As will be seen in more detail below, the control interface connected to the bus BS is intended to receive controls for operations modifying the content of a memory plane, such as write operations, from the processing unit UT.

[0066] The processing circuit MT is connected between the control interface INTC, the auxiliary interface BRX and the memory plane PM, and includes conventional circuits configured to perform operations and other circuits. A structural example of the processing circuit will be described in more detail below, and is intended to communicate information indicating the end of the operation (here a write operation) to the processing unit UT via the auxiliary interface BRX.

[0067] Finally, the memory device includes one pin connected to a power supply voltage VCC and another pin connected to a reference voltage VSS (eg, ground GND).

[0068] As will be seen in more detail below, the auxiliary interface BRX may be a pin of a memory device that is not normally used when the memory device is no longer selected by the processing unit.

[0069] Now more specifically refer to Figure 2 An embodiment of a method for managing operations for modifying the contents of a memory plane PM of a memory device DM is described.

[0070] Typically, in step ST20, the processing unit communicates control of the modification operation (here, write control) to the memory device DM.

[0071] In this communication phase, the auxiliary interface BRX is managed by the processing unit UT (step ST200).

[0072] The auxiliary interface BRX is then in input mode.

[0073] Once the write control has been received and the memory device has been deselected on the bus BS, the memory device DM performs the operation in step ST21, in this case writing the given data to the defined address.

[0074] Although in step ST200 the logical state of the auxiliary interface BRX is managed by the processing unit UT and can be interpreted by the memory device, during the execution ST21 of the write, the logical state of the auxiliary interface BRX is this time managed by the memory device (step ST201) and the processing unit UT is configured in the interrupt detection mode IT on the auxiliary interface BRX (step ST202).

[0075] The auxiliary interface BRX is then in output mode.

[0076] At the end of the write operation, the memory device DM communicates (step ST22 ) information INFF indicating the end of the write operation to the processing unit via the auxiliary interface BRX.

[0077] At this stage of communication ST22, the management of the logic state of the auxiliary pin is always performed by the memory device (step ST220), and the communication of the stop information INFF comprises a modification of the logic state of the auxiliary interface BRX by the memory device DM, which can be interpreted by the processing unit UT as an interruption IT. The detection of this interruption IT by the processing unit indicates to the latter that the write operation is completed.

[0078] Now we will describe in more detail the case where the bus BS is supported by I 2 C protocol and SPI protocol buses are two specific exemplary embodiments and implementations that can be used, respectively.

[0079] Figure 3 The diagram shows the ability to 2 Integrated non-volatile memory devices of EEPROM type communicating on a bus BS of type C.

[0080] In this example, the memory device includes three hardware identification pins E0, E1, E2, but the number is not limited.

[0081] The hardware identification pins E0, E1, E2 are intended to be assigned a corresponding potential which defines an assignment code specific to the memory device DM. The assignment of these potentials is performed in a substantial manner, for example, during integration of an integrated circuit on a card.

[0082] These hardware identification pins E0, E1, E2 are coupled to VCC or VSS. When not connected, these inputs usually default to reading at VSS. Coupling to VCC defines a logic signal with a value of "1" in the assigned code, and coupling to VSS defines a logic signal with a value of "0".

[0083] The memory plane of the memory device DM allows digital data to be stored in memory locations arranged in rows and columns. The memory locations typically include floating gate transistors capable of physically storing representations of digital data (that is to say bits) in a conventional manner known per se. Each bit is stored in a memory location and is assigned a corresponding memory address, the communication of which allows the memory to access the memory location in a read mode or a write mode.

[0084] The integrated memory device DM further includes an input / output pin of a serial data line SDA and an input pin of a serial clock line SCL, and an auxiliary pin BRX for receiving a write control signal / WC.

[0085] The input / output pin of the serial data line SDA and the input pin of the serial clock line SCL are part of the control interface INTC, and the auxiliary pin BRX forms an auxiliary interface.

[0086] The input / output pin SDA is used to communicate incoming data or outgoing data.

[0087] The signal applied to the input pin SLC is used to clock the incoming and outgoing signals on the line SDA.

[0088] The presence of the signal / WC on the auxiliary pin BRX allows the contents of the memory to be protected from accidental write operations.

[0089] For example, when the signal / WC present at the pin BRX is at a high level, a write operation in the memory becomes impossible. When the signal / WC present at the pin BRX is at a low level or floating, a write operation is possible.

[0090] I 2 C-bus is a well-known serial inter-IC communication standard.

[0091] Figure 4 I2 C-bus.

[0092] I 2 The C bus consists of two wires (serial data line SDA and serial clock line SCL), which are connected to the I 2 C-bus communicates information between devices. Each device is identified by a unique slave address (e.g., whether it is a microcontroller, memory, or keyboard interface), and each device can be used as a transmitter or receiver depending on the function of the device. For example, a memory device DM can receive data (e.g., write) or send data (e.g., read). The host is the device that initiates data communication on the bus and generates a clock signal to allow the communication. At this time, any device being addressed is considered a slave device.

[0093] The SDA line is a bidirectional line, via I 2 C-bus communication is implemented by signals that can have either a high level or a low level.

[0094] During data communication, the line signal SDA must be stable during the high level period of the clock signal. The high state or low state of the data line SDA can only change when the clock signal on the line SCL is at a low level.

[0095] All transitions start with a "start" condition STT and end with a "stop" condition STP. A high-to-low transition on the line SDA when SCL is high defines the start condition STT. A low-to-high transition on the line SDA when SCL is high defines the stop condition STP.

[0096] On the SDA line, the high and low levels of the signal represent the logical values ​​"1" and "0" respectively.

[0097] Data communication complies with Figure 1 After the start condition STT, the slave address SLADR is sent. This address is encoded in 7 bits, followed by the direction The eighth bit, "zero" indicates communication (or writing) W, and "one" indicates request data (or reading) R.

[0098] The data DATA1, DATA2 are communicated by bytes (i.e., 8 bits) on line SDA. There is no limit to the number of bytes that can be communicated per transmission. Each byte must be followed by an acknowledgement bit ACK. Conventionally, the data DATA1, DATA2 are transmitted with the most significant bit MSB in the first position.

[0099] An acknowledgement occurs after each byte. The acknowledgement bit ACK allows the receiver to signal to the transmitter that the byte has been successfully received and another byte can be sent.

[0100] Data transmission always ends with a stop condition STP generated by the master.

[0101] In a read or write operation, the first memory address to be accessed in the memory plane is communicated to the memory device immediately following the slave address SLADR.

[0102] The selection of a memory device on a bus among the several devices connected to the same bus is well known to a person skilled in the art and depends, among other things, on the type and memory size of the memory device.

[0103] For example, in some cases, the last three least significant bits of the slave address SLADR allow an EEPROM memory device to be selected from among several memory devices by comparing the value of the bits XXX to an assigned code associated with each EEPROM memory device.

[0104] Now more specifically refer to Figure 5 and Figure 6 , Figure 5 and Figure 6 The prior art ( Figure 5 ) and according to the embodiments and implementations of the present invention ( Figure 6 ) is written in a memory device.

[0105] like Figure 5 As shown, during a duration D0 extending between a start condition STT and a stop condition STP, the processing unit UT communicates on the line SDA the data to be written at the addresses defined in the memory plane.

[0106] Furthermore, for this duration D0 , the signal / WC generated by the processing unit and communicated to the auxiliary pin BRX is in the low state, which therefore enables a write operation.

[0107] Upon receipt of the stop condition STP, phase D1 begins, during which the memory device performs a write operation.

[0108] Also, during phase D1 , the auxiliary pin BRX is not used and its logic state is not interpreted by the memory device, which is no longer selected on the bus during this phase D1 .

[0109] Unlike the prior art, although in the corresponding Figure 2 During the duration D0 of step ST20 the auxiliary signal / WC remains in the low state and is managed by the processing unit UT, but the logic state of this signal / WC is now managed by the memory device from the occurrence of the stop condition STP.

[0110] More specifically, when the stop condition STP occurs, the memory device generates a rising edge FM on the auxiliary signal / WC in order to switch the logic state of the signal to a high level state.

[0111] Then, the write operation is performed during the duration D2.

[0112] And, at the end of the duration D2, that is, when the write operation is completed, the memory device switches the logic state of the auxiliary signal / WC to a low level state again.

[0113] Therefore, a falling edge is generated, which is interpreted by the processing unit as an interrupt IT which means the end of the write operation and corresponds to the stop information INFF.

[0114] It should be noted here that the rising edge FM of the signal / WC is not interpreted as an interrupt by the processing unit, since it is configured to detect the falling edge of the signal / WC as an interrupt.

[0115] From a hardware perspective, Figure 7 The example of a schematic circuit shown in allows managing the logic state of a signal delivered to the auxiliary terminal BRX by the processing circuit of the memory device during a duration D2.

[0116] In this regard, the processing circuit MT comprises a control module CTRL comprising a PMOS transistor MP1, whose source is connected to the voltage VCC and whose drain is connected to the auxiliary terminal BRX, and an NMOS transistor MN1, whose source is connected to the ground GND and whose drain is also connected to the auxiliary pin BRX.

[0117] The gate of transistor MP1 is connected to the output of a NOR logic gate of reference PL1, and the gate of transistor MN1 is connected to the output of a NOR logic gate of reference PL2.

[0118] A first input of logic gate PL1 and a first input of logic gate PL2 receive a bit of reference BUSY.

[0119] A second input of the logic gate PL1 receives the bit of reference OUTPUT_BUSY, and a second input of the logic gate PL2 receives the inverted bit OUTPUT_BUSY via the inverter INV1.

[0120] The bit OUTPUT_BUSY is delivered by the control logic LGC1 , while the bit BUSY is delivered by the control logic LGC2 .

[0121] The bit OUTPUT_BUSY represents the "input mode" state or the "output mode" state of the auxiliary pin BRX, that is to say the device managing its logic state (processing unit in input mode or memory device in output mode).

[0122] Thus, for example, during step ST20 (duration D0 ), the bit OUTPUT_BUSY has a logic value of 0 and it assumes a logic state of 1 when the stop condition STP occurs.

[0123] The value of this bit is managed by the processing unit according to the control sent to the memory ("write" signal) and the end of communication condition (corresponding to the deselection of the memory device on the bus). A person skilled in the art will know how to implement the control logic LGC1 accordingly.

[0124] As for the bit BUSY, it is usually a bit passed by the memory, which indicates whether it is available. In other words, as long as the write operation has not started, the bit BUSY is 0. Then, it is switched to 1 during the write operation and switched back to 0 at the end of the write operation.

[0125] Logic LGC2 is conventional structural logic.

[0126] Therefore, from Figure 7 As can be seen in FIG. 1 , when the bit OUTPUT_BUSY is 0, a high state is applied to the gate of transistor MP1 and turns transistor MP1 off. Similarly, a state 0 is applied to the gate of transistor MN1 and turns transistor MN1 off. Thus, transistors MP1 and MN1 are disconnected from the auxiliary pin BRX, which allows the processing unit to manage the logic state of the auxiliary pin.

[0127] On the other hand, when the stop condition STP occurs, the bit OUTPUT_BUSY switches to 1, as does the bit BUSY, the transistor MP1 is turned on, and the transistor MN1 is turned off. Therefore, the auxiliary signal / WC switches to a high level state.

[0128] The auxiliary signal remains in a high state until the write operation is completed. And, once the write operation is completed, the bit BUSY switches to 0, which turns off the transistor MP1 and turns on the transistor MN1. Therefore, the auxiliary signal / WC switches to state 0, which causes the falling transition to be detected by the processing unit as an interrupt and interpreted as the write end information INFF.

[0129] exist Figure 8 In an embodiment, the memory device is connected to the processing unit via a bus supporting the SPI protocol.

[0130] The SPI protocol is well known to those skilled in the art.

[0131] Some of the features are reviewed below.

[0132] The master is connected to one or more slaves via 4 (in simultaneous bidirectional transfer mode) or more lines:

[0133] SCLK: Clock

[0134] MOSI: master output, slave input, to transmit data to the slave

[0135] MISO: Master input, slave output, to receive data from the slave

[0136] SS: Slave Select Line (Active LOW to select the slave).

[0137] Therefore, the memory device comprises four protocol pins connected to the SS line, the MISO line, the MOSI line and the SCLK line respectively. These protocol pins are part of the control interface.

[0138] The memory device DM further comprises two auxiliary pins BRX intended to receive an auxiliary signal WP and an auxiliary signal HOLD, respectively, from the processing unit UT.

[0139] The auxiliary signal WP is a signal that activates or deactivates the memory device from a write operation.

[0140] When the signal WP is at a high level, writing is possible.

[0141] When the signal WP is low, writing is impossible.

[0142] The signal HOLD is an auxiliary logic signal that causes or does not cause the communication between the processing unit and the memory device to be suspended.

[0143] When the signal HOLD is in a low level state, if the signal HOLD is in a high level state, when the signal HOLD is not suspended, the communication is suspended.

[0144] As will be seen in more detail below, one of the two auxiliary pins may be selected as the auxiliary interface.

[0145] The SPI system can be configured to operate with a single master and a single slave, and it can be configured to operate with multiple slaves controlled by a single master. There are two ways to connect several slaves to a master. If the master has several slave select pins, the slaves can be wired in parallel. If only one slave select pin is available, the slaves can be connected in cascade.

[0146] The clock signal SCLK synchronizes the output of the data bits from the master with the bits sampled by the slave. One data bit is transmitted per clock cycle, so that the data transfer rate is determined by the frequency of the clock signal. The SPI communication clock is always initiated by the master because the master configures and generates the clock signal.

[0147] By keeping the SS line of the slave at a low voltage level, the master can select which slave it wants to interact with. In the inactive state, in the absence of transmission, the slave select line is held at a high voltage level.

[0148] The master sends data to the slave in series, bit by bit, via the MOSI line. The slave receives the data sent by the master on the MOSI pin. Data sent from the master to the slave is usually (but not necessarily) sent with the most significant bit (MSB) first.

[0149] The slave can also send data back to the master via the serial MISO line.Data sent from the slave to the master is usually sent with the least significant bit (LSB) first.

[0150] Data is valid only during the low period of SS.

[0151] The steps of SPI data transmission are as follows:

[0152] The master passes the clock signal; the master switches the SS pin to a low voltage state that activates the slave; the master sends data bit by bit to the slave on the MOSI line. The slave reads the bits as it receives them; if a response is required, the slave sends the data back bit by bit to the master on the MISO line. The master reads the bits as it receives them.

[0153] During a write operation, the processing unit is the master on the bus and the memory device is the slave.

[0154] Fig. 9 A write operation in a memory device DM according to the prior art is illustrated.

[0155] During the D0 phase of selecting a memory device on the SPI bus, the SS select signal is in a low state and a write control containing the data to be written and the address to which the data must be written is communicated on the MOSI line.

[0156] When the product is deselected (SS signal in high state), phase D1 begins during which the actual writing is performed.

[0157] It can be seen that during phase D0 the auxiliary signals HOLD and WP are in the high state here, which means that the communication is not interrupted and writing in the memory is possible.

[0158] Furthermore, during D1, these signals remain in a high state and cannot be interpreted by the memory device under any circumstances.

[0159] On the other hand, Fig.10 In the illustrated implementation of the invention, when the memory device is deselected at the end of phase D0 (SS signal is in the high state), the auxiliary signal HOLD or the auxiliary signal WP (depending on the selection that has been made) returns to the low state under the action of the processing circuit of the memory device, thereby generating a falling edge FD.

[0160] During the duration D2 of the actual write operation, the auxiliary signal remains at a low level.

[0161] And, when the write operation is completed, the processing circuit MT of the memory device returns the auxiliary signal to a high level state, generating an interrupt IT which is interpreted by the processing unit as stop information INFF of the write operation.

[0162] It should be noted here that in the case of the SPI bus, the processing unit is configured in an interrupt detection mode on a rising edge.

[0163] Fig.11 An example of a hardware circuit is illustrated which allows the auxiliary signal HOLD or WP to be managed by the processing circuit during the duration D2 .

[0164] It can be seen here that the structure of the processing circuit is similar to that already referred to Figure 7 The structure described is different in that an inverter INV2 is now provided which is connected between the drains of the transistors MP1 and MN1 and the selected auxiliary pin BRX.

[0165] The operation of the circuit is therefore similar to that already described below, the inversion of the logic signal delivered to the terminal BRX being produced by the inverter INV2.

[0166] Furthermore, the internal structure of the logic LGC1 is adapted to the signals of the SPI bus.

Claims

1. A method of managing operations for a memory plane of a memory device, the memory plane of the memory device being coupled to a processing unit, the operations being for modifying contents of the memory plane, the memory device comprising auxiliary pins, and the method comprising: communicating, by the processing unit, control of the operation to the memory device; being interpreted by said memory device only during said communication controlled by said processing unit; performing the operation by the memory device; managing, by the memory device, a logic state of the auxiliary pin during the execution; configuring the processing unit in an interrupt detection mode on the auxiliary pin; as well as Information indicating the end of the operation is communicated by the memory device to the processing unit, the communication comprising modifying, by the memory device, the logic state of the auxiliary pin, the logic state for being interpreted by the processing unit as an interrupt.

2. The method of claim 1 , wherein the memory device is coupled to the processing unit via a communication medium, the communication medium supporting a serial communication protocol and comprising a clock signal line, at least one data signal line, and an auxiliary line connecting the processing unit to the auxiliary pin, the auxiliary line being separate from the clock signal line and the at least one data signal line.

3. The method of claim 2, wherein the communication medium supports inter-integrated circuit (IIC) communication. 2 C) a communication protocol, and the method comprises receiving, by the auxiliary pin, an auxiliary logic signal during the communication of the control by the processing unit, the auxiliary logic signal inhibiting or authorizing the performance of the operation.

4. The method of claim 2 , wherein the communication medium supports a serial peripheral interface (SPI) communication protocol, and the method includes receiving an auxiliary logic signal by the auxiliary pin during the communication controlled by the processing unit, the auxiliary logic signal causing or not causing the communication between the processing unit and the memory device to be suspended.

5. The method of claim 2 , wherein the communication medium supports a serial peripheral interface (SPI) communication protocol, and the method includes receiving an auxiliary logic signal by the auxiliary pin during the communication of the control by the processing unit, the auxiliary logic signal activating or deactivating protection of the memory device from the impact of the operation. The method of claim 1 , wherein the memory device is a non-volatile memory device.

7. A memory device comprising: Memory plane; a control interface configured to be coupled to a processing unit and to receive from the processing unit a control for an operation to modify the contents of the memory plane; an auxiliary interface configured to be coupled to the processing unit, the auxiliary interface comprising an auxiliary pin, a logic state of the auxiliary pin being managed by the processing unit and interpreted by the processing unit only during communication of the control through the processing unit; as well as A processing circuit is configured to perform the operation and, at the end of the operation, communicate information indicating the end of the operation to the processing unit via the auxiliary interface, wherein the processing circuit is also configured to manage the logic state of the auxiliary pin and modify the logic state of the auxiliary pin during the execution of the operation and during the communication of the stop information so as to generate an interrupt that is interpreted by the processing unit as information about the end of the operation.

8. The device of claim 7, wherein the control interface and the auxiliary interface are configured to be coupled to the processing unit via a communication medium, the communication medium being configured to support a serial communication protocol, and the communication medium comprising a clock signal line, at least one data signal line, and an auxiliary line connecting the processing unit to the auxiliary pin, the auxiliary line being separate from the clock signal line and the at least one data signal line.

9. The apparatus of claim 8, wherein the communication medium is configured to support inter-integrated circuit (IIC) communication. 2 C) a communication protocol, and said auxiliary pin is configured to receive an auxiliary logic signal during said communication of said control by said processing unit, said auxiliary logic signal inhibiting or authorizing said execution of said operation.

10. The device of claim 8, wherein the communication medium is configured to support a serial peripheral interface (SPI) communication protocol, and the auxiliary pin is configured to receive an auxiliary logic signal during the communication of the control by the processing unit, the auxiliary logic signal causing or not causing the communication between the processing unit and the memory device to be suspended.

11. The device of claim 8, wherein the communication medium is configured to support a serial peripheral interface (SPI) communication protocol, and the auxiliary pin is configured to receive an auxiliary logic signal during the communication of the control by the processing unit, the auxiliary logic signal activating or deactivating protection of the memory device from the impact of the operation.

12. The device of claim 7, wherein the memory device is a non-volatile memory device.

13. An electronic system comprising: Processing unit; Memory devices, including: Memory plane; a control interface configured to receive from the processing unit a control for an operation to modify the contents of the memory plane; an auxiliary interface comprising an auxiliary pin, the logic state of which is managed by the processing unit and interpreted by the processing unit only during communications of the control through the processing unit; and a processing circuit configured to perform the operation and, at the end of the operation, communicate information indicating the end of the operation to the processing unit via the auxiliary interface, wherein the processing circuit is further configured to manage the logic state of the auxiliary pin and modify the logic state of the auxiliary pin during the execution of the operation and during the communication of stop information so as to generate an interrupt that is interpreted by the processing unit as information of the end of the operation; and A communication medium couples the control interface and the auxiliary interface of the memory device to the processing unit.

14. The electronic system of claim 13, wherein the control interface and the auxiliary interface are configured to be coupled to the processing unit via a communication medium, the communication medium being configured to support a serial communication protocol, and the communication medium comprising a clock signal line, at least one data signal line, and an auxiliary line connecting the processing unit to the auxiliary pin, the auxiliary line being separate from the clock signal line and the at least one data signal line.

15. The electronic system of claim 14, wherein the communication medium is configured to support inter-integrated circuit (I 2 C) a communication protocol, and said auxiliary pin is configured to receive an auxiliary logic signal during said communication of said control by said processing unit, said auxiliary logic signal inhibiting or authorizing said execution of said operation.

16. The electronic system of claim 14 , wherein the communication medium is configured to support a serial peripheral interface (SPI) communication protocol, and the auxiliary pin is configured to receive an auxiliary logic signal during the communication controlled by the processing unit, the auxiliary logic signal causing or not causing the communication between the processing unit and the memory device to be suspended.

17. The electronic system of claim 14, wherein the communication medium is configured to support a serial peripheral interface (SPI) communication protocol, and the auxiliary pin is configured to receive an auxiliary logic signal during the communication of the control by the processing unit, the auxiliary logic signal activating or deactivating protection of the memory device from the effects of the operation.

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