Semiconductor device

Abstract

A semiconductor device includes a memory block, a second power supply wiring, a third power supply wiring, and a short-circuit switch, the memory block has a plurality of memory cells, a sense amplifier connected to a memory cell selected from the plurality of memory cells, a first power supply wiring, a first switch connected between the sense amplifier and the first power supply wiring and in an on state when the sense amplifier operates, and a second switch connected to the sense amplifier and in an on state when the sense amplifier operates, the second power supply wiring is arranged outside the memory block and connected to the first power supply wiring, the third power supply wiring is arranged outside the memory block and connected to the sense amplifier via the second switch, and the short-circuit switch is arranged outside the memory block and connected between the second power supply wiring and the third power supply wiring. Here, the short-circuit switch is in an on state when the sense amplifier operates.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Japanese Patent Application No. 2020-177830, filed on October 23, 2020, the contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to a semiconductor device, such as a semiconductor device including a memory. Background Technology

[0004] The memory included in semiconductor devices includes, for example, dynamic memory and static memory.

[0005] The publicly available technologies are listed below.

[0006] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2008-299893 Summary of the Invention

[0007] Semiconductor devices are becoming increasingly faster, and power supply voltages are decreasing. When a sense amplifier in a memory is driven by a single power supply voltage, it may become inoperable if its operating margin is small. To increase the operating margin of the sense amplifier, the OD method shown in Patent Document 1 exists.

[0008] In the OD method, the sense amplifier is driven by two types of supply voltages with different values. Specifically, during the initial period when the sense amplifier starts operating (the initial sensing phase), it is driven by a supply voltage with a high voltage value, and then by a supply voltage with a low voltage value. This allows for an increased operating margin for the sense amplifier during the initial period. However, during the initial period, a relatively large drive current flows through the sense amplifier from the supply voltage with the high voltage value, resulting in increased power consumption.

[0009] The inventors have considered applying the OD method to sense amplifiers with smaller operating margins rather than to sense amplifiers with larger operating margins. The operating margin of a sense amplifier determines (limits) the operating margin of a semiconductor device and varies, for example, due to process variations and / or component variations in the manufacture of the semiconductor device. Figure 12 This is a view illustrating the process variations of semiconductor devices. Figure 12 In this context, Fast, Typ, and Slow indicate the speed of the components that make up a semiconductor device, such as the speed of a field-effect transistor (hereinafter also referred to as a MOSFET). The speed of a MOSFET also varies due to variations in manufacturing processes. Figure 12 As shown.

[0010] The operating margin of a sense amplifier decreases as the speed of (multiple) components decreases and increases as the speed of components increases. Applying the over-displacement (OD) method when the operating margin is small (i.e., at low speeds) increases power consumption, but this prevents the semiconductor device from becoming inoperable. Conversely, when the operating margin is large, i.e., at standard and high speeds, not applying the OD method (in the absence of OD) reduces power consumption.

[0011] However, the inventors' research has found that the sense amplifier may not operate stably when the OD method is not applied. Taking Figure 5 of Patent Document 1 as an example, when the OD method is not applied, the MOSFET (Tr6) is in the off state during the initial period. At this time, it becomes difficult for the sense amplifier to operate stably at high speed when the driving capability of the MOSFET (Tr5) driving the sense amplifier is insufficient, when the power supply wiring network supplying the power supply voltage to the sense amplifier via the MOSFET (Tr5) is weak, or when the timing of the operation of the MOSFET (Tr5) is inappropriate.

[0012] A semiconductor device according to an embodiment described in this specification will now be described.

[0013] That is, the semiconductor device includes a memory block, a second power supply line, a third power supply line, and a third switch. The memory block has: a plurality of memory cells, a sense amplifier connected to a memory cell selected from the plurality of memory cells, a first power supply line, a first switch connected between the sense amplifier and the first power supply line and in an ON state when the sense amplifier is operating, and a second switch connected to the sense amplifier and in an ON state when the sense amplifier is operating. The second power supply line is disposed outside the memory block and connected to the first power supply line. The third power supply line is disposed outside the memory block and connected to the sense amplifier via the second switch. The third switch is disposed outside the memory block and connected between the second power supply line and the third power supply line. Here, the third switch is in an ON state when the sense amplifier is operating.

[0014] Other objects and novel features of the present invention will become clear from the description in this specification and the accompanying drawings.

[0015] According to one embodiment, a semiconductor device having a memory capable of high-speed and stable operation can be provided. Attached Figure Description

[0016] Figure 1 This is a view showing the construction of the storage body according to the first embodiment;

[0017] Figure 2This is a schematic plan view illustrating the construction of a memory block according to the first embodiment;

[0018] Figure 3 This is a circuit diagram illustrating each construction of the sub-block, sense amplifier group, and word line driver according to the first embodiment;

[0019] Figure 4A This is a diagram illustrating the operation of the memory chip according to the first embodiment;

[0020] Figure 4B This is a diagram illustrating the operation of the memory chip according to the first embodiment;

[0021] Figure 5A This is a diagram illustrating the short-circuit switch according to the second embodiment;

[0022] Figure 5B This is a diagram illustrating the short-circuit switch according to the second embodiment;

[0023] Figure 6A This is a diagram illustrating the operation of the sensing amplifier according to the third embodiment;

[0024] Figure 6B This is a diagram illustrating the operation of the sensing amplifier according to the third embodiment;

[0025] Figure 6C This is a diagram illustrating the operation of the sensing amplifier according to the third embodiment;

[0026] Figure 7A This is a diagram illustrating the semiconductor device according to the fourth embodiment;

[0027] Figure 7B This is a diagram illustrating the semiconductor device according to the fourth embodiment;

[0028] Figure 7C This is a diagram illustrating the semiconductor device according to the fourth embodiment;

[0029] Figure 8 This is a schematic cross-sectional view showing the construction of a semiconductor device according to the first embodiment;

[0030] Figure 9 This is a schematic cross-sectional view illustrating the construction of a stacked memory according to the first embodiment;

[0031] Figure 10A This is a diagram illustrating the stacked memory according to the first embodiment;

[0032] Figure 10B This is a diagram illustrating the stacked memory according to the first embodiment;

[0033] Figure 11 This is a circuit diagram illustrating the arrangement of the short-circuit switch according to the first embodiment; and

[0034] Figure 12 It is a view showing the process variations of semiconductor devices. Detailed Implementation

[0035] In the following description, various embodiments of the invention will be illustrated with reference to the accompanying drawings. Incidentally, the disclosure is merely exemplary, and matters that can be readily implemented by those skilled in the art with appropriate modifications while maintaining the spirit of the invention are naturally included within the scope of the invention.

[0036] Furthermore, in this specification and the corresponding drawings, elements that are the same as those already described in the figures above may be indicated by the same reference numerals, and their detailed descriptions may be omitted as appropriate.

[0037] (First Embodiment)

[0038] In the following description, embodiments will be illustrated using semiconductor devices suitable for learning and inference applications performed to realize AI (artificial intelligence). Of course, the invention is not limited to semiconductor devices for such applications.

[0039] <Semiconductor Device Structure>

[0040] Semiconductor devices used in learning and reasoning applications require the integration of neural networks (such as large-scale multiplication and computation circuits) and the processing of massive amounts of data in real time. Furthermore, memory is installed on such semiconductor devices. The installed memory is used to store and update large amounts of analytical data (e.g., image data) generated by real-time processing. Additionally, the installed memory is used for high-speed storage and updating of intermediate feature data and weight data generated by the neural network. For high-speed saving and updating, wide bandwidth and large capacity memory are required as the installed memory. Furthermore, to reduce heat generation, the installed memory is also required to have low power consumption.

[0041] Figure 8 This is a schematic cross-sectional view illustrating the construction of a semiconductor device according to a first embodiment. In the figure, reference numeral "1" denotes the semiconductor device according to the first embodiment. The semiconductor device 1 is composed of a plurality of semiconductor chips to have a construction suitable for applications such as learning. Figure 8 The image only shows the semiconductor chip needed for the explanation among multiple semiconductor chips. That is to say, in... Figure 8In the figure, reference numeral "200" indicates a semiconductor chip used for data processing, which is equipped with large-scale multiplication and computing circuits to process large amounts of data. Furthermore, reference numeral "100" indicates a stacked memory consisting of semiconductor chips (hereinafter also referred to as memory chips) used for multiple memories.

[0042] The data processing semiconductor chip 200 and the stacked memory 100 are connected to the substrate 300 via multiple bumps, and the substrate 300 is connected to the packaging substrate 400 via multiple bumps. The stacked memory 100, the semiconductor chip 200, and the substrate 300 are covered and sealed by a hermetically sealed package 500. Figure 8 As shown, some electrodes of the stacked memory 100 are connected to some electrodes of the data processing semiconductor chip 200 via wiring formed in the substrate 300. Furthermore, some electrodes of the stacked memory 100 and the data processing semiconductor chip 200 are connected to bumps disposed on the packaging substrate 400.

[0043] By connecting the electrodes of the data processing semiconductor chip 200 and the electrodes of the stacked memory 100, data (intermediate feature data, etc.) generated by the data processing semiconductor chip 200 is provided to the stacked memory 100 and stored and updated in the stacked memory 100.

[0044] <<Construction of Stacked Memory>>

[0045] The construction of the stacked memory 100 will be described next. Figure 9 This is a schematic cross-sectional view illustrating the construction of a stacked memory according to the first embodiment.

[0046] exist Figure 9 In the accompanying drawings, reference numerals "110_1" to "110_8" denote memory chips, and "120" denotes semiconductor chips used as substrates (hereinafter also referred to as substrate chips). Figure 9 As shown, memory chips 110_1 to 110_8 are stacked on and above substrate chip 120. The memory chips 110_1 to 110_8 and substrate chip 120 are connected via TSV (Through Silicon Via) technology. That is, a through-hole is formed in each of the stacked memory chips 110_1 to 110_8, and the different memory chips are electrically connected to each other through a conductive material, and further connected to substrate chip 120.

[0047] Bumps are formed on the substrate chip 120, and the stacked memory 100 is connected to the substrate 300 through the bumps. Incidentally, various circuits are also formed on the substrate chip 120.

[0048] Using a stacked memory 100 with this configuration allows multiple memory chips 110_1 to 110_8 to be connected to the data processing semiconductor chip 200. That is, the semiconductor chip 200 can use a wideband memory. In this case, due to the use of TSV technology, the power consumption required for data transfer between the semiconductor chip 200 and the memory chips can be suppressed. Therefore, the power consumed in the memory chips limits the power consumption of the stacked memory 100. In other words, reducing the power consumption in the memory chips becomes very effective in reducing the power consumption of the stacked memory 100.

[0049] Figure 10 is a diagram illustrating the stacked memory according to the first embodiment. Figure 10 shows the relationship between the stacked memory 100 and the memory chips. Figure 10A In, similar to Figure 9 The structure of the stacked memory 100 is schematically shown in perspective. While not particularly limited, the memory chips 110_1 to 110_8 constituting the stacked memory 100 have similar structures to each other. Therefore, memory chip 110_4 will be used as an example for explanation here. Figure 10B In the diagram, the structure of memory chip 110_4 is schematically shown using a plan view.

[0050] exist Figure 10B In the accompanying drawings, reference numeral "111" denotes a memory cell consisting of multiple memory banks. Although not particularly limited, the memory cell 111 in the first embodiment consists of eight memory banks BK0 to BK7 (BK8 to BK15), and the eight memory cells are arranged on a memory chip 110_4. In the memory chip 110_4, the TSV region TSV_R, connected via TSV interconnect technology, and the control region FCT, equipped with fuses, are arranged in the central portion (center row) sandwiched between the four memory cells 111. Memory banks BK0 to BK15 will be referred to later. Figure 1 The description is provided, and multiple memory blocks, including multiple memory cells, sense amplifiers, etc., are arranged.

[0051] <<Storage Structure>>

[0052] Figure 1 This is a view showing the structure of the memory bank according to the first embodiment. Since memory banks BK0 to BK15 have the same structure as each other, memory banks BK0 to BK15 will be collectively referred to as memory bank BK in the following description.

[0053] The memory bank BK is not particularly limited, but includes multiple memory blocks MAT arranged in a matrix and power supply wiring arranged in a grid outside the multiple memory blocks MAT to provide power supply voltage to the memory blocks MAT. In the first embodiment, although there are no particular limitations, three types of power supply wiring are arranged in a grid shape. That is, a first power supply wiring (hereinafter referred to as ground power wiring) providing ground voltage Vss to the memory blocks MAT, a second power supply wiring providing a first power supply voltage Vdd to the memory blocks MAT, and a third power supply wiring providing a second power supply voltage Vod to the memory blocks MAT are arranged in a grid shape outside the multiple memory blocks MAT. Figure 1 In this document, the grounding power supply wiring in these three types of power supply wiring is omitted; the second power supply wiring is indicated by the reference numeral "L_dd", and the third power supply wiring is indicated by the reference numeral "L_od". Furthermore, in... Figure 1 The image shows two memory blocks MAT arranged in a matrix.

[0054] In the memory bank BK according to the first embodiment, a plurality of short-circuit switches SHT (third switches) are arranged outside the memory block MAT. Figure 1 In this circuit, the short-circuit switch SHT is composed of an N-channel (hereinafter also referred to as N-type) MOSFET N1, and the source / drain path of the N-type MOSFET N1 is connected in series between the second power supply line L_dd and the third power supply line L_od. Furthermore, as... Figure 1 As shown, when viewed in a plan view, the short-circuit switches SHT are arranged distributed outside the memory block MAT. A short-circuit control signal Sh is provided to the gate of the N-type MOSFET N1. When the short-circuit control signal Sh goes high, the N-type MOSFET N1 (i.e., the short-circuit switches SHT) becomes on, and the second power supply line L_dd and the third power supply line L_od are electrically short-circuited. Connecting the second power supply line L_dd and the third power supply line L_od using distributed short-circuit switches SHT reduces the connection resistance generated during connection.

[0055] Please refer to later Figure 2 and 3 The memory block MAT is described, and a detailed description thereof will be omitted. However, the memory block MAT includes: multiple memory cells arranged in a matrix; multiple sense amplifiers; word line drivers; and three types of power supply wiring arranged in a grid pattern. The third type of power supply wiring arranged in the memory block MAT is a fourth power supply wiring that provides a ground voltage Vss to the sense amplifiers, etc. Figure 3 The fifth power supply wiring (Li_ss) provides the first power supply voltage Vdd to the sensing amplifier, etc. Figure 3In this context, Li_dd (also known as the first power supply wiring) and the sixth power supply wiring that provides the second power supply voltage Vod to the sensing amplifier, etc. Figure 3 In this context, the fourth power supply line (Li_ss) is connected to the aforementioned ground power supply line, the fifth power supply line (Li_dd: the first power supply line) is connected to the aforementioned second power supply line L_dd, and the sixth power supply line (Li_od) is connected to the aforementioned third power supply line L_od.

[0056] exist Figure 1 In the figure, the reference numeral "Cd" indicates the parasitic capacitance connected to the second power supply line L_dd, and "Co" indicates the parasitic capacitance connected to the third power supply line L_od. Furthermore, the reference numeral "P_Vd" indicates the power electrode (pad) connected to the second power supply line L_dd. For example, a first power supply voltage Vdd is supplied to this pad P_Vd from outside the memory chip 110. Therefore, the first power supply voltage Vdd is supplied to each memory block MAT.

[0057] In addition, Figure 1 In the accompanying drawings, the reference numeral "P_Ve" indicates a power pad supplied with a predetermined external voltage, for example, from outside the memory chip 110. The voltage value of the external voltage supplied to the pad P_Ve is a voltage whose absolute value is higher than the absolute value of the first power supply voltage Vdd. This external voltage is supplied to a buck power supply circuit (voltage conversion circuit) 112. The operation of the buck power supply circuit 112 is controlled by an operation control signal Vcnt. When the operation control signal Vcnt indicates buck operation, the external voltage is stepped down and the aforementioned second power supply voltage Vod is generated. That is, the buck power supply circuit 112 converts the external voltage into the second power supply voltage Vod. The voltage value of the second power supply voltage Vod is a voltage whose absolute value is higher than the absolute value of the first power supply voltage Vdd. Conversely, when the operation control signal Vcnt indicates to stop buck operation, the buck power supply circuit 112 stops buck operation and places its output in a floating state.

[0058] Figure 1 An example is shown in which the buck power supply circuit 112 consists of a conversion circuit that performs a buck operation, but the invention is not limited thereto. For example, the buck power supply circuit 112 may be a voltage conversion circuit that performs a step-up operation. When using a voltage conversion circuit that performs a step-up operation, for example, a first power supply voltage Vdd is supplied to the voltage conversion circuit, and a second power supply voltage Vod having a voltage value higher than the first power supply voltage Vdd is generated and the generated second power supply voltage Vod is supplied to a third power supply wiring L_od.

[0059] also, Figure 1An example of a buck power supply circuit 112 arranged in a memory bank BK is shown, but the invention is not limited thereto. For example, a buck power supply circuit 112 may be shared among multiple memory banks BK, or it may be shared among multiple memory chips 110.

[0060] Figure 2 This is a schematic plan view illustrating the construction of a memory block according to the first embodiment. The memory block MAT includes: a plurality of sub-blocks Sub_MAT arranged in a matrix; a plurality of sense amplifier groups SA; and a plurality of word line drivers (hereinafter also referred to as WL drivers) SWD. Here, the sense amplifier groups SA are arranged along the rows of the corresponding sub-blocks Sub_MAT. In addition, the WL drivers SWD are arranged along the columns of the corresponding sub-blocks Sub_MAT.

[0061] The sub-block Sub_MAT includes: a plurality of memory cells arranged in a matrix; word lines WL arranged along each row of the matrix; and bit lines BL arranged along each column of the matrix. Each word line corresponds to a plurality of memory cells on a row on which word lines are arranged, and is connected to a plurality of associated memory cells thereon. Furthermore, each bit line also corresponds to a plurality of memory cells on a column on which bit lines are arranged, and is connected to a plurality of associated memory cells thereon.

[0062] The WL driver SWD is provided with a word line selection signal WL_s from a decoder (not shown), and this signal is provided to the word lines in the corresponding sub-block Sub_MAT. Therefore, the memory cell selected from a plurality of memory cells arranged in the sub-block Sub_MAT is determined based on the address signal provided to the decoder. Data read from the selected memory cell and then amplified via the bit lines by the sense amplifiers in the corresponding sense amplifier group SA, is output as read data Data.

[0063] Next, the sub-block Sub_MAT, the corresponding sense amplifier group SA, and the corresponding WL driver SWD will be described in detail with reference to the accompanying drawings. Figure 3 This is a circuit diagram illustrating the construction of the sub-block, sense amplifier group, and word line driver according to the first embodiment.

[0064] exist Figure 3 In the attached diagram, the reference numeral "MC" indicates a memory cell arranged in a matrix on the sub-block Sub_MAT. Furthermore, "WL_0" to "WL_255" and "BL_0" to "BL_255" represent word lines and bit lines arranged within the sub-block Sub_MAT. Additionally, in... Figure 3 In the diagram, "X_DEC" represents the decoder, "CNT" represents the control circuit, and "SAC" represents the sense amplifier drive control circuit.

[0065] The memory cell MC includes a select MOSFET Nm and a storage capacity Cm. The storage capacity Cm is connected in series between the corresponding bit line (e.g., BL_0) and the ground voltage Vss via the select MOSFET Nm. Furthermore, the gate of the select MOSFET Nm is connected to the corresponding word line (e.g., WL_255). Incidentally, the ground voltage Vss of the memory cell MC is provided via the aforementioned fourth power supply wiring Li_ss.

[0066] The WL driver SWD is equipped with a cell driver DRV connected to each word line. The decoder X_DEC decodes the address signal Add and sets the word line selection signal WL_s corresponding to the word line specified by the address signal Add (e.g., WL_255) high, while setting the remaining word lines low. Therefore, word line WL_255 is selected, the memory cell MC connected to the selected word line WL_255 is selected, and the selection MOSFET Nm in the selected memory cell is turned on. As a result, the corresponding potentials of bit lines BL_0 to BL_255 change according to the data (charge) stored in the storage capacity Cm of the selected memory cell MC. The corresponding potentials of bit lines BL_0 to BL_255 are amplified by the sense amplifier USA in the sense amplifier group SA described below, and output from the sense amplifier group SA as read data Data (Data_0 to Data_255).

[0067] The sense amplifier group SA includes multiple sense amplifiers USA corresponding to bit lines BL_0 to BL_255. Here, the structure of the sense amplifier USA corresponding to bit line BL_0 will be described as an example. The sense amplifier USA includes P-channel type (hereinafter also referred to as P-type) MOSFETs P1 and P2, and N-type MOSFETs N2 and N3, and is connected between the sense amplifier power supply line L_sp and the sense amplifier ground power supply line L_sn. The source / drain paths of the P-type MOSFET P1 and the N-type MOSFET N2 are connected in series between the sense amplifier power supply line L_sp and the sense amplifier ground power supply line L_sn, and the gates of the P-type MOSFET P1 and the N-type MOSFET N2 are interconnected. Therefore, the first inverting circuit IV1 is composed of the P-type MOSFET P1 and the N-type MOSFET N2. Similar to the P-type MOSFET P1 and N-type MOSFET N2, the P-type MOSFET P2 and N-type MOSFET N3 are also connected in series between the sense amplifier power supply line L_sp and the sense amplifier ground power supply line L_sn, and their gates are also shared. Therefore, the second inverting circuit IV2 is composed of a P-type MOSFET P2 and an N-type MOSFET N3.

[0068] The input of the first inverter IV1 is connected to the output node n2 of the second inverter IV2, and the input of the second inverter IV2 is connected to the output node n1 of the first inverter IV1. That is, the first inverter IV1 and the second inverter IV2 are cross-connected. The corresponding bit line BL_0 is connected to the output node n1 of the first inverter IV1, and the read data Data_0 is output from the output node of the second inverter IV2. Because they are cross-connected, output nodes n1 and n2 can be considered as input / output nodes.

[0069] The sense amplifier drive control circuit SAC includes a switching P-type MOSFET P3 (first switch) and switching N-type MOSFETs N4 and N5 (second switches), and is connected to a fourth power supply line Li_ss, a fifth power supply line (first power supply line) Li_dd, a sixth power supply line Li_od, a sense amplifier power supply line L_sp, and a sense amplifier ground power supply line L_sn. These lines are arranged in a memory block MAT. For example, the size of the N-type MOSFET N5 is larger than that of the N-type MOSFET N2, resulting in a higher drive capability than the N-type MOSFET N2. Incidentally, in this specification, the gates of the larger MOSFETs are clearly shown by thick lines.

[0070] like Figure 3As shown, the source / drain path of the P-type MOSFET P3 is connected between the fifth power supply line Li_dd and the sense amplifier power supply line L_sp, and the source / drain path of the N-type MOSFET N5 is connected between the sixth power supply line Li_od and the sense amplifier power supply line L_sp. Furthermore, the source / drain path of the N-type MOSFET N4 is connected between the fourth power supply line Li_ss and the sense amplifier ground power supply line L_sn.

[0071] The sense amplifier control signals SAd1, SAs, and SAd2 output from the control circuit CNT are provided to the gates of P-type MOSFET P3 and N-type MOSFETs N4 and N5. That is, the on / off state of each switching P-type MOSFET P3 and switching N-type MOSFETs N4 and N5 is controlled by the sense amplifier control signals from the control circuit CNT. When the switching MOSFETs are turned on by the sense amplifier control signals, the ground voltage Vss is provided to the sense amplifier ground power supply wiring L_sn, and the first power supply voltage Vdd or the second power supply voltage Vod is provided to the sense amplifier power supply wiring L_sp. Therefore, the cross-connected first inverting circuit IV1 and second inverting circuit IV2 operate and perform positive feedback operation, which amplifies the potential of the bit line BL.

[0072] The control circuit CNT outputs a short-circuit control signal Sh and an operation control signal Vcnt. These control signals control the N-type MOSFET N1, which constitutes... Figure 1 The short-circuit switch SHT is shown. Incidentally, in... Figure 3 In this diagram, the control circuit CNT is depicted as being located within the memory block MAT, but the invention is not limited thereto. For example, the control circuit CNT may be located outside the memory block MAT.

[0073] <Operation of Semiconductor Devices>

[0074] Next, the operation of the memory chip 110 will be described with reference to the accompanying drawings. FIG4 is a diagram illustrating the operation of the memory chip according to the first embodiment. Here, Figure 4A The SAC (Sense Amplifier Drive Control Circuit) is shown. Figure 3 The circuit diagram of the relevant part. Figure 4B The waveform diagram of the read operation of memory cell MC is shown.

[0075] like Figure 2 and Figure 3As shown, the memory block MAT includes multiple sub-blocks Sub_MAT, multiple sense amplifier groups SA, etc. However, for ease of explanation, Figure 4 only shows one sense amplifier USA, sense amplifier power supply wiring L_sp, power supply wiring L_od, L_dd, Li_od, and Li_dd, and a short-circuit switch SHT. As mentioned above, the fifth power supply wiring Li_dd and the sixth power supply wiring Li_od are power supply wirings arranged within the memory block MAT, and the second power supply wiring L_dd and the third power supply wiring L_od are power supply wirings arranged outside the memory block MAT. Since the sense amplifier group SA is arranged within the memory block MAT, the sense amplifier power supply wiring L_sp is naturally a power supply wiring arranged within the memory block MAT.

[0076] like Figure 4A As shown, the sixth power supply line Li_od and the fifth power supply line Li_dd, which are arranged in the memory block MAT, are electrically connected to the corresponding third power supply line L_od and the corresponding second power supply line L_dd, which are arranged outside the memory block MAT.

[0077] In the first embodiment, when the speed of components (MOSFETs, etc.) decreases due to process variations (hereinafter also referred to as the low-speed state), and in situations below low speed (standard and fast) (hereinafter also referred to as the normal state), the state of the short-circuit switch SHT and the buck power supply circuit 112 ( Figure 1 The operation of the short-circuit switch SHT and the operation of the buck power supply circuit 112 are selectively changed according to the magnitude of the operating margin of the sensing amplifier USA. For example, using the operating margin when the operation of the sensing amplifier USA becomes unstable as a reference, when the operating margin is less than the reference, it corresponds to a low-speed state, and when the operating margin is greater than the reference, it corresponds to a normal state.

[0078] At low speeds, i.e., when the operating margin is small, the control circuit CNT ( Figure 3 The control circuit CNT instructs the buck power supply circuit 112 to perform a voltage reduction operation by using the operation control signal Vcnt. In this case, the control circuit CNT uses the short-circuit control signal Sh to keep the short-circuit switch SHT in the off state. Conversely, in the normal state, i.e., when the operating margin is large (when the operating margin is not small), the control circuit CNT instructs the buck power supply circuit 112 to stop the voltage reduction operation by using the operation control signal Vcnt. In this case, the control circuit CNT uses the short-circuit control signal Sh to keep the short-circuit switch SHT in the on state.

[0079] Next, we will describe the read operations in normal and low-speed states.

[0080] <<Common Read Operations>>

[0081] Here, the connection from Figure 3 The example shown is a typical case of data being read from the memory cell MC at the intersection of word line WL_0 and bit line BL_0.

[0082] During reading, bit line BL_0 is pre-charged to an intermediate potential (1 / 2Vdd) between the ground voltage Vss and the first supply voltage Vdd. After bit line BL_0 is pre-charged, word line WL_0 goes high and is selected. Therefore, the selection MOSFET Nm in the memory cell MC (the memory cell MC at the intersection) connected to word line WL_0 and bit line BL_0 turns on, and the potential of bit line BL_0 changes from 1 / 2Vdd according to the charge accumulated in the storage capacity Cm. That is, as... Figure 4B As shown, the potential of bit line BL_0 changes from 1 / 2Vdd before time t1.

[0083] <<Low Speed ​​State>>

[0084] At low speeds, the control circuit CNT turns off the short-circuit switch SHT and causes the buck power supply circuit 112 to perform a step-down operation. Due to this step-down operation, the buck power supply circuit 112 outputs a second power supply voltage Vod to the third power supply wiring L_od, the value of which is higher than the value of the first power supply voltage Vdd. This can lead to overload.

[0085] In addition, such as Figure 4B As shown, the control circuit CNT keeps the sense amplifier control signal SAd1 high during the initial time period TP1 from time t1 to time t2, and keeps the sense amplifier control signal SAd2 low during the time period TP2 from time t2 to time t3. Incidentally, although in Figure 4B It is not shown in the figure, but the control circuit CNT keeps the sense amplifier control signal SAs at a high level during the combined period of the initial period TP1 and period TP2 (period TP3).

[0086] Therefore, in the initial time period TP1, Figure 3 The N-type MOSFETs N4 and N5 shown are in the ON state, and Figure 3 The P-type MOSFET P3 shown is in the off state. Furthermore, during time period TP2, the N-type MOSFET N4 and the P-type MOSFET P3 are in the on state, while the N-type MOSFET N5 is in the off state.

[0087] As a result, in the initial period TP1, the sense amplifier USA is connected to the sixth power supply line Li_od and the third power supply line L_od via the sense amplifier power supply line L_sp and the N-type MOSFET N5. Conversely, in the period TP2, the sense amplifier USA is connected to the fifth power supply line Li_dd and the second power supply line L_dd via the sense amplifier power supply line L_sp and the P-type MOSFET N3. Therefore, the potential of the bit line BL_0 is amplified by the sense amplifier USA and output as data Data_0. Incidentally, although in Figure 4B Not shown, but during time period T3 (T1+T2), the sense amplifier USA is connected to the ground power supply line outside the fourth power supply line Li_ss and the memory block via the sense amplifier ground power supply line L_sn and the N-type MOSFET N4, and the ground voltage Vss is provided to the sense amplifier USA.

[0088] During the initial period TP1, the large drive current Id( Figure 4A The large-size N-type MOSFET N5 is supplied to the sense amplifier USA, and in the period TP2 after the initial period TP1, overdrive is achieved by providing a relatively small drive current through the small-size P-type MOSFET P3.

[0089] <<<Normal State>>>

[0090] Under normal conditions, the control circuit CNT keeps the short-circuit switch SHT in the ON state and stops the buck power supply circuit 112. Since the buck power supply circuit 112 is stopped, no overdrive is performed. Although there are no particular restrictions, the control circuit CNT keeps the short-circuit switch SH in the ON state through the short-circuit control signal Sh during the periods when the N-type MOSFET N5 and the P-type MOSFET P3 are in the ON state (initial period TP1 and period TP2).

[0091] Because the short-circuit switch SHT is in the ON state, the third power supply wiring L_od and the second power supply wiring L_dd are connected outside the memory block MAT. That is, the corresponding parasitic capacitances Co and Cd are combined. In the initial period TP1, the drive current Id( Figure 4A The first power supply voltage Vdd supplied to the sense amplifier USA is provided via the third power supply line L_od and the second power supply line L_dd through the large-size N-type MOSFET N5. At this time, since the parasitic capacitance added to the power supply line is a composite capacitance of parasitic capacitances Co and Cd, the fluctuation of the first power supply voltage Vdd supplied to the sense amplifier USA is suppressed even if a large drive current Id flows in the sense amplifier USA, so that the sense amplifier USA can operate stably.

[0092] During the initial period TP1 followed by period TP2, the P-type MOSFET P3 turns on, and the drive current is supplied to the sense amplifier USA via the P-type MOSFET P3. The potential of the bit line is amplified by the sense amplifier USA and output as data Data_0. Since the short-circuit switch SHT is also on during period TP2, even if a large drive current Id flows through the P-type MOSFET P3 during this period, the operation of the sense amplifier USA can be prevented from becoming unstable.

[0093] Since the buck power supply circuit 112 is stopped under normal conditions, power consumption can be reduced. Incidentally, because the buck power supply circuit 112 is stopped and the short-circuit switch SHT is on, the second power supply voltage Vod becomes essentially equal to the first power supply voltage Vdd, such as... Figure 4B As shown.

[0094] An example of keeping the short-circuit switch SHT in the ON state during the initial time period TP1 and time period TP2 has been described, but the invention is not limited thereto. For example, during time period TP2, the short-circuit switch SHT can be kept in the OFF state. Even in this case, the operation of the sense amplifier USA can be prevented from becoming unstable due to a large drive current Id during the initial time period TP1.

[0095] It is conceivable that the short-circuit switch SHT is placed inside the memory block MAT, rather than outside it. However, placing the short-circuit switch SHT outside the memory block MAT would be appropriate. Figure 11 This is a circuit diagram illustrating the arrangement of the short-circuit switch according to the first embodiment. Figure 11 Similar to Figure 4A The difference between them is that, Figure 11 In this configuration, the short-circuit switch SHT is located within the memory block MAT. Figure 11 In this arrangement, the sixth power supply line Li_od and the fifth power supply line Li_dd are connected in the memory block MAT. Therefore, under normal conditions, the parasitic capacitance Co of the third power supply line L_od is not used to suppress fluctuations in the first power supply voltage Vdd. This is therefore unsuitable for stabilizing the operation of the sense amplifier USA under normal conditions. Furthermore, when the linewidth of the fifth power supply line Li_dd is narrower than that of the second power supply line L_dd and the unit resistance of the fifth power supply line Li_dd is higher than that of the second power supply line L_dd, the amount of drive current Id consumed by the resistance of the fifth power supply line Li_dd increases, leading to increased power consumption.

[0096] For example, when measuring the characteristics of stacked memory 100 or memory chip 110, it is determined whether the speed of the component has decreased due to process variations. Based on the results of (multiple) measurements, for example, Figure 10B The fuses in the control area FCT shown are melted and disconnected. That is, the low-speed state or the normal state is indicated by the state of the fuse. Figure 3 The control circuit CNT shown generates sense amplifier control signals SAd1, SAd2, short-circuit control signal Sh, and operation control signal Vcnt based on the state of the fuse. The placement of the control circuit CNT is not particularly limited; for example, the control circuit CNT can be placed in the same control area FCT as the fuse.

[0097] (Second Embodiment)

[0098] Figure 5 is a diagram illustrating the short-circuit switch according to the second embodiment. Here, Figure 5A This illustrates the case where the short-circuit switch SHT is constructed using an N-type MOSFET. Figure 5A The example shows a short-circuit switch (SHT) constructed from an N-type MOSFET. Figure 5B The example shows a short-circuit switch (SHT) constructed from a P-type MOSFET.

[0099] One electrode (source electrode) of the N-type MOSFET N1 is connected to the second power supply line L_dd, and its other electrode (drain electrode) is connected to the third power supply line L_od. Additionally, ground voltage Vss is provided to the back gate electrode. When the short-circuit switch SHT is on, the high-level voltage (WL voltage) provided to the word line WL during word line selection is provided as the short-circuit control signal Sh.

[0100] The first power supply voltage Vdd is, for example, approximately 1.0 (V), and the second power supply voltage Vod is, for example, approximately 1.2 (V). When selecting the memory cell MC, a relatively high voltage value (e.g., a WL voltage of approximately 3.0 (V)) is provided as the word line select signal WL_s to reduce the voltage drop caused by the threshold voltage of the selected MOSFET Nm. Figure 5A In the configuration shown, when the N-type MOSFET N1 is in the ON state, a relatively high voltage value is provided to the gate, which reduces the voltage drop caused by the threshold voltage of the N-type MOSFET N1 and reduces the potential difference between the second power supply line L_dd and the third power supply line L_od.

[0101] When the short-circuit switch SHT is in the off state, the short-circuit control signal Sh of the ground voltage Vss is provided to the gate of the N-type MOSFET N1.

[0102] exist Figure 5BIn this circuit, the short-circuit switch SHT is composed of a P-type MOSFET Psw. The aforementioned WL voltage is supplied to the back gate electrode of the P-type MOSFET Psw. When the short-circuit switch SHT is in the ON state, a voltage value lower than the first power supply voltage Vdd (e.g., ground voltage Vss) is supplied to the gate of the P-type MOSFET Psw as a short-circuit control signal Sh. Conversely, when the short-circuit switch SHT is in the OFF state, the second power supply voltage Vod is supplied to the gate of the P-type MOSFET Psw as a short-circuit control signal Sh.

[0103] Similarly, in the second embodiment, each short-circuit switch can be constructed from a single MOSFET, which allows for suppression of increased footprint. Furthermore, since the WL voltage supplied to the selected word line can be diverted, a dedicated power supply for the short-circuit switches is not required.

[0104] (Third Embodiment)

[0105] Figure 6 is a diagram illustrating the operation of the sensing amplifier according to the third embodiment. Here, Figure 6A The construction of the memory block MAT is shown. For example, Figure 6A Similar to Figure 4A The main difference between them is that... Figure 4A The grounding power supply wiring L_sn and N-type MOSFET N4, which have been omitted in the code, are in... Figure 6A As clearly shown, the N-type MOSFET N4 provides the ground voltage Vss to the sense amplifier USA.

[0106] In the third embodiment, the N-type MOSFET N5, connected between the sense amplifier power supply line L_sp and the sixth power supply line Li_od, and the P-type MOSFET P3, connected between the sense amplifier power supply line L_sp and the fifth power supply line Li_dd, are time-controlled to become on by overlapping with at least a portion of them. Therefore, when the potential of the bit line is amplified by the sense amplifier USA, the drive current that can be supplied to the sense amplifier USA can be increased, and the operating margin of the sense amplifier USA can be further increased.

[0107] Specifically, in Figure 6B In this circuit, the control circuit CNT outputs sense amplifier control signals SAd1 and SAd2 such that the high-level period (TP1) of sense amplifier control signal SAd2 partially overlaps with the low-level period (TP2) of sense amplifier control signal SAd1. Therefore, the initial period TP1 becomes the overlapping period Tov, and the current driving capability of this period can be enhanced.

[0108] In addition, Figure 6CIn this circuit, the control circuit CNT outputs sense amplifier control signals SAd1 and SAd2 such that the high-level period (TP1) of sense amplifier control signal SAd2 coincides with the low-level period (TP2) of sense amplifier control signal SAd1. Therefore, the current driving capability of the overlapping period Tov can be enhanced.

[0109] (Fourth Embodiment)

[0110] In the fourth embodiment, the region used to control whether overdriving is performed is subdivided. Overdriving can increase the operating margin of the sense amplifier USA, but this leads to increased power consumption. Therefore, by reducing the region used for overdriving, the increase in power consumption can be further suppressed.

[0111] Figure 7 is a diagram illustrating the semiconductor device according to the fourth embodiment. Here, Figure 7A The structure of the stacked memory 100 is shown. Figure 7B The structure of memory chip 110 is shown. Figure 7C The construction of memory BK is shown.

[0112] Figure 7A Similar to Figure 10A The difference between the two is that whether a driver has been executed is determined on a per-chip basis. That is, Figure 3 The control circuit shown, CNT, controls memory chips on a per-chip basis. Figure 7A In the process, the control circuit CNT controls the memory chip 110_4 to enable overdrive, and controls the remaining memory chips to be in a normal state so as not to enable overdrive. Figure 7A The design allows overdriving only memory chips with reduced operating margins caused by process variations in the manufacture of the memory chips, which helps to suppress increases in power consumption per memory chip.

[0113] Figure 7B Similar to Figure 10B The difference between the two is that whether a driver has been executed is determined on a per-memory basis. That is, Figure 3 The control circuit CNT shown controls memory cells on a per-cell basis. Figure 7B In the memory chip 110_4, the control circuit CNT controls two of the sixty-four (64) memory banks to perform overdrive, and controls the remaining memory banks to be in a normal state so as not to perform overdrive. Figure 7B The design allows for overdriving only memory banks with reduced operating margins, caused by variations in the power supply voltage in memory chip 110_4, which helps suppress increases in power consumption per memory bank.

[0114] Figure 7C This is a schematic plan view illustrating the structure of memory module BK12. In the figure, the reference numeral "PH" indicates the peripheral circuitry. Figure 7C In this memory module, BK12 comprises eight memory blocks MAT. The control circuit CNT controls the memory blocks individually. Figure 7C In this circuit, the control circuit CNT controls one of the eight memory blocks MAT to enable overdrive, and controls the remaining memory blocks to remain in the normal state to prevent overdrive. Figure 7C The configuration, for example, allows overdriving only memory banks with reduced operating margins caused by element variations, which enables suppression of power consumption increases per memory block.

[0115] The control circuit CNT according to the fourth embodiment is not particularly limited, but is provided on a per-target basis. For example, in Figure 7A In this case, the control circuit CNT is provided in units of one hundred memory chips; Figure 7B In this case, it is provided in units of storage BK; Figure 7C In this case, it is provided in units of memory blocks (MAT). Of course, the invention is not limited to this, and a common control circuit (CNT) can also be provided.

[0116] Typical embodiments have been described with reference to the accompanying drawings, but the following may be used as other embodiments.

[0117] A. Control circuit CNT ( Figure 3 This system dynamically switches between the presence and absence of overdrive by detecting temperature, voltage drop, and operating status (parallel / continuous operation, operating frequency, high-speed / low-speed mode switching, etc.). In this case, power consumption can be suppressed not only in the memory chip but also throughout the entire system (due to increased temperature, etc.).

[0118] B. It can not only switch between the presence or absence of a drive, but also perform other controls.

[0119] B1. For example, a power reduction control method is added to further reduce power consumption. In this case, under the power reduction control mode, the OD N-type MOSFET N5 ( Figure 3 It is in the off state via the OD control signal (sensor amplifier control signal SAd2). This power reduction control mode is set to be executed during low-speed operations such as refresh operations.

[0120] B2. In overdrive, a control mode is added whereby the overdrive second supply voltage Vod is applied not only during the initial period used to operate the sensing amplifier USA (TP1: Figure 4B Furthermore, it is always applied during the period (TP3) used to activate the sense amplifier USA. This allows for an increase in the operating margin of the sense amplifier USA even outside the initial period, thereby improving the write voltage to the memory cell and the read margin from the memory cell. In this case, yield can be further improved by using it in conjunction with the redundancy relief function.

[0121] B3. Alternatively, the operating mode can be switched by changing the first power supply voltage Vdd. When the first power supply voltage Vdd is shared as the power supply voltage of another circuit, the operating mode can adapt to the change in the shared first power supply voltage Vdd.

[0122] C. In the first embodiment, the second power supply voltage Vod is generated by forming an external power supply voltage from the outside through a buck circuit. However, the second power supply voltage Vod can also be generated by boosting the external power supply voltage through a boost circuit. Furthermore, both the first power supply voltage Vdd and the second power supply voltage Vod can be generated by boosting or bucking the external power supply voltage. Further, the second power supply voltage Vod can be generated using an external power supply voltage, and the first power supply voltage Vdd can be generated by bucking the external power supply voltage.

[0123] D. Stacked memory can be used as a common memory chip for various products with different power supply voltages for the base chip 120 (Figure 10).

[0124] According to this embodiment, power consumption can be reduced while the sense amplifier operates at low voltage and maintains high speed. That is, the sense amplifier can operate stably even when no overdrive is performed, and the yield reduction can be suppressed even if process and device changes occur.

[0125] Furthermore, in the semiconductor device according to the embodiment, overdrive is performed in a low-speed state. In the low-speed state, currents such as the leakage current flowing through the MOSFET are reduced. Therefore, even if overdrive is performed in a low-speed state, the increase in power consumption of the entire semiconductor device can be suppressed.

[0126] Furthermore, this embodiment can achieve this by changing the control circuit CNT and adding a short-circuit switch, thus suppressing the increase in occupied area.

[0127] As described above, although the invention made by the inventors has been specifically described based on embodiments, the invention is not limited to the above embodiments, and needless to say, various modifications can be made without departing from its spirit. For example, in the embodiments, a dynamically typed memory has been described, but the invention is not limited thereto, and may also be a statically typed memory, etc.

Claims

1. A semiconductor device, comprising: Memory blocks, including: Multiple memory units; A sensing amplifier is connected to at least one memory cell selected from the plurality of memory cells; A first switch is connected to the sensing amplifier via a ground power supply wiring and is in the ON state when the sensing amplifier is operating; and The second switch is connected to the sensing amplifier via the sensing amplifier power supply wiring and is in the ON state when the sensing amplifier is operating; A first power supply wiring is arranged outside the memory block to provide ground voltage to the memory block; A second power supply wiring is arranged outside the memory block for supplying the first power supply voltage to the memory block; A third power supply wiring, disposed outside the memory block, is used to supply a second power supply voltage to the memory block, the second power supply voltage being higher than the first power supply voltage; and A third switch is located outside the memory block and connected between the second power supply wiring and the third power supply wiring. When the sensing amplifier is operating, the third switch is in the ON state. The memory block further includes: The fourth switch is connected to the sensing amplifier via the sensing amplifier power supply wiring and is in the ON state when the sensing amplifier is operating; The fourth power supply cable is connected to the first switch; The fifth power supply wiring is connected to the fourth switch; and The sixth power supply cable connects to the second switch. The first power supply cable is connected to the fourth power supply cable. The second power supply cable is connected to the fifth power supply cable. The third power supply wiring is connected to the sixth power supply wiring, and When the operating margin of the sensing amplifier is small, the third switch is in the off state, and when the operating margin is not small, the third switch is in the on state.

2. The semiconductor device according to claim 1, The voltage conversion circuit is connected to the third power supply wiring, and when the operating margin is small, the voltage conversion circuit converts a predetermined voltage into a second power supply voltage, and the voltage conversion circuit provides the second power supply voltage to the third power supply wiring.

3. The semiconductor device according to claim 2, When the third switch is in the ON state, the operation of the voltage conversion circuit stops.

4. The semiconductor device according to claim 3, The first switch, the second switch, the third switch, and the fourth switch are each composed of a MOSFET.

5. The semiconductor device according to claim 1, During the initial period before the first switch becomes the ON state, the second switch becomes the ON state.

6. The semiconductor device according to claim 1, The period during which the fourth switch becomes the ON state partially overlaps with the period during which the second switch becomes the ON state.

7. The semiconductor device according to claim 1 further comprises a plurality of memory chips, each memory chip having a plurality of memory blocks composed of the memory blocks. In at least one predetermined memory chip among the plurality of memory chips, the third switch is in the ON state.

8. The semiconductor device of claim 1 further comprises a plurality of memory cells, each memory cell having a plurality of memory blocks composed of the memory blocks. In at least one predetermined storage cell among the plurality of storage cells, the third switch is in the ON state.

9. The semiconductor device according to claim 1, further comprising a plurality of memory blocks composed of the memory blocks, In at least one predetermined memory block among the plurality of memory blocks, the third switch is in the ON state.

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