Pseudo dual-port memory and its bit line control method and device

Abstract

A pseudo dual-port memory and its bit line control method and device, the method comprising: when performing a read operation and a write operation after the read operation within an access cycle, acquiring information of corresponding read data and write data; when determining that the read data and the write data are the same, generating a corresponding first control signal, so that the bit line precharging unit, at the end of the read operation, based on the first control signal, pulls down a corresponding bit line in a bit line pair of a corresponding column of the storage array from a first logical low level to a second logical low level; the first logical low level is a voltage signal on the corresponding bit line at the end of the read operation, and the second logical low level is a voltage signal applied to the corresponding bit line during the write operation. The above solution can save the energy consumption of the pseudo dual-port memory and improve the working speed, thereby enhancing the performance of the pseudo dual-port memory.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and particularly to a pseudo dual-port memory and a bit line control method and device thereof. Background Art

[0002] A dual-port memory processes both a read operation and a write operation within a single clock cycle. A dual-port memory typically includes two ports that operate with a memory cell array, and the memory cell array can be accessed simultaneously from the two ports.

[0003] In order to reduce the area occupied by the memory, a pseudo dual-port memory can be used instead of a dual-port memory. The core of a pseudo dual-port memory is a single-core memory array, which provides a single memory access, rather than two simultaneous memory accesses as in a dual-port memory. However, a pseudo dual-port memory is configured to simulate a dual-port memory by sequentially performing two memory accesses within an access cycle. For example, in a specific access cycle, a pseudo dual-port memory can perform a read operation and then perform a write operation after the read operation.

[0004] However, the performance of existing pseudo dual-port memories still needs to be improved. Summary of the Invention

[0005] The problem solved by the present invention is to provide a pseudo dual-port memory and a bit line control method and device thereof to improve the performance of the pseudo dual-port memory.

[0006] To solve the above problem, the present invention provides a bit line control method for a pseudo dual-port memory. The pseudo dual-port memory includes a memory array and a bit line precharging unit; the memory array includes memory cells arranged in multiple rows and multiple columns; the memory cells in the same row are coupled to the same word line, and the memory cells in the same column are coupled to the same pair of bit lines; the bit line precharging unit is coupled to the pairs of bit lines of the memory array; the pair of bit lines includes a complementary first bit line and a second bit line; the method includes:

[0007] When performing a read operation and a write operation after the read operation within an access cycle, obtaining information of corresponding read data and write data; the objects of the read operation and the write operation are the first memory cell and the second memory cell in the same column of the memory array;

[0008] When it is determined that the read data and the write data are the same, a corresponding first control signal is generated, so that at the end of the read operation, the bit line precharging unit pulls down the corresponding bit line in the bit line pair of the corresponding column of the storage array from the first logic low level to the second logic low level based on the first control signal; the first logic low level is the voltage signal on the corresponding bit line at the end of the read operation, and the second logic low level is the voltage signal applied to the corresponding bit line during the write operation.

[0009] Optionally, when both the read data and the write data are "0", the corresponding bit line in the bit line pair of the corresponding column is the first bit line.

[0010] Optionally, when both the read data and the write data are "1", the corresponding bit line in the bit line pair of the corresponding column is the second bit line.

[0011] Optionally, when it is determined that the read data and the write data are different, the method further includes:

[0012] Generating a second control signal, so that at the end of the execution of the read operation, the bit line precharging unit pulls up the corresponding bit line in the bit line pair of the corresponding column of the storage array from the first logic low level to the logic high level based on the second control signal.

[0013] Optionally, when the read data is "0" and the write data is "1", the corresponding bit line in the bit line pair of the corresponding column is the first bit line.

[0014] Optionally, when the read data is "1" and the write data is "0", the corresponding bit line in the bit line pair of the corresponding column is the second bit line.

[0015] Correspondingly, an embodiment of the present invention further provides a bit line control device for a pseudo dual-port memory. The pseudo dual-port memory includes a storage array and a bit line precharging unit; the storage array includes a plurality of rows and columns of storage units; the storage units in the same row are coupled to the same word line, and the storage units in the same column are coupled to the same bit line pair; the bit line precharging unit is coupled to the bit line pair of the storage array; the bit line pair includes a complementary first bit line and a second bit line; the device includes:

[0016] An acquisition unit, adapted to acquire information on corresponding read data and write data when a read operation and a write operation after the read operation are performed within an access cycle; the read operation and the write operation are performed on the first storage unit and the second storage unit in the same column of the storage array;

[0017] A control unit, adapted to generate a corresponding first control signal when determining that the read data and the write data are the same, so that the bit line precharging unit, at the end of the read operation, based on the first control signal, pulls down the corresponding bit line in the bit line pair of the corresponding column of the storage array from a first logic low level to a second logic low level; the first logic low level is the voltage signal on the corresponding bit line at the end of the read operation, and the second logic low level is the voltage signal applied to the corresponding bit line during the write operation.

[0018] Optionally, when both the read data and the write data are "0", the corresponding bit line in the bit line pair of the corresponding column is the first bit line.

[0019] Optionally, when both the read data and the write data are "1", the corresponding bit line in the bit line pair of the corresponding column is the second bit line.

[0020] Optionally, the control unit is further adapted to generate a second control signal when determining that the read data and the write data are different, so that the bit line precharging unit, at the end of the execution of the read operation, based on the second control signal, pulls up the corresponding bit line in the bit line pair of the corresponding column of the storage array from a first logic low level to a logic high level.

[0021] Optionally, when the read data is "0" and the write data is "1", the corresponding bit line in the bit line pair of the corresponding column is the first bit line.

[0022] Optionally, when the read data is "1" and the write data is "0", the corresponding bit line in the bit line pair of the corresponding column is the second bit line.

[0023] Correspondingly, an embodiment of the present invention further provides a pseudo dual-port memory, including the bit line control device described in any one of the above.

[0024] Optionally, the bit line control device is an exclusive OR gate circuit.

[0025] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0026] In the above solution, when a read operation and a write operation are respectively performed on a first storage unit and a second storage unit in the same column within one access cycle, information on corresponding read data and write data is obtained; when it is determined that the read data and the write data are the same, a corresponding first control signal is generated, so that at the end of the read operation, the bit line precharging unit, based on the first control signal, pulls down the corresponding bit line in the bit line pair of the corresponding column from a first logic low level to a second logic low level. In this way, at the end of the read operation within the access cycle, it is possible to avoid the time and power consumption caused by first pulling up the corresponding bit line in the bit line pair of the corresponding column of the storage array from the first logic low level to the logic high level and then pulling it down to the second logic low level. Therefore, the energy consumption of the pseudo dual-port memory can be saved and the working speed can be increased, thereby improving the performance of the pseudo dual-port memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 FIG. shows a schematic circuit structure diagram of a storage unit of a pseudo dual-port memory;

[0028] Figure 2 FIG. shows Figure 1 a pulse timing diagram of related signals of the pseudo dual-port memory within one access cycle;

[0029] Figure 3 FIG. shows a schematic frame structure diagram of a pseudo dual-port memory according to an embodiment of the present invention;

[0030] Figure 4 FIG. shows a schematic flowchart of a bit line control method of a pseudo dual-port memory according to an embodiment of the present invention;

[0031] Figure 5 FIG. shows a pulse timing diagram of a related signal of a pseudo dual-port memory within one access cycle according to an embodiment of the present invention;

[0032] Figure 6 FIG. shows a pulse timing diagram of another related signal of a pseudo dual-port memory within one access cycle according to an embodiment of the present invention;

[0033] Figure 7 FIG. shows a pulse timing diagram of yet another related signal of a pseudo dual-port memory within one access cycle according to an embodiment of the present invention;

[0034] Figure 8 FIG. shows a pulse timing diagram of yet another related signal of a pseudo dual-port memory within one access cycle according to an embodiment of the present invention;

[0035] Figure 9 FIG. shows a schematic structure diagram of a bit line control device of a pseudo dual-port memory according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] As known from the background art, a pseudo dual-port memory can simulate a dual-port memory by sequentially performing two memory accesses during a storage cycle.

[0037] Generally speaking, a pseudo dual-port memory includes a storage array. The storage array includes storage units of the storage array arranged in multiple rows and columns. Among them, the storage units in the same row are coupled to the same word line, and the storage units in the same column are coupled to the same pair of bit lines. Each storage unit is used to store one bit of data.

[0038] Figure 1 The circuit structure schematic diagram of a storage unit of a pseudo dual-port memory is shown. Refer to Figure 1 , the storage unit 10 may include a first inverter (not labeled) and a second inverter (not labeled), a first access NMOS transistor NM3 and a second access NMOS transistor NM4.

[0039] The first inverter and the second inverter form a latch (not labeled). The latch has a first latch node Q and a second latch node QB, and the data on the first latch node Q and the second latch node QB are opposite.

[0040] The first inverter includes a first PMOS transistor PM1 and a first NMOS transistor NM1; the second inverter includes a second PMOS transistor PM2 and a second NMOS transistor NM2.

[0041] The gate terminal of the first PMOS transistor PM1 is coupled to the gate terminal of the first NMOS transistor NM1 and the second latch node QB of the latch. The source terminal of the first PMOS transistor PM1 is coupled to the power supply voltage VDD. The drain terminal of the first PMOS transistor PM1 is coupled to the drain terminal of the first NMOS transistor NM1 and serves as the first latch node Q of the latch. The source terminal of the first NMOS transistor NM1 is coupled to the ground voltage VSS.

[0042] The gate terminal of the second PMOS transistor PM2 is coupled to the gate terminal of the second NMOS transistor NM2 and the first latch node Q of the latch. The source terminal of the second PMOS transistor PM2 is coupled to the power supply voltage VDD and serves as the second latch node QB of the latch. The drain terminal of the second PMOS transistor PM1 is coupled to the drain terminal of the second NMOS transistor NM1. The source terminal of the second NMOS transistor NM1 is coupled to the ground voltage VSS;

[0043] The gate terminals of the first access NMOS transistor NM3 and the second access NMOS transistor NM4 are both coupled to the same word line WL. The source terminal of the first access NMOS transistor NM3 is coupled to the first latch node Q, and the drain terminal of the first access NMOS transistor NM3 is coupled to the first bit line BL in the corresponding bit line pair. The source terminal of the second access NMOS transistor NM4 is coupled to the second latch node QB, and the drain terminal of the second access NMOS transistor NM4 is coupled to the second bit line BLB in the corresponding bit line pair.

[0044] As described above, the pseudo dual-port memory can perform a read operation and then a write operation within one access cycle of the external clock signal CLK.

[0045] Figure 2 A pulse timing diagram of related signals of the pseudo dual-port memory within one access cycle is shown. Refer to Figure 2 , the pseudo dual-port memory can receive the external clock signal CLK and generate a read clock signal RD-CLK for the read operation and a write clock signal WR-CLK for the write operation after the read operation within one access cycle of the external clock signal CLK.

[0046] Please continue to refer to Figure 2 , and in combination with Figure 1 , within one access cycle of the external clock signal CLK:

[0047] When performing a read operation, before the rising edge of the read clock signal RD-CLK arrives, the first bit line BL and the second bit line BLB in the bit line pairs of all the memory cells in the memory array are pre-charged to the power supply voltage VDD. When the rising edge of the read clock signal RD-CLK arrives, the word line WL of the row where the memory cell to be read is located is charged to a high level, the first access NMOS transistor NM3 and the second access NMOS transistor NM4 of the corresponding memory cell are turned on, and the data on the first latch node Q and the second latch node QB are respectively transmitted to their first bit line BL and second bit line BLB through the first access NMOS transistor NM3 and the second access NMOS transistor NM4. By detecting the voltage difference between the first bit line BL and the second bit line BLB, the data stored in the corresponding memory cell can be read.

[0048] When the read operation is completed, the first bit line BL and the second bit line BLB in the bit line pairs of all the memory cells in the memory array are re-pre-charged to the power supply voltage VDD to prepare for the write operation after the read operation.

[0049] When the falling edge of the external clock signal CLK arrives, the write operation is triggered. Specifically, when the rising edge of the write clock signal WR-CLK arrives, the word line WL of the row where the memory cell to be written is located is charged to a high level, and the first access NMOS transistor NM3 and the second access NMOS transistor NM4 of the corresponding memory cell are turned on. The write data is transmitted to the first latch node Q and the second latch node QB of the memory cell to be written through the first bit line BL and the second bit line BLB of the row where the memory cell to be written is located, respectively, so as to write the write data into the corresponding memory cell.

[0050] When both the read data corresponding to the read operation and the write data corresponding to the write operation are 0, when the read clock signal RD-CLK is at a high level, the first bit line BL of the corresponding memory cell is pulled down from the power supply voltage VDD to the first low level VSS1 by the first latch node Q of the corresponding memory cell. Subsequently, before the read operation ends and the rising edge of the write clock signal WR-CLK arrives, the first bit line BL is pre-charged from the first low level to the power supply voltage VDD. After that, when the rising edge of the write clock signal WR-CLK arrives, the first bit line BL is pulled down from the power supply voltage VDD to the second low level VSS2.

[0051] Similarly, when both the read data and the write data are 1 and the read operation ends, the second bit line BLB will also be pulled up from the first low level VSS1 to the power supply voltage VDD, and then pulled down from the power supply voltage VDD to the second logic low level VSS2.

[0052] At the end of the read operation, pulling up the first bit line BL or the second bit line BLB from the first low level VSS1 to the power supply voltage VDD and then pulling it down from the power supply voltage VDD to the second logic low level VSS2 will not only cause a large amount of dynamic power consumption, but also cause a delay in the working speed of the pseudo dual-port memory, affecting the performance of the pseudo dual-port memory.

[0053] To solve the above problems, in the technical solution of the embodiment of the present invention, when performing read operations and write operations cyclically within each access cycle of an external clock signal, information on corresponding read data and write data is obtained; when it is determined that the read data and the write data are the same and the read operation ends, the corresponding bit line in the bit line pair of the storage unit to be written is continuously pulled down from a first logic low level to a second logic low level; the first logic low level is the voltage signal on the corresponding bit line of the storage unit when the write operation ends, and the second logic low level is the voltage signal applied to the corresponding bit line of the storage unit during the write operation. This can avoid the power and time losses caused by first pulling up the corresponding bit line in the bit line pair of the storage unit from the first logic low level to a logic high level and then pulling it down to the second logic low level when the read operation ends within the access cycle. Therefore, the energy consumption of the pseudo dual-port memory can be saved and the speed of the write operation can be increased, improving the performance of the pseudo dual-port memory.

[0054] For ease of understanding, first, the structure of a dual-port memory in the embodiment of the present invention will be introduced below.

[0055] Figure 3 The structure of a pseudo dual-port memory in the embodiment of the present invention is shown. Refer to Figure 3 , a pseudo dual-port memory in the embodiment of the present invention includes a storage array 310, a timing control circuit 320, a word line decoding and word line driving circuit 330, a bit line decoding circuit 340, and an input / output circuit 350.

[0056] The storage array 310 includes (M*N) storage units, word lines WL0 to WLm provided in one-to-one correspondence with the rows of the storage units, and bit line pairs (BL0 / BLB0) to (BLn / BLBn). Wherein, M represents the number of rows of the storage array 310, N represents the number of columns of the storage array 310, and both M and N are positive integers greater than 1, m=(M - 1), and n=(N - 1).

[0057] In the storage array 310, the storage units in the same row are coupled to the same read word line WLi (0≤i≤m, and i is a positive integer), and the storage units in the same column are coupled to the same word line pair BLj, BLBj (0≤j≤n, and j is a positive integer). Specifically, the storage units in the first row are respectively coupled to the first word line WL0, the storage units in the second row are respectively coupled to the second word line WL1... the storage units in the Mth row are coupled to the Mth word line WLm; the storage units in the first column are respectively coupled to the first bit line pair BL0, BLB0, the storage units in the second column are respectively coupled to the second bit line pair BL1, BLB1... the storage units in the Nth column are respectively coupled to the Nth bit line pair BLn, BLBn.

[0058] The size of the memory array 310, that is, the number of memory cells, can be set according to actual needs and can vary according to specific applications, speed requirements, layout and test requirements, and overall design requirements imposed on the system. Generally, the memory array can contain thousands or millions of memory cells.

[0059] The timing control circuit 320 can receive an external clock signal, a read address, and a write address, and control the read operation of the memory array and the write operation after the read operation within one access cycle of the external clock signal. Specifically, the timing control circuit 320 can generate a read clock signal for the read operation and a write clock signal for the write operation after the read operation within one access cycle of the external clock signal. Among them, the read operation is triggered by the rising edge of the external clock signal, and the write operation is triggered by the falling edge of the external clock signal.

[0060] When performing a read operation, the timing control circuit 320 can send the read address to the word line decoding and word line driving circuit 330 and the bit line decoding circuit 340 respectively for read row address decoding and read column address decoding. The word line decoding and word line driving circuit 330 charges the word lines corresponding to the row in the memory array to the power supply voltage according to the row address decoding result of the read address. The bit line decoding circuit 340 can generate a corresponding read selection signal according to the column address decoding result of the read address and send it to the input / output circuit 350. The input / output circuit 350 can then read the corresponding stored data from the corresponding memory cell through the corresponding bit line pair according to the read selection signal.

[0061] When performing a write operation, the timing control circuit 320 can send the write address to the word line decoding and word line driving circuit 330 and the bit line decoding circuit 340 respectively for row address and column address decoding of the write address. The word line decoding and word line driving circuit 330 can charge the word lines corresponding to the row in the memory array to the power supply voltage according to the row address decoding result of the write address. The bit line decoding circuit 340 can generate a corresponding write selection signal according to the column address decoding result of the write address and send it to the input / output circuit 350. The input / output circuit 350 can then write the write data received from the peripheral device into the corresponding memory cell in the memory array for storage through the corresponding bit line pair according to the write selection signal.

[0062] The timing control circuit 320 can also generate a corresponding precharge control signal to the input / output circuit 350 so that the input / output circuit 350 can precharge the bit line pairs of the memory cells in the memory array to a high level before the read operation.

[0063] In some embodiments, the input / output circuit 350 may include a read column multiplexer 351, a sense amplifier 352, an output data latch 353, an input data latch 354, a write driver 355, a write column multiplexer 356, a bit line control device 357, and a bit line precharge circuit 358.

[0064] When performing a read operation, the read column multiplexer 351 may receive the read select signal sent by the timing control circuit 320, and couple the first bit line and the second bit line of the memory cell corresponding to the read address to the sense amplifier 352 according to the read select signal. The sense amplifier 352 may receive the differential voltage signals on the coupled first bit line and second bit line, and read the data stored in the memory cell corresponding to the read address according to the differential voltage signals on the first bit line and the second bit line, and send it to the output data latch 353; the output data latch 353 may latch the received read data and transmit it to the peripheral device.

[0065] When performing a write operation, the input data latch 354 may latch the write data sent by the peripheral device and send it to the write driver 355; the write column multiplexer 356 may couple the first bit line and the second bit line of the memory cell corresponding to the write address to the write driver 335 according to the write select signal when receiving the write select signal sent by the bit line decoding circuit 340. The write driver 335 may drive the received write data to the memory cell corresponding to the write address through the corresponding first bit line and second bit line for storage.

[0066] Next, in conjunction with Figure 4 The bit line control method of the pseudo dual-port memory in the embodiments of the present invention, that is, the working methods of the bit line control device and the bit line precharge circuit in the input / output circuit, will be described in detail.

[0067] Figure 4 The flow diagram of a bit line control method of a pseudo dual-port memory in the embodiments of the present invention is shown. Refer to Figure 4 , a bit line control method of a pseudo dual-port memory may specifically include:

[0068] Step S401: When performing a read operation and a write operation on a first memory cell and a second memory cell in the same column within an access cycle, the bit line control device obtains information of the corresponding read data and write data.

[0069] In a specific implementation, the bit line control device can respectively obtain whether the first storage unit and the second storage unit corresponding to the read operation and the write operation executed within the same access cycle belong to the same column in the storage array through the read column multiplexer and the write column multiplexer of the pseudo dual-port memory.

[0070] Specifically, when the read operation is executed within the access cycle, the bit line decoding circuit can generate a corresponding read selection signal according to the information of the received read address, so that when the read column multiplexer of the corresponding column receives the read selection signal, it couples the bit line pair of the corresponding column to the differential input terminal of the sense amplifier.

[0071] Similarly, when the write operation is executed after the read operation within the access cycle, the bit line decoding circuit can respectively generate corresponding write selection signals according to the information of the received write address, so that when the write multiplexer of the corresponding column receives the write selection signal, it couples the bit line pair of the corresponding column to the write driver.

[0072] Therefore, the bit line control device can determine whether the first storage unit, which is the operation object of the read operation, and the second storage unit, which is the operation object of the write operation, within the access cycle are storage units in the same column by whether the read selection signal obtained through the read column multiplexer is the same as the write selection signal obtained through the write column multiplexer.

[0073] When it is determined that the first storage unit and the second storage unit are storage units in the same column, the bit line control device can obtain the data read from the first storage unit when executing the read operation, and obtain the write data to be written into the second storage unit. Specifically, the bit line control device can obtain the read data from the sense amplifier and obtain the information of the write data from the write driver.

[0074] Step S402: The bit line control device determines whether the read data and the write data are the same; if the determination result is yes, step S403 can be executed; otherwise, step S405 can be executed.

[0075] In a specific implementation, when the read data and the write data are obtained, the bit line control device can compare the obtained read data and write data to determine whether the read data and the write data are the same. Among them, the read data and the write data being the same includes two cases where both the read data and the write data are 0 or 1.

[0076] Step S403: The bit line control device generates a corresponding first control signal and sends it to the bit line precharge unit.

[0077] In a specific implementation, when it is determined that the read data and the write data are the same, the bit line control device may generate a corresponding first control signal and send it to the bit line pre-charging unit.

[0078] In an embodiment of the present invention, when it is determined that the read data and the write data are the same, the bit line control device may generate a corresponding high-level signal as the first control signal and send it to the bit line pre-charging unit.

[0079] Step S404: When the bit line pre-charging unit determines that the read operation is ended, based on the first control signal, it further pulls down the corresponding bit line in the bit line pair of the corresponding column from the first logic low level to the second logic low level.

[0080] In a specific implementation, the bit line pre-charging unit may receive the first control signal, and when the read operation is ended, based on the first control signal, it further pulls down the corresponding bit line in the bit line pair of the corresponding column from the first logic low level to the second logic low level.

[0081] As described above, the read data and the write data being the same may include two cases where both the read data and the write data are 0 or both are 1.

[0082] See Figure 5 , when both the read data and the write data are 0 and the read operation is ended, that is, when the falling edge of the read clock signal RD-CLK arrives, the first bit line BL of the columns where the first storage unit and the second storage unit are located is pulled down from the preset power supply voltage VDD to the first logic low level VSS1 by the first storage unit. Then, before the rising edge of the write clock signal WR-CLK arrives when the read operation is ended, the bit line pre-charging unit further pulls down the first bit line BL of the corresponding column from the first logic low level VSS1 to the second logic low level VSS2.

[0083] Similarly, see Figure 6 , when both the read data and the write data are 1, when the falling edge of the read clock signal RD-CLK arrives, the second bit line BLB of the columns where the first storage unit and the second storage unit are located is pulled down from the preset power supply voltage VDD to the first logic low level VSS1 by the first storage unit. Subsequently, before the rising edge of the write clock signal WR-CLK arrives when the read operation is ended, the bit line pre-charging unit further pulls down the second bit line BLB of the corresponding column from the first logic low level VSS1 to the second logic low level VSS2.

[0084] It can be seen therefrom that at the end of the read operation, directly pulling down the first bit line BL or the second bit line BLB in the bit line pair corresponding to the column in the storage array from the first logic low level VSS1 to the second logic low level VSS1 can avoid the dynamic power consumption caused by first pulling up the first bit line BL or the second bit line BLB from the first logic low level VSS1 to the power supply voltage VDD and then pulling it down from the power supply voltage VDD to the second logic low level VSS2, and can shorten the operation time and improve the working speed, thus improving the working performance of the pseudo dual-port memory.

[0085] Step S405: The bit line control device generates a corresponding second control signal and sends it to the bit line precharging unit.

[0086] In a specific implementation, when it is determined that the read data and the write data are different, the bit line control device can generate a corresponding second control signal and send it to the bit line precharging unit. Among them, the read data and the write data being different includes two cases: the read data is 0 and the write data is 1, or the read data is 1 and the write data is 0.

[0087] In an embodiment of the present invention, when it is determined that the read data and the write data are the same, the bit line control device can generate a corresponding low-level signal as the second control signal and send it to the bit line precharging unit.

[0088] Step S406: The bit line precharging unit receives the first control signal and, when it is determined that the read operation ends, based on the first control signal, pulls up the corresponding bit line in the bit line pair corresponding to the column from the first logic low level to the logic high level.

[0089] See Figure 7 , when the read data is 0 and the write data is 1, the first bit line BL in the corresponding column where the first storage unit and the second storage unit are located is pulled down from the preset power supply voltage VDD to the first logic low level VSS1 by the first storage unit at the end of the read operation. Then, before the rising edge of the write clock signal WR-CLK arrives after the read operation ends, the bit line precharging unit pulls up the first bit line BL in the corresponding column from the first logic low level VSS1 to the high level VDD to prepare for the subsequent write operation.

[0090] See Figure 8, when the read data is 1, the write data is 0, and the read operation ends, that is, when the falling edge of the read clock signal RD-CLK arrives, the second bit line BLB of the corresponding column where the first storage unit and the second storage unit are located is pulled down from the preset high level VDD to the first logic low level VSS1 by the first storage unit. Subsequently, before the rising edge of the write clock signal WR-CLK arrives after the read operation ends, the bit line precharging unit pulls up the second bit line BLB of the corresponding column from the first logic low level VSS1 to the high level VDD to prepare for the subsequent write operation.

[0091] Correspondingly, an embodiment of the present invention further provides a bit line control device for a pseudo dual-port memory.

[0092] Figure 9 The structural schematic diagram of a bit line control device in an embodiment of the present invention is shown. Refer to Figure 9 , a bit line control device 90 includes:

[0093] An acquisition unit 901, adapted to acquire information of corresponding read data and write data when a read operation and a write operation after the read operation are performed within an access cycle; the objects of the read operation and the write operation are the first storage unit and the second storage unit in the same column of the storage array;

[0094] A control unit 902, adapted to generate a corresponding first control signal when it is determined that the read data and the write data are the same, so that the bit line precharging unit, at the end of the read operation, based on the first control signal, pulls down the corresponding bit line in the bit line pair of the corresponding column of the storage array from the first logic low level to the second logic low level; the first logic low level is the voltage signal on the corresponding bit line at the end of the read operation, and the second logic low level is the voltage signal applied to the corresponding bit line during the write operation. Wherein, when both the read data and the write data are "0", the corresponding bit line in the bit line pair of the corresponding column is the first bit line; when both the read data and the write data are "1", the corresponding bit line in the bit line pair of the corresponding column is the second bit line. Wherein, the voltage values corresponding to the first logic low level and the second logic low level can be set according to actual needs and are not limited herein.

[0095] In a specific implementation, the control unit 902 is further adapted to generate a second control signal when it is determined that the read data and the write data are different, so that the bit line precharging unit pulls up the corresponding bit line in the bit line pair of the corresponding column of the storage array from the first logic low level to the logic high level based on the second control signal at the end of the execution of the read operation. Wherein, when the read data is "0" and the write data is "1", the corresponding bit line in the bit line pair of the corresponding column is the first bit line; when the read data is "1" and the write data is "0", the corresponding bit line in the bit line pair of the corresponding column is the second bit line.

[0096] Correspondingly, an embodiment of the present invention further provides a pseudo dual-port memory, including the bit line control device described in any one of the above.

[0097] In an embodiment of the present invention, the bit line control device is an exclusive OR gate circuit to save the layout occupation area and reduce the leakage current loss. [[ID=⑧]]

[0098] Those skilled in the art can also implement it by using other circuits with the above bit line control functions of the bit line control device in the embodiments of the present invention, which are not limited herein.

[0099] By adopting the above solution in the embodiment of the present invention, when the pseudo dual-port memory performs a read operation and a write operation on the first storage unit and the second storage unit in the same column respectively within an access cycle, it obtains the information of the corresponding read data and write data; when it is determined that the read data and the write data are the same, it generates a corresponding first control signal, so that the bit line precharging unit pulls down the corresponding bit line in the bit line pair of the corresponding column from the first logic low level to the second logic low level based on the first control signal at the end of the read operation. In this way, the energy consumption and time loss caused by first pulling up the corresponding bit line in the bit line pair of the corresponding column from the first logic low level to the logic high level and then pulling it down to the second logic low level at the end of the read operation within the access cycle can be avoided. Therefore, the energy of the pseudo dual-port memory can be saved, the working speed can be increased, and the performance of the pseudo dual-port memory can be improved.

[0100] The above-described embodiments of the present invention are combinations of elements and features of the present invention. Unless otherwise mentioned, the elements or features may be considered optional. Each element or feature may be practiced without combination with other elements or features. Additionally, embodiments of the present invention may be constructed by combining some of the elements and / or features. The operation sequences described in the embodiments of the present invention may be rearranged. Some configurations of any embodiment may be included in another embodiment and replaced by corresponding configurations of another embodiment. It is obvious to those skilled in the art that claims that do not have an explicit citation relationship with each other in the appended claims may be combined into embodiments of the present invention or included as new claims in amendments after the filing of this application.

[0101] Embodiments of the present invention can be implemented by various means such as, for example, hardware, firmware, software, or combinations thereof. In a hardware configuration, the method according to an exemplary embodiment of the present invention can be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, etc.

[0102] In a firmware or software configuration, embodiments of the present invention can be implemented in the form of modules, procedures, functions, etc. The software code can be stored in a memory unit and executed by a processor. The memory unit is located inside or outside the processor and can send data to and receive data from the processor via various known means.

[0103] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

[0104] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A bit line control device for a pseudo dual-port memory, the pseudo dual-port memory comprising a memory array and a bit line precharging unit; the memory array includes a plurality of rows and columns of memory cells; the memory cells in the same row are coupled to the same word line, and the memory cells in the same column are coupled to the same bit line pair; the bit line precharging unit is coupled to the bit line pairs of the memory array; the bit line pairs include a complementary first bit line and a second bit line; characterized in that, The device includes: An acquisition unit, adapted to acquire information on corresponding read data and write data when a read operation and a write operation after the read operation are performed within an access cycle; the objects of the read operation and the write operation are a first storage unit and a second storage unit in the same column of the storage array; a control unit, adapted to generate a corresponding first control signal when it is determined that the read data and the write data are the same, so that the bit line precharging unit, at the end of the read operation, based on the first control signal, pulls down a corresponding bit line in the bit line pair of the corresponding column of the storage array from a first logic low level to a second logic low level; the first logic low level is the voltage signal on the corresponding bit line at the end of the read operation, and the second logic low level is the voltage signal applied to the corresponding bit line during the write operation.

2. The bit line control device of the pseudo dual-port memory according to claim 1, characterized in that, When both the read data and the write data are "0", the corresponding bit line in the bit line pair of the corresponding column is the first bit line.

3. The bit line control device of the pseudo dual-port memory according to claim 1, wherein When both the read data and the write data are "1", the corresponding bit line in the bit line pair of the corresponding column is the second bit line.

4. The bit line control device of the pseudo dual-port memory according to claim 1, wherein The control unit is further adapted to generate a second control signal when it is determined that the read data and the write data are different, so that the bit line precharging unit, at the end of the execution of the read operation, based on the second control signal, pulls up the corresponding bit line in the bit line pair of the corresponding column of the storage array from the first logic low level to a logic high level.

5. The bit line control device of the pseudo dual-port memory according to claim 4, characterized in that, When the read data is "0" and the write data is "1", the corresponding bit line in the bit line pair of the corresponding column is the first bit line.

6. The bit line control device of the pseudo dual-port memory according to claim 4, characterized in that When the read data is "1" and the write data is "0", the corresponding bit line in the bit line pair of the corresponding column is the second bit line.

7. A pseudo dual-port memory, characterized in that, Includes the bit line control device according to any one of claims 1 to 6.

8. The pseudo dual-port memory according to claim 7, wherein The bit line control device is an exclusive OR gate circuit.

9. A bit line control method for a pseudo dual-port memory, the pseudo dual-port memory including a memory array and a bit line precharging unit; the memory array including memory cells arranged in multiple rows and multiple columns; the memory cells in the same row being coupled to the same word line, and the memory cells in the same column being coupled to the same bit line pair; the bit line precharging unit being coupled to the bit line pairs of the memory array; the bit line pairs including a complementary first bit line and second bit line; characterized in that, The method includes: When a read operation and a write operation after the read operation are performed within an access cycle, acquire information on corresponding read data and write data; the objects of the read operation and the write operation are respectively a first storage unit and a second storage unit in the same column of the storage array; When it is determined that the read data and the write data are the same, generate a corresponding first control signal, so that the bit line precharging unit, at the end of the read operation, based on the first control signal, pulls down a corresponding bit line in the bit line pair of the corresponding column of the storage array from a first logic low level to a second logic low level; the first logic low level is the voltage signal on the corresponding bit line at the end of the read operation, and the second logic low level is the voltage signal applied to the corresponding bit line during the write operation.

10. The bit line control method of the pseudo dual-port memory according to claim 9, wherein, When both the read data and the write data are "0", the corresponding bit line in the bit line pair of the corresponding column is the first bit line.

11. The bit line control method of the pseudo dual-port memory according to claim 9, characterized in that, When both the read data and the write data are "1", the corresponding bit line in the bit line pair of the corresponding column is the second bit line.

12. The bit line control method of the pseudo dual-port memory according to claim 9, characterized in that, When it is determined that the read data and the write data are different, it further includes: Generate a second control signal, so that at the end of the execution of the read operation, the bit line precharge unit pulls up the corresponding bit line in the bit line pair of the corresponding column of the storage array from the first logic low level to the logic high level based on the second control signal.

13. The bit line control method of the pseudo dual-port memory according to claim 12, characterized in that When the read data is "0" and the write data is "1", the corresponding bit line in the bit line pair of the corresponding column is the first bit line.

14. The bit line control method of the pseudo dual-port memory according to claim 12, characterized in that, When the read data is "1" and the write data is "0", the corresponding bit line in the bit line pair of the corresponding column is the second bit line.

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