A 12T radiation-hardened SRAM memory cell based on polarity strengthening technology

Abstract

The present invention discloses a 12T radiation-hardened SRAM memory cell based on polarity reinforcement technology, which includes 4 NMOS transistors and 8 PMOS transistors; the internal storage nodes I2 and I3 are cross-coupled by P2 and P3, and the external storage nodes I1 and I4 are cross-coupled by N1 and N2; P1 and P4 serve as pull-up transistors, and P1 and P4 reinforce I2 and I3. I2 and I3 are entirely surrounded by PMOS transistors, which constitutes a polarity reinforcement structure; I2 is connected to the BLB through P7, I3 is connected to the BL through P8, I1 is connected to the BL through N3, I4 is connected to the BLB through N4, and N3 and N4 are controlled by the WL, while P7 and P8 are controlled by the WWL. The present invention can improve the single-event upset resistance of the SRAM memory cell, and can significantly improve the write speed of the SRAM memory cell while sacrificing a small cell area, and reduce the power consumption of the SRAM memory cell.

Description

Technical Field

[0001] The present invention relates to the technical field of SRAM (Static Random Access Memory), and in particular to a 12T (12T refers to 12 CMOS transistors) radiation-hardened SRAM memory cell based on a polarity hardening technique. It is a cell circuit structure that can improve the write speed of the memory cell and the ability of the cell to resist single event upset (SEU), hereinafter referred to as RHMC-12T. Background Art

[0002] With the rapid development of the integrated circuit industry, static random access memory has become a key component of high-performance integrated circuits (ICs). In aerospace electronic equipment, integrated circuit chips are almost indispensable components, and aerospace electronic equipment is often in a space radiation environment. Once a high-energy particle from cosmic rays hits a sensitive node of a memory cell, it will occasionally cause a temporary single event upset (SEU). At the same time, the storage node capacitance of the SRAM cell decreases as the total area decreases, and the power supply voltage decreases with technological development, which reduces the charge of the storage node. Therefore, the influence of high-energy particles (high-energy particles such as neutrons exist in cosmic rays and ray particles) easily leads to SEU chaos. When high-energy particles pass through the silicon substrate, minority carriers (electron-hole pairs) are generated, and these carriers are collected and accumulated at the source or drain diffusion, generating a voltage transient at the sensitive node. If the accumulated charge is greater than the charge on the sensitive node, the data on the sensitive storage node will be changed.

[0003] To solve the influence of SEU on SRAM cells and improve the ability of memory cells to resist SEU, the following main solutions are included in the prior art:

[0004] (1) As Figure 1 shown, the circuit is a Soft Error Tolerant 10T SRAM BitCell (QUATRO 10T) circuit proposed by Shah M. Jahinuzzamandeng and David J. Rennie in 2009. It consists of four PMOS transistors and six NMOS transistors, and two NOMS transistors are used as transmission transistors; the write ability of this circuit is poor, the write delay is high, and the write failure rate is large at high frequencies.

[0005] (2) As Figure 2The circuit shown is a basic 6T SRAM memory cell, which consists of two PMOS transistors and four NMOS transistors; the number of transistors used in this memory cell is the least, so it has the smallest area, but this circuit does not have any ability to resist single-event upsets.

[0006] (3) As Figure 3 The circuit shown is a soft-error-aware-14T (SEA14T) circuit proposed by Soumitra Pal in 2021. It is composed of six PMOS transistors and eight NMOS transistors, and two NMOS transistors are used as transmission transistors; although it has good SEU resistance, the area consumed by the circuit is large and the write data delay is high.

[0007] (4) As Figure 4 The circuit shown is the Quadruple Cross-Coupled Memory (QCCM12T) circuit proposed by Aibin Yan in 2019. It uses four access transistors, has a lower read / write access time, can better tolerate single-event upsets and a few double-node pair upsets, but this circuit has a large static power consumption.

[0008] (5) As Figure 5 The circuit shown is a soft-error resilient read decoupled 12T (SRRD12T) circuit proposed by Soumitra Pal in 2021. It is composed of eight PMOS transistors and four NMOS transistors, and two NMOS transistors and two PMOS transistors are used as transmission transistors. Although it has a lower write delay, its read delay is high.

[0009] In view of this, the present invention is specifically proposed. Summary of the Invention

[0010] The object of the present invention is to provide a 12T radiation-hardened SRAM memory cell based on a polarity reinforcement technology to solve the above technical problems existing in the prior art. The present invention can not only improve the single-event upset resistance of the SRAM memory cell, but also greatly improve the write speed of the SRAM memory cell while sacrificing a small cell area, and reduce the power consumption of the SRAM memory cell.

[0011] The object of the present invention is achieved by the following technical solutions:

[0012] A 12T radiation-hardened SRAM memory cell based on polarity strengthening technology, comprising 4 NMOS transistors and 8 PMOS transistors. These 4 NMOS transistors are respectively defined as N1, N2, N3, and N4; these 8 PMOS transistors are respectively defined as P1, P2, P3, P4, P5, P6, P7, and P8. The internal storage nodes I2 and I3 are cross-coupled by the PMOS transistor P2 and the PMOS transistor P3, and the external storage nodes I1 and I4 are cross-coupled by the NMOS transistor N1 and the NMOS transistor N2. The PMOS transistors P1 and P4 serve as pull-up transistors, and the NMOS transistors N1 and N2 serve as pull-down transistors. The PMOS transistors P1 and P4 strengthen the internal storage nodes I2 and I3, and the internal storage nodes I2 and I3 are all surrounded by PMOS transistors, which constitutes a polarity strengthening structure. The internal storage node I2 is connected to the second bit line BLB through the PMOS transistor P7, the internal storage node I3 is connected to the first bit line BL through the PMOS transistor P8, the external storage node I1 is connected to the first bit line BL through the NMOS transistor N3, the external storage node I4 is connected to the second bit line BLB through the NMOS transistor N4, the NMOS transistors N3 and N4 are controlled by the first word line WL, and the PMOS transistors P7 and P8 are controlled by the second word line WWL.

[0013] Preferably, the drain of the PMOS transistor P2 is electrically connected to the gate of the PMOS transistor P3 and the source of the PMOS transistor P5 at the internal storage node I2, the drain of the PMOS transistor P5 is grounded, the drain of the PMOS transistor P3 is electrically connected to the gate of the PMOS transistor P2 and the source of the PMOS transistor P6 at the internal storage node I3, and the drain of the PMOS transistor P6 is grounded. The drain of the NMOS transistor N1 is electrically connected to the gate of the NMOS transistor N2 and the gate of the PMOS transistor P6 at the external storage node I1, the source of the NMOS transistor N1 is grounded, the drain of the NMOS transistor N2 is electrically connected to the gate of the NMOS transistor N1 and the gate of the PMOS transistor P5 at the external storage node I4, and the source of the NMOS transistor N2 is grounded. The source of the PMOS transistor P1 is connected to the voltage VDD, the gate of the PMOS transistor P1 is electrically connected to the internal storage node I2, and the drain of the PMOS transistor P1 is electrically connected to the external storage node I1 and the source of the PMOS transistor P3. The source of the PMOS transistor P4 is connected to the voltage VDD, the gate of the PMOS transistor P4 is electrically connected to the internal storage node I3, and the drain of the PMOS transistor P4 is electrically connected to the external storage node I4 and the source of the PMOS transistor P2.

[0014] The drain of PMOS transistor P7 is electrically connected to the internal storage node I2, the source of PMOS transistor P7 is electrically connected to the second bit line BLB, and the gate of PMOS transistor P7 is electrically connected to the second word line WWL; the drain of PMOS transistor P8 is electrically connected to the internal storage node I3, the source of PMOS transistor P8 is electrically connected to the first bit line BL, and the gate of PMOS transistor P8 is electrically connected to the second word line WWL;

[0015] The drain of NMOS transistor N3 is electrically connected to the external storage node I1, the source of NMOS transistor N3 is electrically connected to the first bit line BL, and the gate of NMOS transistor N3 is electrically connected to the first word line WL; the drain of NMOS transistor N4 is electrically connected to the external storage node I4, the source of NMOS transistor N4 is electrically connected to the second bit line BLB, and the gate of NMOS transistor N4 is electrically connected to the first word line WL.

[0016] Preferably, the gate length of all NMOS transistors and all PMOS transistors is 65 nm; the gate widths of PMOS transistors P1 and P4 are 420 nm, the gate widths of PMOS transistors P2 and P3 are 280 nm, the gate widths of PMOS transistors P5 and P6 are 85 nm, the gate widths of PMOS transistors P7 and P8 are 140 nm, the gate widths of NMOS transistors N1 and N2 are 280 nm, and the gate widths of NMOS transistors N3 and N4 are 140 nm.

[0017] Compared with the prior art, the present invention includes 4 NMOS transistors and 8 PMOS transistors. The internal storage nodes I2 and I3 are cross-coupled by PMOS transistors P2 and P3, and the external storage nodes I1 and I4 are cross-coupled by NMOS transistors N1 and N2; PMOS transistors P1 and P4 serve as pull-up transistors, and NMOS transistors N1 and N2 serve as pull-down transistors; PMOS transistors P1 and P4 reinforce the internal storage nodes I2 and I3, and the internal storage nodes I2 and I3 are all surrounded by PMOS transistors, which constitutes a polarity reinforcement structure; NMOS transistors N3, N4, PMOS transistors P7 and P8 are transfer transistors. NMOS transistors N3 and N4 are controlled by the first word line WL, and PMOS transistors P7 and P8 are controlled by the second word line WWL; that is to say, the present invention is designed by adopting the polarity reinforcement principle that different types of transistors have a single flip characteristic under the bombardment of space heavy ions. Using this design ensures the stability of the internal storage nodes I2 and I3, and further enhances the anti-flip ability of the internal nodes of the circuit of the present invention. At the same time, the circuit uses four transfer transistors for reading and writing. When writing data, the bit lines write data to the internal nodes I1\I4 and I2\I3 simultaneously through the transfer transistors N3, N4, P7, and P8, which makes it easier for the storage nodes to be written with data. Therefore, the present invention greatly improves the data writing speed of the unit. Due to the improvement of the writing speed, the circuit has lower power consumption. Description of the Drawings

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0019] Figure 1 It is a schematic structural diagram of the Quatro 10T circuit in the prior art;

[0020] Figure 2 It is a schematic structural diagram of the 6T circuit in the prior art;

[0021] Figure 3 It is a schematic structural diagram of the SEA14T circuit in the prior art;

[0022] Figure 4 It is a schematic structural diagram of the QCCM12T circuit in the prior art;

[0023] Figure 5 It is a schematic structural diagram of the SRRD12T circuit in the prior art;

[0024] Figure 6 It is a schematic structural diagram of the 12T radiation-hardened SRAM memory cell (abbreviation: RHMC-12T) based on the polarity reinforcement technology provided by the embodiment of the present invention;

[0025] Figure 7 It is a timing waveform diagram of the 12T radiation-hardened SRAM memory cell based on the polarity reinforcement technology provided by Embodiment 1 of the present invention (simulation conditions: Corner: TT; Temperature: 25°C; VDD: 1.2V);

[0026] Figure 8 It is a transient waveform simulation diagram of the 12T radiation-hardened SRAM memory cell based on the polarity reinforcement technology provided by Embodiment 1 of the present invention when it is injected with a double-exponential current source pulse at different times and different nodes (simulation conditions: VDD: 1.2V);

[0027] Figure 9 It is a comparison diagram of EQM values of the Quatro 10T circuit, 6T circuit, SEA14T circuit, QCCM12T circuit, SRRD12T circuit in the prior art and the 12T radiation-hardened SRAM memory cell based on the polarity reinforcement technology provided by Embodiment 1 of the present invention (simulation conditions: VDD: 1.2V);

[0028] Figure 10 It is a comparison diagram of HSNM, RSNM, and WSNM of the Quatro 10T circuit, 6T circuit, SEA14T circuit, QCCM12T circuit, SRRD12T circuit in the prior art and the 12T radiation-hardened SRAM memory cell based on the polarity reinforcement technology provided by Embodiment 1 of the present invention (simulation conditions: Corner: TT; Temperature: 27°C; VDD: 1.2V). Detailed implementation manners

[0029] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention; obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments, which does not constitute a limitation to the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0030] First, the following explanations are made for the terms that may be used in this article:

[0031] Descriptions with semantic meanings such as "comprising", "including", "containing", "having" or other similar terms shall be construed as non-exclusive inclusion. For example, including a technical feature element (such as raw material, component, ingredient, carrier, dosage form, material, size, part, component, mechanism, device, step, process, method, reaction condition, processing condition, parameter, algorithm, signal, data, product or article, etc.) shall be construed as not only including the explicitly listed technical feature element, but also including other technical feature elements well-known in the art that are not explicitly listed.

[0032] The 12T radiation-hardened SRAM memory cell based on the polarity strengthening technology provided by the present invention will be described in detail below. The content not described in detail in the present invention belongs to the prior art well-known to those skilled in the art. For those conditions not specified in the embodiments of the present invention, they shall be carried out according to the conventional conditions in the art or the conditions recommended by the manufacturer. For the reagents or instruments not specified in the embodiments of the present invention for the manufacturer, they are all conventional products that can be obtained through commercial purchase.

[0033] Embodiment 1

[0034] As Figure 6 shown, Embodiment 1 of the present invention provides a 12T radiation-hardened SRAM memory cell (abbreviated as RHMC-12T) based on the polarity strengthening technology. Its structure mainly includes 4 NMOS transistors and 8 PMOS transistors. These 4 NMOS transistors are respectively defined as N1, N2, N3, and N4; these 8 PMOS transistors are respectively defined as P1, P2, P3, P4, P5, P6, P7, and P8. The internal storage nodes I2 and I3 are cross-coupled by the PMOS transistors P2 and P3, and the external storage nodes I1 and I4 are cross-coupled by the NMOS transistors N1 and N2; the PMOS transistors P1 and P4 serve as pull-up transistors, and the NMOS transistors N1 and N2 serve as pull-down transistors; the PMOS transistors P1 and P4 strengthen the internal storage nodes I2 and I3, and the internal storage nodes I2 and I3 are all surrounded by PMOS transistors, which constitutes a polarity strengthening structure; the internal storage node I2 is connected to the second bit line BLB through the PMOS transistor P7, the internal storage node I3 is connected to the first bit line BL through the PMOS transistor P8, the external storage node I1 is connected to the first bit line BL through the NMOS transistor N3, the external storage node I4 is connected to the second bit line BLB through the NMOS transistor N4, the NMOS transistors N3 and N4 are controlled by the first word line WL, and the PMOS transistors P7 and P8 are controlled by the second word line WWL.

[0035] Specifically, the specific structure of the 12T radiation-hardened SRAM memory cell based on the polarity hardening technology includes: the drain of PMOS transistor P2 is electrically connected to the gate of PMOS transistor P3 and the source of PMOS transistor P5 at the internal storage node I2, the drain of PMOS transistor P5 is grounded, the drain of PMOS transistor P3 is electrically connected to the gate of PMOS transistor P2 and the source of PMOS transistor P6 at the internal storage node I3, and the drain of PMOS transistor P6 is grounded; the drain of NMOS transistor N1 is electrically connected to the gate of NMOS transistor N2 and the gate of PMOS transistor P6 at the external storage node I1, the source of NMOS transistor N1 is grounded, the drain of NMOS transistor N2 is electrically connected to the gate of NMOS transistor N1 and the gate of PMOS transistor P5 at the external storage node I4, and the source of NMOS transistor N2 is grounded; the source of PMOS transistor P1 is connected to the voltage VDD, the gate of PMOS transistor P1 is electrically connected to the internal storage node I2, and the drain of PMOS transistor P1 is electrically connected to the external storage node I1 and the source of PMOS transistor P3; the source of PMOS transistor P4 is connected to the voltage VDD, the gate of PMOS transistor P4 is electrically connected to the internal storage node I3, and the drain of PMOS transistor P4 is electrically connected to the external storage node I4 and the source of PMOS transistor P2. Thus, PMOS transistor P1 and PMOS transistor P4 reinforce the internal storage nodes I2 and I3, and the internal storage nodes I2 and I3 are all surrounded by PMOS transistors, which constitutes the polarity hardening structure. The drain of PMOS transistor P7 is electrically connected to the internal storage node I2, the source of PMOS transistor P7 is electrically connected to the second bit line BLB, and the gate of PMOS transistor P7 is electrically connected to the second word line WWL; the drain of PMOS transistor P8 is electrically connected to the internal storage node I3, the source of PMOS transistor P8 is electrically connected to the first bit line BL, and the gate of PMOS transistor P8 is electrically connected to the second word line WWL. The drain of NMOS transistor N3 is electrically connected to the external storage node I1, the source of NMOS transistor N3 is electrically connected to the first bit line BL, and the gate of NMOS transistor N3 is electrically connected to the first word line WL; the drain of NMOS transistor N4 is electrically connected to the external storage node I4, the source of NMOS transistor N4 is electrically connected to the second bit line BLB, and the gate of NMOS transistor N4 is electrically connected to the first word line WL; that is to say, NMOS transistor N3, NMOS transistor N4, PMOS transistor P7, and PMOS transistor P8 are transfer transistors.

[0036] Furthermore, in the 12T radiation-hardened SRAM memory cell based on the polarity strengthening technology provided in Embodiment 1 of the present invention, the gate lengths of all NMOS transistors and all PMOS transistors are 65 nm. The gate widths of PMOS transistors P1 and P4 are 420 nm, the gate widths of PMOS transistors P2 and P3 are 280 nm, the gate widths of PMOS transistors P5 and P6 are 85 nm, the gate widths of PMOS transistors P7 and P8 are 140 nm, the gate widths of NMOS transistors N1 and N2 are 280 nm, and the gate widths of NMOS transistors N3 and N4 are 140 nm. Using NMOS transistors and PMOS transistors with these dimensions can increase the anti-interference performance of the 12T radiation-hardened SRAM memory cell based on the polarity strengthening technology in Embodiment 1 of the present invention. If the dimensions of these transistors are changed, it may cause the function of the designed circuit to change and fail to achieve the anti-single-event upset ability.

[0037] Furthermore, the principle of the 12T radiation-hardened SRAM memory cell based on the polarity strengthening technology provided in Embodiment 1 of the present invention is as follows:

[0038] (1) In the holding stage, the first bit line BL and the second bit line BLB are both precharged to a high level, the first word line WL is at a low level, the second word line WWL is at a high level, the circuit maintains the initial state internally, and the circuit does not work.

[0039] (2) In the data reading stage, the first bit line BL and the second bit line BLB are both precharged to a high level, the first word line WL is at a high level, the second word line WWL is at a high level, NMOS transistors N3 and N4 are turned on, and PMOS transistors P7 and P8 are turned off; if the data stored in the cell circuit is '0', that is, "I1 = I3 = 0, I2 = I4 = 1", then the first bit line BL discharges to the ground through NMOS transistors N3 and N1, causing a voltage difference in the bit line, and then the data is read through a sense amplifier; if the data stored in the cell circuit is '1', that is, "I1 = I3 = 1, I2 = I4 = 0", then the second bit line BLB discharges to the ground through NMOS transistors N4 and N2, causing a voltage difference in the bit line, and then the data is read through a sense amplifier.

[0040] (3) In the data writing stage, the first word line WL is at a high level, and the second word line WWL is at a low level. If the first bit line BL is at a high level and the second bit line BLB is at a low level, then a '1' is written to the external storage node I1 and the internal storage node I3 respectively through the NMOS transistor N3 and the PMOS transistor P8; if the first bit line BL is at a low level and the second bit line BLB is at a high level, then a '0' is written to the external storage node I1 and the internal storage node I3 respectively through the NMOS transistor N3 and the PMOS transistor P8. During the writing process, since data is written to the storage nodes I1\I4 and I3\I2 simultaneously through the NMOS transistor N3, the NMOS transistor N4, the PMOS transistor P7, and the PMOS transistor P8, the storage nodes are more easily written with data, thus greatly improving the writing speed. At the same time, due to the greatly improved writing speed, the power consumption of the circuit is reduced.

[0041] Compared with the prior art, in the 12T radiation-hardened SRAM memory cell based on the polarity reinforcement technology provided in Embodiment 1 of the present invention, when only considering the improvement of the radiation resistance performance by the circuit structure, if the storage nodes of the circuit are bombarded by particles, since the internal storage node I2 and the internal storage node I3 of the circuit are both surrounded by PMOS transistors, according to the principle of polarity reinforcement, when the spatial particles bombard the sensitive node PMOS transistor, only a voltage pulse of '0-1' is generated at the node, and this pulse cannot affect the states of other transistors due to the existence of the gate capacitance. This enables the internal node I2 and the internal storage node I3 to effectively avoid flipping. At the same time, the stability of the node data of the internal storage node I2 and the internal storage node I3 ensures that the external storage node I1 and the external storage node I4 can be restored to the initial state after flipping, thereby greatly improving the SEU resistance ability of the circuit; if other non-critical nodes are bombarded by particles, then the memory cell is less likely to be affected; therefore, Embodiment 1 of the present invention can improve the single-event upset resistance ability of the SRAM memory cell, and can greatly improve the writing speed of the SRAM memory cell while sacrificing a smaller cell area, and reduce the power consumption of the SRAM memory cell.

[0042] The following is a performance comparison and analysis of the Quatro 10T circuit in the prior art as shown in Figure 1 , the 6T circuit in the prior art as shown in Figure 2 , the SEA14T circuit in the prior art as shown in Figure 3 , the QCCM12T circuit in the prior art as shown in Figure 4 , the SRRD12T circuit in the prior art as shown in Figure 5 and the 12T radiation-hardened SRAM memory cell based on the polarity reinforcement technology provided in Embodiment 1 of the present invention as shown in Figure 6 :

[0043] (1) The 12T radiation-resistant SRAM memory cell based on the polarity reinforcement technology provided in Example 1 of the present invention is simulated (the simulation conditions are: Corner: TT; Temperature: 25°C; VDD: 1.2V), and the following can be obtained: Figure 7 The timing waveform is shown in Figure 2. Figure 7 It can be seen that the 12T radiation-resistant SRAM memory cell based on the polarity hardening technology provided in Example 1 of the present invention can implement normal storage node operations of writing '1', reading '1', writing '0' and reading '0'.

[0044] (2) The 12T radiation-resistant SRAM storage cell based on the polarity reinforcement technology provided in Example 1 of the present invention is simulated (the simulation condition is: VDD: 1.2V), and the following can be obtained: Figure 8 The transient waveform simulation diagram of the 12T radiation-resistant SRAM memory cell based on polarity reinforcement technology provided by the embodiment 1 of the present invention is shown at different times and different nodes when subjected to double exponential current source pulse injection. Figure 8 It can be seen that the 12T radiation-resistant SRAM memory cell based on polarity reinforcement technology provided in Example 1 of the present invention can achieve all single-node upset recovery and has good single-node and multi-node upset immunity characteristics.

[0045] (3) For example Figure 1 The prior art Quatro 10T circuit shown in FIG. Figure 2 The 6T circuit in the prior art shown in FIG. Figure 3 The SEA14T circuit in the prior art shown in FIG. Figure 4 The prior art QCCM12T circuit shown in FIG. Figure 5 The SRRD12T circuit in the prior art shown is similar to the Figure 6 The 12T radiation-resistant SRAM memory cell based on the polarity reinforcement technology provided in Example 1 of the present invention is simulated and compared (the simulation condition is: VDD: 1.2V), and the following can be obtained: Figure 9 The EQM (circuit performance metric) value comparison chart shown in Figure 1 is shown in Figure 2. Figure 9 It can be seen that the circuit performance of Example 1 of the present invention is better.

[0046] (4) For example Figure 1 The prior art Quatro 10T circuit shown in FIG. Figure 2 The 6T circuit in the prior art shown in FIG. Figure 3 The SEA14T circuit in the prior art shown in FIG. Figure 4 The prior art QCCM12T circuit shown in FIG. Figure 5 The SRRD12T circuit in the prior art shown is similar to theFigure 6 The 12T radiation-hardened SRAM memory cell based on the polarity strengthening technology provided in Embodiment 1 of the present invention shown in the figure is subjected to simulation comparison (simulation conditions: Corner: TT; Temperature: 27°C; VDD: 1.2V), and the following can be obtained Figure 10 The comparison diagrams of HSNM (holding noise margin), RSNM (read noise margin), and WSNM (write noise margin) shown in the figure. From Figure 10 It can be seen that: the anti-interference capabilities of maintaining data, reading data, and writing data in Embodiment 1 of the present invention are relatively good.

[0047] (5) For the Quatro 10T circuit in the prior art as shown in Figure 1 the figure, the 6T circuit in the prior art as shown in Figure 2 the figure, the SEA14T circuit in the prior art as shown in Figure 3 the figure, the QCCM12T circuit in the prior art as shown in Figure 4 the figure, the SRRD12T circuit in the prior art as shown in Figure 5 the figure, and the 12T radiation-hardened SRAM memory cell based on the polarity strengthening technology provided in Embodiment 1 of the present invention as shown in Figure 6 the figure, a circuit area comparison, a read / write time and power consumption simulation comparison are carried out (simulation conditions: Corner: TT; Temperature: 25°C; VDD: 1.2V), and the circuit area, read / write time, and power consumption simulation comparison table shown in Table 1 below can be obtained

[0048] Table 1

[0049] SRAM memory cell circuit Circuit area (μm) Read operation time (ps) Write operation time (ps) Power consumption (μW) SRRD12T 8.82 90.00 38.80 57.59 6T 4.56 41.19 103.08 59.90 Quatro 10T 7.09 60.73 389.40 62.75 QCCM12T 8.36 21.27 57.60 97.20 SEA14T 9.05 48.00 100.42 58.44 Embodiment 1 of the present invention 8.76 46.20 39.22 57.35

[0050] It can be seen from Table 1 that: compared with the five SRAM memory cell circuits in the prior art, the 12T radiation-hardened SRAM memory cell based on the polarity strengthening technology provided in Embodiment 1 of the present invention has the lowest power consumption, and the write operation speed of Embodiment 1 of the present invention is equivalent to that of the SRRD12T circuit in the prior art, far better than the other several existing SRAM memory cell circuits. At the same time, the read operation speed of Embodiment 1 of the present invention is far better than that of the SRRD12T circuit in the prior art. Therefore, Embodiment 1 of the present invention can greatly improve the read / write speed of the SRAM memory cell while sacrificing a smaller cell area, and can reduce the power consumption of the SRAM memory cell.

[0051] (6) For the Quatro 10T circuit in the prior art as shown in Figure 1 the figure, the 6T circuit in the prior art as shown in Figure 2 the figure, the SEA14T circuit in the prior art as shown in Figure 3 the figure, the QCCM12T circuit in the prior art as shown in Figure 4The QCCM12T circuit in the prior art shown, such as Figure 5 The SRRD12T circuit in the prior art shown and the 12T radiation-hardened SRAM memory cell based on the polarity strengthening technology provided in Embodiment 1 of the present invention shown in Figure 6 are subjected to a critical charge comparison simulation (simulation conditions: Corner: TT; Temperature: 27°C; VDD: 1.2V), and thus the critical charge comparison table shown in Table 2 below can be obtained:

[0052] Table 2

[0053]

[0054] It can be seen from Table 2 that: compared with the SRAM memory cell circuit in the prior art, the critical charge of Embodiment 1 of the present invention is relatively high, indicating that the single-event upset resistance of Embodiment 1 of the present invention is relatively strong.

[0055] In summary, the embodiments of the present invention can not only improve the single-event upset resistance of SRAM memory cells, but also greatly improve the write speed of SRAM memory cells while sacrificing a relatively small cell area, and reduce the power consumption of SRAM memory cells.

[0056] The above is only the preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims. The information disclosed in the background art part of this article is only intended to deepen the understanding of the overall background art of the present invention, and should not be regarded as an admission or any form of implication that this information constitutes the prior art known to those skilled in the art.

Claims

1. A 12T radiation-hardened SRAM memory cell based on polarity strengthening technology, characterized in that, It includes 4 NMOS transistors and 8 PMOS transistors. These 4 NMOS transistors are respectively defined as N1, N2, N3, and N4; these 8 PMOS transistors are respectively defined as P1, P2, P3, P4, P5, P6, P7, and P8. The internal storage nodes I2 and I3 are cross-coupled by the PMOS transistors P2 and P3, and the external storage nodes I1 and I4 are cross-coupled by the NMOS transistors N1 and N2; the PMOS transistors P1 and P4 serve as pull-up transistors, and the NMOS transistors N1 and N2 serve as pull-down transistors; the PMOS transistors P1 and P4 reinforce the internal storage nodes I2 and I3. The internal storage nodes I2 and I3 are surrounded by the PMOS transistors P1 - P8, which constitutes a polarity reinforcement structure; the internal storage node I2 is connected to the second bit line BLB through the PMOS transistor P7, the internal storage node I3 is connected to the first bit line BL through the PMOS transistor P8, the external storage node I1 is connected to the first bit line BL through the NMOS transistor N3, the external storage node I4 is connected to the second bit line BLB through the NMOS transistor N4. The NMOS transistors N3 and N4 are controlled by the first word line WL, and the PMOS transistors P7 and P8 are controlled by the second word line WWL. Among them, the drain of the PMOS transistor P2 is electrically connected to the gate of the PMOS transistor P3 and the source of the PMOS transistor P5 at the internal storage node I2. The drain of the PMOS transistor P5 is grounded. The drain of the PMOS transistor P3 is electrically connected to the gate of the PMOS transistor P2 and the source of the PMOS transistor P6 at the internal storage node I3. The drain of the PMOS transistor P6 is grounded; the drain of the NMOS transistor N1 is electrically connected to the gate of the NMOS transistor N2 and the gate of the PMOS transistor P6 at the external storage node I1. The source of the NMOS transistor N1 is grounded. The drain of the NMOS transistor N2 is electrically connected to the gate of the NMOS transistor N1 and the gate of the PMOS transistor P5 at the external storage node I4. The source of the NMOS transistor N2 is grounded; the source of the PMOS transistor P1 is connected to the voltage VDD. The gate of the PMOS transistor P1 is electrically connected to the internal storage node I2. The drain of the PMOS transistor P1 is electrically connected to the external storage node I1 and the source of the PMOS transistor P3; the source of the PMOS transistor P4 is connected to the voltage VDD. The gate of the PMOS transistor P4 is electrically connected to the internal storage node I3. The drain of the PMOS transistor P4 is electrically connected to the external storage node I4 and the source of the PMOS transistor P2. The drain of PMOS transistor P7 is electrically connected to the internal storage node I2, the source of PMOS transistor P7 is electrically connected to the second bit line BLB, and the gate of PMOS transistor P7 is electrically connected to the second word line WWL; the drain of PMOS transistor P8 is electrically connected to the internal storage node I3, the source of PMOS transistor P8 is electrically connected to the first bit line BL, and the gate of PMOS transistor P8 is electrically connected to the second word line WWL; The drain of NMOS transistor N3 is electrically connected to the external storage node I1, the source of NMOS transistor N3 is electrically connected to the first bit line BL, and the gate of NMOS transistor N3 is electrically connected to the first word line WL; the drain of NMOS transistor N4 is electrically connected to the external storage node I4, the source of NMOS transistor N4 is electrically connected to the second bit line BLB, and the gate of NMOS transistor N4 is electrically connected to the first word line WL.

2. The 12T radiation-hardened SRAM memory cell based on the polarity strengthening technology according to claim 1, wherein The gate length of all NMOS transistors and all PMOS transistors is 65 nm; the gate width of PMOS transistors P1 and P4 is 420 nm, the gate width of PMOS transistors P2 and P3 is 280 nm, the gate width of PMOS transistors P5 and P6 is 85 nm, the gate width of PMOS transistors P7 and P8 is 140 nm, the gate width of NMOS transistors N1 and N2 is 280 nm, and the gate width of NMOS transistors N3 and N4 is 140 nm.

Images