Hybrid port memory and method of operation thereof

Abstract

A hybrid port memory and its operating method are disclosed. The memory includes: a memory array comprising multiple rows and columns of memory cells; a hybrid port comprising multiple second address input pins; a rising edge of a clock signal received by the hybrid port latches a first address signal input on a first address input pin into the hybrid port memory and initiates a write operation to a first memory cell in the memory array; a rising edge of an external clock signal further latches a second address signal input on a second address input pin into the hybrid port memory and initiates a read operation to a second memory cell in the memory array; the second memory cell is in the same row but different column from the first memory cell. This solution can save memory layout area, power consumption, and leakage current loss, and can improve read speed.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuits, and more particularly to a hybrid port memory and its operating method. Background Technology

[0002] Single-port static random access memory (SP-SRAM) is a static random access memory with only one access port. Because it has only one port, SP-SRAM can only provide one memory access operation at a time.

[0003] Dual-port static random access memory (DP-SRAM) offers more bandwidth than single-port static random access memory (SP-SRAM) because DP-SRAM typically comprises two ports operated by a memory array that can be accessed simultaneously from both ports. Due to this increased bandwidth, the demand for DP-SRAM is increasing relative to the demand for single-port static random access memory.

[0004] However, the performance of existing dual-port static random access memory still needs to be improved. Summary of the Invention

[0005] The problem solved by this invention is to provide a hybrid port memory that can perform write and read operations simultaneously in each access cycle of an external clock signal, while saving memory layout area, power and leakage current loss, and improving read speed.

[0006] To address the above problems, the present invention provides a hybrid port memory, comprising:

[0007] A storage array comprises multiple rows and columns of storage cells; storage cells in the same row are coupled to the same word line, and storage cells in the same column are coupled to the same bit line pair.

[0008] The mixed port includes a clock signal input pin, multiple first address input pins, and multiple second address input pins; wherein:

[0009] The first address input pin is adapted to receive a first address signal;

[0010] The second address input pin is adapted to receive a second address signal;

[0011] The clock signal input pin is adapted to receive a preset external clock signal; wherein, the rising edge of the external clock signal causes the first address signal input on the first address input pin to be latched into the hybrid port memory and initiates a write operation of the first memory cell in the memory array; the rising edge of the external clock signal also causes the second address signal input on the second address input pin to be latched into the hybrid port memory and initiates a read operation of the second memory cell in the memory array; the second memory cell is in the same row but different column from the first memory cell.

[0012] Optionally, the first address signal is information about the row address and column address of the first storage unit, and the second address signal is information about the column address of the second storage unit.

[0013] Optionally, the hybrid port memory further includes;

[0014] A timing control circuit is adapted to generate a write clock signal for the write operation and a read clock signal for the read operation based on an external clock signal.

[0015] The word line decoding and word line driving circuit is adapted to decode the first address signal to obtain the corresponding row address signal and drive the word line of the corresponding row of the memory array;

[0016] The bit-line decoding circuit is adapted to perform column address decoding on the first address and the second address respectively, generate corresponding first column address decoding signals and second column address decoding signals, and send them to the input / output circuit.

[0017] The input / output circuit is adapted to drive the write data received from the peripheral device to the first storage cell corresponding to the first column address decoding signal under the control of the write clock signal and the read clock signal; and to read the stored data in the second storage cell corresponding to the second column address decoding signal and send it to the peripheral device.

[0018] Optionally, the first column address decoding signal is a write selection signal, and the second column address decoding signal is a read selection signal.

[0019] Optionally, the input / output circuit includes a write data latch, a plurality of write multiplexers and read multiplexers arranged corresponding to the columns of the storage array, a write driver, a detection amplifier, and an output data latch;

[0020] The write data latch is adapted to latch write data received from a peripheral device;

[0021] The write multiplexer is adapted to couple the write bit line pairs of the corresponding column to the write driver when the write select signal is received.

[0022] The write driver is adapted to drive the write data received from the write data latch to the bit line pair of the first memory cell corresponding to the write address, so as to write to the first memory cell.

[0023] The read multiplexer is adapted to couple the bit line pairs of the corresponding column of the storage array to the detection amplifier when the read selection signal is received;

[0024] The detection amplifier is adapted to read the data stored in the second memory cell corresponding to the second address by reading the bit line pairs coupled to the corresponding column of the memory array;

[0025] The output data latch is adapted to latch the read data sent by the detection amplifier and output it to the peripheral device.

[0026] Optionally, the rising edge of the write clock signal arrives before the rising edge of the read clock signal, and the falling edge of the write clock signal arrives later than the falling edge of the read clock signal.

[0027] The bit line decoding circuit is adapted to perform column address decoding on the second address and generate the read selection signal after performing column address decoding on the first address and generating the write selection signal.

[0028] Optionally, the hybrid port further includes: a read enable pin, adapted to receive a second address enable signal, so that the bit line decoding circuit decodes the second address and generates a corresponding read select signal.

[0029] Optionally, the hybrid port further includes: a detection amplifier enable pin, adapted to receive a detection amplifier enable signal, so that the detection amplifier reads the data stored in the second memory cell corresponding to the second address.

[0030] Optionally, the detection amplifier enable pin and the read enable pin are the same signal pin, and the detection amplifier enable signal is the same as the second address enable signal.

[0031] Optionally, the hybrid port further includes a clock signal enable pin adapted to receive a clock enable signal to enable the external clock signal.

[0032] Optionally, the hybrid port further includes: the write enable pin, adapted to receive a write enable signal to enable the first address signal.

[0033] Optionally, the number of the second address pins is (N-1); N represents the number of columns of the memory array and is an integer greater than or equal to 2.

[0034] Optionally, the storage unit is a 6T static random access memory (SRAM) unit.

[0035] Accordingly, embodiments of the present invention also provide a method for operating a hybrid port memory, the method comprising:

[0036] Receive the first address signal and the second address signal;

[0037] A write operation is performed on the first memory cell corresponding to the first address signal;

[0038] When the first storage unit performs a write operation, a read operation is performed on the second storage unit corresponding to the second address signal; the first storage unit and the second storage unit are in the same row but different columns.

[0039] Optionally, the first address signal includes information about the row address and column address of the first storage unit; the second address signal includes information about the column address of the second storage unit.

[0040] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0041] The hybrid port memory provided in this embodiment of the invention receives a first address signal for row and column addressing of a first memory cell in the memory array through a first address input pin in the hybrid port, and receives a second address signal for column addressing of a second memory cell in the same row as the first memory cell through a second address input pin. This allows for simultaneous writing to the first memory cell and reading from the second memory cell within the access cycle of an external clock signal. Compared with a dual-port static random access memory, this saves layout area, power, and leakage current loss, and improves read speed. Attached Figure Description

[0042] Figure 1 A schematic diagram of a dual-port static random access memory is shown.

[0043] Figure 2 A schematic diagram of the circuit structure of a memory cell in a dual-port static random access memory is shown.

[0044] Figure 3 A schematic diagram of a hybrid port memory according to an embodiment of the present invention is shown;

[0045] Figure 4 A schematic diagram of the circuit structure of a storage cell in a hybrid port memory according to an embodiment of the present invention is shown;

[0046] Figure 5The diagram illustrates the pulse timing of the external clock signal, write clock signal, and read clock signal of a hybrid port memory according to an embodiment of the present invention.

[0047] Figure 6 This diagram illustrates a performance comparison of the hybrid port memory with a single-port random access memory and a dual-port random access memory in an embodiment of the present invention.

[0048] Figure 7 A flowchart illustrating the operation method of a hybrid port memory according to an embodiment of the present invention is shown. Detailed Implementation

[0049] As can be seen from the background technology, a dual-port static random access memory has two ports. The same memory cell in the memory array can be read by two different ports at the same time, and two different memory cells in the same row of the memory array can be written with different data at the same time.

[0050] Figure 1 The structure of a dual-port static random access memory is shown. See also Figure 1 The dual-port static random access memory shown includes a memory array 110, a timing control circuit 120, a word line decoding and word line driving circuit 130, a bit line decoding circuit 140, and an input / output circuit 150. The memory array 110 is coupled to both the word line decoding and word line driving circuit 130 and the input / output circuit 140. The word line decoding and word line driving circuit 130 is also coupled to the timing control circuit 120, and the timing control circuit 120 is further coupled to the input / output circuit 140 via the bit line decoding circuit.

[0051] The storage array 110 includes storage cells of an M-row * N-column array, M write word lines WWL0~WWLm (m=(M-1)), N sets of write bit line pairs (WBL0, WBLB0)~(WBLm, WBLBm), M read word lines RWL0~RWLm, and N read bit lines RBL0~RBLn (n=(N-1)). Storage cells in the same row are coupled to the same write word line WWLi (i is an integer greater than or equal to 0 and less than or equal to m) and the same read bit line RWLi, respectively. Storage cells in the same column are coupled to the same write bit line pairs WBLj, WBLBj (j is a positive integer greater than or equal to 0 and less than or equal to n) and the same read bit line RBLj. Each storage cell stores one bit of data. Here, M represents the number of rows in the storage array and is an integer greater than or equal to 2, and N represents the number of columns in the storage array and is an integer greater than or equal to 2.

[0052] The storage array 110 is coupled to the word line decoding and word line driving circuit 120 through M write word lines WWL0~WWLm and M read word lines RWL0~RWLm, respectively, and is coupled to the input / output circuit 140 through N write bit line pairs (WBL0, WBLB0)~(WBLm, WBLBm) and N write bit lines RBL0~RBLn, respectively.

[0053] Figure 2 The structure of a memory cell in a dual-port static random access memory is shown. See also Figure 2 A memory cell includes: a first inverter (not shown) and a second inverter (not shown), a first access NMOS transistor NM3 and a second access NMOS transistor NM4, a third access NMOS transistor NM4 and a fourth access NMOS transistor NM5.

[0054] The first inverter and the second inverter constitute a latch. The latch has a first latch node Q and a second latch node QB, and the data on the first latch node Q and the second latch node QB are opposite.

[0055] The first inverter includes a first PMOS transistor PM1 and a first NMOS transistor NM1; the second inverter includes a second PMOS transistor PM2 and a second NMOS transistor NM2.

[0056] The gate of the first PMOS transistor PM1 is coupled to the gate of the first NMOS transistor NM1 and the second latch node QB of the latch. The source of the first PMOS transistor PM1 is coupled to the power supply voltage VDD. The drain of the first PMOS transistor PM1 is coupled to the drain of the first NMOS transistor NM1 and serves as the first latch node Q of the latch. The source of the first NMOS transistor NM1 is coupled to the ground voltage VSS.

[0057] The gate of the second PMOS transistor PM2 is coupled to the gate of the second NMOS transistor NM2 and the first latch node Q of the latch. The source of the second PMOS transistor PM2 is coupled to the power supply voltage VDD. The drain of the second PMOS transistor PM1 is coupled to the drain of the second NMOS transistor NM1 and serves as the second latch node QB of the latch. The source of the second NMOS transistor NM1 is coupled to the ground voltage VSS.

[0058] The gate terminals of the first access NMOS transistor NM3 and the second access NMOS transistor NM4 are both coupled to the write word line WWL. The source terminal of the first access NMOS transistor NM3 is coupled to the first latch node Q, and the drain terminal of the first access NMOS transistor NM3 is coupled to the corresponding first write bit line WBL. The source terminal of the second access NMOS transistor NM4 is coupled to the second latch node QB, and the drain terminal of the second access NMOS transistor NM4 is coupled to the corresponding second write bit line WBLB.

[0059] The gate of the third access NMOS transistor NM5 is coupled to the read word line RWL, the source of the third access NMOS transistor NM5 is coupled to the read bit line RBL, and the drain of the third access NMOS transistor NM5 is coupled to the source of the fourth access NMOS transistor NM6. The gate of the fourth access NMOS transistor NM6 is coupled to the second latch node QB of the latch, and the source of the fourth access NMOS transistor NM6 is coupled to the ground voltage VSS.

[0060] Please see Figure 1 and Figure 2 When a write operation is performed, the timing control circuit 120 provides word line decoding and word line driving circuit 130 and bit line decoding circuit 140 with the write address received from the peripheral device (not shown) to perform row address decoding and column address decoding respectively.

[0061] The write row address decoding result of the word line decoding and word line driving circuit 130 will drive one of the M write word lines WWL0 to WWLm in the memory array, thereby turning on the first access NMOS transistor NM3 and the second access NMOS transistor NM4 of the memory cell in the corresponding row.

[0062] The write column address decoding result from the bit line decoding circuit 140 will cause the corresponding write multiplexer in the input / output circuit 140 to couple the write driver to one of the N write bit line pairs (WBL0, WBLB0) to (WBLm, WBLBm) of the memory array.

[0063] Therefore, when the rising edge of the write enable signal WEN arrives, the write driver drives the write data sent by the peripheral device through the write data latch to one of the N write bit line pairs (WBL0, WBLB0) to (WBLm, WBLBm) of the memory array, and writes it to the target memory cell in the memory array through the first access NMOS transistor NM3 and the second access NMOS transistor NM4 coupled to the driven write word line WWL.

[0064] When a read operation is performed, the timing control circuit 120 provides the read address received from the peripheral device (not shown) to the word line decoding and word line driving circuit 130 and the bit line decoding circuit 140 for row address decoding and column address decoding, respectively.

[0065] The read row address decoding result from the word line decoding and word line driving circuit 130 will drive one of the M read word lines RWL0 to RWLm in the memory array. The read column address decoding result from the bit line decoding circuit 140 will cause the corresponding read multiplexer in the input / output circuit 140 to couple the bit line detection unit to one of the N read bit lines RBL0 to RBLn of the memory array.

[0066] Therefore, when the rising edge of the read enable signal REN arrives, the bit line detection unit (not shown) in the input / output circuit 140 will read the stored data in the target storage cell of the storage array 110 from one of the N read bit lines RBL0 to RBLn and send it to the output data latch for latching and output to the peripheral device.

[0067] As mentioned earlier, a dual-port static random access memory (SRAM) can perform read and write operations simultaneously within one access cycle of an external clock signal. Therefore, within the same access cycle, the dual-port SRAM needs to simultaneously receive write and read addresses from the peripheral device, and almost simultaneously perform row address decoding and column address decoding on the write and read addresses. It writes the data from the peripheral device to the memory array and reads the corresponding data from the memory array. Consequently, it requires two sets of logic operations, including write and read operation logic, for control. Compared to a single-port SRAM, which only needs to execute one of the write or read operation logics within one access cycle of an external clock signal, this results in greater power consumption and leakage current loss.

[0068] Furthermore, dual-port static random access memory uses, for example... Figure 2 The memory cell shown, containing 8 transistors (8T), requires a larger footprint compared to the 6 transistors (6T) memory cell used in a single-port static random access memory.

[0069] Furthermore, when performing a read operation, a single-port static random access memory reads data through bit line pairs in a 6T memory cell, while a dual-port static random access memory reads the stored data in the memory cell through only a single read bit line, resulting in a slower read speed.

[0070] Therefore, although dual-port static random access memory has advantages in bandwidth, it also has problems such as large layout area, high power and leakage current loss, and slow read speed.

[0071] To address the aforementioned issues, the hybrid port memory in this embodiment of the invention receives a first address signal for row and column addressing of a first memory cell in the memory array via a first address input pin in the hybrid port, and receives a second address signal for column addressing of a second memory cell in the same row as the first memory cell via a second address input pin. This allows for simultaneous writing to the first memory cell and reading from the second memory cell within the access cycle of an external clock signal. Compared to a dual-port static random access memory, this saves on layout area, power consumption, and leakage current loss, and also improves read speed.

[0072] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0073] Figure 3 The structure of a hybrid port memory according to an embodiment of the present invention is shown. See also... Figure 3 A hybrid port memory includes a storage array 310 and a hybrid port 320.

[0074] The storage array 310 includes M*N storage cells 311, word lines WL0 to WLm that correspond one-to-one with the rows of the storage cells, and bit line pairs (BL0 / BLB0) to (BLn / BLBn).

[0075] In the storage array 310, storage cells 311 in the same row are coupled to the same read word line WLi, and storage cells 311j in the same column are coupled to the same bit line pairs (BLj, BLBj). Specifically, the storage cells 311 in the first row are coupled to the first word line WL0, the storage cells 311 in the second row are coupled to the second word line WL1, ... the storage cells in the Mth row are coupled to the Mth word line WLm; the storage cells 311 in the first column are coupled to the first bit line pairs BL0 and BLB0, the storage cells in the second column are coupled to the second bit line pairs BL1 and BLB1, ... the storage cells in the Nth column are coupled to the Nth bit line pairs WBLn and WBLBn.

[0076] The hybrid port 320 includes a clock signal input pin (not shown), multiple first address input pins (not shown), and multiple second address input pins (not shown), wherein:

[0077] The first address input pin is adapted to receive a first address signal A_wr[0; k-1]; the first signal A_wr[0; k-1] is a write address signal used for row address and column address addressing of the first memory cell in the memory array;

[0078] The second address input pin is adapted to receive the second address signal A_rd[0; N-2]; the second signal is a read address signal used to perform column address addressing of the second memory cell in the memory array that is in the same row but different column as the first memory cell; N represents the number of columns in the memory array; wherein, the number of the second address pins is (N-1).

[0079] The clock signal input pin is adapted to receive a preset external clock signal CLK; wherein, the rising edge of the external clock signal CLK causes the first address signal A_wr[0; k-1] input on the first address input pin to be latched into the hybrid port memory and initiates a write operation of the first memory cell in the memory array; the rising edge of the external clock signal CLK also causes the second address signal A_rd[0; N-2] input on the second address input pin to be latched into the hybrid port memory and initiates a read operation of the second memory cell in the memory array.

[0080] In specific implementations, the hybrid port may further include a clock signal enable pin, a write enable pin, a read enable pin, and a detection amplification enable pin. Wherein:

[0081] The clock signal enable pin can receive a clock enable signal CEN to enable the external clock signal;

[0082] The write enable pin can receive a write enable signal WEN to enable the first address signal;

[0083] The read enable pin can receive a read enable signal REN to enable the second address signal;

[0084] The detection amplifier enable pin can receive a detection amplifier enable signal SAE to enable the detection amplifier.

[0085] In one embodiment of the present invention, the read enable pin and the detection amplifier enable pin are the same pin, that is, the same enable signal is used to enable the column address decoder to read the column address decoding of the second address signal and enable the detection amplifier.

[0086] See Figure 4 The storage cell 310 in the storage array in this embodiment of the invention may include: a first inverter (not shown) and a second inverter (not shown), a first access NMOS transistor NM3 and a second access NMOS transistor NM4.

[0087] The first inverter and the second inverter constitute a latch (not shown). The latch has a first latch node Q and a second latch node QB, and the data on the first latch node Q and the second latch node QB are opposite.

[0088] The first inverter includes a first PMOS transistor PM1 and a first NMOS transistor NM1; the second inverter includes a second PMOS transistor PM2 and a second NMOS transistor NM2.

[0089] The gate of the first PMOS transistor PM1 is coupled to the gate of the first NMOS transistor NM1 and the second latch node QB of the latch. The source of the first PMOS transistor PM1 is coupled to the power supply voltage VDD. The drain of the first PMOS transistor PM1 is coupled to the drain of the first NMOS transistor NM1 and serves as the first latch node Q of the latch. The source of the first NMOS transistor NM1 is coupled to the ground voltage VSS.

[0090] The gate of the second PMOS transistor PM2 is coupled to the gate of the second NMOS transistor NM2 and the first latch node Q of the latch. The source of the second PMOS transistor PM2 is coupled to the power supply voltage VDD and serves as the second latch node QB of the latch. The drain of the second PMOS transistor PM1 is coupled to the drain of the second NMOS transistor NM1. The source of the second NMOS transistor NM1 is coupled to the ground voltage VSS.

[0091] The gate terminals of the first access NMOS transistor NM3 and the second access NMOS transistor NM4 are both coupled to the word line WL. The source terminal of the first access NMOS transistor NM3 is coupled to the first latch node Q, and the drain terminal of the first access NMOS transistor NM3 is coupled to the corresponding first bit line BL. The source terminal of the second access NMOS transistor NM4 is coupled to the second latch node QB, and the drain terminal of the second access NMOS transistor NM4 is coupled to the corresponding second bit line BLB.

[0092] When a write operation is performed on the memory cell 310, the word line WL coupled to the first access NMOS transistor NM3 and the second access NMOS transistor NM4 is charged to the power supply voltage VDD. Both the first access NMOS transistor NM3 and the second access NMOS transistor NM4 are turned on. The write data sent by the peripheral device is transmitted to the first latch node Q and the second latch node QB of the memory cell through the bit line pairs BL and BLB of the column where the memory cell 310 is located, respectively, so that the write data is written into the corresponding memory cell 310 in the memory array.

[0093] When a read operation is performed on the memory cell 310, the word line WL coupled to the first access NMOS transistor NM3 and the second access NMOS transistor NM4 is charged to the power supply voltage VDD. Both the first access NMOS transistor NM3 and the second access NMOS transistor NM4 are turned on. The data on the first latch node Q and the second latch node QB are transmitted to the bit line pairs BL and BLB of the corresponding column of the memory array through the first access NMOS transistor NM3 and the second access NMOS transistor NM4, respectively. By reading the differential voltage signal on the bit line pairs BL and BLB of the corresponding column of the memory array, the stored data in the corresponding memory cell can be read out.

[0094] Please continue reading Figure 3In some embodiments, the hybrid port memory may further include a timing control circuit 330, a word line decoding and word line driving circuit 340, a bit line decoding circuit 350, and an input / output circuit 360. The timing control circuit 330 is respectively connected to the hybrid port 320, or the hybrid port 320 is disposed within the timing control circuit 330. The timing control circuit 330 is also coupled to the word line decoding, word line driving circuit 340, and bit line decoding circuit 350, respectively. The bit line decoding circuit 350 is also coupled to the input / output circuit 360.

[0095] The timing control circuit 330 can receive the external clock signal CLK sent by the hybrid port, and based on the external clock signal CLK, generate a write clock signal WR-CLK for performing the write operation on the first memory cell and a read clock signal RD-CLK for performing the read operation on the second memory cell in a different column than the first memory cell, so as to perform the write operation and the read operation within one access cycle of the external clock signal CLK.

[0096] As previously described, the hybrid port memory in this embodiment of the invention can simultaneously perform a write operation on the first memory cell and a read operation on the second memory cell within one access cycle of an external clock signal. Please refer to... Figure 5 Because the write operation is slower than the read operation, the rising edge of the write clock signal WR-CLK generated by the timing control circuit 330 arrives before the rising edge of the read clock signal RD-CLK, and the falling edge of the write clock signal WR-CLK arrives after the falling edge of the read clock signal RD-CLK. In other words, the period of the read clock signal RD-CLK is within the period of the write clock signal WR-CLK, and the read operation of the second memory cell is performed within the write operation period of the first memory cell.

[0097] When the write and read operations are performed within the access cycle of the external clock signal CLK, the rising edge of the write clock signal WR-CLK arrives first. The timing control circuit 330 first sends the first address signal received by the first address input pin of the mixing port 320 to the word line decoding and word line driving circuit 340 and the bit line decoding circuit 350 respectively to perform row address addressing and column address addressing of the first memory cell in the memory array. Then, the timing control circuit 330 sends the second address signal received by the second address input pin to the bit line decoding circuit 350 to perform column address addressing of the second memory cell.

[0098] Please continue reading Figure 3In one embodiment of the present invention, the word line decoding and word line driving circuit 340 may include a word line decoding unit 341 and a word line driving unit 342. When receiving a first address signal sent by the timing control circuit 330, the word line decoding unit 341 can perform row address decoding on the write address output by the timing control circuit to determine the row information of the first memory cell corresponding to the write address and send it to the word line driving unit 342. The word line driving unit 342 can receive the row address decoding result of the write address from the word line decoding unit 341, and charge the word line coupled to the corresponding row of the memory array to the power supply voltage VDD according to the row address decoding result.

[0099] The bitline decoding circuit 350 can first perform column address decoding on the first address signal output 320 of the timing control circuit, and send the corresponding column address decoding result to the input / output circuit 360. Then, the bitline decoding circuit 350 performs column address decoding on the second address signal output 320 of the timing control circuit, and sends the corresponding column address decoding result to the input / output circuit 360.

[0100] Please continue reading Figure 3 In this embodiment of the invention, the input / output circuit 360 includes an input data latch 361, a write driver 362, a write column multiplexer 363 corresponding to the column-to-column devices of the storage array, a read column multiplexer 364 corresponding to the column-to-column devices of the storage array, a detection amplifier 365, an output data latch 366, and a bit line precharge circuit 367.

[0101] When the write column address decoding result, i.e., the write selection signal, is received from the bit line decoding circuit 350, the write multiplexer 363 of the corresponding column couples the two output nodes of the write driver 363 to the bit line pairs BL and BLB of the corresponding column in the memory array indicated by the write selection signal, respectively. When write is enabled, when the word line WL of the corresponding row in the memory array is driven to the power supply voltage VDD by the word line decoding and word line driving circuit 340, the first access NMOS transistor NM3 and the second access NMOS transistor NM4 of the memory cell in the corresponding row in the memory array are both turned on. The write driver 362 transmits the write data sequentially through the bit line pairs BL and BLB of the corresponding column in the memory array and through the first access NMOS transistor NM3 and the second access NMOS transistor NM4 to the corresponding first memory cell in the memory array for storage.

[0102] The bit line precharge circuit 367 can precharge all bit line pairs of all memory cells in the memory array 310 to the power supply voltage VDD before performing a read operation, under the control of the precharge control signal output by the timing control circuit 330.

[0103] Subsequently, when read is enabled, the read column address decoding result sent by the bit line decoding circuit 350, i.e., the read selection signal, causes the read column multiplexer 364 of the corresponding column to couple the bit line pairs BL and BLB of the corresponding column in the memory array indicated by the read selection signal to the detection amplifier 365. When the word line WL of the corresponding row in the memory array is driven to the power supply voltage VDD by the word line decoding and word line driving circuit 340, the data on the first latch node Q and the second latch node QB in the corresponding second memory cell in the memory array is transmitted to the corresponding bit line pairs BL and BLB through the first access NMOS transistor NM3 and the second access NMOS transistor NM4. The detection amplifier 365 reads the stored data in the second memory cell by reading the differential voltage signal on the corresponding bit line pairs BL and BLB, and then sends the read stored data to the peripheral device through the output data buffer 366.

[0104] As can be seen from the above description, the hybrid port memory in the embodiments of the present invention only needs to add a second address signal for column addressing of the second memory cell in the same row but different column of the first memory cell corresponding to the write address to the single port of the single port random access memory. In this way, write operations and read operations can be performed simultaneously in each access cycle of the external clock signal.

[0105] See Figure 6 The hybrid port memory in this embodiment of the invention is comparable to a single-port random access memory in terms of layout area, performance, power consumption, and leakage current. In other words, compared with a dual-port random access memory, the hybrid port memory in this embodiment of the invention can save layout area, power consumption, and leakage current losses, and can improve memory performance.

[0106] Accordingly, embodiments of the present invention also provide a method for operating a hybrid port memory.

[0107] Figure 7 A flowchart illustrating the operation of a hybrid port memory according to an embodiment of the present invention is shown. Please refer to... Figure 7 The operating method of the hybrid port memory in this embodiment of the invention may specifically include the following steps:

[0108] Step 701: Receive a first address signal and a second address signal; the first address signal includes information about the row address and column address of the first storage unit; the second address signal includes information about the column address of the second storage unit;

[0109] Step 702: Perform a write operation on the first memory cell corresponding to the first address signal;

[0110] Step 703: When the first storage unit performs a write operation, a read operation is performed on the second storage unit corresponding to the second address signal; the first storage unit and the second storage unit are in the same row but different columns.

[0111] The operation method of the hybrid port memory in this embodiment of the invention can be found in the detailed description in the foregoing section, and will not be repeated here.

[0112] The embodiments of the present invention described above are combinations of elements and features of the present invention. Unless otherwise stated, the elements or features described are optional. Individual elements or features may be practiced without combination with other elements or features. Furthermore, embodiments of the present invention may be constructed by combining some elements and / or features. The order of operations described in the embodiments of the present invention may be rearranged. Some constructions of any embodiment may be included in another embodiment and may be replaced by corresponding constructions of another embodiment. It will be apparent to those skilled in the art that claims in the appended claims that are not expressly referenced to each other may be combined to form embodiments of the present invention, or may be included as new claims in amendments made after the filing of this application.

[0113] Embodiments of the present invention can be implemented by various means, such as hardware, firmware, software, or combinations thereof. In a hardware configuration, the method according to an exemplary embodiment of the present invention can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, etc.

[0114] In firmware or software configuration, embodiments of the present invention can be implemented in the form of modules, processes, functions, etc. Software code can be stored in a memory unit and executed by a processor. The memory unit is located inside or outside the processor and can send data to and receive data from the processor via various known means.

[0115] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is accorded the widest scope consistent with the principles and novel features disclosed herein.

[0116] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A hybrid ported memory, comprising: Comprising: a memory array comprising a plurality of rows and columns of memory cells; memory cells in the same row are coupled to the same word line, and memory cells in the same column are coupled to the same bit line pair; a hybrid port comprising a clock signal input pin, a plurality of first address input pins, and a plurality of second address input pins; wherein: the first address input pins are adapted to receive first address signals; the second address input pins are adapted to receive second address signals; the clock signal input pin is adapted to receive a preset external clock signal; wherein a rising edge of the external clock signal causes the first address signals input on the first address input pins to be latched to the hybrid port memory and initiates a write operation of a first memory cell in the memory array; and a rising edge of the external clock signal also causes the second address signals input on the second address input pins to be latched to the hybrid port memory and initiates a read operation of a second memory cell in the memory array; the second memory cell is in the same row but a different column as the first memory cell.

2. The hybrid port memory of claim 1, wherein, The first address signals comprise information of the row address and the column address of the first memory cell, and the second address signals comprise information of the column address of the second memory cell.

3. The hybrid port memory of claim 1, wherein, Further comprising: a timing control circuit adapted to receive the first address signals and the second address signals, and generate corresponding write clock signals and read clock signals based on the external clock signal to control the read operation and the write operation; a word line decoding and driving circuit adapted to decode the first address signals to obtain a corresponding row address signal, and drive the word line of the corresponding row of the memory array; a bit line decoding circuit adapted to decode the column addresses of the first address and the second address respectively, and generate corresponding first column address decoding signals and second column address decoding signals and send them to an input / output circuit; the input / output circuit is adapted to drive write data received from a peripheral device to the first memory cell corresponding to the first column address decoding signal under the control of the timing control circuit; read the stored data in the second memory cell corresponding to the second column address decoding signal and send it to the peripheral device.

4. The hybrid port memory of claim 3, wherein, The first column address decoding signal is a write selection signal, and the second column address decoding signal is a read selection signal.

5. The hybrid port memory of claim 4, wherein, The input / output circuit comprises a write data latch, a plurality of write multiplexers and a plurality of read multiplexers respectively arranged one-to-one corresponding to the columns of the memory array, a write driver, a sense amplifier, and an output data latch; The write data latch is adapted to latch the write data received from the peripheral device and send it to the write driver; The write multiplexer is adapted to couple the bit line pair of the corresponding column to the write driver when the write selection signal is received; The write driver is adapted to drive the write data received from the write data latch to the bit line pair of the first memory cell corresponding to the write address, so as to write the first memory cell; The read multiplexer is adapted to couple the bit line pair of the corresponding column of the memory array to the sense amplifier when the read selection signal is received; The detection amplifier is adapted to read data stored in a second memory cell corresponding to the second address by reading a bit line pair of a column of the memory array coupled to the detection amplifier; The output data latch is adapted to latch and output read data sent by the detection amplifier to the peripheral device.

6. The hybrid port memory of claim 4, wherein, The rising edge of the write clock signal arrives before the rising edge of the read clock signal, and the falling edge of the write clock signal arrives later than the falling edge of the read clock signal; The bit line decoding circuit is adapted to decode the second address and generate a corresponding read selection signal after decoding the first address and generating the write selection signal.

7. The hybrid port memory of any of claims 1-6, wherein, The mixed port further comprises a read enable pin adapted to receive a second address enable signal to enable the bit line decoding circuit to decode the second address and generate a corresponding read selection signal.

8. The hybrid port memory of claim 7, wherein, The mixed port further comprises a detection amplifier enable pin adapted to receive a detection amplifier enable signal to enable the detection amplifier.

9. The hybrid port memory of claim 8, wherein, The detection amplifier enable pin and the read enable pin are the same signal pin, and the detection amplifier enable signal and the second address enable signal are the same.

10. The hybrid port memory of claim 1, wherein, The mixed port further comprises a clock signal enable pin adapted to receive a clock enable signal to enable the external clock signal.

11. The hybrid port memory of claim 1, wherein, The mixed port further comprises the write enable pin adapted to receive a write enable signal to enable the first address signal.

12. The hybrid port memory of claim 1, wherein, The number of the second address pins is (N-1); N represents the number of columns of the memory array and is an integer greater than or equal to 2.

13. The hybrid port memory of claim 1, wherein, The memory cell is a 6T static random memory cell.

14. A method of operating a hybrid port memory according to any one of claims 1 to 13, characterized by, Comprising: receiving a first address signal and a second address signal; performing a write operation on a first memory cell corresponding to the first address signal; performing a read operation on a second memory cell corresponding to the second address signal while the first memory cell is performing the write operation; the first memory cell and the second memory cell are in the same row but different columns.

15. The method of claim 14, wherein, The first address signal includes information of the row address and the column address of the first memory cell; the second address signal includes information of the column address of the second memory cell. The first address signal includes information of the row address and the column address of the first memory cell; the second address signal includes information of the column address of the second memory cell.

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