A write assist device, a data write method thereof, and a memory

Abstract

The embodiment of the present application discloses a write auxiliary device, a data writing method thereof and a memory, relates to the technical field of computers, and can improve data writing effect.The device comprises an address comparison unit configured to compare a first access address and a second access address of a memory, wherein the first access address is accessed through a first port of the memory, and the second access address is accessed through a second port of the memory; and an auxiliary writing unit, which is connected with the address comparison unit at a first end, connected with the second port at a second end, and connected with the first port at a third end, and configured to, in response to a row address in the first access address being the same as a row address in the second access address and a column address in the first access address being different from a column address in the second access address, assist in writing first data into the second access address through the first port when the second access address is written with the first data through the second port.

Description

TECHNICAL FIELD

[0001] The present application relates to the computer technical field, and particularly relates to a write assist device and a data write-in method thereof and a memory. BACKGROUND

[0002] The memory is provided with an array of memory cells, each of which is used to store a binary digit 0 or 1, and each memory cell can be read or written through a read-write control line. If a memory has a set of read-write control lines, the memory is a single-port memory; if a memory has two sets of independent read-write control lines, the memory can be operated independently in parallel, and the memory is a dual-port memory. For example, a DP SRAM (Dual Port Static Random Access Memory) is a dual-port static random access memory.

[0003] Each memory cell of the DP SRAM can include two word lines, which are controlled by different ports respectively. Each word line corresponds to a row of memory cells in the memory array, and when a word line is selected, the row of memory cells is selected. At this time, if a bit line of a memory cell in the row is also selected, the memory cell can be read or written. In the row, the memory cells whose bit lines are not selected are in a half-selected state (i.e., a state in which the row is selected but the column is not selected). The memory cell in the half-selected state is in a pseudo-read state because the word line is selected but the bit line is not selected. When a write operation is performed on the memory cell in the pseudo-read state, the write operation is affected by the pseudo-read, resulting in additional current and charge-discharge nodes, and thus a long time is required for the write operation, or even the write operation fails. SUMMARY

[0004] Therefore, the present application provides a write assist device and a data write-in method thereof and a memory, which can effectively overcome the influence of the pseudo-read on the write operation of the dual-port memory, effectively reduce the data write-in time, and greatly improve the data write-in effect.

[0005] In a first aspect, an embodiment of the present application provides a write assist device, comprising: an address comparison unit configured to compare a first access address and a second access address of a memory, wherein the first access address is accessed through a first port of the memory, and the second access address is accessed through a second port of the memory; and an assist write unit having a first end connected to the address comparison unit, a second end connected to the second port, and a third end connected to the first port, and configured to, in response to a row address in the first access address being the same as a row address in the second access address and a column address in the first access address being different from a column address in the second access address: assist writing of first data into the second access address through the second port and writing of the first data into the second access address through the first port, and / or assist writing of second data into the first access address through the first port and writing of the second data into the first access address through the second port.

[0006] Optionally, each column of the memory corresponds to one of the assist write units; and the assist write unit corresponding to a column in which a memory cell of the second access address is located comprises a control module, a pull-down module, and a pull-up module; a first input end of the control module is connected to a positive input end of the first data, a second input end of the control module is connected to a logical NOT input end of the first data, and a third input end of the control module is connected to a same-row different-column enable signal, which is obtained by performing a preset logical operation on a comparison result of the address comparison unit and a write enable signal of the memory; an output end of the control module is connected to a control end of the pull-down module, and is configured to control whether the pull-down module discharges a positive signal bit line or a negative signal bit line corresponding to the second access address in the first port, wherein the positive signal bit line is configured to input or output a storage value of the memory cell of the second access address, and the negative signal bit line is configured to input or output a logical NOT value of the storage value; and an output end of the pull-down module is connected to a control end of the pull-up module, and is configured to control whether the pull-up module charges the positive signal bit line or the negative signal bit line corresponding to the second access address in the first port.

[0007] Optionally, the first control end of the pull-down module is connected with the first output end of the control module, the second control end is connected with the second output end of the control module, the first output end of the pull-down module is connected with the positive signal bit line corresponding to the second access address in the first port, the second output end is connected with the negative signal bit line corresponding to the second access address in the first port, and the first ground end and the second ground end of the pull-down module are grounded; the pull-down module is used for determining whether to discharge the positive signal bit line or the negative signal bit line according to the output signal of the control module; the first control end of the pull-up module is connected with the second output end of the pull-down module, the second control end of the pull-up module is connected with the first output end of the pull-down module, the first output end of the pull-up module is connected with the first output end of the pull-down module, the second output end of the pull-up module is connected with the second output end of the pull-down module, and the first power supply end and the second power supply end of the pull-up module are connected with the power supply; the pull-up module is used for determining whether to charge the positive signal bit line or the negative signal bit line according to the output signal of the pull-down module.

[0008] Optionally, the auxiliary writing unit further comprises a protection module, the input end of the protection module is connected with the output end of the pull-down module, and the output end of the protection module is connected with the positive signal bit line and the negative signal bit line corresponding to the second access address in the first port; the protection module is used for cutting off the connection between the output end of the pull-down module, the output end of the pull-up module and the positive signal bit line and the negative signal bit line when the output end of the pull-down module is at a preset level, and keeping the output end of the pull-down module, the output end of the pull-up module and the positive signal bit line and the negative signal bit line corresponding to the second access address in the first port in connection when the output end of the pull-down module is at a non-pre-set level.

[0009] Optionally, the control module comprises a first NAND gate and a second NAND gate, a first input terminal of the first NAND gate is connected with the first data, a first input terminal of the second NAND gate is connected with a logic negation value of the first data, and a second input terminal of the first NAND gate and a second input terminal of the second NAND gate are both connected with the same row different column enable signal; the pull-down module comprises a first transistor and a second transistor, the pull-up module comprises a third transistor and a fourth transistor; the protection module comprises a NOR gate, a fifth transistor and a sixth transistor; a first pole of the first transistor is connected with an output terminal of the first NAND gate, a first pole of the second transistor is connected with an output terminal of the second NAND gate, a second pole of the first transistor is connected with a second pole of the third transistor, a second pole of the second transistor is connected with a second pole of the fourth transistor, and a third pole of the first transistor and a third pole of the second transistor are both connected with the ground; a first pole of the third transistor is connected with the second pole of the second transistor, a first pole of the fourth transistor is connected with the second pole of the first transistor, a second pole of the third transistor is connected with the second pole of the first transistor, a first pole of the fourth transistor is connected with the second pole of the second transistor, and a third pole of the third transistor and a third pole of the fourth transistor are both connected with a power supply; a first pole of the fifth transistor and a first pole of the sixth transistor are both connected with an output terminal of the NOR gate, a second pole of the fifth transistor is connected with the second pole of the first transistor, a second pole of the sixth transistor is connected with the second pole of the second transistor, a third pole of the fifth transistor is connected with a positive signal bit line corresponding to the second access address in the first port, and a third pole of the sixth transistor is connected with a negative signal bit line corresponding to the second access address in the first port; a first input terminal of the NOR gate is connected with the second pole of the fifth transistor, and a second input terminal of the NOR gate is connected with the second pole of the sixth transistor.

[0010] Optionally, the preset logic operation is a logic and operation.

[0011] In a second aspect, the embodiments of the present application further provide a data write method of a write assist device, comprising: comparing a first access address and a second access address of a memory, wherein the first access address is accessed through a first port of the memory, and the second access address is accessed through a second port of the memory; in response to a row address in the first access address being the same as a row address in the second access address, and a column address in the first access address being different from a column address in the second access address, assisting the first port to write first data into the second access address through the second port; and / or, in response to the row address in the first access address being the same as the row address in the second access address, and the column address in the first access address being different from the column address in the second access address, assisting the second port to write second data into the first access address through the first port.

[0012] Optionally, the assisting the first port to write first data into the second access address through the second port in response to the row address in the first access address being the same as the row address in the second access address, and the column address in the first access address being different from the column address in the second access address comprises: generating a first address comparison result in a case that the row address in the first access address is the same as the row address in the second access address, and the column address in the first access address is different from the column address in the second access address; setting a write enable signal of the memory to a first enable state when the first data is written into the second access address through the second port; generating a same-row different-column enable signal according to the first address comparison result and the first enable state; and charging and / or discharging a bit line corresponding to the second access address in the first port according to the same-row different-column enable signal and the first data, so that the first data is written into the second access address through the bit line.

[0013] Optionally, the charging and / or discharging the bit line corresponding to the second access address in the first port according to the same-row different-column enable signal and the first data comprises: charging a positive signal bit line corresponding to the second access address in the first port and discharging a negative signal bit line corresponding to the second access address in the first port according to the same-row different-column enable signal and the first data; or discharging the positive signal bit line corresponding to the second access address in the first port and charging the negative signal bit line corresponding to the second access address in the first port according to the same-row different-column enable signal and the first data.

[0014] Optionally, the charging and / or discharging of the bit line corresponding to the second access address in the first port according to the same-row-different-column enabling signal and the first data comprises: in the case that the bit line of the memory cell corresponding to the second access address in the first port changes in level due to a dummy read operation, detecting whether the level of the bit line corresponding to the first data is consistent with the level formed by the dummy read operation; in the case that the level of the bit line corresponding to the first data is not consistent with the level formed by the dummy read operation, suspending the charging and / or discharging operation of the bit line corresponding to the second access address in the first port; after adjusting the level of the bit line corresponding to the first data to be consistent with the level formed by the dummy read operation through the charging and / or discharging operation, starting the charging and / or discharging operation of the bit line corresponding to the second access address in the first port.

[0015] In a third aspect, embodiments of the present application further provide a memory, wherein any one of the write assist devices provided by the embodiments of the present application is arranged in the memory.

[0016] The address comparison unit of the write assist device and the data writing method thereof and the memory provided by the embodiments of the present application can compare the first access address and the second access address of the memory, and the auxiliary writing unit can respond to the case that the row address in the first access address is the same as the row address in the second access address, and the column address in the first access address is different from the column address in the second access address: when the first data is written into the second access address through the second port, assisting the first port to write the first data into the second access address, and / or when the second data is written into the first access address through the first port, assisting the second port to write the second data into the first access address. In this way, the address comparison unit can timely find the same-row-different-column operation, and in the same-row-different-column operation, when one of the ports performs the same-row-different-column write operation on a memory cell, the auxiliary writing unit can drive the other port to also perform the same write operation on the memory cell, that is, the same-row-different-column write operation is performed on the same memory cell through the two ports, thereby effectively overcoming the influence of the dummy read on the write operation, shortening the time required for the write operation, and greatly improving the data writing effect. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without any creative effort.

[0018] Figure 1A schematic diagram of a dual-port memory in the prior art for row-major column-sequential operation;

[0019] Figure 2 A circuit structure schematic diagram of the storage unit cell 23 shown in the figure; Figure 1

[0020] Figure 3 A structure schematic diagram of the write assist device provided by the embodiment of the present application;

[0021] Figure 4 Another structure schematic diagram of the write assist device provided by the embodiment of the present application;

[0022] Figure 5 A structure schematic diagram of the auxiliary write-in unit in the write assist device provided by the embodiment of the present application;

[0023] Figure 6 Another structure schematic diagram of the auxiliary write-in unit in the write assist device provided by the embodiment of the present application;

[0024] Figure 7 A circuit structure schematic diagram of the auxiliary write-in unit in the write assist device provided by the embodiment of the present application;

[0025] Figure 8 A flow chart of the data write-in method of the write assist device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0026] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0027] It should be clear that the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0028] As mentioned in the background, for the dual-port memory, the pseudo read condition will affect the normal write-in operation of the storage unit. For example, as shown in the figure, Figure 1 ​As shown, a certain memory has two ports A and B, wherein the port A has a word line AWL and a bit line ABL (ABLB is opposite to ABL in logic, not shown), and the port B has a word line BWL and a bit line BBL (BBLB is opposite to BBL in logic, not shown). When a same-row-different-column (SRDC) operation is performed on the dual-port SRAM memory, AWL being "H" will simultaneously open all the memory cells in the row corresponding to AWL, and if cell 22 is the memory cell corresponding to the address decoding of the port A at this time, a read or write operation will be performed on cell 22. For the adjacent memory cell of cell 22, for example, cell 23, since AWL is open, the bit line transfer tube is not open, and the pre-charge circuit is closed, the cell 23 is in a half-select state.

[0029] Figure 2 For Figure 1 A specific circuit schematic diagram of cell 23. In combination with Figure 1 and Figure 2 As shown, when cell 23 is in a half-select state, cell 23 can perform a dummy read operation through ABL and ABLB. At this time, if a write operation is performed on CELL 23 through the port B, since CELL 23 is in a dummy read state, the normal write operation of the port B on cell 23 will be affected by the dummy read of the port A on cell 23, that is, a read-disturb-write problem will occur.

[0030] As Figure 2 shown, the worst case is that the node QT is "0" and QB is "1", AWL first comes to CELL 23 to perform a dummy read, discharges ABL to "0" and ABLB is "1", then BWL is open, "1" is written to QT and "0" is written to QB, BBLB pulls down the QB node at the same time, and also pulls down the ABLB node voltage through APG1, causing an additional current I2, and when the QT node voltage is lifted, the ABL node voltage is also lifted through APG0, causing an additional current I1. Since the ABL and ABLB nodes are bit lines, they have a large capacitance, so the above operation takes a long time, causing the problem of difficulty in writing CELL.

[0031] In order to solve the technical problem, the inventors found in research that a special write assist design can be made to the write circuit of the dual-port memory, when a same-row-different-column operation is found to be performed on the memory, if a write operation is performed on a memory cell in the row through one of the ports, the same write operation can be controlled to be performed on the memory cell through the other port, that is, the write operation is performed on the same memory cell through the two ports, thereby effectively overcoming the influence of the dummy read on the write operation of the dual-port memory, effectively shortening the time required for the write operation, and greatly improving the data write effect.

[0032] In order to enable those skilled in the art to better understand the concept of the present application, the following describes in detail the write assisting device and the data writing method thereof according to the embodiments of the present application through specific examples.

[0033] In the first aspect, the embodiments of the present application provide a write assisting device, which can effectively overcome the influence of pseudo reading on the write operation of a dual-port memory, effectively shorten the time required for the write operation of the dual-port memory, and greatly improve the data writing effect.

[0034] As shown in Figure 3 The embodiments of the present application provide a write assisting device, which can include:

[0035] An address comparison unit 11 is configured to compare a first access address and a second access address of a memory, wherein the first access address is accessed through a first port 21 of the memory 2, and the second access address is accessed through a second port 22 of the memory 2.

[0036] An assisting writing unit 12 is connected to the address comparison unit 11 at a first end, connected to the second port 22 at a second end, and connected to the first port 21 at a third end. The assisting writing unit 12 is configured to, in response to the row address in the first access address being the same as the row address in the second access address and the column address in the first access address being different from the column address in the second access address: assist the first port in writing first data to the second access address through the second port, and / or assist the second port in writing second data to the first access address through the first port.

[0037] The address comparison unit 11 of the write assisting device can compare the first access address and the second access address of the memory, and the assisting write unit 12 can assist the first port to write the first data into the second access address when the row address of the first access address is the same as the row address of the second access address, and the column address of the first access address is different from the column address of the second access address, and / or assist the second port to write the second data into the first access address when the first port writes the second data into the first access address, so that the address comparison unit 11 can find the same-row different-column operation in time, and the assisting write unit 12 can drive the other port to write the same data into the same memory cell when the same-row different-column operation is performed on the memory cell through one port, that is, the same data is written into the same memory cell through two ports, so that the influence of the pseudo read on the write operation is effectively overcome, the time required for the write operation is shortened, and the data write effect is greatly improved.

[0038] Optionally, the input end of the address comparison unit 11 can include the address line of the first port 21 and the address line of the second port 22, the row address of the first access address in the first port 21 can be compared with the row address of the second access address in the second port 22, and the column address of the first access address in the first port 21 can be compared with the column address of the second access address in the second port 22, and when the row addresses are the same and the column addresses are different, the same-row different-column operation occurs in the memory. For example, if 3 rows and 5 columns of the memory are accessed through the first port, and 3 rows and 8 columns of the memory are accessed through the second port, the same-row different-column operation occurs in the memory.

[0039] Specifically, in one embodiment of the present invention, the auxiliary write unit 12 detects that in a parallel operation, after one port performs a write operation on a certain memory cell, it can drive another port to perform the same write operation on the memory cell based on the write operation. This operation can be achieved by adjusting the bit line signal in the pseudo-read port to be consistent with the bit line signal in the write operation port. That is, if for a certain memory cell cell A, the first port is a pseudo-read port and the second port is a write port, the data signal (or bit line signal) to be written in the second port can be used, through certain circuit logic, to make the bit line in the first port the same as the data signal (or bit line signal) to be written in the second port, thereby causing the original pseudo-read port to also perform the same data write operation. Through dual-port writing, the data write performance is effectively improved. For example, if the number 1 is written to cell A through the second port, the data to be written in the second port is 1, and the bit line signal of the second port is 1. Based on this, the bit line signal in the first port can also be changed to 1, thereby realizing the writing of the number 1 in the first port as well.

[0040] It should be noted that, although the embodiments of the present invention use the first port as a pseudo-read port and the second port as a write port as an example for explanation, the embodiments of the present invention are not limited thereto. The first port and the second port simply represent two different ports of the memory, where either port may become a pseudo-read port and the other port may become a write port. The working principle of the write assist device is similar in different ports. During memory access, when a cross-column operation occurs, the pseudo-read port and the write port can be random. Furthermore, the pre-charge circuit in the pseudo-read port is in a closed state to effectively reduce power consumption.

[0041] Since the auxiliary write unit 12 assists write operations by adjusting the bit lines of the port, and memory cells in the same column share the bit lines, the auxiliary write unit 12 can correspond one-to-one with each column in the memory; that is, each column of memory cells corresponds to one auxiliary write unit 12. Each auxiliary write unit 12 can be used to assist write operations to memory cells in different columns, and their specific structures are generally similar. The auxiliary write unit 12 corresponding to the column where the memory cell of the second access address is located will be described in detail below.

[0042] like Figure 4 As shown, in one embodiment of the present invention, the auxiliary writing unit 12 corresponding to the column where the storage unit of the second access address is located may include: a control module 121, a pull-down module 122 and a pull-up module 123;

[0043] The first input end of the control module 121 is connected with the forward input end BWDT of the first data, the second input end is connected with the logical negation input end BWDC of the first data, and the third input end is connected with a same-row and different-column enabling signal B_SRDC_EN, which is obtained by preset logical operation of a comparison result same-row and different-column signal SRDC of the address comparison unit 11 and a write enabling signal W_EN of the memory; wherein the first data is the to-be-written data to be written into the second access address through the second port. Optionally, in an embodiment of the present application, the preset logical operation can be logical AND operation.

[0044] The output end of the control module 121 is connected with the control end of the pull-down module 122, for controlling whether the pull-down module 122 discharges the positive signal bit line or the negative signal bit line corresponding to the second access address in the first port 21, wherein the positive signal bit line is used for inputting or outputting the storage value of the storage unit of the second access address, and the negative signal bit line is used for inputting or outputting the logical negation value of the storage value.

[0045] The output end of the pull-down module 122 is connected with the control end of the pull-up module 123, for controlling whether the pull-up module 123 charges the positive signal bit line or the negative signal bit line corresponding to the second access address in the first port 21.

[0046] In this way, whether the positive signal bit line or the negative signal bit line corresponding to the second access address in the first port 21 is discharged or charged can be controlled through the control module 121, so that the bit line in the first port can be adjusted to the required level as needed, so as to realize writing the first data into the second access address from the first port, thereby improving the data writing effect.

[0047] Further, since the same storage unit in the memory can store differential data, that is, stores the storage data itself and the logical negation value of the storage data at the same time, similarly, the data writing and the data reading are also differentially input through the corresponding positive signal bit line and the negative signal bit line, therefore, in an embodiment of the present application, the pull-down module 122 can also form two pull-down branches corresponding to the positive signal bit line and the negative signal bit line, and the pull-up module 123 can also form two pull-up branches corresponding to the positive signal bit line and the negative signal bit line. Optionally, as shown in FIG. 1, the pull-down module 122 can form two pull-down branches, and the pull-up module 123 can also form two pull-up branches. Figure 5As shown, the first control end gdown1 of the pull-down module 122 is connected to the first output end of the control module 121, the second control end gdown2 is connected to the second output end of the control module 121, the first output end sdown1 of the pull-down module 122 is connected to the positive signal bit line ABL corresponding to the second access address in the first port, the second output end sdown2 is connected to the negative signal bit line ABLB corresponding to the second access address in the first port, and the first ground end ddown1 and the second ground end ddown2 of the pull-down module 122 are both connected to the ground; the pull-down module 122 is used for determining whether to discharge the positive signal bit line ABL or the negative signal bit line ABLB according to the output signal of the control module 121.

[0048] The first control end gup1 of the pull-up module 123 is connected to the second output end sdown2 of the pull-down module 122, the second control end gup2 is connected to the first output end sdown1 of the pull-down module 122, the first output end sup1 of the pull-up module 123 is connected to the first output end sdown1 of the pull-down module 122, the second output end sup2 of the pull-up module 123 is connected to the second output end sdown2 of the pull-down module 122, and the first power supply end dup1 and the second power supply end dup2 of the pull-up module 123 are both connected to the power supply; the pull-up module 123 is used for determining whether to charge the positive signal bit line ABL or the negative signal bit line ABLB according to the output signal of the pull-down module 122.

[0049] Of course, in other embodiments of the present application, the charging and discharging of the positive signal bit line and the negative signal bit line of the second access address in the first port can also be realized by other ways, as long as the same writing operation as the data writing port can be realized in the pseudo reading port when the same row different column operation occurs.

[0050] Further, when the same data writing operation is performed on the pseudo reading port, since the pseudo reading operation itself will affect the level of the bit line, in order to avoid the problem that one bit line is at low level caused by the pseudo reading operation, and the other bit line is at low level caused by the auxiliary writing circuit, thereby causing the writing difficulty and additional power consumption caused by the part of the auxiliary writing circuit unable to quickly form an effective writing positive feedback, such as Figure 6 As shown, in an embodiment of the present application, the auxiliary writing part 12 can further include a protection module 124, the input end of the protection module 124 is connected to the output end of the pull-down module 122, and the output end of the protection module 124 is connected to the positive signal bit line ABL and the negative signal bit line ABLB corresponding to the second access address in the first port 21;

[0051] The protection module 124 can be used to cut off the connection between the output end of the pull-down module 122, the output end of the pull-up module 123 and the positive signal bit line ABL and the negative signal bit line ABLB when the output end of the pull-down module 122 is at the preset level, and keep the output end of the pull-down module 122, the output end of the pull-up module 123 and the positive signal bit line ABL and the negative signal bit line ABLB corresponding to the second access address in the first port 21 in contact when the output end of the pull-down module 122 is not at the preset level. In this way, when the output end of the pull-down module 122 is at the preset level, in order to avoid the influence of the charging and discharging process on the stored data in the storage unit, and also in order to minimize unnecessary power consumption, the protection module 124 is used to cut off the connection between the output end of the pull-down module 122, the output end of the pull-up module 123 and the positive signal bit line ABL and the negative signal bit line ABLB, that is, when the output end of the pull-down module 122 is at the preset level, the pull-down module 122 and the pull-up module 123 will not be able to charge or discharge the positive signal bit line ABL and the negative signal bit line ABLB, and only when the output end of the pull-down module 122 is not at the preset level, the protection module 124 will be reopened, and the pull-down module 122 and the pull-up module 123 can charge or discharge the positive signal bit line ABL and the negative signal bit line ABLB.

[0052] The write assist device provided by the embodiment of the application will be described in detail below through a specific example.

[0053] The write assist device provided by the embodiment of the application can include an address comparison unit 11 and an auxiliary write unit 12. The address comparison unit 11, for example, can be an address comparator, and is used to compare a first access address and a second access address of a memory. The first access address is accessed through a first port A of the memory 2, and the second access address is accessed through a second port B of the memory 2. Figure 7 As shown in the figure, the auxiliary write unit 12 can include a control module 121, a pull-down module 122 and a pull-up module 123. The control module 121 can specifically include a first NAND gate Nand1 and a second NAND gate Nand2. The first input end of the first NAND gate Nand1 is connected to the first data BWDT, the first input end of the second NAND gate Nand2 is connected to the logical inverse value BWDC of the first data, and the second input end of the first NAND gate Nand1 and the second input end of the second NAND gate Nand2 are both connected to the same row and different column enable signal B_SRDC_EN.

[0054] The pull-down module 122 can include a first transistor N1 and a second transistor N2, and the pull-up module 123 can include a third transistor P1 and a fourth transistor P2. The protection module 124 can include a NOR gate NOR1, a fifth transistor P3 and a sixth transistor P4.

[0055] The first pole of the first transistor N1 is connected to the output terminal of the first NAND gate Nand1, the first pole of the second transistor N2 is connected to the output terminal of the second NAND gate Nand2, the second pole of the first transistor N1 is connected to the second pole of the third transistor P1, the second pole of the second transistor N2 is connected to the second pole of the fourth transistor P2, and the third poles of the first transistor N1 and the second transistor N2 are both connected to the ground;

[0056] The first pole of the third transistor P1 is connected to the second pole of the second transistor N2, the first pole of the fourth transistor P2 is connected to the second pole of the first transistor N1, the second pole of the third transistor P1 is connected to the second pole of the first transistor N1, the first pole of the fourth transistor P2 is connected to the second pole of the second transistor N2, and the third poles of the third transistor P1 and the fourth transistor P2 are both connected to the power supply;

[0057] The first poles of the fifth transistor P3 and the sixth transistor P4 are both connected to the output terminal of the NOR gate NOR1, the second pole of the fifth transistor P3 is connected to the second pole of the first transistor N1, the second pole of the sixth transistor P4 is connected to the second pole of the second transistor N2, the third pole of the fifth transistor P3 is connected to the positive signal bit line ABL corresponding to the second access address in the first port 21, the third pole of the sixth transistor P4 is connected to the negative signal bit line ABLB corresponding to the second access address in the first port 21, the first input terminal of the NOR gate NOR1 is connected to the second pole of the fifth transistor P3, and the second input terminal of the NOR gate NOR1 is connected to the second pole of the sixth transistor P4. Wherein, the first pole can be the gate or the base of the transistor, the second pole can be the drain or the collector, and the third pole can be the source or the emitter.

[0058] Initially, QT is "0" and QB is "1", i.e. the storage unit stores the number 0. When the B port performs the same-row different-column write "1" operation, the B port word line BWL and the A port word line AWL are both "H", the address comparison circuit makes the same-row different-column enable signal B_SRDC_EN "H" through the address signals and the write enable signal. The BWDT is "1", i.e. the B port data to be written, and the BWDC is "0", i.e. the logical inverse of the B port data to be written. According to the inputs of the NAND gates Nand1 and Nand2, the NAND gate Nand1 outputs low level, making the pull-down transistor N1 closed, and the NAND gate Nand2 outputs high level, making the pull-down transistor N2 opened, thus lowering the voltage of the node Char_ABLB, and opening the pull-up transistor P1, so that the power supply raises the voltage of the node Char_ABL to "H". At the same time, since Char_ABL and Char_ABLB have at least one node "H", P3 and P4 are both opened, i.e. ABL is "H" and ABLB is "L". Since AWL is also "H" at this time, the A port also performs the write "1" operation for the storage unit. In this way, for the storage unit, the A port and the B port both perform the write "1" operation, thereby effectively improving the write effect of the storage unit.

[0059] Optionally, in an embodiment of the present application, the A port has a pseudo read condition, ABL is pulled down to low level by the pseudo read operation. If the same-row different-column write operation is performed at this time, if the BWDC is 0, N2 is opened to lower ABLB. At this time, ABL and ABLB are both low level, P1 and P2 are both opened, which may form a metastable state to waste power and may also damage the internal data of the storage unit. In the embodiment of the present application, the protection module 124 formed by the NOR gate NOR1, P3 and P4 can effectively prevent this state from occurring. Specifically, when the nodes Char_ABL and Char_ABLB are both low level, the NOR gate NOR1 outputs high level to turn off P3 and P4. The data to be written is first formed into effective positive feedback on the nodes Char_ABL and Char_ABLB, and then P3 and P4 are opened to perform the write operation from the A port. For example, in the embodiment, since the NAND gate Nand1 makes the pull-down transistor N1 closed and the NAND gate Nand2 makes the pull-down transistor N2 opened, during the process of charging P1 and P2, the node Char_ABLB is not easy to be charged to high level, while Char_ABL is quickly charged to high level, so that P1 continues to be opened and P2 is closed, the node Char_ABL is stabilized at high level, and the node Char_ABLB is stabilized at low level, at this time, the NOR gate NOR1 is opened to write data from the A port.

[0060] It should be noted that, Figure 7In the circuit, transistors P5, P6, and P7 form a pre-charge circuit. When a false read occurs, the pre-charge circuit is turned off to reduce power consumption.

[0061] Secondly, embodiments of the present invention also provide a data writing method for a write-assisted device, which can effectively overcome the influence of false reads on the write operation of a dual-port memory, effectively shorten the time required for the write operation of a dual-port memory, and greatly improve the data writing effect.

[0062] like Figure 8 As shown, the data writing method of the write-aided device provided in the embodiments of the present invention may include:

[0063] S41. Compare the first access address and the second access address of the memory, wherein the first access address is accessed through the first port of the memory, and the second access address is accessed through the second port of the memory;

[0064] S42. In response to the fact that the row address in the first access address is the same as the row address in the second access address, and the column address in the first access address is different from the column address in the second access address, when writing first data to the second access address through the second port, assisting the first port in writing the first data to the second access address; and / or, in response to the fact that the row address in the first access address is the same as the row address in the second access address, and the column address in the first access address is different from the column address in the second access address, when writing second data to the first access address through the first port, assisting the second port in writing the second data to the first access address.

[0065] The data writing method of the write-assist device provided in the embodiments of the present invention can compare a first access address and a second access address of the memory. In response to the fact that the row address in the first access address is the same as the row address in the second access address, and the column address in the first access address is different from the column address in the second access address: when writing first data to the second access address through the second port, the first port is assisted in writing the first data to the second access address, and / or, when writing second data to the first access address through the first port, the second port is assisted in writing the second data to the first access address. In this way, the parallel-column operation can be detected in time. In the parallel-column operation, when a parallel-column write operation is performed on a memory cell through one port, the other port can be driven to perform the same write operation on the memory cell. That is, the same memory cell is written through two ports, thereby effectively overcoming the influence of false reads on the write operation, shortening the time required for the write operation, and greatly improving the data writing effect.

[0066] Optionally, in response to the row address in the first access address being the same as the row address in the second access address and the column address in the first access address being different from the column address in the second access address, when the first data is written to the second access address through the second port, the assisting the first port to write the first data to the second access address can include:

[0067] generating a first address comparison result in the case that the row address in the first access address is the same as the row address in the second access address and the column address in the first access address is different from the column address in the second access address;

[0068] setting a write enable signal of the memory to a first enable state when the first data is written to the second access address through the second port;

[0069] generating a same-row-different-column enable signal according to the first address comparison result and the first enable state;

[0070] charging and / or discharging a bit line corresponding to the second access address in the first port according to the same-row-different-column enable signal and the first data, so that the first data is written to the second access address through the bit line.

[0071] Optionally, the charging and / or discharging the bit line corresponding to the second access address in the first port according to the same-row-different-column enable signal and the first data can specifically include:

[0072] charging a positive signal bit line corresponding to the second access address in the first port and discharging a negative signal bit line corresponding to the second access address in the first port according to the same-row-different-column enable signal and the first data;

[0073] or

[0074] discharging the positive signal bit line corresponding to the second access address in the first port and charging the negative signal bit line corresponding to the second access address in the first port according to the same-row-different-column enable signal and the first data.

[0075] Further, in order to avoid the damage of some preset states to the data of the storage unit and to reduce the loss of power consumption, in an embodiment of the present application, the charging and / or discharging the bit line corresponding to the second access address in the first port according to the same-row-different-column enable signal and the first data can specifically include:

[0076] in the case that the bit line of the memory cell corresponding to the second access address in the first port changes in level due to the dummy read operation, detecting whether the level of the bit line corresponding to the first data is consistent with the level formed by the dummy read operation;

[0077] in the case that the level of the bit line corresponding to the first data is not consistent with the level formed by the dummy read operation, suspending the charging and / or discharging operation on the bit line corresponding to the second access address in the first port;

[0078] after the level of the bit line corresponding to the first data is adjusted to be consistent with the level formed by the dummy read operation through the charging and / or discharging operation, resuming the charging and / or discharging operation on the bit line corresponding to the second access address in the first port.

[0079] For example, in an embodiment of the present application, due to the dummy read operation, the positive signal bit line in the A port of a memory cell is 0, and the write data makes the negative signal bit line in the A port also 0, so the charging of the positive signal bit line and the negative signal bit line in the A port can be suspended. After the level of the bit line corresponding to the write data is adjusted to be consistent with the level formed by the dummy read operation through the charging and / or discharging operation, i.e. adjusted to be the positive signal bit line 1 and the negative signal bit line 0, the charging and / or discharging operation on the bit line corresponding to the memory cell in the A port is resumed.

[0080] The data write method of the write assist device provided by the embodiments of the present application is based on any one of the write assist devices provided by the foregoing embodiments, and the specific circuit structure and working process have been described in the foregoing, which will not be repeated here.

[0081] In a third aspect, correspondingly, the embodiments of the present application also provide a memory, wherein the memory is provided with any one of the write assist devices provided by the foregoing embodiments of the present application, so that the corresponding beneficial technical effects can also be achieved, and details can be referred to the foregoing embodiments, which will not be repeated here. In an embodiment of the present application, the memory can be a dual-port static random access memory.

[0082] It is to be noted that the terms such as first and second, etc., are used herein merely to differentiate one entity or action from another, and do not necessarily require or imply any such actual relationship or order between such entities or actions. Also, the terms "comprising", "containing", or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements recited, but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element defined by the phrase "comprising a" does not exclude the existence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0083] Each of the embodiments in the present specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other. Each of the embodiments focuses on the difference from other embodiments.

[0084] Especially, for the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the description of the method embodiments.

[0085] For the convenience of description, the above device is described in various units / modules respectively according to functions. Of course, in the implementation of the present application, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0086] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, can include the processes of the above-mentioned embodiments. The storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM), a random access memory (RAM), etc.

[0087] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or replacements within the technical scope disclosed by the present application can be easily thought of by those skilled in the art, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A write assist device, comprising: The application relates to a memory device, comprising: an address comparison unit for comparing a first access address and a second access address of a memory, wherein the first access address is accessed through a first port of the memory, and the second access address is accessed through a second port of the memory; an auxiliary write unit, having a first end connected to the address comparison unit, a second end connected to the second port, and a third end connected to the first port, for assisting the first port to write first data into the second access address through the second port and / or assisting the second port to write second data into the first access address through the first port, in response to the row address in the first access address being the same as the row address in the second access address and the column address in the first access address being different from the column address in the second access address; each column of memory cells of the memory corresponds to an auxiliary write unit; wherein the auxiliary write unit corresponding to the column in which the memory cell of the second access address is located comprises a control module, a pull-down module and a pull-up module; a first input end of the control module is connected to a positive input end of the first data, a second input end is connected to a logical NOT input end of the first data, and a third input end is connected to a same-row different-column enable signal obtained by preset logical operation of a comparison result of the address comparison unit and a write enable signal of the memory; an output end of the control module is connected to a control end of the pull-down module, for controlling whether the pull-down module discharges a positive signal bit line or a negative signal bit line corresponding to the second access address in the first port, wherein the positive signal bit line is used for inputting or outputting a storage value of the memory cell of the second access address, and the negative signal bit line is used for inputting or outputting a logical NOT value of the storage value; an output end of the pull-down module is connected to a control end of the pull-up module, for controlling whether the pull-up module charges the positive signal bit line or the negative signal bit line corresponding to the second access address in the first port; the auxiliary write unit further comprises a protection module, an input end of the protection module is connected to an output end of the pull-down module, and an output end of the protection module is connected to the positive signal bit line and the negative signal bit line corresponding to the second access address in the first port; the protection module is used for cutting off the connection between the output end of the pull-down module, the output end of the pull-up module and the positive signal bit line and the negative signal bit line when the output end of the pull-down module is at a preset level, and keeping the connection between the output end of the pull-down module, the output end of the pull-up module and the positive signal bit line and the negative signal bit line corresponding to the second access address in the first port when the output end of the pull-down module is not at the preset level.

2. The write assist device of claim 1, wherein, The first control end of the pull-down module is connected with the first output end of the control module, the second control end of the pull-down module is connected with the second output end of the control module, the first output end of the pull-down module is connected with the positive signal bit line corresponding to the second access address in the first port, the second output end of the pull-down module is connected with the negative signal bit line corresponding to the second access address in the first port, and the first ground end and the second ground end of the pull-down module are grounded; the pull-down module is used for determining whether to discharge the positive signal bit line or the negative signal bit line according to the output signal of the control module; The first control end of the pull-up module is connected with the second output end of the pull-down module, the second control end of the pull-up module is connected with the first output end of the pull-down module, the first output end of the pull-up module is connected with the first output end of the pull-down module, the second output end of the pull-up module is connected with the second output end of the pull-down module, and the first power supply end and the second power supply end of the pull-up module are connected with a power supply; the pull-up module is used for determining whether to charge the positive signal bit line or the negative signal bit line according to the output signal of the pull-down module.

3. The write assist device of claim 1, wherein, The control module comprises a first NAND gate and a second NAND gate, the first input end of the first NAND gate is connected with the first data, the first input end of the second NAND gate is connected with the logical negation value of the first data, and the second input end of the first NAND gate and the second input end of the second NAND gate are both connected with the same-row different-column enable signal; The pull-down module comprises a first transistor and a second transistor, the pull-up module comprises a third transistor and a fourth transistor, and the protection module comprises a NOR gate, a fifth transistor and a sixth transistor; The first pole of the first transistor is connected with the output end of the first NAND gate, the first pole of the second transistor is connected with the output end of the second NAND gate, the second pole of the first transistor is connected with the second pole of the third transistor, the second pole of the second transistor is connected with the second pole of the fourth transistor, and the third pole of the first transistor and the third pole of the second transistor are both grounded; The first pole of the third transistor is connected with the second pole of the second transistor, the first pole of the fourth transistor is connected with the second pole of the first transistor, the second pole of the third transistor is connected with the second pole of the first transistor, the first pole of the fourth transistor is connected with the second pole of the second transistor, and the third pole of the third transistor and the third pole of the fourth transistor are both connected with a power supply; The first pole of the fifth transistor and the first pole of the sixth transistor are both connected with the output end of the NOR gate, the second pole of the fifth transistor is connected with the second pole of the first transistor, the second pole of the sixth transistor is connected with the second pole of the second transistor, the third pole of the fifth transistor is connected with the positive signal bit line corresponding to the second access address in the first port, the third pole of the sixth transistor is connected with the negative signal bit line corresponding to the second access address in the first port, the first input end of the NOR gate is connected with the second pole of the fifth transistor, and the second input end of the NOR gate is connected with the second pole of the sixth transistor.

4. The write assist device of claim 1, wherein, The preset logic operation is a logical AND operation.

5. A data write method of a write assist device, characterized by, It comprises: comparing a first access address and a second access address of a memory, wherein the first access address is accessed through a first port of the memory, and the second access address is accessed through a second port of the memory; in response to a row address in the first access address being the same as a row address in the second access address, and a column address in the first access address being different from a column address in the second access address, assisting the first port to write first data to the second access address through the second port when the second access address is written with the first data through the second port; and / or, in response to a row address in the first access address being the same as a row address in the second access address, and a column address in the first access address being different from a column address in the second access address, assisting the second port to write second data to the first access address through the first port when the first access address is written with the second data through the first port; the assisting the first port to write first data to the second access address through the second port when the second access address is written with the first data through the second port in response to a row address in the first access address being the same as a row address in the second access address, and a column address in the first access address being different from a column address in the second access address comprises: generating a first address comparison result in a case where a row address in the first access address is the same as a row address in the second access address, and a column address in the first access address is different from a column address in the second access address; setting a write enable signal of the memory to a first enable state when the second access address is written with the first data through the second port; generating a same-row-different-column enable signal according to the first address comparison result and the first enable state; charging and / or discharging a bit line corresponding to the second access address in the first port with the first data according to the same-row-different-column enable signal and the first data, so that the first data is written to the second access address through the bit line; the charging and / or discharging a bit line corresponding to the second access address in the first port with the first data according to the same-row-different-column enable signal and the first data comprises: detecting whether a bit line level corresponding to the first data is consistent with a level formed by a dummy read operation in a case where a bit line of a memory cell corresponding to the second access address in the first port changes in level due to the dummy read operation; suspending the charging and / or discharging operation of the bit line corresponding to the second access address in the first port in a case where the bit line level corresponding to the first data is not consistent with the level formed by the dummy read operation; starting the charging and / or discharging operation of the bit line corresponding to the second access address in the first port after adjusting the bit line level corresponding to the first data to be consistent with the level formed by the dummy read operation through the charging and / or discharging operation.

6. The data write method of claim 5, wherein, the charging and / or discharging a bit line corresponding to the second access address in the first port with the first data according to the same-row-different-column enable signal and the first data comprises: According to the same-row different-column enable signal and the first data, the positive signal bit line corresponding to the second access address in the first port is charged, and the negative signal bit line corresponding to the second access address in the first port is discharged; Or According to the same-row different-column enable signal and the first data, the positive signal bit line corresponding to the second access address in the first port is discharged, and the negative signal bit line corresponding to the second access address in the first port is charged.

7. A memory, comprising: The memory is provided with the write assist device in any one of claims 1-4.

Images