A method and device for obtaining FRT table in solid state hard disk

Abstract

The present invention provides a method for obtaining an FRT table in a solid-state drive, including: processing FRT raw data, summarizing the FRT data obtained by NAND testing in a lower page all list, a middle page all list, and an upper page all list for representing A, B, C, D, E, F, and G axis data, wherein the lower page all list includes three groups of data: FRT1, FRT2, and FRT3; obtaining a data position offset table for FRT1, FRT2, and FRT3; extracting A, B, C, D, E, F, and G axis data from the FRT raw data table; reorganizing the FRT table, reorganizing the extracted A, B, C, D, E, F, and G axis data, and saving the generated data to a file. The present invention performs script analysis on the offset voltage table obtained by the NAND test, and finally obtains the FRT table applied in the SSD firmware, applies the FRT table to the SSD firmware, and greatly reduces the occurrence of read errors.

Description

Technical Field

[0001] The present invention relates to the field of file management technology, and in particular to a method and device for obtaining data in a FRT table in a solid-state hard disk. Background Art

[0002] As a leading storage device, SSDs are experiencing rapid technological development and product adoption. SSDs consist of a control unit and a storage unit (FLASH chip, DRAM chip). Flash-based solid-state drives (SSDs), the primary type of SSD, have a very simple internal structure. The SSD itself consists of a single PCB board, with the most basic components being the control chip, cache chips (some low-end hard drives lack cache chips), and the flash memory chips used to store data. With the rapid development of information technology-related industries, the demand for storage devices is also growing. Currently, SSDs are widely used in military, industrial control, video surveillance, network monitoring, network terminals, banking, healthcare, aviation, and other fields.

[0003] Nand Flash is a non-volatile memory, and the main control chip of a solid-state drive must handle these errors. Currently, the storage medium used in most SSDs is Nand Flash. Due to its physical structure, its basic storage unit is a floating-gate transistor. Due to physical characteristics such as charge leakage and oxide aging, Nand Flash is affected by drift, over-programming, read interference, and temperature during use. This inevitably leads to errors such as read errors, programming failures, and erase / program failures, resulting in bit flips. SSDs use FRT tables to correct these data errors. Throughout Nand Flash's lifecycle, drift, over-programming, read interference, and temperature can cause the optimal read reference voltage to shift, resulting in read errors.

[0004] To address these issues, we developed a method for obtaining the FRT table in SSDs. By performing script analysis on the offset voltage table obtained during NAND testing, we ultimately obtained the FRT table used in the SSD firmware. Applying the FRT table to the SSD firmware significantly reduces read errors. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a method and device for obtaining an FRT table in a solid-state hard disk, so as to solve the problem of reference voltage offset and read error in the prior art.

[0006] Based on the above purpose, the present invention provides a method for obtaining an FRT table in a solid-state drive, comprising the following steps:

[0007] Step 101: FRT raw data processing;

[0008] The FRT data obtained from the NAND test is summarized in the lower page all list, middle page all list, and upper page all list. The minimum element of the lower page all list is in the "[A,E]" format, which is used to represent the A-axis and E-axis data. The minimum element of the middle page all list is in the "[B,D,F]" format, which is used to represent the B-axis, D-axis, and F-axis data. The minimum element of the upper page all list is in the "[C,G]" format, which is used to represent the C-axis and G-axis data. The lower page all list table is used to determine the number of erase and write cycles PE and the data retention time. The lower page all list contains three groups of data: FRT1, FRT2, and FRT3.

[0009] Step 102: Obtain the data position offset table of FRT1, FRT2, and FRT3;

[0010] Step 103: Extract A, B, C, D, E, F, and G axis data from the FRT original data table;

[0011] Step 104 : Reorganize the FRT table, reorganize the extracted A, B, C, D, E, F, and G axis data, and save the generated data to a file.

[0012] In some embodiments, the method further comprises:

[0013] The step 102 of obtaining the data position offset table of FRT1, FRT2, and FRT3 includes the following steps:

[0014] Step 201: Obtain the coordinate offset table of FRT1;

[0015] Step 202: Calculate the coordinate offset table of FRT2 and FRT3 based on the coordinate offset table of FRT1;

[0016] Step 203: Combine FRT1, FRT2, and FRT3 into an frt pos list.

[0017] In some embodiments, the method further comprises:

[0018] The coordinate offset table for obtaining FRT1 is specifically: FRT1 data position offset = current PE offset + current RET offset × RET offset step; where PE is the number of erase and write times of the NAND flash memory, and RET is the data storage time in the NAND flash memory.

[0019] In some embodiments, the method further comprises:

[0020] The coordinate offset table of FRT2 and FRT3 is calculated based on the coordinate offset table of FRT1, specifically:

[0021] FRT2 data position offset = PE offset step + FRT1 data position offset,

[0022] FRT3 data position offset = 2×PE offset step + FRT1 data position offset.

[0023] In some embodiments, the method further comprises:

[0024] Extract the A, B, C, D, E, F, and G axis data from the FRT original data table, specifically:

[0025] Step 301: traverse the frt pos list table to obtain the currently processed FRTx table;

[0026] Step 302: traverse the elements in the FRTx table;

[0027] Step 303: Get the data list of axes A, B, C, D, E, F, and G of the FRTx table.

[0028] In some embodiments, the method further comprises:

[0029] The reorganization of the FRT table is specifically as follows: combining the data lists A, B, C, D, E, F, and G axis data lists into the FRT format required by SSD;

[0030] Save the data to a file.

[0031] In some embodiments, the method further comprises:

[0032] After saving the data to the file, continue to traverse the elements in the FRTx table until all data lists of the data lists A, B, C, D, E, F, and G axes are combined into the FRT format required by SSD, and the data is saved to the file.

[0033] Another aspect of the present invention further provides a device for obtaining an FRT table in a solid-state hard disk, comprising:

[0034] The raw data acquisition module is used to obtain FRT raw data processing and summarize the FRT data obtained by NAND testing in the lower page all list, middle page all list, and upper page all list. The minimum element of the lower page all list is in the "[A,E]" format, which is used to represent the A-axis and E-axis data. The minimum element of the middle page all list is in the "[B,D,F]" format, which is used to represent the B-axis, D-axis, and F-axis data. The minimum element of the upper page all list is in the "[C,G]" format, which is used to represent the C-axis and G-axis data.

[0035] A data position offset table acquisition module is used to obtain the data position offset tables of FRT1, FRT2, and FRT3;

[0036] Data extraction module, used to extract A, B, C, D, E, F, G axis data from the FRT original data table;

[0037] The reorganization module is used to reorganize the FRT table, reorganize the extracted A, B, C, D, E, F, and G axis data, and save the generated data to a file.

[0038] According to another aspect of the present invention, a computer-readable storage medium is provided, which stores computer program instructions, and the computer program instructions implement any one of the above methods when executed.

[0039] In another aspect of the present invention, a computer device is provided, comprising a memory and a processor, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, any one of the above methods is performed.

[0040] The present invention has at least the following beneficial technical effects:

[0041] 1. The present invention performs script analysis on the offset voltage table obtained from NAND testing to ultimately obtain the FRT table used in the SSD firmware. Applying the FRT table to the SSD firmware can significantly reduce read errors.

[0042] 2. The present invention summarizes the FRT data obtained by NAND testing into the lower page all list, middle page all list, and upper page all list, where the lower page all list is divided into three groups of data: FRT1, FRT2, and FRT3. The coordinate offset table of FRT2 and FRT3 is calculated by obtaining the coordinate offset table of FRT1, and the offset table is combined into the frt pos list table. The elements in the frt pos list table are obtained, the data of the A, B, C, D, E, F, and G axes are extracted and combined into the FRT format, thereby effectively improving the reading accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 A schematic diagram of FRT raw data provided according to an embodiment of the present invention;

[0045] Figure 2 A schematic diagram of the arrangement of FRT raw data according to an embodiment of the present invention;

[0046] Figure 3 A flow chart of an FRT table data processing algorithm according to an embodiment of the present invention;

[0047] Figure 4 An FRT table generated after combining data according to an embodiment of the present invention;

[0048] Figure 5 A schematic diagram of a computer-readable storage medium for implementing a resource monitoring method according to an embodiment of the present invention;

[0049] Figure 6 A schematic diagram of the hardware structure of a computer device for executing a resource monitoring method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0051] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are intended to distinguish two non-identical entities or non-identical parameters with the same name. Therefore, "first" and "second" are used for convenience of expression only and should not be understood as limitations on the embodiments of the present invention. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, other steps or units inherent to a process, method, system, product, or device that includes a series of steps or units.

[0052] Currently, the vast majority of SSDs use flash memory chips as storage media. Flash memory chips are a type of non-volatile memory whose basic storage unit is a floating-gate transistor. Due to physical properties such as charge leakage and oxide layer aging, flash memory chips will inevitably have errors such as read errors, programming failures, or erase programming failures during use. The main control chip of the solid-state drive must handle these errors. In the prior art, the method for handling read errors in the data blocks of solid-state drives is to set the UNC (uncorrectable error) mark for the mapping table entry corresponding to the erroneous data, usually with a granularity of 4KB. The next time the host reads the data corresponding to this mapping table entry, it no longer accesses the flash memory chip, but directly returns an UNC error to the host. Since the mapping table entry is marked with UNC when a read error occurs in the data block, as long as the address read by the host falls on the mapping table entry with the UNC mark, an UNC error is returned to the host. This method may cause some addresses without errors in the addresses read by the host to be unable to be read, resulting in a high data loss rate.

[0053] Based on the above objectives, a first aspect of an embodiment of the present invention provides an embodiment of a method for obtaining an FRT table in a solid-state drive. Figure 1 What is shown is the schematic diagram of the FRT raw data provided by the present invention. First, the terminology of each component adopted in the following embodiment of the present invention is explained as follows:

[0054] SSD: Solid-state drive, a hard drive made with an array of solid-state electronic storage chips (such as Nand Flash).

[0055] Nand Flash: NAND flash memory

[0056] FRT: Fixed Read Table

[0057] PE: The number of program erases (PE) of NAND flash memory. A complete erase of the flash memory is called a P / E. The life of the flash memory is measured in P / E units.

[0058] RET: Retention time of data in NAND flash memory

[0059] The embodiment of the present invention includes the following steps:

[0060] Step 101, FRT raw data processing, such as Figure 1 As shown,

[0061] The NAND flash memory erase and write endurance (PE) is divided into five levels: 0-1500 times, 1500-2500 times, 2500-3500 times, 3500-4500 times, and 4500-5000 times.

[0062] The NAND flash memory data retention time RET is divided into 6 levels: 0-9 days, 9-27 days, 27-45 days, 45-63 days, 63-81 days, and 81-90 days.

[0063] The lower page all list contains three data sets: FRT1, FRT2, and FRT3; the lower page all list has a total of 90 data sets (5*6*3). The smallest element in the lower page all list is in the "[A,E]" format, representing the A-axis and E-axis data, respectively. The smallest element in the middle page all list is in the "[B,D,F]" format, representing the B-axis, D-axis, and F-axis data, respectively. The smallest element in the upper page all list is in the "[C,G]" format, representing the C-axis and G-axis data, respectively.

[0064] Data distribution diagram Figure 2 shown.

[0065] Then in Figure 3 The flowchart shown includes the following steps:

[0066] Step 102: Obtain the data position offset table of FRT1, FRT2, and FRT3;

[0067] In some embodiments, the step of obtaining the data position offset table includes:

[0068] Step 201: Obtain the coordinate offset table of FRT1;

[0069] Step 202: Calculate the coordinate offset table of FRT2 and FRT3 based on the coordinate offset table of FRT1;

[0070] Step 203: Combine FRT1, FRT2, and FRT3 into an frt pos list;

[0071] The coordinate offset table for obtaining FRT1 is as follows:

[0072] FRT1 data position offset = current PE offset + current RET offset × RET offset step; where PE is the number of erase and write times of the NAND flash memory, and RET is the data retention time in the NAND flash memory.

[0073] The coordinate offset table of FRT2 and FRT3 is calculated based on the coordinate offset table of FRT1, specifically:

[0074] FRT2 data position offset = PE offset step + FRT1 data position offset,

[0075] FRT3 data position offset = 2×PE offset step + FRT1 data position offset.

[0076] Combine FRT1, FRT2, and FRT3 into an frt pos list table, and obtain the following list:

[0077] Frt1poslist=[0,15,30,45,60,75,1,16,31,46,61,76,2,17,32,47,62,77,3,18,33,48,63,78,4,19,34,49,64,79]

[0078] frt2poslist=[5,20,35,50,65,80,6,21,36,51,66,81,7,22,37,52,67,82,8,23,38,53,68,83,9,24,39,54,69,84]

[0079] frt3poslist=[10,25,40,55,70,85,11,26,41,56,71,86,12,27,42,57,72,87,13,28,43,58,73,88,14,29,44,59,74,89].

[0080] Step 103: Extract A, B, C, D, E, F, and G axis data from the FRT original data table;

[0081] like Figure 3 As shown, specifically:

[0082] Step 301: traverse the frt pos list table to obtain the currently processed FRTx table;

[0083] Step 302: traverse the elements in the FRTx table;

[0084] Step 303: Get the data list of axes A, B, C, D, E, F, and G of the FRTx table.

[0085] Step 104, reorganize the FRT table, reorganize the extracted A, B, C, D, E, F, G axis data and save the generated data to a file; combine the data lists A, B, C, D, E, F, G axis data lists into the FRT format required by SSD; save the data to a file.

[0086] In some embodiments, the A, B, C, D, E, F, and G axis data in step 103 are reorganized according to the format "{0xGCEA, 0xBDF}" of the FRT table in the solid-state drive firmware, and the generated data is saved to a file. The saved data format is as shown in the attached file. Figure 4 shown.

[0087] It should be noted that after saving the data to the file, continue to traverse the elements in the FRTx table until all data lists of axes A, B, C, D, E, F, and G are combined into the FRT format required by SSD, and the data is saved to the file.

[0088] Another aspect of the present invention further provides a device for obtaining an FRT table in a solid-state hard disk, comprising:

[0089] The raw data acquisition module is used to obtain FRT raw data processing and summarize the FRT data obtained by NAND testing in the lower page all list, middle page all list, and upper page all list. The minimum element of the lower page all list is in the "[A,E]" format, which is used to represent the A-axis and E-axis data. The minimum element of the middle page all list is in the "[B,D,F]" format, which is used to represent the B-axis, D-axis, and F-axis data. The minimum element of the upper page all list is in the "[C,G]" format, which is used to represent the C-axis and G-axis data.

[0090] A data position offset table acquisition module is used to obtain the data position offset tables of FRT1, FRT2, and FRT3;

[0091] Data extraction module, used to extract A, B, C, D, E, F, G axis data from the FRT original data table;

[0092] The reorganization module is used to reorganize the FRT table, reorganize the extracted A, B, C, D, E, F, and G axis data, and save the generated data to a file.

[0093] A third aspect of the embodiments of the present invention further provides a computer-readable storage medium. Figure 5 FIG. 1 is a schematic diagram showing a computer-readable storage medium for implementing a resource monitoring method according to an embodiment of the present invention. Figure 5 As shown, the computer-readable storage medium 3 stores computer program instructions 31, which can be executed by a processor. When the computer program instructions 31 are executed, the method of any one of the above embodiments is implemented.

[0094] It should be understood that, unless they conflict with each other, all the embodiments, features, and advantages described above for the resource monitoring method according to the present invention are also applicable to the resource monitoring system and storage medium according to the present invention.

[0095] A fourth aspect of the embodiments of the present invention further provides a computer device, including a memory 402 and a processor 401, wherein the memory stores a computer program, and when the computer program is executed by the processor, the method of any one of the above embodiments is implemented.

[0096] like Figure 6 FIG. 1 is a schematic diagram of the hardware structure of a computer device for executing a resource monitoring method provided by the present invention. Figure 6 Taking the computer device shown in FIG. 4 as an example, the computer device includes a processor 401 and a memory 402, and may also include: an input device 403 and an output device 404. The processor 401, the memory 402, the input device 403 and the output device 404 may be connected via a bus or other means. Figure 4 The input device 403 can receive input digital or character information and generate key signal input related to user settings and function control of the resource monitoring system. The output device 404 can include a display device such as a display screen.

[0097] The memory 402 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs and modules, such as the program instructions / modules corresponding to the resource monitoring method in the embodiment of the present application. The memory 402 may include a program storage area and a data storage area, wherein the program storage area can store an operating system, an application required for at least one function; the data storage area can store data created by the use of the resource monitoring method, etc. In addition, the memory 402 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 402 may optionally include a memory remotely arranged relative to the processor 401, and these remote memories may be connected to the local module via a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network and a combination thereof.

[0098] The processor 401 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions and modules stored in the memory 402, that is, implements the resource monitoring method of the above method embodiment.

[0099] Finally, it should be noted that the computer-readable storage medium (e.g., memory) herein may be a volatile memory or a non-volatile memory, or may include both a volatile memory and a non-volatile memory. By way of example and not limitation, the non-volatile memory may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), or a flash memory. The volatile memory may include a random access memory (RAM), which may act as an external cache memory. By way of example and not limitation, RAM may be obtained in a variety of forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to include, but are not limited to, these and other suitable types of memory.

[0100] It will also be appreciated by those skilled in the art that the various exemplary logic blocks, modules, circuits and algorithmic steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, a general description has been given of the functions of various schematic components, blocks, modules, circuits and steps. Whether this function is implemented as software or hardware depends on specific applications and the design constraints imposed on the entire system. Those skilled in the art can implement the function in various ways for each specific application, but this implementation decision should not be interpreted as causing a departure from the disclosed scope of the embodiments of the present invention.

[0101] The various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure herein may be implemented or executed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and / or any other such configuration.

[0102] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope of the embodiments disclosed in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless expressly limited to the singular.

[0103] It should be understood that, as used herein, the singular form "a" or "an" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the items listed in association. The serial numbers of the embodiments disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0104] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples. Within the spirit of the embodiments of the present invention, the technical features of the above embodiments or different embodiments may be combined, and there are many other variations of different aspects of the above embodiments of the present invention, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the scope of protection of the embodiments of the present invention.

Claims

1. A method for obtaining an FRT table in a solid state drive, characterized in that: The following steps are involved: Step 101: FRT raw data processing The method includes summarizing the FRT data obtained from the NAND test into the lower page all list, the middle page all list, and the upper page all list. The minimum element of the lower page all list is in the "[A,E]" format, which is used to represent the A-axis and E-axis data. The minimum element of the middle page all list is in the "[B,D,F]" format, which is used to represent the B-axis, D-axis, and F-axis data. The minimum element of the upper page all list is in the "[C,G]" format, which is used to represent the C-axis and G-axis data. The lower page all list table is used to determine the number of erase and write cycles PE and the data retention time. The lower page all list contains three groups of data: FRT1, FRT2, and FRT3. Step 102: Obtain the data position offset table of FRT1, FRT2, and FRT3; Step 103: Extract A, B, C, D, E, F, and G axis data from the FRT original data table; Step 104: reorganize the FRT table, reorganize the extracted A, B, C, D, E, F, and G axis data, and save the generated data to a file; Obtaining the data position offset table of FRT1, FRT2, and FRT3 includes the following steps: Step 201: Get the coordinate offset table of FRT1; Step 202: Calculate the coordinate offset table of FRT2 and FRT3 based on the coordinate offset table of FRT1; Step 203: Combine FRT1, FRT2, and FRT3 into an frt pos list; The coordinate offset table for obtaining FRT1 is as follows: FRT1 data position offset = current PE offset + current RET offset × RET offset step; where PE is the number of erase / write times of the NAND flash memory, and RET is the data storage time in the NAND flash memory; The coordinate offset tables of FRT2 and FRT3 are calculated based on the coordinate offset table of FRT1, specifically: FRT2 data position offset = PE offset step + FRT1 data position offset, FRT3 data position offset = 2 × PE offset step + FRT1 data position offset.

2. The method according to claim 1, characterized in that Extract the A, B, C, D, E, F, and G axis data from the FRT original data table, specifically: Step 301: traverse the frt pos list table to obtain the currently processed FRTx table; Step 302: traverse the elements in the FRTx table; Step 303: Get the data list of axes A, B, C, D, E, F, and G of the FRTx table.

3. The method according to claim 1 or 2, characterized in that The reorganized FRT table is specifically: Combine the data lists A, B, C, D, E, F, and G axis data lists into the FRT format required by SSD; and save the data to a file.

4. The method according to claim 3, characterized in that After saving the data to the file, loop through the frt poslist table until all elements in the FRT1, FRT2, and FRT3 tables are obtained, and all data lists of the data lists A, B, C, D, E, F, and G axes are combined into the FRT format required by SSD, and the data is saved to the file.

5. A device for obtaining an FRT table in a solid state hard disk, characterized in that: include: The raw data acquisition module is used to obtain FRT raw data processing and summarize the FRT data obtained by NAND testing in the lower page all list, middle page all list, and upper page all list. The minimum element of the lower page all list is in the "[A,E]" format, which is used to represent the A-axis and E-axis data. The minimum element of the middle page all list is in the "[B,D,F]" format, which is used to represent the B-axis, D-axis, and F-axis data. The minimum element of the upper page all list is in the "[C,G]" format, which is used to represent the C-axis and G-axis data. A data position offset table acquisition module is used to obtain the data position offset tables of FRT1, FRT2, and FRT3; obtaining the data position offset tables of FRT1, FRT2, and FRT3 includes the following steps: step 201, obtaining the coordinate offset table of FRT1; step 202, calculating the coordinate offset tables of FRT2 and FRT3 based on the coordinate offset table of FRT1; step 203, combining FRT1, FRT2, and FRT3 into an frt pos list table; obtaining the coordinate offset table of FRT1 is specifically as follows: FRT1 data position offset = current PE offset + current RET offset × RET offset step; wherein PE is the number of erase and write times of the NAND flash memory, and RET is the data storage time in the NAND flash memory; calculating the coordinate offset tables of FRT2 and FRT3 based on the coordinate offset table of FRT1 is specifically as follows: FRT2 data position offset = PE offset step + FRT1 data position offset, and FRT3 data position offset = 2 × PE offset step + FRT1 data position offset; Data extraction module, used to extract A, B, C, D, E, F, G axis data from the FRT original data table; The reorganization module is used to reorganize the FRT table, reorganize the extracted A, B, C, D, E, F, and G axis data, and save the generated data to a file.

6. A computer-readable storage medium, characterized in that Computer program instructions are stored, and when the computer program instructions are executed, the method according to any one of claims 1 to 4 is implemented.

7. A computer device comprising a memory and a processor, characterized in that: The memory stores a computer program, which, when executed by the processor, performs the method according to any one of claims 1 to 4.

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