Methods for forming semiconductor structures

Abstract

This invention provides a method for forming a semiconductor structure. The method includes: providing a substrate; forming a patterned barrier layer on the substrate, the barrier layer covering a second trench region and an isolation region, and exposing a first trench region; forming a patterned first mask layer, the first mask layer exposing the substrate of the first trench region, and the barrier layer of the second trench region and the isolation region; etching the substrate using the barrier layer and the first mask layer as masks to form a first trench; forming a second mask layer covering the first trench and the isolation region, and exposing the second trench region; and etching the substrate using the first mask layer and the second mask layer as masks to form a second trench. This method reduces the process complexity and accuracy of semiconductor structure formation.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits, the feature size of integrated circuits continues to shrink. In particular, the feature size is rapidly developing towards micrometers and nanometers, and the linewidth of the patterns will also become increasingly finer, which places higher demands on semiconductor processes.

[0003] In subsequent integrated circuit manufacturing processes, lithography is typically used to transfer integrated circuit patterns. However, the finer the linewidth of the integrated circuit pattern, the higher the requirements for lithography technology. When existing lithography technologies cannot meet these requirements, a series of problems can easily arise, making the fabrication process of existing semiconductor devices complex and demanding high precision. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which reduces the process complexity and process precision of semiconductor structure formation.

[0005] To address the above problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising:

[0006] A substrate is provided, the substrate including a first trench region and a second trench region arranged alternately along a first direction, and an isolation region located between the first trench region and the second trench region;

[0007] A patterned barrier layer is formed on the substrate, the barrier layer covering the second trench area and the isolation area, exposing the first trench area;

[0008] A patterned first mask layer is formed, which exposes the substrate of the first trench region, as well as the barrier layer of the second trench region and the isolation region;

[0009] Using the barrier layer and the first mask layer as masks, the substrate is etched to form a first trench;

[0010] A second mask layer is formed that covers the first trench and the isolation area, and exposes the second trench area;

[0011] Using the first mask layer and the second mask layer as masks, the substrate is etched to form a second trench.

[0012] Optionally, forming a patterned barrier layer on the substrate includes:

[0013] A graphical barrier layer body is formed, the barrier layer body covering the second trench area and exposing the isolation area and the first trench area;

[0014] A barrier layer sidewall is formed on the side wall of the barrier layer body, and the barrier layer sidewall covers the isolation area;

[0015] The barrier layer consists of the barrier layer body and the barrier layer sidewalls.

[0016] Optionally, forming a second mask layer that covers the first trench and the isolation region and exposes the second trench region includes:

[0017] A sacrificial layer is formed to cover the first trench;

[0018] Remove the barrier layer body exposed by the first mask layer, and use the sacrificial layer and the remaining barrier layer as the second mask layer.

[0019] Optionally, the form of the patterned barrier layer body includes:

[0020] A barrier material layer is formed covering the surface of the substrate;

[0021] A patterned photoresist layer is formed on the barrier material layer;

[0022] Using the photoresist layer as a mask, the barrier material layer is patterned to form the barrier layer body.

[0023] Optionally, forming a barrier layer sidewall on the sidewall of the barrier layer body includes:

[0024] A sidewall material layer is formed to conformally cover the main body of the barrier layer;

[0025] Remove the sidewall material layers from the top of the barrier layer body and the top of the base, and use the remaining sidewall material layers as the sidewalls of the barrier layer.

[0026] Optionally, in the step of forming the sacrificial layer covering the first trench, the top surface of the sacrificial layer is not higher than the top surface of the barrier layer.

[0027] Optionally, after forming the second trench, the method further includes:

[0028] Remove the first mask layer and the second mask layer to expose the substrate and the first trench and the second trench located on the substrate;

[0029] A conductive interconnect layer is formed in the first trench and the second trench, wherein the top surface of the conductive interconnect layer is not higher than the surface of the substrate.

[0030] Optionally, the substrate includes a plurality of parallel first trench regions and second trench regions arranged alternately along a first direction, wherein, in a second direction, the first trench regions and second trench regions are arranged alternately, and the second direction is perpendicular to the first direction.

[0031] Optionally, in the first direction, a first trench area, a second trench area, and an isolation area located in the same row are considered as a trench area, wherein adjacent trench areas also include trench partition areas, and in the step of forming the patterned barrier layer, the barrier layer also covers at least a portion of the trench partition areas of the substrate.

[0032] Optionally, forming a second mask layer that covers the first trench and the isolation region and exposes the second trench region includes:

[0033] A second mask material layer is formed covering the side of the substrate where the barrier layer is formed;

[0034] The second mask material layer is patterned to form the second mask layer.

[0035] Optionally, the step of etching the substrate to form the second trench using the second mask layer and the first mask layer as masks includes:

[0036] Using the second mask layer and the first mask layer as masks, the barrier layer is etched to form a second initial trench that exposes the substrate;

[0037] The substrate exposed by the second initial trench is etched to form the second trench.

[0038] Optionally, the material of the first mask layer is one or more of TiN, AlN, or Al2O3, or the material of the first mask layer is one or more of SiC, SiN, SiON, or Si.

[0039] Optionally, the material of the barrier layer body is one or more of TiN, AlN, or Al2O3; the material of the barrier layer sidewall is one or more of TiN, AlN, Al2O3, SiC, SiN, SiON, or Si; and the material of the barrier layer body is different from the material of the barrier layer sidewall.

[0040] Optionally, the sacrificial layer is made of one or more of amorphous silicon, amorphous carbon, organic dielectric layer, or spin-coated carbon layer.

[0041] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0042] In this embodiment of the invention, the barrier layer does not simply isolate adjacent conductive trench regions in the first direction. Instead, it divides the conductive trench pattern into a first trench region and a second trench region, so that the barrier layer simultaneously covers the second trench region and the isolation region, which are interleaved with the first trench region. Compared to the barrier layer only covering the isolation region, this embodiment of the invention effectively reduces the pattern density by half, and the feature size becomes the sum of the second trench region and the isolation region, thereby reducing the process complexity and precision of forming the barrier layer. Furthermore, during the formation of the second trench after the formation of the first trench, the pattern density is also effectively reduced by half, thereby reducing the process complexity and precision. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the layout of conductive trench patterns in a semiconductor structure;

[0044] Figures 2 to 7 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention;

[0045] Figures 8 to 16 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming a semiconductor structure according to the present invention. Detailed Implementation

[0046] As the background technology shows, devices formed by existing processes still have performance issues. This paper analyzes the reasons for these poor device performance using a semiconductor structure formation method.

[0047] In existing technologies, conductive interconnect structures for connecting structures to be interconnected (e.g., gate, source / drain) need to be formed in semiconductor structures. Specifically, this can be achieved by forming conductive trenches above the structures to be interconnected, exposing the structures to be interconnected, and depositing conductive material within the conductive trenches, thereby forming conductive interconnect structures within the conductive trenches. However, reference... Figure 1 As shown, due to the small feature size and complex layout of the conductive trench 110, when forming the conductive trench 110, a patterned mask layer 120 is usually required to achieve lateral isolation between adjacent conductive trenches 110, and a patterned barrier layer 130 is used to achieve longitudinal isolation between adjacent conductive trenches 110 in the same row.

[0048] However, as the feature size of devices shrinks, the feature size of the conductive trench pattern shrinks further, and the pattern density gradually increases. The feature size of the barrier layer used to isolate adjacent conductive trenches also decreases accordingly, and the pattern density increases accordingly. This means that the process of forming the barrier layer requires repeated photolithography and etching processes to meet the requirements of the corresponding feature size and pattern density.

[0049] Clearly, existing technologies are complex and require high precision.

[0050] In an embodiment of the present invention, a method for forming a semiconductor structure is provided. The method includes: providing a substrate, the substrate including a first trench region and a second trench region arranged alternately along a first direction, and an isolation region located between the first trench region and the second trench region; forming a patterned barrier layer on the substrate, the barrier layer covering the second trench region and the isolation region, and exposing the first trench region; forming a patterned first mask layer, the first mask layer exposing the substrate of the first trench region, and the barrier layer of the second trench region and the isolation region; etching the substrate using the barrier layer and the first mask layer as masks to form a first trench; forming a second mask layer covering the first trench and the isolation region and exposing the second trench region; and etching the substrate using the first mask layer and the second mask layer as masks to form a second trench.

[0051] As can be seen, in this embodiment of the invention, the barrier layer does not simply isolate adjacent conductive trench regions in the first direction. Instead, it divides the conductive trench pattern into a first trench region and a second trench region, so that the barrier layer simultaneously covers the second trench region and the isolation region, which are interleaved with the first trench region. Compared with the barrier layer only covering the isolation region, this embodiment of the invention effectively reduces the pattern density by half, and the feature size becomes the sum of the second trench region and the isolation region, thereby reducing the process complexity and precision of forming the barrier layer. Furthermore, during the formation of the second trench after the formation of the first trench, the pattern density is also effectively reduced by half, thereby reducing the process complexity and precision.

[0052] It should be noted that, in the optional example, the barrier layer is formed by combining two structures, namely, forming a barrier layer body covering the second trench area and a barrier layer sidewall covering the longitudinal isolation area. This allows the second mask layer, which exposes the second trench area, to be obtained directly by removing the barrier layer body, thereby simplifying the process steps and reducing the process complexity.

[0053] To make the above-mentioned objectives, features and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0054] Figures 2 to 7 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0055] refer to Figure 2A substrate 200 is provided, the substrate 200 including a first trench region 201 and a second trench region 202 arranged alternately along a first direction X, and an isolation region 203 located between the first trench region and the second trench region;

[0056] The first trench region 201 and the second trench region 202 are used to form conductive trenches. The division of the first trench region 201 and the second trench region 202 is used to distinguish adjacent trench regions, so that conductive trenches at different positions of adjacent trench regions can be formed sequentially in this embodiment of the invention, thereby reducing the density of the mask pattern during the formation of conductive trenches.

[0057] It is understood that the first trench region and the second trench region may differ only in their relative positions and not in their structural form. In other examples, the first trench region and the second trench region may also have structural differences, which are not specifically limited here.

[0058] Understandably, in the process of reducing pattern density, adjacent trench areas can be divided into first trench areas and second trench areas to reduce the pattern density to half of its original value. In some other examples, three adjacent trench areas in the first direction can be divided into first trench areas, second trench areas, and third trench areas respectively, so that conductive trenches can be formed in three stages. This reduces the pattern density to one-third of its original value each time conductive trenches are formed, thereby further reducing process precision and process difficulty.

[0059] In this embodiment of the invention, the trench area is divided into a first trench area 201 and a second trench area 202 as an example for explanation.

[0060] The first direction is the extension direction of the trench area. In this extension direction, a plurality of trench areas are provided at intervals, and the adjacent trench areas are isolated areas, thereby realizing the spacing between the trench areas.

[0061] Optionally, in this embodiment of the invention, the substrate may include a plurality of parallel first trench regions 201 and second trench regions 202 arranged alternately along the first direction X, as shown in the reference. Figure 2Taking the first direction X as the lateral direction as an example, in the first direction, a first trench area 201, a second trench area 202 and an isolation area 203 located in the same row constitute a trench area 20. In this embodiment of the invention, the substrate may include multiple rows of laterally extending trench areas 20, and a trench partition area 204 is also included between adjacent trench areas. In the second direction Y (i.e., the longitudinal direction in this example) which is perpendicular to the first direction, the first trench area 201 and the second trench area 202 are arranged alternately, so that adjacent trench areas are formed sequentially in the second direction Y, which can reduce the density of the mask pattern during the formation of conductive trenches in the second direction Y.

[0062] In this embodiment of the invention, the substrate may include a substrate, a gate structure located on the substrate, and doped structures located between the gate structures. The substrate provides support for other structures. The substrate material may be silicon, germanium, silicon carbide, gallium arsenide, or indium gallium phosphate. Alternatively, the substrate may be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The gate structure serves as the gate of a device structure within the substrate to control the device. The doped structure serves as the source / drain structure of the device structure within the substrate, working together with the gate structure to control the device. An interlayer dielectric layer is formed on the gate structure and the doped structure. The first trench region and the second trench region define the locations of the gate structure and / or doped structure to be exposed, thereby forming a first trench and a second trench penetrating the interlayer dielectric layer at corresponding locations to expose the gate structure and / or doped structure.

[0063] It should be noted that the above-described substrate structure is only an optional example. In other embodiments of the present invention, the substrate may be other types of structures, and the substrate may contain embedded electrical connection structures, which are exposed by forming conductive trenches.

[0064] refer to Figure 3 A patterned barrier layer 210 is formed on the substrate, the barrier layer 210 covering the second trench region 202 and the isolation region 203, exposing the first trench region 201;

[0065] The first trench region 201 of the substrate is exposed by covering the second trench region 202 and the isolation region 203 of the substrate with the barrier layer 210, so that the conductive trench of the first trench region is formed first in the embodiment of the present invention, and the conductive trench of the second trench region is formed after the conductive trench of the first trench region is formed.

[0066] The material of the barrier layer 210 can be TiN, AlN or Al2O3, or one or more of SiC, SiN, SiON or Si.

[0067] Specifically, the formation process of the barrier layer 210 may include: forming a barrier material layer covering the surface of the substrate, forming a patterned photoresist layer on the barrier material layer; and using the photoresist layer as a mask to pattern the barrier material layer, thereby forming the barrier layer.

[0068] The photoresist layer can be either positive or negative photoresist, formed through a photolithography process.

[0069] In this embodiment of the invention, the pattern density of the barrier layer 210 is low, and the feature size of the pattern is the sum of the feature sizes of the isolation region and the second trench region, thus the feature size is large. Therefore, the photoresist layer in this embodiment of the invention can preferably form the corresponding pattern through only one photolithography process, without the need for multiple photolithography processes to form a pattern with high density and small feature size.

[0070] In this embodiment of the invention, the substrate includes a plurality of parallel first trench regions and second trench regions arranged alternately along a first direction. That is, when the substrate includes a plurality of parallel trench regions 20, a trench partition region 204 is also included between adjacent trench regions. The barrier layer can also cover at least part of the trench partition region 204 of the substrate, thereby further expanding the feature size and reducing the process difficulty.

[0071] refer to Figure 4 A patterned first mask layer 220 is formed, which exposes the substrate of the first trench region, as well as the barrier layer 210 of the second trench region and the isolation region.

[0072] Optionally, taking a first direction and a second direction defined as mutually perpendicular on the substrate surface as an example, the first trench region and the second trench region are arranged alternately along the first direction X, and the first mask layer is used to define the positions of the first trench region and the second trench region in the second direction Y.

[0073] by Figure 4 Taking the first direction X as the horizontal direction and the second direction Y as the vertical direction as an example, the first trench region 201 and the second trench region 202 are arranged alternately in the horizontal direction, and the first mask layer 220 is used to define the position of the first trench region 201 and the second trench region 202 in the vertical direction. It can be understood that when there are multiple rows of parallel trench regions, the first mask layer 220 covers the trench partition region 204 to achieve lateral isolation between adjacent rows.

[0074] It is understood that when the barrier layer 210 covers part of the trench partition area 204, the first mask layer 220 simultaneously covers the barrier layer 210 of the trench partition area 204.

[0075] Optionally, when the first mask layer 220 is used only to expose the substrate 200 of the first trench region and the barrier layer 210 of the second trench region and the isolation region, the first mask layer only exposes the substrate 200 of the first trench region and the barrier layer 210 of the second trench region and the isolation region, covering other areas of the substrate.

[0076] Optionally, the first mask layer 220 can be a hard mask layer. Correspondingly, the material of the first mask layer can be one or more of titanium nitride (TiN), aluminum nitride (AlN), or aluminum oxide (Al2O3), or one or more of titanium nitride (TiN), aluminum nitride (AlN), aluminum oxide (Al2O3), silicon carbide (SiC), silicon nitride (SiN), silicon oxynitride (SiON), or silicon (Si). When the first mask layer is made of multiple materials, the corresponding structure can be a multilayer structure of multiple materials.

[0077] refer to Figure 5 Using the barrier layer 210 and the first mask layer 220 as masks, the substrate is etched to form the first trench 230;

[0078] After the barrier layer 210 and the first mask layer 220 are formed, only the first trench region 201 is exposed on the substrate, thereby using the barrier layer 210 and the first mask layer 220 as a mask to etch the substrate 200 and form the first trench 230.

[0079] Optionally, the substrate can be etched using wet etching, dry etching, or a combination of wet and dry etching processes to form the first trench 230.

[0080] refer to Figure 6 A second mask layer 240 is formed that covers the first trench and the isolation area 203 and exposes the second trench area 202;

[0081] The second mask layer 240 is used as a mask to expose the second trench region 202, thereby enabling the etching of the second trench region 202.

[0082] The second mask layer 240 can be a photoresist layer, such as positive or negative photoresist, and is patterned by photolithography to expose the second trench region 202. Alternatively, the second mask layer can be a layer structure different from the barrier layer material, thereby using the second mask layer and the first mask layer as masks to etch the exposed barrier layer and substrate.

[0083] Specifically, forming a second mask layer that covers the first trench and the isolation area and exposes the second trench area includes: forming a second mask material layer that covers the side of the substrate where the barrier layer is formed; and patterning the second mask material layer to form the second mask layer.

[0084] refer to Figure 7 Using the first mask layer and the second mask layer as masks, the substrate is etched to form a second trench;

[0085] In this embodiment, after the second mask layer is formed, a barrier layer is also formed on the exposed second trench area. Accordingly, in this embodiment, the barrier layer exposed by the second mask layer is removed first.

[0086] Specifically, using the second mask layer and the first mask layer as masks, etching the substrate to form a second trench includes: using the second mask layer and the first mask layer as masks, etching the barrier layer to form a second initial trench exposing the substrate; and etching the substrate exposed by the second initial trench to form a second trench.

[0087] Optionally, the barrier layer and the substrate can be etched using wet etching, dry etching, or a combination of wet and dry etching processes.

[0088] In this embodiment of the invention, the barrier layer does not simply isolate adjacent conductive trenches in the same extending direction, but simultaneously covers the second trench area and the isolation area, which are staggered with the first trench area. This is equivalent to reducing the pattern density by half, and the feature size becomes the sum of the second trench area and the isolation area, thereby reducing the process complexity and precision of forming the barrier layer. Furthermore, during the formation of the second trench after the formation of the first trench, the pattern density is also effectively halved, thereby reducing the process complexity and precision.

[0089] In another embodiment of the present invention, a method for forming a semiconductor structure is also provided. This method forms different structures in different regions when forming a barrier layer, thereby exposing the second trench region by removing the structure located in the second trench region and retaining the structure in the isolation region.

[0090] Specifically, Figures 8 to 16 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0091] refer to Figure 8 A substrate 300 is provided, the substrate 300 including a first trench region 301 and a second trench region 302 arranged alternately along a first direction X, and an isolation region 303 located between the first trench region 301 and the second trench region 302;

[0092] Optionally, in this embodiment of the invention, the substrate may include a plurality of parallel first trench regions 301 and second trench regions 302 arranged alternately along the first direction X, as shown in the reference. Figure 8 Taking the first direction X as the lateral direction as an example, in the first direction, a first trench area 301, a second trench area 302 and an isolation area 303 located in the same row constitute a trench area 30. In this embodiment of the invention, the substrate may include multiple rows of laterally extending trench areas 30, and a trench partition area 304 is also included between adjacent trench areas. In the second direction Y (i.e., the longitudinal direction in this example) which is perpendicular to the first direction, the first trench area 301 and the second trench area 302 are arranged alternately, so that adjacent trench areas are formed sequentially in the second direction Y, which can reduce the density of the mask pattern during the formation of conductive trenches in the second direction Y.

[0093] refer to Figure 9 A patterned barrier layer 310 is formed on the substrate, the barrier layer 310 covering the second trench region 302 and the isolation region 303, exposing the first trench region 301;

[0094] In this embodiment, a barrier layer body 311 can be formed in the second trench region 302 and a barrier layer sidewall 312 can be formed in the isolation region 303, thereby forming barrier layers with different structures in different regions. In subsequent steps, the layers can be etched according to different structures, and then used as a second mask layer to expose the second trench region, without having to add another layer of structure as a second mask layer.

[0095] It should be noted that, given the increasingly smaller feature size of the isolation zone, using a sidewall structure to cover the isolation zone can meet the requirements of the small feature size of the isolation zone, and also adapt to the layout requirements of the trench area and the isolation zone.

[0096] Specifically, the steps for forming a graphical barrier layer may include:

[0097] A graphical barrier layer body 311 is formed, which covers the second trench area and exposes the isolation area 303 and the first trench area 301.

[0098] The barrier layer body is used to cover the first trench area. Optionally, when the substrate has multiple rows of trench areas, the barrier layer body can also cover at least part of the trench partition area 304, thereby increasing the feature size of the barrier layer body and reducing the process difficulty and process precision of forming the barrier layer body.

[0099] The barrier layer body 311 is made of one or more of titanium nitride (TiN), aluminum nitride (AlN), or aluminum oxide (Al2O3).

[0100] Specifically, the formation process of the barrier layer body 311 may include: forming a barrier body material layer covering the surface of the substrate; forming a patterned photoresist layer on the barrier body material layer; using the photoresist layer as a mask to pattern the barrier body material layer and form the barrier layer body.

[0101] The barrier material layer can be formed by a deposition process; the photoresist layer can be made of positive or negative photoresist, and the patterned photoresist layer can be formed by a photolithography process; the patterned barrier material layer can be formed by an etching process to form the barrier layer body.

[0102] Next, a barrier layer sidewall 312 is formed on the sidewall of the barrier layer body 311, and the barrier layer sidewall 312 covers the isolation area;

[0103] The barrier layer 310 is defined by the barrier layer body 311 and the barrier layer sidewall 312.

[0104] The material of the barrier layer sidewall 312 can be one or more of titanium nitride (TiN), aluminum nitride (AlN), aluminum oxide (Al2O3), silicon carbide (SiC), silicon nitride (SiN), silicon oxynitride (SiON), or silicon (Si), and the material of the barrier layer sidewall 312 is different from the material of the barrier layer body.

[0105] Specifically, forming a barrier layer sidewall on the sidewall of the barrier layer body includes: forming a sidewall material layer that conformally covers the barrier layer body; removing the sidewall material layer from the top of the barrier layer body and the top of the substrate, and using the remaining sidewall material layer as the barrier layer sidewall.

[0106] The sidewall material layer can be formed by deposition process, and the sidewall material layer on the top of the barrier layer body and the top of the substrate can be removed by dry etching process.

[0107] refer to Figure 10 A patterned first mask layer 320 is formed, which exposes the substrate of the first trench region, as well as the barrier layer of the second trench region and the isolation region.

[0108] When the barrier layer 310 covers part of the trench partition area 304, the first mask layer 320 simultaneously covers the barrier layer 310 of the trench partition area 304.

[0109] refer to Figure 11 Using the barrier layer and the first mask layer 320 as masks, the substrate is etched to form the first trench 330;

[0110] Optionally, the substrate can be etched using wet etching, dry etching, or a combination of wet and dry etching processes to form the first trench 330.

[0111] refer to Figures 12 to 13 A second mask layer is formed that covers the first trench and the isolation area, and exposes the second trench area.

[0112] Optionally, the process of forming the second mask layer may include:

[0113] refer to Figure 12 A sacrificial layer 340 is formed covering the first trench;

[0114] By forming the sacrificial layer 340 to cover the first trench, the first trench is protected and prevented from being damaged in subsequent processes.

[0115] The sacrificial layer 340 can be made of easily removable materials such as amorphous silicon, amorphous carbon, organic dielectric layer (ODL), or spin-coated carbon layer, so that the sacrificial layer 340 can be removed in subsequent processes to expose the first trench.

[0116] The top surface of the sacrificial layer 340 is not higher than the top surface of the barrier layer 310, thereby exposing the barrier layer 310 so that the second trench region 302 can be exposed by subsequently removing part of the barrier layer. Furthermore, the top surface of the sacrificial layer 340 is not lower than the top surface of the substrate, thereby completely covering the first trench and protecting the first trench from damage.

[0117] Specifically, the formation process of the sacrificial layer 340 may include: forming a sacrificial material layer covering the side of the substrate having the first trench; removing a portion of the thickness of the sacrificial material layer until the remaining sacrificial material layer exposes the barrier layer and the first mask layer, with the remaining sacrificial material layer serving as the sacrificial layer.

[0118] refer to Figure 13 Remove the barrier layer body exposed by the first mask layer, and use the sacrificial layer 340 and the remaining barrier layer as the second mask layer.

[0119] Since the barrier layer body covers the second trench area 302 and the barrier layer sidewall 312 covers the isolation area, by removing the barrier layer body exposed by the first mask layer 320, the substrate of the second trench area is exposed, while the barrier layer sidewall 312 is retained to protect the isolation area. In this example, the remaining barrier layer is the barrier layer sidewall 312.

[0120] Correspondingly, since the sacrificial layer 340 has already covered the first trench, the second trench can be etched by using the sacrificial layer 340 and the remaining barrier layer as the second mask layer.

[0121] Optionally, dry etching, wet etching, or a combination of dry and wet etching processes can be used to remove the barrier layer.

[0122] refer to Figure 14 Using the first mask layer 320 and the second mask layer (i.e., the sacrificial layer 340 and the remaining barrier layer sidewall 312) as masks, the substrate is etched to form the second trench 350.

[0123] Optionally, the substrate can be etched using wet etching, dry etching, or a combination of wet and dry etching processes to form the second trench 350.

[0124] refer to Figure 15 Remove the first mask layer and the second mask layer to expose the substrate 300 and the first trench 330 and the second trench 350 located on the substrate;

[0125] By exposing the substrate 300 and the first trench 330 and the second trench 350 located on the substrate, a corresponding conductive interconnect layer is formed in the first trench 330 and the second trench 350.

[0126] Optionally, etching or stripping processes can be used to remove the first mask layer and the second mask layer.

[0127] refer to Figure 16 A conductive interconnect layer 360 is formed in the first trench and the second trench, wherein the top surface of the conductive interconnect layer 360 is not higher than the surface of the substrate.

[0128] The material of the conductive interconnect layer 360 can be one or more of Al, Cu, Ru, Ag, Au, Pt, Ni, Ti, Co or W.

[0129] Specifically, the formation process of the conductive interconnect layer 360 may include: forming a conductive interconnect material layer that completely covers the first trench and the second trench; etching away a portion of the conductive interconnect material layer until the top surface of the substrate is exposed, with the remaining conductive interconnect material layer in the first trench and the second trench serving as the conductive interconnect layer.

[0130] It should be noted that the top surface of the conductive interconnect layer 360 is not higher than the top surface of the substrate 300, and preferably lower than the top surface of the substrate 300, so as to avoid short circuits between adjacent conductive interconnect layers 360.

[0131] In the above embodiments of the present invention, by forming different structures in different regions when forming the barrier layer, the second trench region can be exposed by removing the structure located in the second trench region and retaining the structure in the isolation region, thereby simplifying the formation process of the second mask layer and reducing the process cost.

[0132] The foregoing describes multiple embodiments of the present invention. The optional methods described in each embodiment can be combined and cross-referenced without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed or made public by the present invention.

[0133] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the embodiments of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises: providing a substrate, the substrate comprising first trench regions and second trench regions staggered along a first direction, and isolation regions between the first trench regions and the second trench regions; wherein the first direction is the extending direction of the trench regions; the first trench regions and the second trench regions are used to form conductive trenches; forming a patterned barrier layer on the substrate, the barrier layer covering the second trench regions and the isolation regions, and exposing the first trench regions; forming a patterned first mask layer, the first mask layer exposing the substrate of the first trench regions, and the barrier layer of the second trench regions and the isolation regions; using the barrier layer and the first mask layer as masks, etching the substrate to form first trenches; forming a second mask layer covering the first trenches and the isolation regions, and exposing the second trench regions; using the first mask layer and the second mask layer as masks, etching the substrate to form second trenches.

2. The method of forming a semiconductor structure of claim 1, wherein, The method of forming a patterned barrier layer on the substrate comprises: forming a patterned barrier layer body, the barrier layer body covering the second trench regions, and exposing the isolation regions and the first trench regions; forming a barrier layer sidewall on the sidewall of the barrier layer body, the barrier layer sidewall covering the isolation regions; wherein the barrier layer body and the barrier layer sidewall are used as the barrier layer.

3. The method of forming a semiconductor structure of claim 2, wherein, The method of forming a second mask layer covering the first trenches and the isolation regions, and exposing the second trench regions comprises: forming a sacrificial layer covering the first trenches; removing the barrier layer body exposed by the first mask layer, and using the sacrificial layer and the remaining barrier layer as the second mask layer.

4. The method of forming a semiconductor structure of claim 2, wherein, The method of forming a patterned barrier layer body comprises: forming a barrier body material layer covering the surface of the substrate; forming a patterned photoresist layer on the barrier body material layer; using the photoresist layer as a mask, patterning the barrier body material layer to form the barrier layer body.

5. The method of forming a semiconductor structure of claim 2, wherein, The method of forming a barrier layer sidewall on the sidewall of the barrier layer body comprises: forming a sidewall material layer conformally covering the barrier layer body; removing the sidewall material layer on the top of the barrier layer body and the top of the substrate, and using the remaining sidewall material layer as the barrier layer sidewall.

6. The method of forming a semiconductor structure of claim 3, wherein, In the step of forming a sacrificial layer covering the first trenches, the top surface of the sacrificial layer is not higher than the top surface of the barrier layer.

7. The method of forming a semiconductor structure of claim 1, wherein, After forming the second trenches, the method further comprises: removing the first mask layer and the second mask layer, and exposing the substrate and the first trenches and the second trenches on the substrate; forming a conductive interconnection layer in the first trenches and the second trenches, the top surface of the conductive interconnection layer being not higher than the surface of the substrate.

8. The method of forming a semiconductor structure of claim 1, wherein, The substrate comprises a plurality of first trench regions and second trench regions staggered along a first direction in parallel, wherein in a second direction, the first trench regions and the second trench regions are staggered, and the second direction is perpendicular to the first direction.

9. The method of forming a semiconductor structure of claim 8, wherein, In the first direction, the first trench region, the second trench region and the isolation region located in the same row are taken as one trench region, and a trench partition region is further included between adjacent trench regions. In the step of forming the patterned barrier layer, the barrier layer also covers at least part of the trench partition region of the substrate.

10. The method of forming a semiconductor structure of claim 1, wherein, The forming of the second mask layer covering the first trench and the isolation region and exposing the second trench region comprises: forming a second mask material layer covering the side of the substrate on which the barrier layer is formed; patterning the second mask material layer to form a second mask layer.

11. The method of forming a semiconductor structure of claim 10, wherein, The etching of the substrate with the second mask layer and the first mask layer as masks to form a second trench comprises: etching the barrier layer with the second mask layer and the first mask layer as masks to form a second initial trench exposing the substrate; etching the substrate exposed by the second initial trench to form a second trench.

12. The method of forming a semiconductor structure of claim 1, wherein, The material of the first mask layer is one or more of titanium nitride, aluminum nitride or aluminum trioxide, or the material of the first mask layer is one or more of silicon carbide, silicon nitride, silicon oxynitride or silicon.

13. The method of forming a semiconductor structure of claim 2, wherein, The material of the barrier layer body is one or more of titanium nitride, aluminum nitride or aluminum trioxide; the material of the barrier layer side wall is one or more of titanium nitride, aluminum nitride, aluminum trioxide, silicon carbide, silicon nitride, silicon oxynitride or silicon; and the material of the barrier layer body is different from the material of the barrier layer side wall.

14. The method of forming a semiconductor structure of claim 3, wherein, The material of the sacrificial layer is one or more of amorphous silicon, amorphous carbon, an organic dielectric layer or a spin-on carbon layer.

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