Method for manufacturing a radio frequency high electron mobility transistor, transistor and electronic device

Abstract

The application discloses a radio frequency high electron mobility transistor manufacturing method, a transistor and an electronic device. In the radio frequency high electron mobility transistor manufacturing method, a hard dielectric barrier layer structure is formed on a substrate through lithography and etching, and source contact areas and drain contact areas are exposed on both sides of the hard dielectric barrier layer structure. The hard dielectric barrier layer structure is used for determining a gate region. Because of the existence of the hard dielectric barrier layer structure, self-alignment effect can be realized in subsequent N-type doping injection and deposition of a first metal layer, so that the alignment times are reduced. A groove structure is formed on the side of a second dielectric layer, and the second dielectric layer, a third dielectric layer and the first metal layer deposited thereon are quickly stripped through wet stripping. In this way, a sufficient interval distance can be kept from the gate region to the source and drain regions, the alignment error and the access resistance of the source and drain are greatly reduced, and finally the technical effect of improving the radio frequency performance of the radio frequency high electron mobility transistor is achieved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of transistor manufacturing, and particularly relates to a radio frequency high electron mobility transistor manufacturing method, a transistor and an electronic device. BACKGROUND

[0002] Nowadays, duplex signals are very common (for example, low-band and mid-band / high-band signals), but 5G has brought signal routing complexity to a new level. Given that the maximum number of antennas is starting to stabilize, ultra-high-band frequencies and dual connectivity uplink requirements will require substantial changes in the way signals are routed to antennas, so it is essential to design devices in the radio frequency front-end system architecture of future 5G terminals, for example, the demand for radio frequency high electron mobility transistors is increasing.

[0003] In the prior art, the manufacturing process of the radio frequency high electron mobility transistor has steps that need to be aligned multiple times. Since each alignment needs to reserve a space position, multiple alignments will not only make the manufacturing process of the radio frequency high electron mobility transistor have a large number of steps, but also have the problems of alignment error and source-drain access resistance, which ultimately affect the radio frequency performance of the radio frequency high electron mobility transistor. SUMMARY

[0004] In order to overcome the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a radio frequency high electron mobility transistor manufacturing method, a transistor and an electronic device, which aims to solve the technical problem that the existing radio frequency high electron mobility transistor manufacturing process needs to be aligned multiple times.

[0005] In order to achieve the purpose of the present application, the technical scheme adopted by the present application is as follows:

[0006] A radio frequency high electron mobility transistor manufacturing method, comprising the following steps:

[0007] Depositing a first dielectric layer, a second dielectric layer and a third dielectric layer on a substrate in sequence;

[0008] Performing photoetching and etching on the first dielectric layer, the second dielectric layer and the third dielectric layer to form a source contact area and a drain contact area;

[0009] Performing N-type doping injection on the source contact area and the drain contact area;

[0010] Performing high-temperature activation on the N-type doping of the source contact area and the drain contact area;

[0011] Performing wet etching on the second dielectric layer after photoetching to form a groove structure;

[0012] Depositing a first metal layer;

[0013] wet stripping the second dielectric layer and the third dielectric layer;

[0014] forming a gate contact layer at the position of the first dielectric layer.

[0015] Further, in the step of forming the gate contact layer at the position of the gate window, the following steps are included:

[0016] depositing a fourth dielectric layer;

[0017] performing photolithography and etching on the fourth dielectric layer to form a gate window;

[0018] depositing a fifth dielectric layer;

[0019] performing dry etching on the fifth dielectric layer to extend the gate window to the substrate;

[0020] forming a gate contact layer at the position of the gate window.

[0021] Further, in the step of forming the gate contact layer at the position of the gate window, the following steps are included:

[0022] depositing a sixth dielectric layer;

[0023] depositing a second metal layer at the position of the gate window;

[0024] performing etching and shaping on the second metal layer to form a gate contact layer.

[0025] Further, after the step of performing etching and shaping on the second metal layer to form the gate contact layer, the following steps are included:

[0026] performing photolithography and etching on the fourth dielectric layer and the sixth dielectric layer at the position of the source contact region to expose the first metal layer to form a drain contact layer;

[0027] performing photolithography and etching on the fourth dielectric layer and the sixth dielectric layer at the position of the drain contact region to expose the first metal layer to form a drain contact layer.

[0028] Further, the substrate includes, from bottom to top, a high-resistance silicon layer, a buffer layer, a gallium nitride layer, and an aluminum gallium nitride layer.

[0029] Further, in the step of forming the gate contact layer at the position of the gate window, the following steps are included:

[0030] depositing a second metal layer at the position of the gate window;

[0031] performing photolithography and etching on the second metal layer to form a Schottky gate contact layer.

[0032] Further, in the step of extending the gate window to the substrate by dry etching the fifth dielectric layer, the fifth dielectric layer is dry etched to form an inner spacer structure for determining the size of the gate.

[0033] Further, in the step of performing N-type doping injection on the source contact region and the drain contact region, the N-type doping is injected into the substrate of the source contact region and the drain contact region.

[0034] Correspondingly, the application also provides a transistor manufactured by the above-mentioned method for manufacturing a radio frequency high electron mobility transistor.

[0035] Correspondingly, the application also provides an electronic device comprising the above-mentioned transistor.

[0036] Compared with the prior art, the application has the following beneficial effects:

[0037] The application provides a method for manufacturing a radio frequency high electron mobility transistor. The first dielectric layer, the second dielectric layer and the third dielectric layer are formed into a hard dielectric barrier structure by photoetching and etching on the substrate, and the source contact region and the drain contact region are exposed on both sides of the hard dielectric barrier structure. The hard dielectric barrier structure is used to determine the gate region, and the source contact region and the drain contact region are exposed on the left and right sides of the hard dielectric barrier structure, respectively, so as to preliminarily form the source region, the drain region and the gate region. The N-type doping injection and the deposition of the first metal layer can be self-aligned due to the existence of the hard dielectric barrier structure, so as to reduce the number of alignment. The second dielectric layer in the hard dielectric barrier structure is wet etched, so that the side surface of the second dielectric layer forms a groove structure. The second dielectric layer and the third dielectric layer and the first metal layer deposited thereon can be quickly stripped by wet stripping through the groove structure after the completion of the foregoing steps, so as to keep a sufficient spacing distance from the gate region to the source and drain regions. The radio frequency high electron mobility transistor can be manufactured by only one alignment photoetching, the alignment error and the access resistance of the source and drain regions are greatly reduced, the number of alignment is reduced, the reserved redundancy size is reduced, the transistor size in the horizontal direction can be further shrunk under the same photoetching capacity, and the radio frequency performance of the radio frequency high electron mobility transistor is finally improved. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can also be obtained by those skilled in the art without any creative effort.

[0039] Figure 1 A flow chart of a method in an embodiment of the present application;

[0040] Figure 2 A structural schematic diagram after step S100 in an embodiment of the present application;

[0041] Figure 3 A structural schematic diagram after step S200 in an embodiment of the present application;

[0042] Figure 4 A structural schematic diagram after step S300 in an embodiment of the present application;

[0043] Figure 5 A structural schematic diagram after step S400 in an embodiment of the present application;

[0044] Figure 6 A structural schematic diagram after step S500 in an embodiment of the present application;

[0045] Figure 7 A structural schematic diagram after step S600 in an embodiment of the present application;

[0046] Figure 8 A structural schematic diagram after step S700 in an embodiment of the present application;

[0047] Figure 9 A structural schematic diagram after step S810 in an embodiment of the present application;

[0048] Figure 10 A structural schematic diagram after step S820 in an embodiment of the present application;

[0049] Figure 11 A structural schematic diagram after step S830 in an embodiment of the present application;

[0050] Figure 12 A structural schematic diagram after step S840 in an embodiment of the present application;

[0051] Figure 13 A structural schematic diagram after step S851 in an embodiment of the present application;

[0052] Figure 14 A structural schematic diagram after step S852 in an embodiment of the present application;

[0053] Figure 15 A structural schematic diagram after step S853 in an embodiment of the present application.

[0054] BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Reference Name Reference Name 1 Substrate 8 N-type doping 2 First dielectric layer 9 First metal layer 3 Second dielectric layer 10 Fourth dielectric layer 31 Recess structure 11 Gate window 4 Third dielectric layer 12 Fifth dielectric layer 5 Source contact region 13 Sixth dielectric layer 6 Drain contact region 14 Second metal layer 7 Gate contact layer

[0056] The objectives, features and advantages of the present application will be further illustrated in conjunction with the embodiments, with reference to the accompanying drawings. DETAILED DESCRIPTION

[0057] In order to more clearly understand the above objectives, features and advantages of the present application, the following will give a further detailed description of the present application with reference to the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict. In the following description, a large number of specific details are set forth in order to facilitate a full understanding of the present application. The described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work, fall within the scope of protection of the present application.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application.

[0059] Reference Figures 1-13 An embodiment of the present application provides a method for manufacturing a radio frequency high electron mobility transistor, characterized in that the method comprises the following steps:

[0060] The method for manufacturing a radio frequency high electron mobility transistor comprises the following steps:

[0061] Step S100, referring to Figure 2 A first dielectric layer 2, a second dielectric layer 3 and a third dielectric layer 4 are sequentially deposited on the substrate 1;

[0062] Specifically, the substrate 1 in the embodiment contains an epitaxial layer heterojunction, and a plurality of dielectric layers are deposited above the substrate 1. After lithography, the dielectric layers can form source openings, gate openings and drain openings, and the material selection of the dielectric layers is also suitable for the selection of materials conducive to the implementation of subsequent steps. In the embodiment, the first dielectric layer 2 and the third dielectric layer 4 are silicon nitride SiNx, and the second dielectric layer 3 is silicon dioxide SiO2. Therefore, the first dielectric layer 2, the second dielectric layer 3 and the third dielectric layer 4 form a sandwiched structure, and the silicon nitride SiNx can also be selected according to requirements.

[0063] Step S200, referring to Figure 3 The first dielectric layer 2, the second dielectric layer 3 and the third dielectric layer 4 are subjected to lithography and etching to form a source contact area 5 and a drain contact area 6;

[0064] Specifically, in the embodiment, the source contact region 5 and the drain contact region 6 are mainly photoetched and etched out, so that the contact layer of the source and the drain is processed in the region subsequently, and the remaining part of the first dielectric layer 2, the second dielectric layer 3 and the third dielectric layer 4 is the region of the gate contact layer 7 processed subsequently; thus, the effect of dividing the corresponding positions of the source, the drain and the gate is achieved.

[0065] In step S300, referring to FIG. 3, the N-type doping 8 is injected in the source contact region 5 and the drain contact region 6. Figure 4

[0066] Specifically, the substrate 1 includes, from bottom to top, a high-resistance silicon layer, a buffer layer, a gallium nitride layer and an aluminum gallium nitride layer; and in the embodiment, the N-type doping 8 is injected in the source contact region 5 and the drain contact region 6, that is, the injection is performed in the top layer of the substrate 1, that is, the aluminum gallium nitride layer. The N-type doping 8 injection mainly injects the doped atoms into the position of the silicon atoms in the single crystal silicon to replace the silicon atoms, and a high-temperature annealing process is further needed to activate the free electrons, so as to change the conductivity of the semiconductor material; thus, the type of the injected atoms can be selected according to the specific requirements. In the embodiment, a high-dose silicon atom injection is selected, and the aluminum gallium nitride layer in the source contact region 5 and the drain contact region 6 is injected. Since the dielectric structure composed of the remaining part of the first dielectric layer 2, the second dielectric layer 3 and the third dielectric layer 4 is retained in step 200, the dielectric structure has the effect of defining the boundary of the injection region, and the effect that the N-type doping 8 is not injected into the corresponding position of the gate during the injection process is achieved.

[0067] In step S400, referring to FIG. 4, the N-type doping 8 in the source contact region 5 and the drain contact region 6 is activated at high temperature. Figure 5

[0068] ​​Specifically, the embodiment mainly activates the N-type doping 8 at high temperature to activate free atoms of the N-type doping 8, wherein different doping atoms have different energy differences required to transition from the energy level inside the forbidden band to the conduction band or the valence band, and thus the corresponding high-temperature activation temperature needs to be determined according to the selected atom. In the embodiment, silicon atoms are taken as an example to select ohmic contact annealing 600C-30S to activate free electrons, so as to change the conductivity of the semiconductor material. At this time, the activation process will diffuse the atoms of the N-type doping 8, that is, the N-type doping 8 or the next layer such as the gallium nitride layer of the substrate 1 may be diffused, so that the aluminum gallium nitride layer and the gallium nitride layer of the substrate 1 finally obtain the conductivity. Then, the contact layer of the source and the drain is deposited on the surface of the N-type doping 8, so that the contact layer of the source and the drain and the substrate 1 still exist N-type doping 8 with conductivity. Thus, the problem of the source and the drain in the prior art is solved, the access resistance of the source and the drain is greatly reduced, and the technical effect of improving the key radio frequency performance is achieved.

[0069] Step S500, referring to Figure 6 The second medium layer 3 after lithography is subjected to wet etching to form a groove structure 31.

[0070] Specifically, the second medium layer 3 in the embodiment is subjected to wet etching to form the groove structure 31, that is, to form the undercut of the second medium layer 3. The wet etching is performed by using a wet etching solution to etch the groove structure 31 that meets the requirements according to the actual situation. The groove structure 31 is specifically a notch formed by inwardly recessing the second medium layer 3 relative to the first medium layer 2 and the third medium layer 4. The main function of the groove structure 31 is to prevent the metal from being deposited on the second medium layer 3 when the first metal layer 9 is deposited later. Because the deposition process is mostly metal evaporation, the metal is deposited from top to bottom. Due to the existence of the groove structure 31, the metal is deposited on the upper layer of the third medium layer 4 and the sidewall of the first medium layer 2 and the third medium. Because of the existence of the groove structure 31, the metal cannot be deposited on the sidewall of the second medium. If the groove structure 31 is not provided on the second medium layer 3, a small amount of metal may be deposited on the sidewall of the second medium layer 3. In the subsequent step, the second medium layer 3 needs to be subjected to wet stripping. Because the sidewall of the second medium layer 3 is deposited with metal, the second medium layer 3 cannot be subjected to wet stripping. The groove structure 31 in the embodiment makes it difficult for the metal to be deposited on the sidewall of the second medium layer 3, so that the solution can contact and dissolve the second medium layer 3 through the groove structure 31 during wet stripping, thereby achieving the effect of stripping.

[0071] Step S600, referring to Figure 7 The first metal layer 9 is deposited.

[0072] Specifically, in the embodiment, the metal evaporation process is used to form the source and drain metal deposition when depositing the first metal layer 9, which is deposited from top to bottom, so that the third dielectric layer 4, the upper layer of the source contact area 5 and the drain contact area 6 are deposited, and thus the remaining first dielectric layer 2, the second dielectric layer 3 and the third dielectric layer 4 protect the gate position and prevent the gate position from being deposited on the first metal layer 9, facilitating the subsequent step of forming the gate contact layer 7. The first metal layer 9 deposited on the upper layer of the source contact area 5 and the drain contact area 6 is in contact with the N-type impurities in the previous step, and finally forms the contact layer of the source and the drain. Thus, the problem of the source and the drain in the prior art is solved, and the technical effect of greatly reducing the access resistance of the source and the drain and improving the key radio frequency performance is achieved.

[0073] Step S700, referring to Figure 8 , the second dielectric layer 3 and the third dielectric layer 4 are removed by wet stripping;

[0074] Specifically, in the embodiment, the second dielectric layer 3 and the third dielectric layer 4 are not needed as finished products because the second dielectric layer 3 and the third dielectric layer 4 are used to prevent the first metal layer 9 from being deposited on the gate position, so the second dielectric layer 3 and the third dielectric layer 4 can be removed after the deposition of the first metal layer 9 is completed. The specific steps of wet stripping are as follows: wet etching is used for wet stripping, the wet etching solution contacts the second dielectric layer 3 through the groove structure 31 of the second dielectric layer 3, and the wet etching solution gradually dissolves the second dielectric layer 3. When the second dielectric layer 3 is dissolved and stripped, the first metal layer 9 deposited on the upper surface of the third dielectric layer 4 will be naturally stripped. In the embodiment, the wet etching solution used is a dilute hydrogen fluoride solution, for example, a BOE buffer etching solution. BOE is a mixture of HF and NH4F in different proportions. HF is the main etching solution, and NH4F is used as a buffer. The concentration of [H+] is fixed by using NH4F to maintain a certain etching rate. HF can etch glass and any material containing silicon stone, which can effectively remove the silicon dioxide of the second dielectric layer 3.

[0075] Step S800, referring to Figures 9-15 , the gate contact layer 7 is formed at the position of the first dielectric layer 2.

[0076] Specifically, the contact layer of the source and the drain is completed through the previous steps, and only the gate structure at the position of the first dielectric layer 2 is not completed, so this step is to form the gate contact layer 7 at the position of the first dielectric layer 2. From this, the core device structure is completed, including the three contact layers of the source, the gate and the drain.

[0077] Further, in the step of forming the gate contact layer 7 at the position of the first dielectric layer 2, the following steps are included:

[0078] Step S810, referring to Figure 9 deposits a fourth dielectric layer 10;

[0079] Step S820, referring to Figure 10 performs photolithography and etching on the fourth dielectric layer 10 to form a gate window 11;

[0080] Step S830, referring to Figure 11 deposits a fifth dielectric layer 12;

[0081] Step S840, referring to Figure 12 performs dry etching on the fifth dielectric layer 12 to extend the gate window 11 to the substrate 1;

[0082] Step S850, referring to Figures 13-15 forms a gate contact layer 7 at the position of the gate window 11.

[0083] Specifically, in the embodiment, first, the fourth dielectric layer 10 is deposited, which is silicon dioxide SiO2, and is uniformly deposited on the uppermost layer of the current structure; then, photolithography and etching are performed on the fourth dielectric layer 10 to form the gate window 11, which is connected to the first dielectric layer 2, and the gate window 11 is used as the main position for forming the gate contact layer 7 later; then, the fifth dielectric layer 12 is deposited, which has the same material as the first dielectric layer 2, and is uniformly deposited on the uppermost layer of the current structure, and since the gate window 11 exists, the width of the gate window 11 after the deposition of the fifth dielectric layer 12 can be controlled by controlling the deposition thickness of the fifth dielectric layer 12; then, dry etching is performed on the fifth dielectric layer 12 to extend the gate window 11 to the substrate 1, which performs dry etching on the fifth dielectric layer 12 on the fourth dielectric layer 10 and a part of the fifth dielectric layer 12 in the gate window 11 and stops at the substrate 1, i.e., the gate window 11 is extended to the substrate 1, and finally, the inner sidewall of the fifth dielectric layer 12 is formed in the gate window 11, and since the inner sidewall is formed by deposition, it is self-aligned during the formation process, which realizes the technical effects of reducing the size of the gate and ensuring sufficient spacing distance between the gate and the source and the drain; finally, the gate contact layer 7 is formed at the position of the gate window 11, and thus the core device structure is completed, including the three contact layers of the source, the gate and the drain.

[0084] Further, the step of forming the gate contact layer 7 at the position of the gate window 11 includes the following steps:

[0085] Step S851, referring to Figure 13 deposits a sixth dielectric layer 13;

[0086] Step S852, referring to Figure 14depositing a second metal layer 14 at the position of the gate window 11;

[0087] In step S853, referring to Figure 15 The second metal layer 14 is etched to form the gate contact layer 7.

[0088] Specifically, the embodiment mainly discloses a specific process of forming the gate contact layer 7. First, a sixth dielectric layer 13 is deposited, which is used as the gate contact layer 7 and deposited by atomic layer deposition method. Al2O3, SiNx or AlN can be used, with a thickness of 100 angstroms. The sixth dielectric layer 13 is also uniformly deposited on the uppermost layer of the current structure. Then, a second metal layer 14 is deposited at the position of the gate window 11. The second metal layer 14 extends outward from the bottom of the gate window 11 to both sides of the external gate window 11 to form a predetermined thickness. Finally, the second metal layer 14 is etched to form the gate contact layer 7 for connecting with external electronic devices. Thus, the core device structure, the gate contact layer 7, is completed.

[0089] Further, after the step of etching the second metal layer 14 to form the gate contact layer 7, the following steps are included:

[0090] The fourth dielectric layer 10 and the sixth dielectric layer 13 are subjected to photoetching and etching at the position of the source contact area 5 to expose the first metal layer 9 to form the drain contact layer.

[0091] The fourth dielectric layer 10 and the sixth dielectric layer 13 are subjected to photoetching and etching at the position of the drain contact area 6 to expose the first metal layer 9 to form the drain contact layer.

[0092] Specifically, since the fourth dielectric layer 10 and the sixth dielectric layer 13 in the previous steps are deposited, they will also be deposited on the first metal layer 9. Therefore, the fourth dielectric layer 10 and the sixth dielectric layer 13 need to be subjected to photoetching and etching so that the first metal layer 9 can be connected with external electronic devices. The specific steps are as follows: the fourth dielectric layer 10 and the sixth dielectric layer 13 are subjected to photoetching and etching at the position of the source contact area 5 to expose the first metal layer 9 to form the drain contact layer; the fourth dielectric layer 10 and the sixth dielectric layer 13 are subjected to photoetching and etching at the position of the drain contact area 6 to expose the first metal layer 9 to form the drain contact layer. Finally, the core device structure, the source contact layer and the drain contact layer, is completed.

[0093] Further, in the step of forming the gate contact layer 7 at the position of the gate window 11, the following steps are included:

[0094] A second metal layer 14 is deposited at the position of the gate window 11;

[0095] The second metal layer 14 is subjected to photoetching and etching to form the Schottky gate contact layer 7.

[0096] Specifically, after the step S850, the step S851 and the following steps are not adopted to form the new gate dielectric layer, but the second metal layer 14 is directly deposited on the substrate 1, and then photoetching and etching are performed to form the Schottky contact gate contact layer 7.

[0097] Correspondingly, the application further provides a transistor, which is manufactured by the above-mentioned method for manufacturing a radio frequency high electron mobility transistor.

[0098] Correspondingly, the application further provides an electronic device, which comprises the above-mentioned transistor.

[0099] Obviously, those skilled in the art should understand that the above-mentioned modules or steps of the application can be realized by a general computing device, which can be concentrated on a single computing device or distributed on a network composed of multiple computing devices, and optionally, they can be realized by program codes executable by the computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in different order, or they can be manufactured into individual integrated circuit modules, or multiple modules or steps can be manufactured into a single integrated circuit module. Thus, the application is not limited to any specific combination of hardware and software.

[0100] It should be noted that other contents of the application disclosed in the method for manufacturing a radio frequency high electron mobility transistor, the transistor and the electronic device can be referred to the prior art, and will not be described here.

[0101] The above-mentioned is only the optional embodiment of the application, and does not limit the application in any form, so any modification, equivalent change and modification of the above-mentioned embodiment according to the technical essence of the application, which does not deviate from the technical solution content of the application, still belongs to the range of the technical solution of the application.

Claims

1. A method for fabricating a radio frequency high electron mobility transistor, characterized in that, Includes the following steps: A first dielectric layer, a second dielectric layer, and a third dielectric layer are sequentially deposited on a substrate; Photolithography and etching are performed on the first dielectric layer, the second dielectric layer and the third dielectric layer to form a hard dielectric barrier layer structure, and source contact region and drain contact region are exposed on both sides of the hard dielectric barrier layer structure. N-type doping implantation is performed in the source contact region and the drain contact region; The N-type doping of the source and drain contact regions is activated at high temperature; Wet etching is performed on the second dielectric layer in the hard dielectric barrier layer structure to form a groove structure on the side of the second dielectric layer. A first metal layer is deposited, such that the metal contact region formed by the source contact region and the drain contact region is self-aligned with the N-type doped region, and no metal is deposited on the side of the second dielectric layer in the hard dielectric barrier layer structure. The second dielectric layer and the third dielectric layer, as well as the first metal layer deposited thereon, are stripped off by a wet process; Deposition of the fourth dielectric layer; The fourth dielectric layer is photolithographically and etched to form a gate window; Deposition of the fifth medium layer; Dry etching is performed on the fifth dielectric layer to extend the gate window to the substrate; A gate contact layer is formed at the location of the gate window.

2. The method for fabricating a radio frequency high electron mobility transistor according to claim 1, characterized in that, The step of forming a gate contact layer at the location of the gate window includes the following steps: Deposition of the sixth dielectric layer; A second metal layer is deposited at the location of the gate window; The second metal layer is etched to form a gate contact layer.

3. The method for fabricating a radio frequency high electron mobility transistor according to claim 2, characterized in that, After the step of etching the second metal layer to form the gate contact layer, the method further includes the following steps: Photolithography and etching are performed on the fourth and sixth dielectric layers at the source contact region to expose the first metal layer and form the drain contact layer. Photolithography and etching are performed on the fourth and sixth dielectric layers at the location of the drain contact region to expose the first metal layer and form the drain contact layer.

4. The method for fabricating a radio frequency high electron mobility transistor according to claim 1, characterized in that, The step of forming a gate contact layer at the location of the gate window includes the following steps: A second metal layer is deposited at the location of the gate window; The second metal layer is shaped by photolithography and etching to form a Schottky gate contact layer.

5. The method for fabricating a radio frequency high electron mobility transistor according to claim 1, characterized in that, In the step of dry etching the fifth dielectric layer to extend the gate window to the substrate, the fifth dielectric layer is dry etched to form an inner sidewall structure, which is used to determine the gate size.

6. The method for fabricating a radio frequency high electron mobility transistor according to claim 1, characterized in that, In the step of performing N-type doping implantation in the source contact region and the drain contact region, the N-type doping is implanted into the substrate of the source contact region and the drain contact region.

7. The method for fabricating a radio frequency high electron mobility transistor according to claim 1, characterized in that, The substrate consists of a high-resistivity silicon layer, a buffer layer, a gallium nitride layer, and an aluminum gallium nitride layer, from bottom to top.

8. A transistor, characterized in that, The radio frequency high electron mobility transistor is fabricated using the method described in any one of claims 1-7.

9. An electronic device, characterized in that, Includes the transistor as described in claim 8.

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