Contact structure of semiconductor devices using low-dimensional materials

Abstract

Two-dimensional (2D) materials formed in very thin layers improve the performance of semiconductor devices. However, forming contacts on 2D materials tends to damage and penetrate the 2D material. Relatively gentle etching processes have been developed that are highly selective for 2D materials and allow etching of vertical holes into the 2D material without damaging or penetrating it. Low-power deposition processes form a protective liner when performing metal filling, further preventing damage to the 2D material when forming metal contacts within holes. These processes make it possible to form vertical metal contacts on planar 2D materials or vertical sidewall contacts within 3D NAND without damaging the 2D material. This increases the contact area, reduces contact resistance, and improves the performance of the 2D material in the device.

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims the benefit of U.S. Provisional Application No. 63 / 488,711, filed Mar. 6, 2023, entitled "CONTACT CONSTRUCTION FOR SEMICONDUCTOR DEVICES COMPRISING LOW DIMENSIONAL MATERIALS", which is incorporated herein by reference.

[0002] This technology relates to semiconductor systems, processes, and devices. More particularly, this technology relates to processes and systems for forming conductive contacts using low - dimensional materials in semiconductor devices.

Background Art

[0003] Integrated circuits are enabled by a process of generating intricately patterned material layers on a substrate surface. To generate patterned materials on a substrate, a controlled method for forming and removing materials is required. As device sizes continue to shrink, features within integrated circuits become smaller and the aspect ratio of structures can increase, making it difficult to maintain the dimensions of these structures during processing operations. Additionally, currently, new materials that require special engineering and manufacturing techniques are being used. For example, two - dimensional (2D) materials can have a thickness as small as just a few atoms arranged in a 2D structure. In semiconductor devices, these materials exhibit desirable surface effects and unique quantum mechanical properties. For example, graphene has very high conductivity, and transition metal dichalcogenides (TMDs) may be used in constructing device components with an adjustable bandgap. However, these 2D materials are very difficult to handle because they are small and fragile.

Summary of the Invention

[0004] In some embodiments, the semiconductor device may include a two-dimensional (2D) material and include a channel layer that forms a channel in the semiconductor device, an insulating layer formed on the channel layer which can define features that penetrate the insulating layer and extend to the channel layer, and a metal that fills the features which can contact the top surface of the 2D material of the channel layer.

[0005] In some embodiments, the semiconductor device may include a vertical channel hole defined within the semiconductor device, a 2D material conformally lining the vertical channel hole, and a metal within the vertical channel hole that contacts the 2D material and forms electrodes of the semiconductor device.

[0006] In some embodiments, a method for forming a semiconductor device may include forming a layer of 2D material, forming a layer of insulating material on the 2D material, etching away a portion of the insulating material to form features and expose the surface of the 2D material, and filling the features with metal, wherein the metal is in contact with the surface of the 2D material.

[0007] In any embodiment, any and all of the following features may be implemented in any combination, without limitation: The metal can contact the top surface of the 2D material without penetrating or damaging the 2D material. The 2D material may include a single or double layer of Transition-Metal Dichalcogenide (TMD). The 2D material may include a single or double layer of molybdenum disulfide (MoS2). The channel layer may form a planar channel layer, and the metal may form the drain or source of the semiconductor device. The vertical sides of the channel layer may not be in contact with the metal. The metal can contact the 2D material without penetrating or damaging the 2D material. The metal can substantially fill the vertical channel holes inside the 2D material. The 2D material may also conformally back the top surface of the semiconductor device between the vertical channel holes. The semiconductor device may also include an oxide layer filling a portion of the vertical channel holes below the metal. Etching off a portion of the insulating material may include performing plasma-free vapor phase etching. Etching off a portion of the insulating material may include maintaining a temperature of approximately 45°C or lower to prevent oxidation of the 2D material. Etching off a portion of the insulating material may include supplying an HF etching gas with an NH3 carrier gas at a flow rate ratio of approximately 1:1. Etching off a portion of the insulating material may include raising the temperature of the semiconductor device by bringing it closer to the top plate of the processing chamber and performing annealing at approximately 110°C to approximately 130°C. Filling the feature with metal may include a target tilt angle of approximately 30° to approximately 40°. Filling the feature with metal may include forming a metal liner using a physical vapor deposition (PVD) process performed at a power of approximately 500W or less and a pressure of approximately 0.1 Torr or less, and filling the feature with a metal filler material. The semiconductor device may include a planar device, and the feature may include a vertical hole with the 2D material exposed at the bottom, and the metal may fill the vertical hole to form electrodes of the semiconductor device.Semiconductor devices may include three-dimensional (3D) NAND memory devices, which may feature vertical channel holes conformally lined with a 2D material, and the metal may substantially fill the vertical channel holes inside the 2D material.

[0008] A further understanding of the nature and merits of various embodiments can be achieved by reference to the remainder of this specification and the drawings, in which similar reference numbers are used to refer to similar components throughout several drawings. In some cases, a sublabel is associated with the reference number to indicate one of several similar components. When a reference number is referred to without specifying an existing sublabel, it is intended to refer to all such several similar components. [Brief explanation of the drawing]

[0009] [Figure 1] This is a top view of one embodiment of a processing system comprising a deposition chamber, etching chamber, baking chamber, and curing chamber, which may be included or configured according to some embodiments of this technology. [Figure 2A] This figure shows a semiconductor device 200 utilizing 2D material according to one embodiment. [Figure 2B] This figure shows how a layer of 2D material can be damaged when the upper layer is etched and a metal contact is deposited. [Figure 3] This is a flowchart of a method for forming a semiconductor device using 2D material, according to some embodiments. [Figure 4A] This figure shows a 2D material formed on a substrate according to one embodiment. [Figure 4B] This figure shows an insulating material formed on a 2D material according to some embodiments. [Figure 4C] This figure shows a selective etching process for 2D materials according to some embodiments. [Figure 4D] This figure shows the formation of a liner within a feature that contacts a 2D material, according to some embodiments. [Figure 4E] This figure shows a metal filling operation according to some embodiments. [Figure 4F] This figure shows an example of a semiconductor device with additional components according to some embodiments. [Figure 5A] This figure shows the formation of 2D material in channel holes of a semiconductor device according to some embodiments. [Figure 5B] This figure shows an insulating material formed on a 2D material according to some embodiments. [Figure 5C] This figure shows an etching process that may be used to remove a portion of the insulating material from a semiconductor device, according to some embodiments. [Figure 5D] This figure shows how metal can substantially fill vertical channel holes inside a 2D material according to some embodiments. [Modes for carrying out the invention]

[0010] Two-dimensional (2D) materials are formed in very thin layers and can improve the operation of semiconductor devices such as channels in transistors or memory devices. However, forming vertical contacts on the top surface of 2D materials is extremely difficult because both the etching process to define the contact holes and the metal deposition tend to damage and penetrate the 2D material. Relatively gentle etching processes have been developed that are highly selective for 2D materials and allow etching of vertical holes down to the 2D material without damaging or penetrating it. Low-power deposition processes form a protective liner when performing metal filling to further prevent damage to the 2D material when forming metal contacts. These processes make it possible to form vertical metal contacts on planar 2D materials or vertical sidewall contacts within three-dimensional (3D) NAND without damaging the 2D material. This increases the contact area, reduces contact resistance, and improves the performance of the 2D material in the device.

[0011] The remaining disclosure, as is customary, identifies specific etching and deposition processes that utilize the disclosed technology, but it will be readily apparent that the systems and methods are equally applicable to a variety of other processes that may occur in the described chambers. Therefore, the technology should not be considered limited to use only in the described etching or deposition processes. Before describing the systems and methods or operations of exemplary process sequences according to some embodiments of the technology, this disclosure describes one possible system that can be used with the technology. It should be understood that the technology is not limited to the described apparatus, and the processes discussed can be performed in any number of processing chambers and systems.

[0012] Figure 1 shows a top view of one embodiment of a processing system 100 comprising a deposition chamber, etching chamber, polishing chamber, baking chamber, and curing chamber, which may be included or configured according to some embodiments of the present technology. In this figure, a pair of forward-opening unified pods 102 supply substrates of various sizes, which are received by a robotic arm 104 and placed in a low-pressure holding area 106 before being placed in one of the substrate processing chambers 108a-f located in tandem sections 109a-c. A second robotic arm 110 can be used to transport substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and back. Each substrate processing chamber 108a-f may be equipped to perform several substrate processing operations, including periodic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, annealing, plasma processing, degassing, orientation, and other substrate processes, as well as the dry etching process described herein.

[0013] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching material films on a substrate or wafer. In one configuration, two pairs of processing chambers, e.g., 108c-d and 108e-f, may be used to deposit material on the substrate, and a third pair of processing chambers, e.g., 108a-b, may be used to cure, anneal, or process the deposited film. In another configuration, all three pairs of chambers, e.g., 108a-f, may be configured to both deposit and cure films on the substrate. One or more of the described processes may be performed in additional chambers separated from the manufacturing system shown in different embodiments. It will be understood that in system 100, additional configurations of deposition chambers, etching chambers, annealing chambers, and curing chambers for material films are intended. In addition, any number of other processing systems may be used in conjunction with this technology, and these processing systems may incorporate chambers for performing any of the specific operations. In some embodiments, a chamber system that provides access to multiple processing chambers while maintaining a vacuum environment in various sections such as the aforementioned holding and transfer areas makes it possible to perform operations in multiple chambers while maintaining a specific vacuum environment between individual processes.

[0014] Structures according to some embodiments of this technology can be manufactured using System 100, or more specifically, chambers incorporated into System 100 or other processing systems. For example, System 100 can be used to perform deposition processes, chemical mechanical polishing (CMP) processes, etching processes, etc., to form memory devices, arrays of memory devices, or any other semiconductor devices. In particular, the exemplary structures described below, including transistors and 3D NAND, can be formed using any of the chambers of System 100.

[0015] To improve the performance of semiconductor devices, certain 2D materials are incorporated into them. Generally, 2D materials can include crystalline solids formed in a single atomic layer. For example, one subset of 2D materials can include monolayers of transition metal dichalcogenides (TMDs) containing atomically thin semiconductors. These TMD monolayers can contain transition metal atoms such as molybdenum and tungsten. These metal atoms are bonded to chalcogen atoms such as sulfur, selenium, and tellurium. These TMD materials are characterized by their extremely thin layer size. For example, the thickness of a molybdenum disulfide (MoS2) monolayer is approximately 6.5 Å. These 2D materials are emerging as promising alternative materials for forming different parts of semiconductor devices. For example, 2D materials can offer certain advantages when used to form channels in transistors or other similar devices. Field-effect transistors (FETs) with channels formed from monolayers or bilayers of MoS2 can exhibit very large on / off ratios at room temperature due to the electrostatic control that these materials provide to conduction within the 2D channel. These materials also offer advantages related to electron mobility and bandgap characteristics. Furthermore, the use of 2D materials is desirable because they are extremely thin, which is important when size reduction is a driving factor in device design.

[0016] Figure 2A shows a semiconductor device 200 utilizing a 2D material according to one embodiment. The semiconductor device 200 may include a substrate 202. The substrate 202 may include any type of semiconductor substrate, including silicon, polysilicon, glass, or other materials. In addition, the substrate 202 may include several layers not explicitly shown in Figure 2A. For example, the substrate 202 may include a dielectric layer, a doped silicon layer, a metal layer, and other features that may become part of the semiconductor device 200. Functionally, the substrate 202 can form a surface on which the 2D material can be formed, with any underlying layers abstracted for clarity.

[0017] Semiconductor device 200 can include a layer containing 2D material 204. For example, 2D material 204 may include a TMD layer such as MoS2. MoS2 can include a unit structure in which one layer of molybdenum atoms is covalently bonded to two layers of sulfur atoms. FIG. 2A shows only a single monolayer of MoS2, but other embodiments can include multiple monolayers such as bilayer without limitation. However, as the number of layers decreases, the bandgap increases, which may bring advantages to the operation of semiconductor device 200.

[0018] 2D material 204 can be easily formed on substrate 202, but there are several technical problems when trying to interface 2D material 204 with metal contacts. Specifically, in existing technologies, it is not possible to etch through the material on 2D material 204 without also etching 2D material 204 itself. In planar devices, the layer of 2D material 204 may be formed on substrate 202. Next, an insulating layer such as an interlayer dielectric (e.g., silicon oxide) may be formed on the layer of 2D material 204. Thereafter, features may be etched in the insulating layer to form the positions of metal contacts and expose the top surface of 2D material 204. However, existing etching processes have been shown to damage 2D material 204, which may affect the subsequent performance of semiconductor device 200.

[0019] Figure 2B shows how the layer of 2D material can be damaged when the upper layer is etched and a metal contact is deposited. Recall that the 2D material 204 is relatively thin. For example, the thickness of a single layer of MoS2 may be about 0.7 nm, and the thickness of a bilayer may be about 1.4 nm. Existing etching techniques tend to etch 2D materials. Further, even when forming a metal contact, even gentle deposition techniques can damage the 2D material 204. Figure 2B shows a metal material 206 deposited by a vapor deposition technique that uses physical deposition without using plasma. However, even this deposition technique causes defects 216 to occur on the surface of the 2D material 204, the metal material 206 diffuses through the 2D material 204, and distortion occurs in the covalent bond 214 of the 2D material 204.

[0020] Due to this difficulty, existing techniques for interface metal contacts with 2D material 204 are typically on the surface of the 2D material. Alternatively, existing techniques may attempt alternative methods, such as etching a portion of the planar 2D material 204 to expose its vertical sidewalls. The metal contact can then be deposited next to the exposed vertical sidewalls of the 2D material 204. However, this creates a very small interface between the metal and the planar 2D material 204 because the planar 2D material 204 is very thin. Alternatively, the metal contact may be formed first on the substrate 202, and a layer of 2D material may be formed separately and transferred onto the metal contact. For example, the layer of 2D material 204 can then be separated and placed on top of the metal contact. However, this technique cannot be used for typical manufacturing processes or devices such as vertical 3D NAND devices. Some techniques avoid etching the layer above the 2D material 204 by depositing a patterned photoresist on the 2D material 204. Next, a metal layer can be deposited on top of the 2D material 204 and the photoresist layer. Once the photoresist is removed along with the portion on top of the metal layer, the remaining metal on the 2D material 204 can form a contact. However, this process is typically incompatible with industrial processes for forming memory and other semiconductor devices, and the deposition process can still damage the 2D material 204. No existing solution provides a reliable top contact between the 2D material and metal that is compatible with standard manufacturing processes without damaging the 2D material.

[0021] Embodiments described herein solve these and other technical problems by using etching processes specifically designed to stop at the surface of the 2D material without penetrating or damaging the 2D material. In addition, these embodiments use metal filling processes designed to gently deposit metal on the 2D material without damaging or penetrating the surface of the 2D material. These techniques are compatible with planar devices in which the 2D material may first be formed on a layer of substrate and then covered with an insulating material such as an interlayer dielectric. The pores of the insulating material can then be etched away to expose the 2D material, and the metal filling process can deposit metal contacts on the 2D material without penetrating or damaging the 2D material. These techniques are also compatible with vertical devices such as 3D NAND devices. For example, the 2D material may be conformally formed as a liner on the vertical sidewalls of channel holes in a memory device. The holes may be filled with an insulating material, and then the insulating material can be etched away from the holes to expose a portion of the 2D material. The holes can then be filled with metal to form contact with the 2D material.

[0022] Figure 3 shows a flowchart of method 300 for forming a semiconductor device using 2D material, according to some embodiments. This method 300 can be performed by one or more of the chambers of the processing system 100 described in relation to Figure 1. In addition, this method 300 can be used to manufacture both planar and vertical 3D devices. To illustrate each of these steps, Figures 4A to 4F show the formation of a planar device, and Figures 5A to 5D show the formation of a 3D vertical device. When describing the operation of method 300, the exemplary structures shown in these figures will be referenced. However, these structures are provided only as examples and are not meant to be limiting. Many other types of structures can be adapted to this method 300.

[0023] Method 300 may include forming a layer of 2D material (302). Figure 4A shows a 2D material 404 formed on a substrate 402 according to one embodiment. As described above, the substrate 402 may include any number of underlying layers not specifically shown in Figure 4A. These layers may include doped n-wells, doped p-wells, wiring within a metal layer, insulating layers, conductive layers, interconnection layers, and / or any other type of layer present on a modern semiconductor wafer. For example, the 2D material 204 may include a TMD material such as MoS2. However, any other type of 2D material 204 may be used unless otherwise specified. For example, while MoS2 may have clear advantages in some semiconductor devices, other devices may use tungsten disulfide or other similar materials that may have other advantages.

[0024] Method 300 may also include forming a layer of insulating material on a 2D material (304). Figure 4B shows an insulating material 406 formed on a 2D material 204 according to one embodiment. In some processes, the insulating material 406 may be formed directly on the 2D material 204, resulting in the 2D material 404 being in physical contact with the insulating material 406 with no intervening layer in between. Note that trace amounts of other materials may be present. In other processes, the insulating material 406 may consist of multiple layers of different materials not explicitly shown in Figure 4B. The insulating material 406 may include any type of interlayer dielectric, such as silicon dioxide or other oxides.

[0025] Method 300 may further include etching away a portion of the insulating material to form feature 410 and expose the surface of the 2D material (306). A pattern may be formed on the insulating material 406 to define areas for metal contacts. For example, a photoresist pattern may be formed on the insulating material 406. The photoresist pattern may include openings in which metal contacts are formed. The photoresist pattern may be removed after the etching process is complete.

[0026] Figure 4C shows an etching process 409 selective for the 2D material 404 according to some embodiments. The etching process 409 can be specifically tuned to be selective for the 2D material 404. In other words, the etching process 409 can be configured to readily etch the insulating material 406 without over-etching beyond the surface of the 2D material 404. In some embodiments, the etching process 409 can be carried out using vapor-phase etching. Specifically, these embodiments may avoid the use of liquid etching because it is difficult to control. Vapor-phase etching can be much milder compared to liquid etching, thereby minimizing damage to the 2D material 404. Furthermore, some embodiments can also perform vapor-phase etching without plasma in the processing chamber. By using a plasma-free process, etching can be further controlled and etching of the 2D material 404 can be prevented.

[0027] An etching process can be used to form features 410 in the insulating material 406. These features 410 can define a volume or area for a metal contact. The features 410 may extend from the top surface of the insulating material 406 to the top surface of the 2D material 404. The features 410 may not extend below the top surface of the 2D material 404 so that the 2D material 404 is not damaged or penetrated by the etching process 409. The dimensions of the features 410 may vary depending on the type of embodiment (e.g., type of memory or semiconductor device). For example, features 410 can typically have limiting dimensions (depth:diameter) of about 10:1 or greater. For example, the depth of the hole may be in the range of about 200 nm to about 500 nm, and the diameter of the hole may be in the range of about 20 nm to about 40 nm.

[0028] In addition to using plasma-free vapor phase etching, some embodiments may use etching chemistry that is highly selective for 2D material 404. For example, HF vapor phase etching has been found to be highly selective for 2D material 404 such as MoS2. To perform etching, HF gas may be supplied together with a carrier gas. The carrier gas may include NH3, or other similar gases such as argon, helium, or hydrogen. The flow rate ratio of the etchant gas to the carrier gas may be about 1:1. The flow rates of the etchant gas and / or carrier gas may vary between about 10 sccm and about 1000 sccm. For example, the flow rate may be in the ranges of approximately 10 sccm to 100 sccm, 100 sccm to 200 sccm, 200 sccm to 300 sccm, 300 sccm to 400 sccm, 400 sccm to 500 sccm, 500 sccm to 600 sccm, 600 sccm to 700 sccm, 700 sccm to 800 sccm, 800 sccm to 900 sccm, 900 sccm to 1000 sccm, etc. The flow rate may also include any interval within the above ranges (for example, approximately 450 sccm to 650 sccm). The flow rate may also include any individual value within the above ranges (for example, approximately 550 sccm).

[0029] Some embodiments may also use relatively low temperatures to better control the etching process 409. The temperature of the substrate during the etching process may be in the range of about 30°C to about 130°C. For example, the temperature may be about 30°C to about 40°C, about 40°C to about 50°C, about 50°C to about 60°C, about 60°C to about 70°C, about 70°C to about 80°C, about 80°C to about 90°C, about 90°C to about 100°C, about 100°C to about 110°C, about 110°C to about 120°C, about 120°C to about 130°C, etc. The temperature may also include any interval within the above intervals (e.g., about 35°C to about 55°C). The temperature may also include any individual value within the above intervals (e.g., about 45°C).

[0030] The temperature of the top plate or showerhead of the processing chamber can be maintained at a higher temperature (e.g., about 150°C), and the distance between the top plate and the substrate can be increased to lower the substrate temperature to a specified operating temperature (e.g., about 45°C). The aforementioned lower temperature range can prevent oxidation from occurring during the etching process 409. In one processing chamber, the distance between the pedestal supporting the substrate and the showerhead may be maintained at a distance of about 1000 mils to about 2000 mils during the etching process 409. For example, the distance may be about 1000 mils to about 1200 mils, about 1200 mils to about 1400 mils, about 1400 mils to about 1600 mils, about 1600 mils to about 1800 mils, about 1800 mils to about 2000 mils, etc. This distance may also include any interval within the above intervals (e.g., about 1300 mils to about 1700 mils). This distance can also include any individual value within the above interval (for example, approximately 1500 mils).

[0031] In addition to adjusting the temperature, some embodiments may also maintain the pressure during the etching process 409 between approximately 1 Torr and approximately 10 Torr. For example, the pressure may be approximately 1 Torr to approximately 2 Torr, approximately 2 Torr to approximately 3 Torr, approximately 3 Torr to approximately 4 Torr, approximately 4 Torr to approximately 5 Torr, approximately 5 Torr to approximately 6 Torr, approximately 6 Torr to approximately 7 Torr, approximately 7 Torr to approximately 8 Torr, approximately 8 Torr to approximately 9 Torr, approximately 9 Torr to approximately 10 Torr, and so on. This pressure may also include any interval within the above intervals (e.g., approximately 4 Torr to approximately 6 Torr). This pressure may also include any individual value within the above intervals (e.g., approximately 5.5 Torr).

[0032] In some embodiments, the etching process 409 may include a periodic etching process that periodically repeats annealing and etching. For example, an etchant gas and an optional carrier gas may be supplied to the processing chamber under the above conditions over a first time interval. The etchant gas and the optional carrier gas can then be purged from the processing chamber, and the substrate temperature can be increased over a second time interval to perform annealing. This cycle can be repeated until the surface of the 2D material 404 is exposed (e.g., etching, annealing, etching, annealing, etc.). The required number of cycles may depend on the thickness of the insulating material 406. For example, in some embodiments, more than 20 cycles may be performed to etch through the insulating material 406. Depending on other embodiments and / or the thickness of the insulating material, 20-30 cycles, 30-40 cycles, 40-50 cycles, 50-60 cycles, 60-70 cycles, and / or more than 70 cycles may be used. This iterative process, including thermal annealing, is beneficial in preventing the accumulation of by-products during the etching process 409.

[0033] As described above, the temperature of the top plate or showerhead of the processing chamber can be maintained at a higher temperature (e.g., about 150°C), and the distance between the top plate and the substrate can be reduced to raise the substrate temperature to a specified annealing temperature (e.g., about 120°C). In one processing chamber, the distance between the pedestal supporting the substrate and the showerhead can be maintained at a distance of about 100 mils to about 300 mils during the annealing portion of the etching process 409. For example, this distance may be about 100 mils to about 150 mils, about 150 mils to about 200 mils, about 200 mils to about 250 mils, about 250 mils to about 300 mils, etc. This distance can also include any interval within the above intervals (e.g., about 175 mils to about 225 mils). This distance can also include any individual value within the above intervals (e.g., about 200 mils).

[0034] The temperature during the annealing process can be maintained at approximately 110°C to 130°C. This temperature can be maintained by increasing the temperature inside the processing chamber and / or by bringing the substrate closer to the top plate or showerhead of the processing chamber, as described above. For example, this temperature may be approximately 110°C to 115°C, approximately 115°C to 120°C, approximately 120°C to 125°C, approximately 125°C to 130°C, etc. This temperature can also include any interval within the above intervals (e.g., approximately 115°C to 125°C). This temperature can also include any individual value within the above intervals (e.g., approximately 123°C).

[0035] In addition to controlling the temperature, some embodiments may also maintain a pressure of about 1.0 Torr to about 3.0 Torr during the annealing portion of the etching process 409. For example, this pressure may be about 1.0 Torr to about 1.5 Torr, about 1.5 Torr to about 2.0 Torr, about 2.0 Torr to about 2.5 Torr, about 2.5 Torr to about 3.0 Torr, etc. This pressure may include any interval within the above intervals (e.g., about 1.5 Torr to about 2.5 Torr). This pressure may also include any individual value within the above intervals (e.g., about 2.5 Torr).

[0036] The duration of the annealing portion of etching process 409 may be approximately 30 seconds to approximately 90 seconds. For example, the annealing may be approximately 30 seconds to approximately 40 seconds, approximately 40 seconds to approximately 50 seconds, approximately 50 seconds to approximately 60 seconds, approximately 60 seconds to approximately 70 seconds, approximately 70 seconds to approximately 80 seconds, approximately 80 seconds to approximately 90 seconds, etc. This time may also include any interval within the above intervals (e.g., approximately 40 seconds to approximately 60 seconds). This time may also include any individual value within the above intervals (e.g., approximately 51 seconds).

[0037] Returning to Figure 3, after performing the etching process 409, the method may further include filling the feature with metal (308). Filling the feature with metal allows the metal to come into contact with the surface of the 2D material 404. In some embodiments, filling the feature with metal may include one or more different metallic materials. For example, a liner material may be formed first within the feature to back it and bring it into contact with the 2D material 404. After the liner is formed, a metal film may be used to fill the remaining portion of the feature inside the liner with the metallic material.

[0038] Figure 4D shows the formation of a liner 412 within a feature that contacts the 2D material 404 according to one embodiment. As mentioned above, even if the etching process is carried out carefully to expose the surface of the 2D material 404 without penetrating or damaging it, the deposition process may still damage the 2D material 404. Therefore, the technique described below is designed to carefully form the liner 412 without damaging the 2D material 404. In contrast to the previous technique, the vertical sides of the channel layer are formed by the 2D material 404. Instead, a much larger contact is formed between the metal and the 2D material 404 along the top surface of the 2D material 404.

[0039] The deposition process for forming the liner 412 may be configured to be milder than conventional metal deposition processes. For example, some embodiments may use a physical vapor deposition (PVD) process. Since plasma-free PVD processes have been shown to be mild enough not to damage the 2D material 404, the PVD process may be performed in the absence of plasma to further prevent damage to the 2D material 404. Alternatively, some embodiments may use an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. However, some ALD / CVD precursors can damage 2D materials such as MoS2.

[0040] The liner 412 can be formed from any metallic material. For example, various embodiments can use metals such as Ni, Ti, Au, Pt, Mo, Sb, Sn, Bi, Pt, Pd, Sn, TiN, W, Co, and Ru to form the liner 412.

[0041] To further prevent damage to the 2D material 404, the deposition process can use relatively low power and relatively low pressure during the PVD process. For example, some embodiments can use a power range of about 100W to about 500W in the corresponding pressure range of about 0.1mTorr to about 3.0mTorr. Some embodiments can use a power range of about 200W to about 300W in the corresponding pressure range of about 0.1mTorr to about 0.5mTorr. Some embodiments can use a power of about 220W at a corresponding pressure of about 0.3mTorr. Power may be less than about 500W, less than about 400W, less than about 300W, less than about 200W, less than about 100W, etc. Furthermore, pressure may be less than about 3.0mTorr, less than about 2.5mTorr, less than about 2.0mTorr, less than about 1.5mTorr, less than about 1.0mTorr, less than 0.5mTorr, etc.

[0042] The temperature of the deposition process for forming liner 412 can be maintained between approximately 200°C and approximately 500°C. For example, the temperature may be between approximately 200°C and approximately 250°C, approximately 250°C and approximately 300°C, approximately 300°C and approximately 350°C, approximately 350°C and approximately 400°C, approximately 400°C and approximately 450°C, approximately 450°C and approximately 500°C, etc. This temperature can also include any interval within the above intervals (e.g., approximately 300°C to approximately 500°C). This temperature can also include any individual value within the above intervals (e.g., approximately 350°C). These temperature ranges have been shown to help prevent diffusion defects during deposition, as described above in Figure 2B.

[0043] Some embodiments can perform a multi-cycle deposition process that includes a preheating step to preheat the substrate to an operating temperature within the range described above. This preheating promotes wetting, reduces overhang, and improves step coverage of the sidewalls. To further improve step coverage, some embodiments can angle the deposition process to guide deposition toward the sidewalls of the features. For example, a target for the PVD process can be positioned at an angle to the substrate. As the substrate rotates during the PVD process, the angled target allows the PVD process to better coat the sidewalls of the features. The inclination angle may be about 20° to about 40° with respect to the orthogonal or normal axis of the pedestal and / or the substrate. For example, the inclination angle may be about 20° to about 25°, about 25° to about 30°, about 30° to about 35°, about 35° to about 40°, about 40° to about 45°, about 45° to about 50°, etc. This angle can include any interval within the above interval (for example, approximately 25° to approximately 35°). This angle can also include any individual value within the above interval (for example, approximately 30°).

[0044] The process for forming the liner 412 can be carried out until the liner 412 reaches the target thickness. The thickness of the liner may be approximately 10 Å to approximately 500 Å. For example, the thickness of the liner may be approximately 10 Å to approximately 50 Å, approximately 50 Å to approximately 100 Å, approximately 100 Å to approximately 150 Å, approximately 150 Å to approximately 200 Å, approximately 200 Å to approximately 250 Å, approximately 250 Å to approximately 300 Å, approximately 300 Å to approximately 350 Å, approximately 350 Å to approximately 400 Å, approximately 400 Å to approximately 450 Å, approximately 450 Å to approximately 500 Å, and so on. This thickness may also include any interval within the above intervals (e.g., approximately 30 Å to approximately 100 Å). This thickness may also include any individual value within the above intervals (e.g., approximately 50 Å).

[0045] Figure 4E shows a metal filling operation according to some embodiments. The process of filling the feature 410 with metal after forming the liner 412 may also include performing a metal filling. For example, the metal filler can fill the internal portion or center of the feature 410 that remains inside the liner 412. The liner 412 can play a role in protecting the 2D material 404 during this metal filling operation. In addition, the choice of metal for the liner 412 can greatly affect the performance of the metal contact. Therefore, after the liner 412 is formed, different metal filling operations may be suitable for this process.

[0046] As an example, the ALD conformal filling process can be used. Other exemplary processes include the PVD or CVD processes. Metals that can be used in the metal filling process may include any metal such as W, Ru, Co, Mo, Cu, TiN, and / or TaN. The metal filling process can be angled to the deposition target, or an angle of 0° can be used so that the deposition process is directed straight onto the surface of the substrate. The temperature of the metal filling process may be in the range of room temperature to about 500°C, about 300°C to about 400°C, about 200°C to about 500°C, etc. The pressure of the metal filling process may be in the range of about 0.1 Torr to about 100 Torr, about 1 Torr to about 50 Torr, about 10 Torr to about 30 Torr, etc., depending on the type of process.

[0047] Figure 4F shows an example of a semiconductor device 400 with additional components according to some embodiments. Figure 4F is provided solely to illustrate how the formation of the metal contacts 420, 422 described above can be part of an operating device. In this example, the metal contacts 420, 422 may also be part of a transistor. A gate 424 can be formed between the metal contacts 420 and 422. The metal contacts 420, 422 can form the drain and / or source of a transistor. The formation of the gate 424 and other components shown in Figure 4F is beyond the scope of this disclosure.

[0048] The embodiments of Method 300 shown above in Figures 4A to 4F describe the formation of a planar device in which the feature is a vertical hole, with a 2D material exposed at the bottom of the vertical hole, and a metal fills the vertical hole to form electrodes for a semiconductor device. In addition or alternatively, Method 300 can also be used to form vertical or 3D devices such as 3D NAND memory devices. In a vertical device, the feature may include a vertical channel hole conformally lined with a 2D material. A metal substantially filling the vertical channel hole inside the 2D material can form electrodes within the channel hole that come into contact with the 2D material.

[0049] When forming a 3D vertical device, method 300 can again form a layer of 2D material (302). Figure 5A shows the formation of 2D material 504 in channel holes of a semiconductor device 500 according to one embodiment. The semiconductor device 500 may include a substrate 502 which is part of a 3D NAND device. Thus, the substrate 502 may include many different layers, including nitride layers, oxide layers, metal layers, etc., which are not explicitly shown in Figure 5A. The substrate 502 may have several features, such as features 511 which form holes for individual memory devices of the 3D NAND array. These features may be etched through the layers of the substrate 502, as shown in Figure 5A.

[0050] The 2D material 504 is conformally formed on the substrate 502. For example, the 2D material 504 may also be formed along the top surface of the substrate 502. The 2D material 504 may also be formed along the vertical sidewalls of the feature 511. The 2D material 504 may extend throughout the entire depth of the feature 511. The type of 2D material 504 and the process for forming the 2D material 504 may be the same as the description of the 2D material 404 described above in relation to Figure 4A, and any of the above concepts are also applicable to the 2D material 504 in Figure 5A.

[0051] Method 300 may also include forming a layer of insulating material on the 2D material (304). Figure 5B shows insulating material 506 formed on the 2D material 504 according to one embodiment. Using a filling operation, feature 511 can be filled with insulating material 506. The insulating material 506 may be any dielectric material such as silicon dioxide. As shown in Figure 5B, the insulating material 506 may extend over the top surface of feature 511 and / or the top surface of the 2D material 504. The type of insulating material 506 and the process for forming the insulating material 506 may be the same as that of the insulating material 406 described above in Figure 4B, and any of the concepts described above are also applicable to the insulating material 506 in Figure 5B.

[0052] Method 300 may also include etching away a portion of the insulating material to re-form a feature (306) that exposes the surface of the 2D material. Figure 5C shows an etching process 509 that can be used to remove a portion of the insulating material 506 from the semiconductor device 500 according to some embodiments. The etching process 509 may be highly selective for the 2D material 504, as described above. Thus, the etching process 509 can substantially remove the insulating material 506 above the surface of the feature 511, exposing the top surface of the 2D material 504 along the top of the semiconductor device 500. Furthermore, the etching process 509 can remove a portion of the insulating material 506 from within the feature 511 to a predetermined depth. For example, the insulating material 506 (e.g., oxide) may fill a portion of the vertical channel below a predetermined depth so that the etching process stops before removing all of the insulating material 506 from the vertical channel hole. The etching process 509 for removing the insulating material 506 may be substantially the same as the etching process 409 described above in relation to Figure 4C, and any of the above concepts are also applicable to the etching process 509 in Figure 5C.

[0053] Method 300 may further include filling the feature with metal (308) so that the metal contacts the surface of the 2D material. Figure 5D shows how, according to one embodiment, metal 510 can substantially fill the vertical channel hole inside the 2D material 504. Since the 2D material 504 of the vertical sidewall is exposed by the etching process 509, metal 510 can contact the 2D material without penetrating or damaging it. The metal in the vertical channel hole can form electrodes for a semiconductor device. The metal 510 can be deposited to substantially fill the vertical channel hole and optionally extend above the vertical channel hole to cover the top of the substrate 502, as shown in Figure 5D. A portion of the metal 510 extending above the top surface of the substrate 502 can be removed using a subsequent process, such as a chemical mechanical polishing (CMP) process. As described above, the deposition of metal 510 may include several steps, such as forming a liner and then performing a metal filling process. The liner formation and metal filling processes may be substantially the same as those described above in relation to Figure 4D, and any of the above concepts are also applicable to the formation of the metal 510 in Figure 5D.

[0054] The above description includes numerous details for illustrative purposes to provide an understanding of various embodiments of the Technology. However, it will be apparent to those skilled in the art that certain embodiments can be implemented without some of these details, or with additional details.

[0055] While some embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative configurations, and equivalents can be used without departing from the spirit of the embodiments. In addition, some well-known processes and elements have not been described in order to avoid unnecessarily obscuring the Art. Therefore, the above description should not be construed as limiting the scope of the Art.

[0056] Where a range of values ​​is provided, it is understood that each intervening value, up to the smallest fraction of the unit of the lower limit, between the upper and lower limits of that range, is also specifically disclosed unless the context otherwise explicitly indicates. Any narrower range of any listed or unlisted intervening value within the stated range and any other listed or intervening value within that stated range is included. The upper and lower limits of these smaller ranges may be included in or excluded from the range independently, and each range that includes either limit, does not include either limit, or includes both limits is also included within the scope of the Art, subject to any particularly excluded restrictions within the stated range. Where a stated range includes one or both limits, ranges that exclude one or both of the limits they include are also included.

[0057] As used herein and in the appended claims, the singular forms “a,” “an,” and “the” include plural references unless the context clearly indicates otherwise. For example, a reference to “a pillar” includes multiple such pillars, and a reference to “the layer” includes one or more layers and their equivalents known to those skilled in the art.

[0058] Furthermore, the words “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including,” when used herein and in the following claims, are intended to specify the presence of the described feature, integer, component, or action, but they do not preclude the presence or addition of one or more other features, integers, components, actions, or groups. The terms “approximately,” “about,” and / or “substantially” may indicate nominal dimensions or measurements that deviate by less than 10% of the stated value.

[0059] The foregoing description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the foregoing description of various embodiments provides a feasible disclosure for carrying out at least one embodiment. It should be understood that various modifications can be made to the function and configuration of the elements without departing from the spirit and scope of some embodiments, as described in the appended claims.

[0060] Specific details are provided in the above description to provide a complete understanding of the embodiments. However, it will be understood that embodiments may be carried out without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in the form of block diagrams to avoid obscuring the embodiments with unnecessary details. In other cases, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary details to avoid obscuring the embodiments.

[0061] Furthermore, note that individual embodiments may be described as processes shown as flowcharts, dataflow diagrams, structural diagrams, or block diagrams. While flowcharts may describe operations as sequential processes, many operations can be executed in parallel or simultaneously. In addition, the order of operations may be reordered. A process terminates when its operations are complete, but it may have additional steps not shown in the diagram. A process corresponds to a method, function, procedure, subroutine, subprogram, etc. If a process corresponds to a function, its termination may correspond to the function returning to its calling function or the main function.

[0062] The term “computer-readable medium” includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or transporting instructions and / or data. A code segment or machine-executable instruction can represent a procedure, function, subprogram, program, routine, subroutine, module, software package, class, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or hardware circuit by passing and / or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc., may be passed, transferred, or transmitted via any appropriate means, including memory sharing, message passing, token passing, network transmission, etc.

[0063] Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, a hardware description language, or any combination thereof. If implemented by software, firmware, middleware, or microcode, the program code or code segments for performing the required tasks may be stored in a machine-readable medium. The processor can then perform the required tasks.

[0064] Furthermore, for illustrative purposes, the method has been described in a specific order. It should be understood that in alternative embodiments, the method may be executed in an order different from that described. It should also be understood that the method described above may be executed by hardware components or embodied in a sequence of machine-executable instructions, which may be used to cause a machine, such as a general-purpose or dedicated processor or logic circuit programmed with instructions, to execute the method. These machine-executable instructions may be stored on one or more machine-readable media, such as a CD-ROM or other type of optical disk, floppy diskette, ROM, RAM, EPROM, EEPROM, magnetic or optical card, flash memory, or other type of machine-readable media suitable for storing electronic instructions. Alternatively, the method may be executed by a combination of hardware and software.

Claims

1. It is a semiconductor device, A channel layer comprising a two-dimensional (2D) material, which forms the channel of the semiconductor device, An insulating layer formed on the channel layer, wherein the insulating layer has the characteristic of penetrating the insulating layer and extending to the channel layer, A metal filling the aforementioned features, which is in contact with the top surface of the 2D material in the channel layer, A semiconductor device equipped with the following features.

2. The semiconductor device according to claim 1, wherein the metal contacts the top surface of the 2D material without penetrating or damaging the 2D material.

3. The semiconductor device according to claim 1, wherein the 2D material comprises a single or double layer of a transition metal dichalcogenide (TMD).

4. The aforementioned 2D material is molybdenum disulfide (MoS 2 The semiconductor device according to claim 1, comprising a single or double layer of ).

5. The semiconductor device according to claim 1, wherein the channel layer forms a planar channel layer, and the metal forms a drain or source of the semiconductor device.

6. The semiconductor device according to claim 1, wherein the vertical side surface of the channel layer does not come into contact with the metal.

7. It is a semiconductor device, A vertical channel hole defined within the semiconductor device, A two-dimensional (2D) material that conformally backs the aforementioned vertical channel hole, The metal in the vertical channel hole, which contacts the 2D material and forms the electrodes of the semiconductor device, A semiconductor device equipped with the following features.

8. The semiconductor device according to claim 7, wherein the metal contacts the 2D material without penetrating or damaging the 2D material.

9. The semiconductor device according to claim 7, wherein the metal substantially fills the vertical channel holes inside the 2D material.

10. The semiconductor device according to claim 7, wherein the 2D material also conformally backs the top surface of the semiconductor device between the vertical channel holes.

11. The semiconductor device according to claim 7, further comprising an oxide layer that fills a portion of the vertical channel hole below the metal.

12. Forming a layer of two-dimensional (2D) material, Forming a layer of insulating material on the aforementioned 2D material, A portion of the insulating material is etched away to form features, exposing the surface of the 2D material. The aforementioned features are filled with metal, wherein the metal is in contact with the surface of the 2D material, and the filling is performed accordingly. A method for forming a semiconductor device, including [a specific component].

13. The method according to claim 12, wherein etching off the portion of the insulating material includes performing plasma-free vapor phase etching.

14. The method according to claim 12, wherein etching off the portion of the insulating material is performed while maintaining a temperature of about 45°C or lower so that the 2D material is not oxidized.

15. Etching off the aforementioned portion of the insulating material is performed using HF etching gas and NH 3 The method according to claim 12, comprising supplying a carrier gas at a flow rate ratio of approximately 1:

1.

16. The method according to claim 12, wherein etching off the portion of the insulating material includes bringing the semiconductor device closer to the top plate of the processing chamber to raise the temperature of the semiconductor device and performing annealing to about 110°C to about 130°C.

17. The method according to claim 12, wherein filling the aforementioned features with the metal includes a target inclination angle of about 30° to about 40°.

18. Filling the aforementioned features with the aforementioned metal Forming a metal liner using a physical vapor deposition (PVD) process performed at a power of approximately 500W or less and a pressure of approximately 0.1 Torr or less, The aforementioned features are filled with a metal-filling material, The method according to claim 12, including the method described in claim 12.

19. The method according to claim 12, wherein the semiconductor device includes a planar device, the feature includes a vertical hole, the 2D material is exposed at the bottom of the vertical hole, and the metal fills the vertical hole to form an electrode of the semiconductor device.

20. The method according to claim 12, wherein the semiconductor device includes a three-dimensional (3D) NAND memory device, the feature includes a vertical channel hole conformally lined with the 2D material, and the metal substantially fills the vertical channel hole inside the 2D material.

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