Method for etching a ring gate structure, method for manufacturing a semiconductor device, and semiconductor device

Abstract

The application discloses a gate-all-around structure etching method and a semiconductor device preparation method. The method comprises the following steps: providing an object to be etched, the object to be etched comprising a laminated structure formed on a substrate, the laminated structure comprising a strain layer and a sacrifice layer arranged in an overlapping manner; performing a cyclic etching step on the sidewall of the object to be etched, the cyclic etching step comprising sequentially and cyclically performing an oxidation protection step and a first etching step for a set number of cycles; wherein the oxidation protection step is used to form an oxidation protection layer on the sidewall of the strain layer and the sacrifice layer; performing a second etching step on the sidewall of the object to be etched until the sacrifice layer is etched to a set lateral depth; and the plasma density of the second etching step is greater than that of the first etching step. The application can realize that the sacrifice layer is removed with high selectivity and the strain layer is effectively protected in the etching of the gate-all-around structure.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor manufacturing, and more particularly, relates to a gate-all-around structure etching method, a semiconductor device manufacturing method and a semiconductor device. BACKGROUND

[0002] With the decrease of gate width, the electrostatic problem of fin field effect transistor restricts the further development of the transistor, and the gate-all-around transistor (GAA) is considered as a new technology to replace the traditional method. The original 3D structure thereof needs special processes, such as lateral etching of a sacrificial layer. Due to the special similarity and difference between SiGe and Si, SiGe is usually selected as the material of the sacrificial layer.

[0003] The lattice constants of SiGe and pure Si are not much different (1%≤Ge≤25%), so it can be used as a strain configuration between two silicon layers. At the same time, SiGe can also be distinguished from Si in high-selectivity dry etching. The selectivity ratio of SiGe and Si during etching is gradually becoming the main factor restricting the development of the gate-all-around transistor.

[0004] At present, for SiGe sacrificial layer etching, a one-step etching method is usually used. In order to etch the SiGe sacrificial layer completely, a bias plasma isotropic etching is mainly used, the chamber pressure condition is 100-500mT, the etching power is 500-800W, and the difference between SiGe and Si is used under the condition of high pressure and high power to remove the SiGe sacrificial layer.

[0005] However, under the condition of high pressure and high power, the high selectivity ratio of the SiGe sacrificial layer and the Si layer cannot be guaranteed, and at the same time, a large amount of Si layer will be lost. Reducing the pressure and power will result in a too slow etching rate, and the SiGe layer cannot be removed to the required channel width. The general solution in the industry is to use moderate ion energy, and then extend the etching time, but extending the etching time will also cause the loss of the Si layer to increase. SUMMARY

[0006] The purpose of the present application is to provide a gate-all-around structure etching method, a semiconductor device manufacturing method and a semiconductor device, which can realize that the sacrificial layer is removed with high selectivity and the strain layer is effectively protected in etching the gate-all-around structure.

[0007] In a first aspect, an embodiment of the present application provides a gate-all-around structure etching method, comprising:

[0008] providing a to-be-etched object, the to-be-etched object comprising a stacked structure formed on a substrate, the stacked structure comprising a strain layer and a sacrificial layer arranged in an overlapping manner;

[0009] performing a cyclic etching step on the sidewall of the object to be etched, wherein an oxidation protection step and a first etching step are cyclically performed in sequence for a set number of cycles; wherein the oxidation protection step is used to form an oxidation protection layer on the sidewall of the strain layer and the sacrificial layer;

[0010] performing a second etching step on the sidewall of the object to be etched until the sacrificial layer is etched to a set lateral depth; the plasma density of the second etching step is greater than the plasma density of the first etching step.

[0011] Optionally, the sacrificial layer contains Ge, and the cyclic etching step is used to enrich Ge in the sacrificial layer.

[0012] Optionally, the strain layer is Si, and the sacrificial layer is SiGe.

[0013] Optionally, between the cyclic etching step performed on the sidewall of the object to be etched and the second etching step performed on the sidewall of the object to be etched, further comprising:

[0014] performing the oxidation protection step on the sidewall of the object to be etched.

[0015] Optionally, the set number of cycles is 5-10 times.

[0016] Optionally, the etching gas used in the first etching step and the second etching step is a fluorine-based gas.

[0017] Optionally, the proportion of fluorine in the fluorine-based gas in the first etching step is higher than the proportion of fluorine in the fluorine-based gas in the second etching step.

[0018] Optionally, the fluorine-based gas is a mixed gas of CF4 and C4F6; wherein

[0019] The ratio of C4F6 to CF4 in the first etching step is less than the ratio of C4F6 to CF4 in the second etching step.

[0020] Optionally, the upper electrode radio frequency power used in the first etching step is less than the upper electrode radio frequency power used in the second etching step.

[0021] Optionally, the total flow rate of the etching gas used in the first etching step is less than the total flow rate of the etching gas used in the second etching step.

[0022] Optionally, the process parameters of the first etching step include:

[0023] The process chamber vacuum degree ranges from 40 to 60 mT;

[0024] The upper electrode radio frequency power ranges from 300 to 500 W;

[0025] The total flow rate of C4F6 gas and CF4 gas ranges from 100 to 150 sccm;

[0026] The ratio of C4F6 gas to CF4 gas ranges from 1:7 to 1:10;

[0027] The first etching step ranges from 5 to 10 s.

[0028] Optionally, the process parameters of the oxidation protection step include:

[0029] The vacuum degree of the process chamber ranges from 10 to 20 mT;

[0030] The upper electrode radio frequency power ranges from 500 to 800 W;

[0031] The oxygen flow rate ranges from 100 to 200 sccm;

[0032] The oxidation protection step ranges from 5 to 10 s.

[0033] Optionally, the process parameters of the second etching step include:

[0034] The vacuum degree of the process chamber ranges from 40 to 60 mT;

[0035] The upper electrode radio frequency power ranges from 500 to 800 W;

[0036] The total flow rate of C4F6 gas and CF4 gas ranges from 200 to 250 sccm;

[0037] The ratio of C4F6 gas to CF4 gas ranges from 1:4 to 1:5;

[0038] The duration of the second etching step matches the duration corresponding to etching the remaining sacrificial layer to the set lateral depth.

[0039] In a second aspect, an embodiment of the present application provides a preparation method of a semiconductor device, including the ring gate structure etching method in any one of the first aspect.

[0040] The present application has the following beneficial effects:

[0041] The embodiment of the present application first performs the oxidation protection step, the first etching step and the oxidation protection step on the to-be-etched object in a cycle until a set number of cycles is reached, and then performs the second etching step until the sacrificial layer is etched to the set lateral depth. The oxidation protection step can form a protective layer on the exposed surface of the strain layer and the remaining sacrificial layer. By performing the oxidation protection step, the first etching step and the oxidation protection step in a cycle until a set number of cycles is reached and then performing the oxidation protection step again, the etching selectivity of the sacrificial layer can be improved, the sacrificial layer can be removed with high selectivity, and the strain layer is protected to avoid excessive etching of the strain layer.

[0042] The system of the present invention has other features and advantages that will be apparent from or will be set forth in detail in the accompanying drawings and following detailed description, which together serve to explain the particular principles of the invention. Attached Figure Description

[0043] The above and other objects, features and advantages of the present invention will become more apparent from the accompanying drawings, in which like reference numerals generally denote like parts.

[0044] Figure 1 A simplified diagram of a plasma etching apparatus used in a ring gate structure etching method according to Embodiment 1 of the present invention is shown.

[0045] Figure 2 A step diagram of an etching method for a ring gate structure according to Embodiment 1 of the present invention is shown.

[0046] Figure 3 A schematic diagram of a fin structure in a ring gate structure etching method according to Embodiment 1 of the present invention is shown.

[0047] Figure 4 The diagram shows the device structure before and after etching in a ring gate structure etching method according to Embodiment 1 of the present invention.

[0048] Figure 5 A schematic diagram of the device structure changes corresponding to each process step in a ring gate structure etching method according to Embodiment 1 of the present invention is shown.

[0049] Figure 6a and Figure 6b The diagrams show the device structures obtained by the existing one-step etching method and the ring gate structure etching method of Embodiment 1 of the present invention. Detailed Implementation

[0050] The invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0051] Example 1

[0052] The ring gate structure etching method in this embodiment adopts the following... Figure 1The shown plasma etching equipment is completed, the etching equipment includes process chamber 1, dielectric window 2, upper electrode RF power supply 5 and base 3 for carrying wafer 4, wherein the upper electrode RF power supply 5 transmits RF energy into the process chamber 1 through the dielectric window 2, and the process gas in the process chamber 1 is excited to generate plasma.

[0053] As shown in the figure, Figure 2 An etching method of a ring gate structure, comprising:

[0054] S1: providing an object to be etched, the object to be etched comprising a stacked structure formed on a substrate, the stacked structure comprising a strain layer and a sacrificial layer arranged in an overlapping manner;

[0055] In some optional embodiments of the embodiment of the present application, the sacrificial layer contains Ge. More specifically, the strain layer can be a Si layer, and the sacrificial layer can be a SiGe layer.

[0056] As shown in the figure, Figure 3 Taking the Si layer as the strain layer and the SiGe layer as the sacrificial layer as an example, the preparation method of the object to be etched is as follows: first, epitaxially growing a Si layer 21 and a SiGe layer 22 stack on a substrate 10, then forming a hard mask 30 for etching the stack on the surface of the Si layer 21 and the SiGe layer 22 stack by a self-aligned double imaging or self-aligned quadruple exposure (SAQP) process, and then etching the Si layer 21 and the SiGe layer 22 stack by a deep silicon etching process to form a stacked structure with a SiGe layer 21 spaced Si layer 21 stack with a side wall, and the main target etching layer in the embodiment is the SiGe layer 22. The device structure before and after etching is shown in the figure. Figure 4

[0057] S2: performing a cyclic etching step on the side wall of the object to be etched, and sequentially performing an oxidation protection step and a first etching step for a set number of cycles in the cyclic etching step; wherein the oxidation protection step is used to form an oxidation protection layer on the side wall of the strain layer and the sacrificial layer.

[0058] In the embodiment, when the sacrificial layer contains Ge, the Ge in the sacrificial layer can be enriched by the cyclic etching step.

[0059] Preferably, the process parameters of the oxidation protection step include:

[0060] The process chamber vacuum degree ranges from 10 to 20 mT;

[0061] The upper electrode RF power ranges from 500 to 800 W;

[0062] The oxygen flow ranges from 100 to 200 sccm;

[0063] ​The oxidation protection step is performed for 5-10 seconds.

[0064] Specifically, the oxidation protection step is performed by a plasma process. The oxidation protection step is to oxidize the sidewalls of the SiGe layer and the Si layer. The surface layer of the SiGe layer is oxidized to SiO2, and the subsurface layer is Ge-rich SiGe. The surface layer of the Si layer is oxidized to SiO2, and the subsurface layer is Si. In the oxidation protection step, when the pressure is less than 10 mT and the upper electrode power is less than 500 W, the sidewalls of the SiGe layer and the Si layer cannot be completely oxidized. When the pressure is greater than 20 mT and the upper electrode power is greater than 800 W, the plasma energy is too high, and the sidewalls of the stacked structure can be damaged under ion bombardment. Therefore, the process chamber vacuum degree is selected to be 10-20 mT to ensure that the sidewalls of the SiGe layer and the Si layer are completely oxidized and will not be damaged. When the O2 flow rate is less than 100 sccm, the chamber cannot be stabilized at 10-20 mT. When the flow rate is greater than 200 sccm, the plasma density in the chamber will increase, which will cause damage to the sidewalls under ion bombardment. Therefore, the oxygen flow rate is selected to be 100-200 sccm to ensure that the process chamber vacuum degree is maintained at 10-20 mT, and the sidewalls of the SiGe layer and the Si layer will not be damaged. Under the above process environment, when the oxidation protection step is less than 5 s, the exposed surface of the sidewalls of the SiGe layer and the Si layer cannot be completely oxidized. When the oxidation protection step is greater than 10 s, the exposed surface of the sidewalls of the SiGe layer and the Si layer has been completely oxidized (the formed SiO2 layer will act as a passivation layer and will not form new SiO2), which will cause waste of oxygen. Therefore, the oxidation protection step is selected to be 5-10 s to ensure that the sidewalls of the stacked structure have enough time to be completely oxidized and will not waste oxygen. Therefore, the oxidation protection step process conditions of the embodiment can completely oxidize the sidewalls of the SiGe layer and the Si layer, enrich the Ge element in the subsurface of the SiGe layer sidewall, and prevent the sidewalls of the SiGe layer and the Si layer from being damaged.

[0065] In the etching method of the embodiment, the first etching step is to etch the SiO2 on the sidewalls of the SiGe layer to consume the Si element of the sacrificial layer to achieve Ge enrichment, without damaging the sidewalls of the Si layer. In addition, to achieve the purpose of Ge enrichment of the SiGe layer sidewall, the etching effect on the exposed surface of the SiGe layer needs to be reduced to avoid the Ge-rich SiGe from being completely etched.

[0066] To achieve the above purpose, the proportion of fluorine in the fluorine-based gas used in the first etching step can be higher than the proportion of fluorine in the fluorine-based gas used in the second etching step. The fluorine-based gas with a high proportion of fluorine can etch the SiO2 formed in the oxidation protection step while reducing the etching of SiGe in the first etching step, thereby avoiding the consumption of SiGe that has already enriched Ge by the non-etching gas.

[0067] To achieve the above purpose, the proportion of fluorine in the fluorine-based gas used in the first etching step can be higher than the proportion of fluorine in the fluorine-based gas used in the second etching step. The fluorine-based gas with a high proportion of fluorine can etch the SiO2 formed in the oxidation protection step while reducing the etching of SiGe in the first etching step, thereby avoiding the consumption of SiGe that has already enriched Ge by the non-etching gas.

[0068] The upper electrode radio frequency power used in the first etching step can also be selected to be smaller than the upper electrode radio frequency power used in the second etching step. A smaller upper electrode radio frequency power can achieve the effect of etching the SiO2 formed in the oxidation protection step while not consuming the SiGe that has already enriched Ge.

[0069] Alternatively, the total flow rate of the etching gas used in the first etching step can also be selected to be smaller than the total flow rate of the etching gas used in the second etching step. A smaller etching gas flow rate can also achieve the effect of etching only SiO2 in the first etching step without consuming the SiGe that has already enriched Ge, thereby achieving Ge enrichment of the SiGe layer. To achieve the best Ge enrichment effect, the above schemes are preferably used simultaneously in the present embodiment.

[0070] In this step, the process parameters of the first etching step preferably include:

[0071] The process chamber vacuum degree is in the range of 40-60 mT;

[0072] The upper electrode radio frequency power is in the range of 300-500 W;

[0073] The total flow rate of C4F6 gas and CF4 gas is in the range of 100-150 sccm;

[0074] The ratio of C4F6 gas to CF4 gas is in the range of 1:7-1:10;

[0075] The duration of the first etching step is in the range of 5-10 s.

[0076] Specifically, the first etching step adopts a plasma etching process. When the process chamber pressure is less than 40 mT and the upper electrode radio frequency power is less than 300 W, the etching rate is too low (less than 1 nm / min), which reduces the production rate. When the pressure is greater than 60 mT and the upper electrode radio frequency power is greater than 500 W, the etching rate is too high (greater than 10 nm / min), and the etching is interrupted after multiple cycles. The ratio of C4F6 / CF4 is 1:7-1:10, and the total gas flow is 100-150 sccm. This condition can ensure the selectivity of SiGe to Si (not less than 5:1) and the etching rate of SiGe (≥5 nm / min). The main purpose of the first etching step is to remove the SiO2 surface layer formed on the sidewall of the SiGe layer in the oxidation protection step, so as to expose the SiGe layer rich in Ge elements, which facilitates the enrichment of Ge elements in the exposed SiGe layer in the next execution of the oxidation protection step. The duration of the first etching step is 5-10 s, which can ensure that the SiO2 on the surface of the SiGe layer and the Si layer is completely etched and removed, and the SiGe layer and the Si layer are not over-etched.

[0077] In this step, the setting cycle number of the oxidation protection step-first etching step is preferably 5-10 times, and the preferred cycle number in this embodiment is 8 times. The purpose of multiple cycles of the oxidation protection step-first etching step is to enrich the Ge elements in the remaining SiGe layer and protect the Si layer.

[0078] The specific principle of Ge enrichment in this step is that after the first execution of the oxidation protection step, SiO2 is formed on the surface of the SiGe layer, which oxidizes the Si elements in the SiGe layer and increases (enriches) the Ge elements in the subsurface layer, and SiO2 is formed on the surface of the Si layer. After the first etching step, the SiGe layer is exposed after the SiO2 on the surface of the SiGe layer is etched, and SiO2 is formed on the surface of the exposed SiGe layer after the second execution of the oxidation protection step, which enriches the Ge elements in the subsurface layer of the SiGe layer. After multiple cycles of the oxidation protection step and the first etching step, the Ge elements in the sidewall of the SiGe layer can be enriched to a high degree. With the increase of the cycle number, the surface of the SiGe layer exposed at the sidewall position is less and less due to the enrichment of the Ge elements at the sidewall position of the SiGe layer. Therefore, when the cycle number reaches a certain number, the enrichment effect of the Ge elements is no longer obvious, and too many cycles will waste process resources. The deposition protection step-oxidation protection step-first etching step is executed 5-10 times, which can achieve the obvious enrichment effect of the Ge elements in the SiGe layer.

[0079] S3: after step S2 is completed, a second etching step is performed on the object to be etched until the sacrificial layer is etched to a set lateral depth; the plasma density of the second etching step is greater than that of the first etching step.

[0080] In this embodiment, the purpose of the second etching step is to increase the etching rate and improve efficiency. Therefore, it is necessary to achieve a higher SiGe / Si etching selectivity in the second etching step, accelerate the etching of the remaining SiGe, improve the etching efficiency of the sacrificial layer, and at the same time provide protection to the Si layer. In order to achieve the best etching effect, the plasma density of the etching gas needs to be increased compared to the first etching step, so the proportion of fluorine in the fluorine-based gas used in this step is lower than that in the first etching step, the ratio of C4F6 to CF4 in the fluorine-based gas is higher, the upper electrode radio frequency power is larger, and the total flow rate of the etching gas is also larger.

[0081] In this step, preferably, the process parameters of the second etching step include:

[0082] The vacuum degree of the process chamber ranges from 40 to 60 mT;

[0083] The upper electrode radio frequency power ranges from 500 to 800 W;

[0084] The total flow rate of C4F6 gas and CF4 gas ranges from 200 to 250 sccm;

[0085] The ratio of C4F6 gas to CF4 gas ranges from 1:4 to 1:5;

[0086] The duration of the second etching step matches the duration corresponding to the etching of the remaining sacrificial layer to the set lateral depth.

[0087] Specifically, compared to the first etching step, the density of the plasma in the chamber is increased by increasing the upper electrode power and the concentration of the etching gas, thereby increasing the etching rate of the SiGe sacrificial layer, shortening the etching time, and improving the efficiency. In the process conditions of the second etching step, when the pressure is <40 mT and the upper electrode radio frequency power is <500 W, the requirement of high selectivity >15 cannot be met. When the voltage is >60 mT and the upper electrode radio frequency power is >800 W, the etching speed is too fast (more than 10 nm / min), and the etching will be broken. When the F:C ratio in the plasma is low (less than or equal to 4), the SiGe / Si has a high selectivity. When the F:C ratio in the plasma is high (more than 4), the etching rate of Si is faster than that of SiGe. The total flow rate of the etching gas ranges from 200 to 250 sccm, and the ratio of C4F6 / CF4 is 1:4 to 1:5. This process condition can improve the selectivity of SiGe / Si etching, achieve a selectivity of no less than 15:1, and also ensure the etching speed (≥5 nm / min).

[0088] In this step, after the SiO2 formed on the Si layer and the Ge-rich SiGe surface in step S3 is etched away, the Si surface of the Si layer and the Ge-rich SiGe surface of the SiGe layer are exposed. Since the bond energy of Si-Ge bond is weaker than that of Si-Si bond, there is a higher selectivity between Ge-rich SiGe and Si. When Si and Ge-rich SiGe are simultaneously exposed to fluorine-based etching gas, SiGe can be quickly and massively removed, while the Si layer is protected from over-etching, thereby improving the process effect and obtaining a better ring gate structure.

[0089] In this embodiment, the etching gas used in the first etching step and the second etching step is fluorine-based mixed gas of CF4 and C4F6. CF4 and C4F6 are commonly used fluorine-based gases for etching Si-based materials. By adjusting the ratio of C4F6 / CF4, the selectivity can be optimized, but the present application is not limited to these two fluorine-based gases. Other fluorine-based gases can also be selected according to the F:C ratio in the above plasma, and similar effects can also be achieved.

[0090] The etching process of the ring gate structure etching method of this embodiment can be represented by the following formula:

[0091] (O2dep-ME1) n -ME2

[0092] In the formula, O2dep is the oxidation protection step, ME1 is the first etching step, ME2 is the second etching step, and n is 5-10.

[0093] As shown in Figure 5 , the oxidation protection step-first etching step is executed in a loop to a set number of loops, so that the SiGe layer is enriched with Ge element and the Si layer is protected, Figure 5 where x ranges from 0 to 1. Since the bond energy of Si-Ge bond is weaker than that of Si-Si bond, there is a higher selectivity between Ge-rich SiGe and Si. When exposed to fluorine-based gas at the same time, the Si layer can be protected from over-etching.

[0094] Then, the SiGe is removed by increasing the density of the plasma. By increasing the upper radio frequency power (500-800 W) or increasing the gas flow of CF4 and C4F6 (200-250 sccm), the density of the plasma can be increased, thereby removing the SiGe with high selectivity (etching selectivity of SiGe / Si ≥ 15). As shown in Figure 6a and Figure 6b The ring gate device structure obtained by using the ring gate structure etching method of this embodiment can obtain a better ring gate structure compared to the existing one-step etching method.

[0095] Example 2

[0096] The difference between the embodiment and embodiment 1 is that, on the basis of embodiment 1, an oxidation protection step is added between step S2 and step S3, and the process parameters of the added oxidation protection step are the same as those of the oxidation protection step in step S2 of embodiment 1.

[0097] The specific method of the embodiment is as follows:

[0098] Step S101: providing a to-be-etched object, the to-be-etched object comprising a stack structure formed on a substrate, the stack structure comprising a strain layer and a sacrificial layer arranged in an overlapping manner;

[0099] Step S102: performing a cyclic etching step on the sidewall of the to-be-etched object, the cyclic etching step comprising sequentially and cyclically performing an oxidation protection step and a first etching step for a set number of cycles; wherein the oxidation protection step is used to form an oxidation protection layer on the sidewall of the strain layer and the sacrificial layer.

[0100] Step S103: performing the oxidation protection step again on the sidewall of the to-be-etched object.

[0101] Step S104: performing a second etching step on the sidewall of the to-be-etched object until the sacrificial layer is etched to a set lateral depth; the plasma density of the second etching step is greater than that of the first etching step.

[0102] The related process parameter selection and specific implementation process of each step are described in embodiment 1.

[0103] The etching process of the ring gate structure etching method of the embodiment can be represented by the following formula:

[0104] (O2dep-ME1) n -O2dep-ME2

[0105] In the formula, O2dep is the oxidation protection step, ME1 is the first etching step, ME2 is the second etching step, and n is 5-10.

[0106] After performing the cyclic etching step on the sidewall of the to-be-etched object, at this time, since the Ge element in the surface layer of the SiGe layer sidewall is enriched to a high degree, the oxidation protection step is performed again, and only a small amount of SiO2 (even no SiO2) can be formed on the SiGe layer sidewall, but the exposed surface of the Si layer can still be oxidized to SiO2. Since the etching rate of the fluorine-based gas on SiO2 is greater than that on Si, by performing the oxidation protection step again in step S103, SiO2 can be formed on the surface of the Si layer again, thereby providing a certain etching protection effect for the Si layer when the second etching step is performed, further protecting the Si layer and ensuring that the Si layer is not etched excessively.

[0107] Embodiment 3

[0108] A method for manufacturing a semiconductor device, comprising the ring gate structure etching method of embodiment 1 or embodiment 2.

[0109] The ring gate structure etching method of any of the above embodiments can remove the SiGe sacrificial layer more completely and the Si layer will not be removed excessively in the process of etching to form the ring gate structure, so that a ring gate structure with better topography is obtained, and the full-surrounding gate transistor manufactured thereby can obtain better device performance.

[0110] The above has described various embodiments of the present application, the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A method of etching a ring gate structure, the method comprising: The method comprises: providing a to-be-etched object, the to-be-etched object comprising a stack structure formed on a substrate, the stack structure comprising a strain layer and a sacrificial layer arranged in an overlapping manner; the strain layer is Si, and the sacrificial layer is SiGe; performing a cyclic etching step on the sidewall of the to-be-etched object, the cyclic etching step comprising sequentially and cyclically performing an oxidation protection step and a first etching step for a set number of times; wherein the oxidation protection step is used to form an oxidation protection layer on the sidewall of the strain layer and the sacrificial layer, wherein the surface layer of the sacrificial layer is oxidized into SiO2, the subsurface layer of the sacrificial layer is Ge-rich SiGe, the surface layer of the strain layer is oxidized into SiO2, and the subsurface layer of the strain layer is Si; and the cyclic etching step is used to enrich Ge in the sacrificial layer; performing a second etching step on the sidewall of the to-be-etched object until the sacrificial layer is etched to a set lateral depth; the plasma density of the second etching step is greater than that of the first etching step, so as to improve the SiGe / Si etching selectivity ratio.

2. The method of claim 1, wherein the etching is performed by dry etching. Between the performing of the cyclic etching step on the sidewall of the to-be-etched object and the performing of the second etching step on the sidewall of the to-be-etched object, the method further comprises: performing the oxidation protection step on the sidewall of the to-be-etched object.

3. The method of claim 1, wherein the etching is performed by dry etching. The set number of times is 5-10 times.

4. The method of claim 1-3, wherein, The etching gas used in the first etching step and the second etching step is fluorine-based gas.

5. The method of claim 4, wherein the etching is performed by dry etching. The proportion of fluorine in the fluorine-based gas in the first etching step is higher than that in the second etching step.

6. The method of claim 4, wherein the etching is performed by dry etching. The fluorine-based gas is a mixed gas of CF4 and C4F6; wherein The ratio of C4F6 to CF4 in the first etching step is less than that in the second etching step.

7. The method of claim 1-3, wherein, The upper electrode radio frequency power used in the first etching step is less than that used in the second etching step.

8. The method of claim 1-3, wherein, The total flow rate of the etching gas used in the first etching step is less than that used in the second etching step.

9. The method of claim 1-3, wherein, The process parameters of the first etching step comprise: the process chamber vacuum degree ranges from 40 mT to 60 mT; the upper electrode radio frequency power ranges from 300 W to 500 W; the total flow rate of C4F6 gas and CF4 gas ranges from 100 sccm to 150 sccm; the ratio of C4F6 gas to CF4 gas ranges from 1:7 to 1:10; the duration of the first etching step ranges from 5 s to 10 s.

10. The method of claim 1-3, wherein, The process parameters of the oxidation protection step comprise: the process chamber vacuum degree ranges from 10 mT to 20 mT; the upper electrode radio frequency power ranges from 500 W to 800 W; the oxygen flow rate ranges from 100 sccm to 200 sccm; the duration of the oxidation protection step ranges from 5 s to 10 s.

11. The method of claim 1-3, wherein, The process parameters of the second etching step comprise: the process chamber vacuum degree ranges from 40 mT to 60 mT; the upper electrode radio frequency power ranges from 500 W to 800 W; the total flow rate of C4F6 gas and CF4 gas ranges from 200 sccm to 250 sccm; the ratio of C4F6 gas to CF4 gas ranges from 1:4 to 1:5; the duration of the second etching step matches the duration corresponding to the etching of the remaining sacrificial layer to the set lateral depth.

12. A method of manufacturing a semiconductor device, characterized by, The method for etching a gate-all-around structure according to any one of claims 1-11.

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