Multi-device layered embedded package structure and method of manufacturing the same

Abstract

This invention discloses a method for fabricating a multi-device layered embedded packaging structure, comprising: preparing a polymer support frame; mounting a first device within a first device placement frame to form a first packaging layer; forming a first circuit layer and a second circuit layer, wherein the terminals of the first device are connected to the second circuit layer, and the first conductive circuit layer and the second circuit layer are conductively connected through a first conductive copper pillar layer; forming a second conductive copper pillar layer and a second sacrificial copper pillar layer; forming a second insulating layer on the first circuit layer, and forming a third insulating layer on the second circuit layer; forming a second device placement frame perpendicularly overlapping the first device placement frame; mounting a second device and a third device within the second device placement frame to form a second packaging layer; forming a third circuit layer on the second insulating layer, wherein the terminals of the second device and the third device are respectively connected to the third circuit layer, and the first conductive circuit layer and the third circuit layer are conductively connected through the second conductive copper pillar layer. A multi-device layered embedded packaging structure is also disclosed.

Description

Technical Field

[0001] This invention relates to electronic device packaging structures, specifically to multi-device layered embedded packaging structures and their fabrication methods. Background Technology

[0002] Currently, the field of panel-level embedded packaging has achieved the embedding of multiple components, but there are still certain limitations: the single-time embedding of multiple components in the same layer inside the substrate has a large horizontal dimension, which cannot meet the development needs of miniaturization of embedded packaging. Furthermore, it is impossible to achieve the most reasonable embedded packaging structure according to the actual product structure and wiring design, which increases the wiring difficulty and wire length and affects electrical performance. Summary of the Invention

[0003] The present invention relates to a multi-device layered embedded packaging structure and its fabrication method to solve the aforementioned technical problems. The present invention can embed multiple components into different layers of a substrate according to the actual needs of the packaging module, effectively reducing the dimensions in the XY directions, achieving higher density integrated packaging, reducing wiring difficulty, and realizing the shortest electrical connection between the device and the substrate, thereby improving the electrical performance of the packaging module.

[0004] The first aspect of this invention relates to a method for fabricating a multi-device layered embedded packaging structure, comprising the following steps:

[0005] (a) Prepare a polymer support frame, the polymer support frame including a first insulating layer, a first conductive copper pillar layer penetrating the first insulating layer and a first device placement frame;

[0006] (b) A first device is mounted on the bottom of the first device placement frame, and a first encapsulation layer is formed in the gap between the first device placement frame and the first device;

[0007] (c) A first circuit layer and a second circuit layer are formed on the upper and lower surfaces of the first insulating layer, respectively. The first circuit layer includes a first conductive circuit layer and a first sacrificial circuit layer. The first sacrificial circuit layer covers the first device placement frame. The terminals of the first device are connected to the second circuit layer. The first conductive circuit layer and the second circuit layer are connected through the first conductive copper pillar layer.

[0008] (d) A second copper pillar layer is formed on the first line layer, the second copper pillar layer including a second conducting copper pillar layer and a second sacrificial copper pillar layer, the second sacrificial copper pillar layer being located on the first sacrificial line layer;

[0009] (e) An insulating material is laminated on the first circuit layer and the second copper pillar layer, the insulating material is thinned to expose the end of the second copper pillar layer to form a second insulating layer, and an insulating material is laminated on the second circuit layer to form a third insulating layer;

[0010] (f) Etching the first sacrificial line layer and the second sacrificial copper pillar layer to form a second device placement frame, wherein the second device placement frame and the first device placement frame are perpendicularly overlapped;

[0011] (g) A second device and a third device are mounted on the bottom of the second device placement frame, and a second encapsulation layer is formed in the gap between the second device placement frame and the second device and the third device, wherein the second device and the third device are respectively vertically overlapped with the first device in layers;

[0012] (h) A third circuit layer is formed on the upper surface of the second insulating layer, wherein the terminals of the second device and the third device are respectively connected to the third circuit layer, and the first conductive circuit layer and the third circuit layer are connected through the second conductive copper pillar layer.

[0013] In some implementation schemes, it also includes:

[0014] (i) Following step (h), an insulating material is laminated on the third circuit layer to form a fourth insulating layer, and a first blind via and a second blind via are formed in the third insulating layer and the fourth insulating layer, respectively;

[0015] (j) A first through hole and a fifth circuit layer are formed in the first blind hole and on the surface of the third insulating layer, respectively; a second through hole and a fourth circuit layer are formed in the second blind hole and on the surface of the fourth insulating layer, respectively; the second circuit layer and the fifth circuit layer are connected through the first through hole; and the third circuit layer and the fourth circuit layer are connected through the second through hole.

[0016] (k) A first solder mask layer is formed on the fourth circuit layer, a second solder mask layer is formed on the fifth circuit layer, and the exposed metal surfaces in the first solder mask layer and the second solder mask layer are treated respectively to form a first metal surface treatment layer and a second metal surface treatment layer.

[0017] In some implementations, step (b) includes:

[0018] (b1) A first adhesive layer is provided at the bottom of the first insulating layer;

[0019] (b2) Attach the terminal face of the first device to the first adhesive layer exposed inside the first device placement frame;

[0020] (b3) A packaging material is laminated on the upper surface of the first insulating layer and in the gap between the first device and the first device placement frame, and the packaging material is cured to form a first packaging layer;

[0021] (b4) Thin the first encapsulation layer to expose the end of the first conductive copper pillar layer;

[0022] (b5) Remove the first adhesive layer.

[0023] In some implementations, the first adhesive layer comprises single-sided tape.

[0024] In some embodiments, step (g) includes attaching the second device and the third device to the bottom of the second device placement frame by providing an adhesive material to the bottom of the second device placement frame and then attaching the back of the second device and the back of the third device to the adhesive material, respectively.

[0025] In some embodiments, step (g) includes attaching the second device and the third device to the bottom of the second device placement frame by providing adhesive materials on the back of the second device and the back of the third device, respectively, and then attaching the back of the second device and the back of the third device to the bottom of the second device placement frame.

[0026] In some implementations, step (i) includes forming a blind hole by laser processing.

[0027] In some implementations, the insulating material is selected from pure resin or resin containing glass fiber.

[0028] In some embodiments, the first encapsulation layer and the second encapsulation layer are respectively selected from thermosetting dielectric materials or photosensitive dielectric materials.

[0029] In some implementations, the first device, the second device, and the third device each include one or more active devices and passive devices.

[0030] The second aspect of this invention relates to a method for fabricating a multi-device layered embedded packaging structure, comprising the following steps:

[0031] (a) Prepare a polymer support frame, the polymer support frame including a first insulating layer, a first conductive copper pillar layer penetrating the first insulating layer and a first device placement frame;

[0032] (b) A first device is mounted on top of the first device placement frame, and a first encapsulation layer is formed in the gap between the first device placement frame and the first device;

[0033] (c) A second circuit layer is formed on the lower surface of the first insulating layer, and a fifth insulating layer is formed on the upper surface of the first insulating layer. The fifth insulating layer includes a sixth circuit layer located within the lower surface of the fifth insulating layer and a third conductive copper pillar layer located on the sixth circuit layer. The terminals of the first device are connected to the sixth circuit layer, and the sixth circuit layer and the second circuit layer are conductively connected through the first conductive copper pillar layer.

[0034] (d) A first circuit layer is formed on the upper surface of the fifth insulating layer. The first circuit layer includes a first conductive circuit layer and a first sacrificial circuit layer. The first conductive circuit layer and the sixth circuit layer are connected through the third conductive copper pillar layer. The first sacrificial circuit layer and the first device placement frame are in the same position in the longitudinal direction.

[0035] (e) A second copper pillar layer is formed on the first line layer, the second copper pillar layer including a second conducting copper pillar layer and a second sacrificial copper pillar layer, the second sacrificial copper pillar layer being located on the first sacrificial line layer;

[0036] (f) Laminating insulating material on the first circuit layer and the second copper pillar layer, thinning the insulating material to expose the end of the second copper pillar layer to form a second insulating layer, and laminating insulating material on the second circuit layer to form a third insulating layer;

[0037] (g) Etching the first sacrificial line layer and the second sacrificial copper pillar layer to form a second device placement frame, wherein the second device placement frame and the first device placement frame are perpendicularly overlapped;

[0038] (h) The second device and the third device are mounted on the bottom of the second device placement frame, and a second encapsulation layer is formed on the upper surface of the second insulating layer and in the gap between the second device placement frame and the second device and the third device, wherein the first device and the second device and the third device are vertically overlapped in layers.

[0039] (i) A third blind via is formed in the second encapsulation layer, a third via is formed in the third blind via, a third circuit layer is formed on the surface of the second encapsulation layer and the third via, the terminals of the second device and the third device are respectively connected to the third circuit layer through the third via, and the first circuit layer and the third circuit layer are connected to each other through the second copper pillar layer and the third via.

[0040] In some implementation schemes, it also includes:

[0041] (j) Following step (i), an insulating material is laminated on the third circuit layer to form a fourth insulating layer, and a first blind via and a second blind via are formed in the third insulating layer and the fourth insulating layer, respectively;

[0042] (k) A first through hole and a fifth circuit layer are formed in the first blind hole and on the surface of the third insulating layer, respectively; a second through hole and a fourth circuit layer are formed in the second blind hole and on the surface of the fourth insulating layer, respectively; the second circuit layer and the fifth circuit layer are connected through the first through hole; and the third circuit layer and the fourth circuit layer are connected through the second through hole.

[0043] (l) A first solder mask layer is formed on the fourth circuit layer, a second solder mask layer is formed on the fifth circuit layer, and the exposed metal surfaces in the first solder mask layer and the second solder mask layer are treated respectively to form a first metal surface treatment layer and a second metal surface treatment layer.

[0044] The third aspect of the present invention relates to a multi-device layered embedded packaging structure, which is prepared using the fabrication method of the multi-device layered embedded packaging structure described in the first aspect of the present invention.

[0045] In some embodiments, the device includes a first insulating layer and a second insulating layer above the first insulating layer. The first insulating layer includes a first conductive copper pillar layer extending through the first insulating layer in the height direction and a first device placement frame. A first device is mounted on the bottom of the first device placement frame. A first encapsulation layer is disposed in the gap between the first device placement frame and the first device. The second insulating layer includes a second device placement frame, a first conductive line layer located in the lower surface of the second insulating layer, and a second conductive copper pillar layer located on the first conductive line layer. A second device and a third device are mounted on the bottom of the second device placement frame. A second encapsulation layer is disposed in the gap between the second device placement frame and the second and third devices. The first device placement frame and the second device placement frame overlap vertically, and the first device overlaps vertically with the second and third devices in layers.

[0046] In some implementation schemes,

[0047] It also includes a third insulating layer below the first insulating layer and a fourth insulating layer above the second insulating layer. The third insulating layer includes a second circuit layer located on the upper surface of the third insulating layer, a first via on the second circuit layer, and a fifth circuit layer located on the lower surface of the third insulating layer. The second circuit layer and the fifth circuit layer are connected through the first via. The first conductive circuit layer and the second circuit layer are connected through the first conductive copper pillar layer. The terminals of the first device are connected to the second circuit layer.

[0048] The fourth insulating layer includes a third circuit layer located on the lower surface of the fourth insulating layer, a second via on the third circuit layer, and a fourth circuit layer located on the upper surface of the fourth insulating layer. The terminals of the second device and the third device are respectively connected to the third circuit layer. The third circuit layer and the fourth circuit layer are connected through the second via. The first conductive circuit layer and the third circuit layer are connected through the second conductive copper pillar layer.

[0049] In some embodiments, the system further includes a first solder resist layer and a second solder resist layer formed on the fourth circuit layer and the fifth circuit layer, respectively, wherein a first metal surface treatment layer is disposed within the first solder resist layer, and a second metal surface treatment layer is disposed within the second solder resist layer.

[0050] The fourth aspect of the present invention relates to a multi-device layered embedded packaging structure, which is prepared using the fabrication method of the multi-device layered embedded packaging structure described in the second aspect of the present invention.

[0051] In some embodiments, the device includes a first insulating layer, a fifth insulating layer above the first insulating layer, and a second insulating layer above the fifth insulating layer. The first insulating layer includes a first conductive copper pillar layer penetrating the first insulating layer along its height and a first device placement frame. A first device is mounted on the top of the first device placement frame. A first encapsulation layer is disposed within the gap between the first device placement frame and the first device. The fifth insulating layer includes a sixth circuit layer located within the lower surface of the fifth insulating layer and a third conductive copper pillar layer located on the sixth circuit layer. The second insulating layer includes a second device placement frame and a third conductive copper pillar layer located on the lower surface of the fifth insulating layer. The second device has a first conductive line layer on the lower surface of the layer and a second conductive copper pillar layer on the first conductive line layer. The bottom of the second device placement frame is fitted with a second device and a third device. A second encapsulation layer is provided on the upper surface of the second insulating layer and in the gap between the second device placement frame and the second and third devices. The sixth circuit layer and the first conductive line layer are conductively connected through the third conductive copper pillar layer. The terminal of the first device is connected to the sixth circuit layer. The first device placement frame and the second device placement frame overlap vertically. The first device overlaps vertically with the second and third devices in layers.

[0052] In some implementation schemes,

[0053] It also includes a third insulating layer below the first insulating layer and a fourth insulating layer above the second insulating layer. The third insulating layer includes a second circuit layer located in the upper surface of the third insulating layer, a first via on the second circuit layer, and a fifth circuit layer located on the lower surface of the third insulating layer. The second circuit layer and the fifth circuit layer are connected through the first via. The sixth circuit layer and the second circuit layer are connected through the first conductive copper pillar layer.

[0054] The fourth insulating layer includes a third circuit layer located on the lower surface of the fourth insulating layer, a second via on the third circuit layer, and a fourth circuit layer located on the upper surface of the fourth insulating layer. The third circuit layer and the fourth circuit layer are connected through the second via. A third via is provided in the second encapsulation layer. The terminals of the second device and the third device are connected to the third circuit layer through the third via. The first conductive circuit layer and the third circuit layer are connected through the second conductive copper pillar layer and the third via.

[0055] In some embodiments, a first solder resist layer and a second solder resist layer formed on the fourth circuit layer and the fifth circuit layer respectively are also included, wherein a first metal surface treatment layer is disposed in the first solder resist layer and a second metal surface treatment layer is disposed in the second solder resist layer. Attached Figure Description

[0056] To better understand the present invention and to illustrate embodiments thereof, reference is made below purely by way of example to the accompanying drawings.

[0057] When referring specifically to the accompanying drawings, it must be emphasized that the particular illustrations are exemplary and intended only to illustrately discuss preferred embodiments of the invention, and are presented for the purpose of providing illustrations that are considered most useful and readily understood for describing the principles and concepts of the invention. In this regard, no attempt is made to illustrate the structural details of the invention to a degree beyond what is necessary for a basic understanding of the invention; the description with reference to the drawings enables those skilled in the art to recognize how various forms of the invention can be practically embodied. In the drawings:

[0058] Figure 1 This is a cross-sectional schematic diagram of an integrated circuit packaging method and packaging structure in the prior art;

[0059] Figure 2 This is a cross-sectional schematic diagram of a multi-device layered embedded packaging structure according to an embodiment of the present invention;

[0060] Figure 3 This is a cross-sectional schematic diagram of a multi-device layered embedded packaging structure according to an embodiment of the present invention;

[0061] Figures 4(a) to 4(m) This diagram illustrates a cross-sectional view of the intermediate structure in each step of a method for fabricating a multi-device layered embedded packaging structure according to an embodiment of the present invention. Detailed Implementation

[0062] With the continuous development of electronic technology, electronic products are trending towards higher functionality and higher integration density. As the miniaturization of components has approached its limit, how to rationally package multiple components to achieve high functionality and high integration density has become a crucial research topic in the industry. Simultaneously, for cost and efficiency considerations, panel-level packaging has become a current trend. During substrate fabrication, components are embedded within the substrate, effectively reducing package size while improving production efficiency, and significantly lowering costs compared to wafer-level packaging. Through continuous development and evolution, panel-level embedded packaging technology is increasingly used and plays an increasingly important role in the semiconductor packaging field. At the same time, panel-level embedded packaging technology has also developed, and currently, it can achieve the embedded packaging of multiple components, but certain limitations still exist.

[0063] Existing panel-level embedded packaging solutions can already achieve embedded packaging of multiple chips and other components, such as the board-level embedded packaging solution disclosed in existing technology CN109686669B. Figure 1 As shown, this packaging structure embeds multiple components 11 into a frame 10 in the middle layer of the substrate at once, followed by single-sided fan-out and then double-sided layer addition. This approach has certain limitations. All components must be embedded and packaged in the initial layer at once, making it impossible to embed and package multiple chips or other components in different layers. Because multiple components can only be embedded and packaged in the same layer within the substrate at once, the horizontal dimension is large, failing to meet the miniaturization requirements of embedded packaging. Furthermore, it cannot achieve the most reasonable embedded packaging structure based on the actual product structure and wiring design, increasing wiring difficulty and wire length, and affecting electrical performance.

[0064] To address the aforementioned problems, this invention provides a multi-device layered embedded packaging structure and its fabrication method, which will be described in detail below with reference to the accompanying drawings.

[0065] Reference Figure 2The diagram shows a cross-sectional schematic of a multi-device layered embedded packaging structure 100. The packaging structure 100 includes a first insulating layer 101 and a second insulating layer 201 above the first insulating layer 101. The first insulating layer 101 and the second insulating layer 201 may include the same material or different materials. The first insulating layer 101 and the second insulating layer 201 may be selected from pure resin or resin containing glass fiber, respectively. Preferably, the first insulating layer is selected from polyimide, epoxy resin, bismaleimide triazine resin (BT), ceramic filler, glass fiber, or a combination thereof, and the second insulating layer is selected from resin containing glass fiber.

[0066] The first insulating layer 101 includes a first conductive copper pillar layer 1012 penetrating the first insulating layer 101 along its height direction and a first device placement frame 1013. A first device 1041 is mounted on the bottom of the first device placement frame 1013, and a first encapsulation layer 1015 is disposed in the gap between the first device placement frame 1013 and the first device 1041. Typically, the device mentioned in this embodiment may include one or more of active and passive devices; the device may be a bare chip, such as an integrated circuit driver chip (IC driver), a field-effect transistor (FET), etc., or a passive device, such as a capacitor, resistor, or inductor, etc., or a single package after preliminary encapsulation, such as a ball grid array (BGA) / grid array (LGA), etc., or a combination of multiple devices; preferably, the first device 1041 is a passive device.

[0067] The conductive copper pillar layer mentioned in this embodiment may include at least one copper via pillar as an I / O channel to achieve conduction between layers. The size and / or shape of the multiple copper via pillars may be the same or different. The copper via pillar may be a solid copper pillar or a hollow pillar with copper plating on the surface. Preferably, the first conductive copper pillar layer 1012 includes multiple copper via pillars as I / O channels. The end of the first conductive copper pillar layer may be flush with the first insulating layer or may be higher than the first insulating layer.

[0068] The encapsulation layer mentioned in this embodiment can be selected from thermosetting dielectric materials or photosensitive dielectric materials. Preferably, the first encapsulation layer 1015 is selected from thermosetting resin materials. The first encapsulation layer 1015 covers the first device 1041, which can fix the first device 1041 and prevent short circuits between the first device 1041 and the second device 1042 or the third device 1043.

[0069] The second insulating layer 201 includes a second device placement frame 2016, a first conductive line layer 2012 located within the lower surface of the second insulating layer 201, and a second conductive copper pillar layer 2014 located on the first conductive line layer 2012. Preferably, the second conductive copper pillar layer 2014 includes multiple copper via pillars as I / O channels. The ends of the second conductive copper pillar layer 2014 can be flush with or extend above the second insulating layer 201. A second device 1042 and a third device 1043 are mounted on the bottom of the second device placement frame 2016. Preferably, both the second device 1042 and the third device 1043 are passive devices. A second encapsulation layer 2018 is disposed in the gap between the second device 1042 and the third device 1043. Preferably, the second encapsulation layer 2018 is selected from a thermosetting resin material. The second encapsulation layer 2018 can fix the second device 1042 and the third device 1043. The first device placement frame 1013 and the second device placement frame 2016 are vertically overlapped. The first device 1041 is layered and vertically overlapped with the second device 1042 and the third device 1043. This effectively reduces the size of the substrate in the XY direction, achieves higher density integrated packaging, reduces wiring difficulty, and achieves the shortest distance electrical connection between the device and the substrate, thereby improving the electrical performance of the packaging module.

[0070] The encapsulation structure 100 further includes a third insulating layer 301 below the first insulating layer 201 and a fourth insulating layer 401 above the second insulating layer 201. Preferably, the third insulating layer 301 and the fourth insulating layer 401 are selected from pure resin. The third insulating layer 301 includes a second circuit layer 3012 located in the upper surface of the third insulating layer 301, a first through hole 3014 on the second circuit layer 3012, and a fifth circuit layer 3015 located on the lower surface of the third insulating layer 301. The second circuit layer 3012 and the fifth circuit layer 3015 are electrically connected through the first through hole 3014. The first conductive circuit layer 2012 and the second circuit layer 3012 are electrically connected through the first conductive copper pillar layer 1012. The terminals of the first device are connected to the second circuit layer.

[0071] The fourth insulating layer 401 includes a third circuit layer 4012 located in the lower surface of the fourth insulating layer 401, a second through hole 4014 on the third circuit layer 4012, and a fourth circuit layer 4015 located on the upper surface of the fourth insulating layer 401. The terminals of the second device 1042 and the third device 1043 are respectively connected to the third circuit layer 4012. The third circuit layer 4012 and the fourth circuit layer 4015 are electrically connected through the second through hole 4014. The first conductive circuit layer 1012 and the third circuit layer 4012 are electrically connected through the second conductive copper pillar layer 2014.

[0072] Reference Figure 2The packaging structure 100 also includes a first solder resist layer 601 and a second solder resist layer 701 formed on the fourth circuit layer 4015 and the fifth circuit layer 3015, respectively. A first metal surface treatment layer 6011 is disposed in the first solder resist layer 601, and a second metal surface treatment layer 7011 is disposed in the second solder resist layer 701.

[0073] Reference Figure 3 The diagram shows a cross-sectional view of a multi-device layered embedded packaging structure 200. The difference between packaging structure 200 and packaging structure 100 is that packaging structure 200 includes a fifth insulating layer 501 located between the first insulating layer 101 and the second insulating layer 201. Preferably, the fifth insulating layer 501 is selected from a resin containing glass fiber. The fifth insulating layer 501 includes a sixth circuit layer 5012 located within the lower surface of the fifth insulating layer 501 and a third conductive copper pillar layer 5013 located on the sixth circuit layer 5012. Preferably, the third conductive copper pillar layer 5013 includes multiple copper via pillars as I / O channels. The end of the third conductive copper pillar layer 5013 can be flush with or extend above the fifth insulating layer 501. The first conductive circuit layer 2012 and the sixth circuit layer... 5012 is electrically connected through the third conductive copper pillar layer 5013; the first device 1041 is mounted on the top of the first device placement frame 1013, and the terminals of the first device 1041 are connected to the sixth circuit layer 5012; a second encapsulation layer 2018 is provided on the upper surface of the second insulating layer 201 and in the gap between the second device placement frame 2016 and the second device 1042 and the third device 1043, and a third through hole 2019 is provided in the second encapsulation layer 2018, and the terminals of the second device 1042 and the third device 1043 are respectively connected to the third circuit layer 4012 through the third through hole 2019; the first conductive circuit layer 2012 and the third circuit layer 4012 are electrically connected through the second conductive copper pillar layer 2014 and the third through hole 2019.

[0074] Reference Figures 4(a) to 4(m) The diagram shows a cross-sectional schematic of the intermediate structure of each step in the fabrication method of a multi-device layered embedded packaging structure 100 according to an embodiment of the present invention.

[0075] The manufacturing method includes the following steps: preparing a polymer support frame, as shown in Figure 4(a). The polymer support frame includes a first insulating layer 101, a first conductive copper pillar layer 1012 penetrating the first insulating layer 101, and a first device placement frame 1013. Typically, the first device placement frame 1013 can penetrate the first insulating layer 101. Multiple first device placement frames 1013 can be provided for subsequent device mounting. Their dimensions can be the same or different, depending on the shape and size of the device to be embedded.

[0076] Typically, the manufacturing method of polymer support frames includes the following sub-steps:

[0077] Obtain the sacrificial vessel;

[0078] A copper seed layer was applied to the sacrificial carrier;

[0079] Apply an anti-corrosion layer to the sacrificial carrier;

[0080] Apply another copper seed layer;

[0081] Apply a photoresist layer;

[0082] Patterned photoresist is a pattern with copper vias and loop-shaped vias;

[0083] In the pattern, electroplated copper forms the first conductive copper pillar layer 1012 and the first loop-shaped copper pillar layer;

[0084] Remove the photoresist layer;

[0085] The first conductive copper pillar layer 1012 and the first loop strip copper pillar layer are laminated with insulating material.

[0086] Thinning and planarizing the insulating material exposes the ends of the first conductive copper pillar layer 1012 and the first loop strip copper pillar layer, forming the first insulating layer 101;

[0087] Remove the sacrificial carrier;

[0088] Etching the resist layer;

[0089] An upper photoresist layer and a lower photoresist layer are applied to the upper and lower surfaces of the first insulating layer 101, respectively. The upper and lower photoresist layers are exposed and developed to expose the loop-shaped copper pillars in the first loop-shaped copper pillar layer.

[0090] A loop-shaped copper pillar is etched and the dielectric material inside is removed to form the first device placement frame 1013. The upper and lower photoresist layers are removed to obtain the polymer support frame.

[0091] Next, a first adhesive layer 1014 is provided at the bottom of the first insulating layer 101, and the terminal surface of the first device 1041 is attached to the exposed first adhesive layer 1014 within the first device placement frame 1013, as shown in FIG4(b). Typically, the first adhesive layer 1014 can be single-sided tape, usually a commercially available transparent film that is thermally degradable or degradable under ultraviolet light. The first adhesive layer 1014 provides temporary support and fixation for the first device 1041. Preferably, the first device is a passive component.

[0092] Then, a packaging material is laminated on the upper surface of the first insulating layer 101 and in the gap between the first device 1041 and the first device placement frame 1013. The packaging material is cured to form a first packaging layer 1015. The first packaging layer 1015 is thinned to expose the end of the first conductive copper pillar layer 1012. The first adhesive layer 1014 is removed, as shown in FIG4(c). Typically, the first adhesive layer 1014 can be removed by ultraviolet light irradiation or thermal decomposition. The packaging material can be selected from thermosetting dielectric materials or photosensitive dielectric materials. Preferably, a thermosetting resin material is laminated and cured by heating to form the first packaging layer 1015. The first packaging layer 1015 can be thinned as a whole by plasma etching or grinding to expose the end of the first conductive copper pillar layer 1012.

[0093] Next, a first circuit layer and a second circuit layer 3012 are formed on the upper and lower surfaces of the first insulating layer 101, respectively. The first circuit layer includes a first conductive circuit layer 2012 and a first sacrificial circuit layer 2013. The first sacrificial circuit layer 2012 covers the first device placement frame 1013. The terminals of the first device 1041 are connected to the second circuit layer 3012. The first conductive circuit layer 2012 and the second circuit layer 3012 are electrically connected through a first conductive copper pillar layer 1012, as shown in Figure 4(d). Typically, the following steps are included:

[0094] A first metal seed layer 2011 and a second metal seed layer 3011 are formed on the upper and lower surfaces of the first insulating layer 101, respectively.

[0095] A first photoresist layer is applied on the first metal seed layer 2011, and a second photoresist layer is applied on the second metal seed layer 3011;

[0096] The first and second photoresist layers are exposed and developed to form the first and second feature patterns, respectively.

[0097] A first circuit layer is formed by electroplating in a first feature pattern, and a second circuit layer 3012 is formed by electroplating in a second feature pattern;

[0098] Remove the first and second photoresist layers.

[0099] Typically, a metal seed layer can be formed by chemical plating or sputtering. The metal seed layer can comprise titanium, copper, titanium-tungsten alloy, or a combination thereof. Preferably, titanium and copper are sputtered to form the first metal seed layer 2011 and the second metal seed layer 3011. Copper is electroplated in the first and second feature patterns to form the first circuit layer and the second circuit layer 3012, respectively. The thickness of the first circuit layer and the second circuit layer 3012 can be determined according to actual needs. The number of sacrificial lines included in the first sacrificial circuit layer 2013 in the first circuit layer can be determined according to the number of devices to be embedded.

[0100] Then, a second copper pillar layer is formed on the first circuit layer. The second copper pillar layer includes a second conductive copper pillar layer 2014 and a second sacrificial copper pillar layer 2015, which is located on the first sacrificial circuit layer 2013, as shown in Figure 4(e). Typically, the following steps are included:

[0101] A third photoresist layer is applied on the first circuit layer, and the third photoresist layer is exposed and developed to form a third feature pattern.

[0102] In the third feature pattern, copper is electroplated to form a second copper pillar layer;

[0103] Remove the third photoresist layer and etch the exposed first metal seed layer 2011 and second metal seed layer 3011.

[0104] Next, an insulating material is laminated onto the first circuit layer and the second copper pillar layer. The insulating material is thinned to expose the ends of the second copper pillar layer to form a second insulating layer 201. An insulating material is then laminated onto the second circuit layer 3012 to form a third insulating layer 301, as shown in FIG4(f). Preferably, the second insulating layer is selected from a resin containing glass fiber, and the third insulating layer is selected from pure resin. Typically, the insulating material can be thinned entirely, for example, by grinding or plasma etching; or the insulating material can be thinned partially, for example, by laser or mechanical drilling to partially thin the insulating material on the second copper pillar layer to expose the ends of the second copper pillar layer; preferably, the insulating material is thinned entirely to expose the ends of the second copper pillar layer by grinding or plasma etching.

[0105] Then, the first sacrificial circuit layer 2013 and the second sacrificial copper pillar layer 2015 are etched to form the second device placement frame 2016, which is perpendicularly overlapped with the first device placement frame 1013, as shown in Figure 4(g). Typically, the process may include the following steps:

[0106] A fourth photoresist layer is applied to the upper surface of the second insulating layer 201;

[0107] Exposure and development form the fourth feature pattern, exposing the end of the second sacrificial copper pillar layer 2015;

[0108] Etch the second sacrificial copper pillar layer 2015 and the first sacrificial circuit layer 2013 to form the second device placement frame 2016;

[0109] Remove the fourth photoresist layer.

[0110] Next, the second device 1042 and the third device 1043 are mounted on the bottom of the second device placement frame 2016. The second device 1042 and the third device 1043 are respectively layered and vertically overlapped with the first device 1041, as shown in Figure (h). Typically, this can be achieved by providing an adhesive material 2017 to the bottom of the second device placement frame 2016, and then attaching the back surfaces of the second device 1042 and the third device 1043 to the adhesive material 2017. Alternatively, this can be achieved by providing adhesive material 2017 to the back surfaces of the second device 1042 and the third device 1043 respectively, and then attaching the back surfaces of the second device 1042 and the third device 1043 to the bottom of the second device placement frame 2016. Preferably, the second device 1042 and the third device 1043 are both passive components.

[0111] Next, a second encapsulation layer 2018 is formed within the gap between the second device placement frame 2016 and the second device 1042 and the third device 1043, as shown in FIG4(i). Typically, this includes the following steps:

[0112] Encapsulation material is laminated on the upper surface of the second insulating layer 201 and in the gap between the second device placement frame 2016 and the second device 1042 and the third device 1043, and the encapsulation material is cured to form the second encapsulation layer 2018.

[0113] Thinning the second encapsulation layer 2018 exposes the end of the second conductive copper pillar layer 2014, the terminals of the second device 1042, and the terminals of the second device 1043.

[0114] Preferably, the second encapsulation layer 2018 is formed by laminating a thermosetting resin material and curing the thermosetting resin material by heating; the second encapsulation layer 2018 can be thinned as a whole by plasma etching or grinding to expose the ends of the second conductive copper pillar layer 2014, the second device 1042 and the second device 1043.

[0115] Then, a third circuit layer 4012 is formed on the upper surface of the second insulating layer 201. The terminals of the second device 1042 and the third device 1043 are respectively connected to the third circuit layer 4012. The first conductive circuit layer 2012 and the third circuit layer 4012 are connected through the second conductive copper pillar layer 2014, as shown in Figure 4(j). Typically, the following steps may be included:

[0116] A third metal seed layer 4011 is formed on the upper surface of the second insulating layer 201;

[0117] A fifth photoresist layer is applied to the third metal seed layer 4011, and the fifth feature pattern is formed by exposure and development.

[0118] In the fifth feature pattern, copper is electroplated to form the third circuit layer 4012;

[0119] Remove the fifth photoresist layer and etch the exposed third metal seed layer 4011.

[0120] Preferably, the third metal seed layer 4011 is prepared by sputtering titanium and copper.

[0121] Next, an insulating material is laminated onto the third circuit layer 4012 to form a fourth insulating layer 401. A first blind via 3017 and a second blind via 4017 are formed within the third insulating layer 301 and the fourth insulating layer 401, respectively, as shown in Figure 4(k). Typically, blind vias can be formed by laser processing. Preferably, the fourth insulating layer is selected from pure resin.

[0122] Then, a first through-hole 3014 and a fifth circuit layer 3015 are formed in the first blind via 3017 and on the surface of the third insulating layer 301, respectively. A second through-hole 4014 and a fourth circuit layer 4015 are formed in the second blind via 4017 and on the surface of the fourth insulating layer 401, respectively. The second circuit layer 3012 and the fifth circuit layer 3015 are connected through the first through-hole 3014, and the third circuit layer 4012 and the fourth circuit layer 4015 are connected through the second through-hole 4014, as shown in Figure 4(l). Typically, the following steps may be included:

[0123] A fifth metal seed layer 3013 is formed on the bottom and sidewalls of the first blind hole 3017 and on the surface of the third insulating layer 301, and a fourth metal seed layer 4013 is formed on the bottom and sidewalls of the second blind hole 4017 and on the surface of the fourth insulating layer 401.

[0124] A sixth photoresist layer is applied on the fourth metal seed layer 4013, and a seventh photoresist layer is applied on the fifth metal seed layer 3013. The sixth and seventh photoresist layers are exposed and developed to form the sixth feature pattern and the seventh feature pattern, respectively.

[0125] In the sixth feature pattern, copper is electroplated to form the second via 4014 and the fourth circuit layer 4015, and in the seventh feature pattern, copper is electroplated to form the first via 3014 and the fifth circuit layer 3015.

[0126] Remove the sixth and seventh photoresist layers, and etch the exposed fourth metal seed layer 4013 and fifth metal seed layer 3013.

[0127] Preferably, the fourth metal seed layer 4013 and the fifth metal seed layer 3013 are fabricated by sputtering titanium and copper.

[0128] Finally, a first solder mask layer 601 is formed on the fourth circuit layer 4015, and a second solder mask layer 701 is formed on the fifth circuit layer 3015. The exposed metal surfaces within the first solder mask layer 601 and the second solder mask layer 701 are then treated to form a first metal surface treatment layer 6011 and a second metal surface treatment layer 7011, as shown in Figure 4(m). Typically, anti-oxidation, nickel-palladium-gold plating, tin plating, silver plating, etc., can be selected to form the first metal surface treatment layer 6011 and the second metal surface treatment layer 7011.

[0129] The present invention also provides a method for fabricating a multi-device layered embedded packaging structure 200. The method for fabricating the packaging structure 200 differs from the method for fabricating the packaging structure 100 in that: 1. The first device 1041 is mounted on the top of the first device placement frame 1013; 2. After forming the first packaging layer 1015, a fifth insulating layer 501 is formed on the upper surface of the first insulating layer 101. The fifth insulating layer 501 includes a sixth circuit layer 5012 located in the lower surface of the fifth insulating layer 501 and a third conductive copper pillar layer 5013 located on the sixth circuit layer 5012. The terminals of the first device 1041 are connected to the sixth circuit layer 5012, and the sixth circuit layer 5012 and the second circuit layer 3012 are conductively connected through the first conductive copper pillar layer 1012; 3. On the fifth insulating layer 501... A first circuit layer is formed, comprising a first conductive circuit layer 2012 and a first sacrificial circuit layer 2013. The first conductive circuit layer 2012 and the sixth circuit layer 5012 are conductively connected through a third conductive copper pillar layer 5013. A second encapsulation layer 2018 is formed on the upper surface of the second insulating layer 201 and in the gap between the second device placement frame 2016 and the second device 1042 and the third device 1043. A third through hole 2019 is formed in the second encapsulation layer 2018. The terminals of the second device 1042 and the third device 1043 are conductively connected to the third circuit layer 4012 through the third through hole 2019, respectively. The first conductive circuit layer 2012 and the third circuit layer 4012 are conductively connected through a second conductive copper pillar layer 2014 and the third through hole 2019.

[0130] The other steps in the fabrication method of package structure 200 are the same as the corresponding steps in the fabrication method of package structure 100, and will not be repeated here.

[0131] Those skilled in the art will recognize that the present invention is not limited to the specific illustrations and descriptions in the context. Furthermore, the scope of the invention is defined by the appended claims, including combinations and sub-combinations of the various technical features described above, as well as variations and modifications thereof, which will be foreseen by those skilled in the art upon reading the foregoing description.

[0132] In the claims, the term "comprising" and its variations, such as "including" or "containing," means that the listed components are included, but generally do not exclude other components.

Claims

1. A method for fabricating a multi-device layered embedded packaging structure, comprising the following steps: (a) Prepare a polymer support frame, the polymer support frame including a first insulating layer, a first conductive copper pillar layer penetrating the first insulating layer and a first device placement frame; (b) A first device is mounted on the bottom of the first device placement frame, and a first encapsulation layer is formed in the gap between the first device placement frame and the first device; (c) A first circuit layer and a second circuit layer are formed on the upper and lower surfaces of the first insulating layer, respectively. The first circuit layer includes a first conductive circuit layer and a first sacrificial circuit layer. The first sacrificial circuit layer covers the first device placement frame. The terminals of the first device are connected to the second circuit layer. The first conductive circuit layer and the second circuit layer are connected through the first conductive copper pillar layer. (d) A second copper pillar layer is formed on the first line layer, the second copper pillar layer including a second conducting copper pillar layer and a second sacrificial copper pillar layer, the second sacrificial copper pillar layer being located on the first sacrificial line layer; (e) An insulating material is laminated on the first circuit layer and the second copper pillar layer, the insulating material is thinned to expose the end of the second copper pillar layer to form a second insulating layer, and an insulating material is laminated on the second circuit layer to form a third insulating layer; (f) Etching the first sacrificial line layer and the second sacrificial copper pillar layer to form a second device placement frame, wherein the second device placement frame and the first device placement frame are perpendicularly overlapped; (g) A second device and a third device are mounted on the bottom of the second device placement frame, and a second encapsulation layer is formed in the gap between the second device placement frame and the second device and the third device, wherein the second device and the third device are respectively vertically overlapped with the first device in layers; (h) A third circuit layer is formed on the upper surface of the second insulating layer, wherein the terminals of the second device and the third device are respectively connected to the third circuit layer, and the first conductive circuit layer and the third circuit layer are connected through the second conductive copper pillar layer.

2. The manufacturing method according to claim 1 further includes: (i) Following step (h), an insulating material is laminated on the third circuit layer to form a fourth insulating layer, and a first blind via and a second blind via are formed in the third insulating layer and the fourth insulating layer, respectively; (j) A first through hole and a fifth circuit layer are formed in the first blind hole and on the surface of the third insulating layer, respectively; a second through hole and a fourth circuit layer are formed in the second blind hole and on the surface of the fourth insulating layer, respectively; the second circuit layer and the fifth circuit layer are connected through the first through hole; and the third circuit layer and the fourth circuit layer are connected through the second through hole. (k) A first solder mask layer is formed on the fourth circuit layer, a second solder mask layer is formed on the fifth circuit layer, and the exposed metal surfaces in the first solder mask layer and the second solder mask layer are treated respectively to form a first metal surface treatment layer and a second metal surface treatment layer.

3. The manufacturing method according to claim 1, wherein step (b) comprises: (b1) A first adhesive layer is provided at the bottom of the first insulating layer; (b2) Attach the terminal face of the first device to the first adhesive layer exposed inside the first device placement frame; (b3) A packaging material is laminated on the upper surface of the first insulating layer and in the gap between the first device and the first device placement frame, and the packaging material is cured to form a first packaging layer; (b4) Thin the first encapsulation layer to expose the end of the first conductive copper pillar layer; (b5) Remove the first adhesive layer.

4. The manufacturing method according to claim 3, wherein the first adhesive layer comprises single-sided adhesive tape.

5. The manufacturing method according to claim 1, wherein step (g) includes attaching an adhesive material to the bottom of the second device placement frame, and then attaching the back of the second device and the back of the third device to the adhesive material respectively, so as to attach the second device and the third device to the bottom of the second device placement frame.

6. The manufacturing method according to claim 1, wherein step (g) includes attaching the second device and the third device to the bottom of the second device placement frame by respectively providing adhesive materials on the back side of the second device and the back side of the third device, and then attaching the back side of the second device and the back side of the third device to the bottom of the second device placement frame.

7. The manufacturing method according to claim 2, wherein step (i) includes forming a blind hole by laser processing.

8. The manufacturing method according to claim 2, wherein the insulating material is selected from pure resin or resin containing glass fiber.

9. The manufacturing method according to claim 1, wherein the first encapsulation layer and the second encapsulation layer are respectively selected from thermosetting dielectric materials or photosensitive dielectric materials.

10. The manufacturing method according to claim 1, wherein the first device, the second device and the third device respectively include one or more of active devices and passive devices.

11. A method for fabricating a multi-device layered embedded packaging structure, comprising the following steps: (a) Prepare a polymer support frame, the polymer support frame including a first insulating layer, a first conductive copper pillar layer penetrating the first insulating layer and a first device placement frame; (b) A first device is mounted on top of the first device placement frame, and a first encapsulation layer is formed in the gap between the first device placement frame and the first device; (c) A second circuit layer is formed on the lower surface of the first insulating layer, and a fifth insulating layer is formed on the upper surface of the first insulating layer. The fifth insulating layer includes a sixth circuit layer located within the lower surface of the fifth insulating layer and a third conductive copper pillar layer located on the sixth circuit layer. The terminals of the first device are connected to the sixth circuit layer, and the sixth circuit layer and the second circuit layer are conductively connected through the first conductive copper pillar layer. (d) A first circuit layer is formed on the upper surface of the fifth insulating layer. The first circuit layer includes a first conductive circuit layer and a first sacrificial circuit layer. The first conductive circuit layer and the sixth circuit layer are connected through the third conductive copper pillar layer. The first sacrificial circuit layer and the first device placement frame are in the same position in the longitudinal direction. (e) A second copper pillar layer is formed on the first line layer, the second copper pillar layer including a second conducting copper pillar layer and a second sacrificial copper pillar layer, the second sacrificial copper pillar layer being located on the first sacrificial line layer; (f) Laminating insulating material on the first circuit layer and the second copper pillar layer, thinning the insulating material to expose the end of the second copper pillar layer to form a second insulating layer, and laminating insulating material on the second circuit layer to form a third insulating layer; (g) Etching the first sacrificial line layer and the second sacrificial copper pillar layer to form a second device placement frame, wherein the second device placement frame and the first device placement frame are perpendicularly overlapped; (h) The second device and the third device are mounted on the bottom of the second device placement frame, and a second encapsulation layer is formed on the upper surface of the second insulating layer and in the gap between the second device placement frame and the second device and the third device, wherein the first device and the second device and the third device are vertically overlapped in layers. (i) A third blind via is formed in the second encapsulation layer, a third via is formed in the third blind via, a third circuit layer is formed on the surface of the second encapsulation layer and the third via, the terminals of the second device and the third device are respectively connected to the third circuit layer through the third via, and the first circuit layer and the third circuit layer are connected to each other through the second copper pillar layer and the third via.

12. The manufacturing method according to claim 11, further comprising: (j) Following step (i), an insulating material is laminated on the third circuit layer to form a fourth insulating layer, and a first blind via and a second blind via are formed in the third insulating layer and the fourth insulating layer, respectively; (k) A first through hole and a fifth circuit layer are formed in the first blind hole and on the surface of the third insulating layer, respectively; a second through hole and a fourth circuit layer are formed in the second blind hole and on the surface of the fourth insulating layer, respectively; the second circuit layer and the fifth circuit layer are connected through the first through hole; and the third circuit layer and the fourth circuit layer are connected through the second through hole. (l) A first solder mask layer is formed on the fourth circuit layer, a second solder mask layer is formed on the fifth circuit layer, and the exposed metal surfaces in the first solder mask layer and the second solder mask layer are treated respectively to form a first metal surface treatment layer and a second metal surface treatment layer.

13. A multi-device layered embedded packaging structure, which is prepared by the fabrication method of the multi-device layered embedded packaging structure according to any one of claims 1-10.

14. The multi-device layered embedded packaging structure according to claim 13, comprising a first insulating layer and a second insulating layer above the first insulating layer, the first insulating layer comprising a first conductive copper pillar layer penetrating the first insulating layer along the height direction and a first device placement frame, a first device being mounted on the bottom of the first device placement frame, a first encapsulation layer being disposed in the gap between the first device placement frame and the first device, the second insulating layer comprising a second device placement frame, a first conductive line layer located in the lower surface of the second insulating layer and a second conductive copper pillar layer located on the first conductive line layer, a second device and a third device being mounted on the bottom of the second device placement frame, a second encapsulation layer being disposed in the gap between the second device placement frame and the second device and the third device, wherein the first device placement frame and the second device placement frame vertically overlap, and the first device, the second device, and the third device are layered and vertically overlapped.

15. The multi-device layered embedded packaging structure according to claim 14 further includes a third insulating layer below the first insulating layer and a fourth insulating layer above the second insulating layer, the third insulating layer including a second circuit layer located in the upper surface of the third insulating layer, a first via on the second circuit layer and a fifth circuit layer located on the lower surface of the third insulating layer, the second circuit layer and the fifth circuit layer being electrically connected through the first via, the first conductive circuit layer and the second circuit layer being electrically connected through the first conductive copper pillar layer, and the terminal of the first device being connected to the second circuit layer; The fourth insulating layer includes a third circuit layer located on the lower surface of the fourth insulating layer, a second via on the third circuit layer, and a fourth circuit layer located on the upper surface of the fourth insulating layer. The terminals of the second device and the third device are respectively connected to the third circuit layer. The third circuit layer and the fourth circuit layer are connected through the second via. The first conductive circuit layer and the third circuit layer are connected through the second conductive copper pillar layer.

16. The multi-device layered embedded packaging structure according to claim 15 further includes a first solder resist layer and a second solder resist layer formed on the fourth circuit layer and the fifth circuit layer respectively, wherein a first metal surface treatment layer is disposed in the first solder resist layer and a second metal surface treatment layer is disposed in the second solder resist layer.

17. A multi-device layered embedded packaging structure, which is prepared by the fabrication method of the multi-device layered embedded packaging structure according to any one of claims 11-12.

18. The multi-device layered embedded packaging structure according to claim 17, comprising a first insulating layer, a fifth insulating layer above the first insulating layer, and a second insulating layer above the fifth insulating layer, wherein the first insulating layer comprises a first conductive copper pillar layer penetrating the first insulating layer along the height direction and a first device placement frame, a first device is mounted on the top of the first device placement frame, and a first encapsulation layer is disposed in the gap between the first device placement frame and the first device, the fifth insulating layer comprises a sixth circuit layer located in the lower surface of the fifth insulating layer and a third conductive copper pillar layer located on the sixth circuit layer, and the second insulating layer comprises a second device placement frame, The second device has a first conductive line layer located on the lower surface of the second insulating layer and a second conductive copper pillar layer located on the first conductive line layer. The bottom of the second device placement frame is fitted with a second device and a third device. A second encapsulation layer is provided on the upper surface of the second insulating layer and in the gap between the second device placement frame and the second and third devices. The sixth circuit layer and the first conductive line layer are conductively connected through the third conductive copper pillar layer. The terminal of the first device is connected to the sixth circuit layer. The first device placement frame and the second device placement frame overlap vertically. The first device overlaps vertically with the second and third devices in layers.

19. The multi-device layered embedded packaging structure according to claim 18 further includes a third insulating layer below the first insulating layer and a fourth insulating layer above the second insulating layer, wherein the third insulating layer includes a second circuit layer located in the upper surface of the third insulating layer, a first via on the second circuit layer and a fifth circuit layer located on the lower surface of the third insulating layer, the second circuit layer and the fifth circuit layer are connected through the first via, and the sixth circuit layer and the second circuit layer are connected through the first conductive copper pillar layer; The fourth insulating layer includes a third circuit layer located on the lower surface of the fourth insulating layer, a second via on the third circuit layer, and a fourth circuit layer located on the upper surface of the fourth insulating layer. The third circuit layer and the fourth circuit layer are connected through the second via. A third via is provided in the second encapsulation layer. The terminals of the second device and the third device are connected to the third circuit layer through the third via. The first conductive circuit layer and the third circuit layer are connected through the second conductive copper pillar layer and the third via.

20. The multi-device layered embedded packaging structure according to claim 19 further includes a first solder mask layer and a second solder mask layer formed on the fourth circuit layer and the fifth circuit layer respectively, wherein a first metal surface treatment layer is disposed in the first solder mask layer and a second metal surface treatment layer is disposed in the second solder mask layer.

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