Fan-out package structure of multi-element device and packaging method thereof

Abstract

The application discloses a fan-out packaging structure and method of multi-component devices, which comprises at least two components with different thicknesses. The component with smaller thickness is firstarily molded, then the metal bumps are made on the surface of each component, and then each component is attached to the substrate in an upward manner and secondarily molded. The re-routed layer electrically connected with the metal bumps is made. The method can not only be compatible with the thickness difference of the two components, but also effectively overcome the difficulty caused by the uneven wafer surface due to the component bump in the subsequent photoetching step and chemical mechanical polishing process.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a fan-out packaging structure integrating ASIC and capacitor and a packaging method thereof. Background Art

[0002] The massive mobile device market, a key growth driver for both low-density and high-density fan-out packaging, has garnered increasing attention for fan-out packaging technology. Fan-out technology can be broadly categorized into three types: die-first face-down placement, die-first face-up placement, and die-last placement. In a typical die-first process, the wafer fab first processes the die on the wafer, then moves the wafer to the packaging facility for dicing. Finally, a high-precision die-attachment system places the die face-down on a designated position on a temporary carrier. Wafer-level molding is then performed to create the molded package. After molding, debonding is performed to separate the molded package from the temporary carrier, where the embedded die is embedded. Next, multiple rewiring layers are constructed, including sputtering the seed layer, photolithography, electroplating, resist stripping, etching the seed layer, and forming the passivation layer. In the face-up placement process, metal bumps are first fabricated on the die. A high-precision die-attachment system then places the qualified die face-up on a designated position on a temporary carrier, followed by wafer-level molding. After the plastic package solidifies, the surface is ground to expose the metal bumps on the chip. A multi-layer redistribution layer connecting the metal bumps is then prepared. The main process flow is sputtering the seed layer, photolithography, electroplating, debonding, etching the seed layer, and passivation layer fabrication.

[0003] For fan-out integration based on application-specific integrated circuits (ASICs) and supporting capacitor components, face-down placement is more suitable due to the large thickness tolerances between the ASICs and ceramic capacitors. However, one of the challenges of face-down chip placement is the chip bumping, which affects wafer flatness. This chip bumping poses challenges to the photolithography and chemical mechanical polishing processes. Summary of the Invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a high-density fan-out packaging structure and a packaging method thereof that integrates an ASIC chip and a matching capacitor element based on a chip-face-up patch method.

[0005] It is well known to those skilled in the art that the front surface of the first component and the second component mentioned in the present invention refers to the surface of the component having the pad for external circuit connection.

[0006] In order to achieve the above objectives, the technical solution of the present invention is:

[0007] A fan-out packaging method for a multi-component device includes at least a first component and a second component, wherein the thickness of the first component is smaller than that of the second component, and the packaging method includes the following steps:

[0008] 1) Encapsulating a first component in a first plastic encapsulation layer with the front surface exposed, and forming a first metal bump on the front surface to obtain a first component encapsulation unit; and forming a second metal bump on the front surface of a second component;

[0009] 2) providing a substrate and attaching a permanent bonding film to the substrate;

[0010] 3) mounting the first component package unit and the second component with the second metal bump on the permanent bonding film with the front side facing upward;

[0011] 4) encapsulating the first component packaging unit and the second component with the second metal bump in a second plastic packaging layer, and grinding and thinning the surface of the second plastic packaging layer until the first metal bump and the second metal bump are exposed;

[0012] 5) Use embedded copper wire technology to make a rewiring layer on the thinned surface.

[0013] Optionally, in step 1), the first plastic encapsulation layer covers the back and side surfaces of the first component, and the thickness on the back side of the first component is the same as the difference in thickness between the first component and the second component.

[0014] Optionally, step 1) specifically includes:

[0015] 1.1) Provide a temporary carrier and apply temporary bonding adhesive on the carrier;

[0016] 1.2) placing a plurality of the first components face down on a temporary carrier coated with temporary bonding glue at a preset position;

[0017] 1.3) performing wafer-level plastic encapsulation on the first component to obtain a first plastic encapsulation layer;

[0018] 1.4) Debonding to separate the first plastic encapsulation layer embedded with the first component from the temporary carrier;

[0019] 1.5) forming the first metal bump on the front surface of the first component;

[0020] 1.6) Slicing to obtain individual first component packaging units.

[0021] Optionally, the second component is a chip, and step 1) further includes:

[0022] 1.7) forming a second metal bump on the front side of the second component wafer;

[0023] 1.8) Slicing to obtain individual second components with second metal bumps.

[0024] Optionally, the first metal bump and the second metal bump are manufactured using an electroplating process.

[0025] Optionally, in step 4), the grinding and thinning is performed by mechanical grinding.

[0026] Optionally, in step 6), the embedded copper wire process is to form a dielectric layer on the thinned surface, etch the dielectric layer for patterning, then fill it with metal, and then use a chemical mechanical polishing process to flatten the surface and remove the surface metal to obtain a multi-layer rewiring layer.

[0027] A fan-out packaging structure for a multi-component device comprises a substrate, a permanent bonding film provided on the substrate, a multi-component plastic package provided on the permanent bonding film, and a redistribution layer provided on the multi-component plastic package; the multi-component plastic package comprises a plastic package material and a first component and a second component encapsulated in the plastic package material, the first component and the second component having different thicknesses; the front surfaces of the first component and the second component face upward and are located on the same horizontal plane, and are respectively provided with a first metal bump and a second metal bump, the first component and the second component being electrically connected to the redistribution layer via the first metal bump and the second metal bump, respectively.

[0028] Optionally, the thickness of the first component is smaller than that of the second component, the second component is attached to the permanent bonding film, and a plastic packaging material of a certain thickness is located between the first component and the permanent bonding film.

[0029] Optionally, the first component is a capacitor, and the second component is an ASIC chip.

[0030] The beneficial effects of the present invention are:

[0031] Compared with the chip-face-down mounting solution, this method solves the difficulties caused by the uneven wafer surface caused by the chip protrusion, which comes in the subsequent photolithography steps and chemical mechanical polishing processes. It is also compatible with components with large thickness tolerances, thereby realizing the formation of a high-density three-dimensional packaging structure of two heterogeneous components. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a process flow chart of a capacitor packaging unit according to an embodiment, showing the structure obtained in each step;

[0033] Figure 2 is a schematic diagram of an ASIC chip with second metal bumps according to an embodiment;

[0034] Figures 3 to 6 for Figure 1 and Figure 2 Figure 1 is a flow chart of the packaging process for the capacitor packaging unit and ASIC chip, showing the structure obtained in each step. DETAILED DESCRIPTION

[0035] The present invention will be further explained below with reference to the accompanying drawings and specific embodiments. The accompanying drawings are merely for illustration to facilitate understanding of the present invention, and their specific proportions may be adjusted according to design requirements.

[0036] The following is an example of fan-out integration of a ceramic capacitor component with a large thickness tolerance (thickness difference of about 50μm) and an integrated circuit chip (ASIC) as the first component and the second component respectively. Figures 1 to 3 The following describes a fan-out packaging method that integrates ASIC and capacitors.

[0037] refer to Figure 1 First, make the capacitor packaging unit 100. Specific steps: refer to Figure 1 a. Apply a temporary bonding adhesive 2 on a temporary carrier 1 with a patch alignment mark A; Figure 1 b. Use a high-precision placement machine to pick up the capacitor 3 and place it face down on the set position of the temporary carrier 1 coated with temporary bonding glue 2; Figure 1 c. Perform wafer-level plastic packaging to obtain a first plastic packaging layer 4. The first plastic packaging layer 4 covers the back and side surfaces of the capacitor 3 and has a certain thickness on the back; Figure 1 d. After the plastic packaging, the bonding is removed to separate the first plastic packaging layer 4 embedded in the capacitor 3 and the temporary carrier 1; Figure 1 e. Making a first metal bump 5 (usually a copper pillar bump) on the front surface of the capacitor 3. Conventionally, the insulating layer I1 formed on the front surface of the capacitor 3 is opened and then a metal pillar connected to the pad is made, including sputtering the seed layer, photolithography, electroplating, debonding, etching the seed layer, etc.; Figure 1 f. Slice the capacitors 3 into individual capacitors with first metal bumps 5, thus obtaining capacitor packaging units 100. Electrically test the individual capacitors to select good quality capacitors.

[0038] refer to Figure 2 For the ASIC chip 6, a second metal bump 61 (usually a copper pillar bump) is first made on the upper surface of the chip wafer. Similarly, the insulating layer I2 formed on the front of the ASIC chip 6 is opened and a metal pillar connected to the pad is made. Then, by scribing, a single ASIC chip 6 with the second metal bump 61 is obtained.

[0039] refer to Figure 3 , provide a silicon-based substrate 7 with a patch alignment mark B, and attach a permanent bonding film 8 to the surface of the silicon-based substrate 7. Figure 4, through a high-precision chip mounting system, the ASIC chip 6 with the second metal bump 61 and the capacitor packaging unit 100 are mounted on a set position of the silicon-based substrate 7 with a permanent bonding film 8 attached. Figure 5 , the ASIC chip 6 and the capacitor packaging unit 100 with the second metal bumps 61 are plastic-encapsulated to obtain a second plastic layer 9, forming a so-called reconstructed wafer. Next, the plastic material surface is mechanically polished and thinned to achieve surface flatness, and the first metal bumps 5 and the second metal bumps 61 need to be exposed at the same time. The first metal bumps 5 and the second metal bumps 61 are I / O ports that need to be interconnected or led out on the chip and capacitor. Figure 6 , prepare a multi-layer rewiring layer 10 connecting metal bumps. In order to obtain a high-density wiring layer (line width and line spacing of 5μm / 5μm), an embedded copper wire technology, namely the Damascus inlay process, is used here. Specifically, a dielectric layer is coated on the surface of the wafer using a glue coater, and the dielectric layer is solidified after photolithography patterning. Then a copper seed layer is deposited, and then metal is filled. Finally, chemical mechanical polishing is used to flatten the surface and remove the surface copper. After the rewiring layer 10 is completed, solder bumps 11 are prepared on the metal pads of the rewiring layer 10 by electroplating or ball planting. In order to improve the reliability of the electrical interconnection between the capacitor pad and the copper pillar (the first metal bump 5), three copper pillars are made for each capacitor pad. After the plastic cover is ground thin to expose the copper pillars, a rewiring layer is formed to connect the three copper pillars.

[0040] The materials of the first plastic sealing layer 4 and the second plastic sealing layer 9 can be, for example, epoxy resin plastic sealing compound, and can be the same material or different materials.

[0041] refer to Figure 6 The fan-out packaging structure of a multi-device obtained by the above packaging method includes a silicon-based substrate 7, a permanent bonding film 8 provided on the silicon-based substrate 7, a multi-device plastic package provided on the permanent bonding film 8, and a redistribution layer 10 provided on the multi-device plastic package. The multi-device plastic package includes a plastic packaging material (including the above-mentioned first plastic packaging layer 4 and second plastic packaging layer 9) and a capacitor 3 and an ASIC chip 6 encapsulated in the plastic packaging material. The thickness of the capacitor 3 is smaller than that of the ASIC chip 6. The front faces of the capacitor 3 and the ASIC chip 6 face upward and are located at the same horizontal plane, and are respectively provided with a first metal bump 5 and a second metal bump 61. The capacitor 3 and the ASIC chip 6 are electrically connected to the redistribution layer 10 via the first metal bump 5 and the second metal bump 61. The ASIC chip 6 is attached to the permanent bonding film 8, and there is a certain thickness of plastic packaging material (i.e., the first plastic packaging layer 4) between the capacitor 3 and the permanent bonding film 8, so that the front faces of the two are located at the same horizontal plane.

[0042] In addition, the first component and the second component can also be two other heterogeneous chips with a larger thickness tolerance, or more than two heterogeneous chips. Through multi-level plastic packaging and pre-made metal bumps, they can be located on the same horizontal plane, thereby realizing the formation of a high-density three-dimensional packaging structure of multiple heterogeneous components.

[0043] The above embodiments are only used to further illustrate a fan-out packaging structure of a multi-device and a packaging method thereof of the present invention, but the present invention is not limited to the embodiments. Any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention fall within the protection scope of the technical solution of the present invention.

Claims

1. A fan-out packaging method for a multi-device, characterized in that: The device comprises at least a first component and a second component, wherein the thickness of the first component is smaller than that of the second component, and the packaging method comprises the following steps: 1) Encapsulating a first component in a first plastic encapsulation layer with its front surface exposed, and forming a first metal bump on the front surface to obtain a first component encapsulation unit; forming a second metal bump on the front surface of a second component; the first plastic encapsulation layer covers the back and side surfaces of the first component, and the thickness difference on the back side of the first component is the same as the thickness difference between the first component and the second component; 2) providing a substrate and attaching a permanent bonding film to the substrate; 3) Mounting the first component package unit and the second component with the second metal bump face up on the permanent bonding film; 4) Encapsulating the first component packaging unit and the second component with the second metal bump in a second plastic packaging layer, and grinding and thinning the surface of the second plastic packaging layer until the first metal bump and the second metal bump are exposed; 5) Use embedded copper wire technology to make a redistribution layer on the thinned surface.

2. The packaging method according to claim 1, wherein: The production of the first component packaging unit in step 1) specifically includes: 1.1) Provide a temporary carrier and apply temporary bonding adhesive on the carrier; 1.2) placing a plurality of the first components face downward on a preset position of a temporary carrier coated with temporary bonding glue; 1.3) Performing wafer-level plastic encapsulation on the first component to obtain a first plastic encapsulation layer; 1.4) Debonding to separate the first plastic packaging layer embedded with the first component from the temporary carrier; 1.5) Fabricating the first metal bump on the front surface of the first component; 1.6) Slicing to obtain individual first component packaging units.

3. The packaging method according to claim 1, wherein: The second component is a chip, and the step 1) of forming the second metal bump on the front surface of the second component specifically includes: 1.7) Fabricating a second metal bump on the front side of the second component wafer; 1.8) Slicing to obtain individual second components with second metal bumps.

4. The packaging method according to claim 1, wherein: The first metal bumps and the second metal bumps are manufactured using an electroplating process.

5. The packaging method according to claim 1, wherein: In step 4), the grinding and thinning is performed by mechanical grinding.

6. The packaging method according to claim 1, wherein: In step 6), the embedded copper wire process is to form a dielectric layer on the thinned surface, etch the dielectric layer for patterning, then fill it with metal, and then use a chemical mechanical polishing process to flatten the surface and remove the surface metal to obtain a multi-layer rewiring layer.

7. A fan-out packaging structure of a multi-device obtained by the fan-out packaging method of any one of claims 1 to 6, characterized in that: It includes a substrate, a permanent bonding film provided on the substrate, a multi-component plastic package provided on the permanent bonding film, and a redistribution layer provided on the multi-component plastic package; the multi-component plastic package includes a plastic package material and a first component and a second component encapsulated in the plastic package material; the front surfaces of the first component and the second component face upward and are located on the same horizontal plane, and are respectively provided with a first metal bump and a second metal bump, and the first component and the second component are respectively electrically connected to the redistribution layer through the first metal bump and the second metal bump; the plastic package material includes a first plastic package layer and a second plastic package layer; the thickness of the first component is smaller than that of the second component, the second component is attached to the permanent bonding film, and the first plastic package layer is provided between the first component and the permanent bonding film.

8. The fan-out packaging structure of a multi-device according to claim 7, wherein: The first component is a capacitor, and the second component is an ASIC chip.

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