Redistribution Structure and Method of Forming the Same

Abstract

The present invention discloses a redistribution structure and a method for forming the redistribution structure, including: forming a first redistribution layer and a first compensation line layer that are electrically insulated from each other on a substrate, wherein the first compensation line layer surrounds the first redistribution layer; forming a first dielectric layer on the first redistribution layer and the first compensation line layer; and forming a second redistribution layer and a second compensation line layer that are electrically insulated from each other on the first dielectric layer, wherein the second compensation line layer surrounds the second redistribution layer, the second compensation line layer is connected to the first compensation line layer, and the second redistribution layer is connected to the first redistribution layer.

Description

Technical Field

[0001] The present invention relates to a package and a method for forming the same, and more particularly to a redistribution structure and a method for forming the same. Background Art

[0002] The redistribution layer (RDL) is a key part of the package. The conductor layer of the redistribution layer is usually formed by electroplating. However, when the wafer or substrate size increases, there is often a problem of uneven thickness of the conductor layer between the central region and the edge region. Summary of the Invention

[0003] The present invention provides a redistribution layer and a method for forming the same, which can improve the problem of uneven thickness of the plating layer in a large area.

[0004] According to an embodiment of the present invention, a method for forming a redistribution structure is provided, including: forming a first redistribution layer and a first compensation line layer that are electrically insulated from each other on a substrate, wherein the first compensation line layer surrounds the first redistribution layer; forming a first dielectric layer on the first redistribution layer and the first compensation line layer; and forming a second redistribution layer and a second compensation line layer that are electrically insulated from each other on the first dielectric layer, wherein the second compensation line layer surrounds the second redistribution layer, the second compensation line layer is connected to the first compensation line layer, and the second redistribution layer is connected to the first redistribution layer.

[0005] According to an embodiment of the present invention, a redistribution structure is provided, including: a first redistribution layer and a first compensation line layer that are electrically insulated from each other, wherein the first compensation line layer surrounds the first redistribution layer; a first dielectric layer disposed on the first redistribution layer and the first compensation line layer; and a second redistribution layer and a second compensation line layer that are electrically insulated from each other and disposed on the first dielectric layer, wherein the second compensation line layer surrounds the second redistribution layer, and the second compensation line layer is connected to the first compensation line layer, and the second redistribution layer is connected to the first redistribution layer.

[0006] Based on the above, the embodiment of the present invention can solve the problem of uneven thickness distribution of the plating layer in a large area by providing a compensation line layer. Brief Description of the Drawings

[0007] Figures 1A to 1D is a top view of several samples with a compensation line layer according to an embodiment of the present invention;

[0008] Figure 1E is Figure 1A a three-dimensional schematic diagram of;

[0009] Figures 2A to 2ISchematic cross-sectional view of a method for forming a redistribution structure according to an embodiment of the present invention;

[0010] Figure 2I-1 Schematic cross-sectional view of a redistribution structure according to another embodiment of the present invention;

[0011] Figures 3A to 3F Top views of several embodiments of the present invention having a compensation line layer and a seed layer above it;

[0012] Figure 4 Flowchart of forming a compensation line layer according to an embodiment of the present invention;

[0013] Figures 5A to 5C Cross-sectional view of a manufacturing process of a packaging structure according to an embodiment of the present invention;

[0014] Figure 5D and Figure 5E Cross-sectional views of some other packaging structures according to an embodiment of the present invention;

[0015] Figures 6A to 6C Cross-sectional view of a manufacturing process of another packaging structure according to an embodiment of the present invention. Detailed implementation manners

[0016] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0017] An embodiment of the present invention provides a method for forming a redistribution structure RDLS, including: providing a sample 100. The sample 100 includes a substrate 10. The substrate 10 may be a square temporary substrate, such as glass, such as Figure 1A , Figure 1C , Figure 1D and Figure 1E shown. The substrate 10 may also be a wafer, such as Figure 1B shown. The substrate 10 includes a plurality of packaging units P. The plurality of packaging units P may also be referred to as units to be electroplated.

[0018] Please refer to Figure 1A , Figure 1E and Figure 2A, each encapsulation unit P includes region R1 and region R2. Region R2 is beside region R1. In some embodiments, region R1 is, for example, a die region; region R2 is, for example, a scribe line region. In other embodiments, region R1 is, for example, a die region; region R2 is, for example, a die region adjacent to the scribe line region and does not extend into the scribe line region. In still other embodiments, region R1 is, for example, a die region; region R2 is, for example, a die region adjacent to the scribe line region and extends into the scribe line region. Next, a dielectric layer PM0 is formed on the substrate 10. The dielectric layer PM0 can be a polymer, such as polyimide (PI). The formation method of the dielectric layer PM0 is, for example, spin coating method.

[0019] Thereafter, referring to Figure 1A , Figure 1E , Figure 2A and Figure 2B , a first layer structure T1 is formed on the dielectric layer PM0. The first layer structure T1 includes a redistribution layer RDL1, a compensation line layer COL1, and a dielectric layer PM1. For clarity, Figure 1A , Figure 1B shows the compensation line layer COL1, while the redistribution layer RDL1 and the dielectric layer PM1 are not shown. The formation method of the first layer structure T1 is described as follows.

[0020] Referring to Figure 2A , a seed layer SD1 is formed on the dielectric layer PM0. The seed layer SD1 is a continuous layer, extending from region R1 to R2. The seed layer SD1 can be a single layer or multiple layers, such as a titanium / copper layer. The formation method of the seed layer SD1 is, for example, sputtering method. Next, a patterned mask layer PR1 is formed on the seed layer SD1. The patterned mask layer PR1 is, for example, a patterned photoresist layer. The patterned mask layer PR1 has openings O11 and O12. The opening O11 exposes the seed layer SD1 on region R1. The opening O12 exposes the seed layer SD1 on region R2. Thereafter, conductor layers CL1 are respectively formed on the seed layer SD1 in the openings O11 and O12. The material of the conductor layer CL1 is, for example, copper or copper-aluminum alloy. The formation method of the conductor layer CL1 is, for example, electroplating method.

[0021] Referring to Figure 2B , the patterned mask layer PR1 is removed. After that, the seed layer SD1 not covered by the conductor layer CL1 is removed, so as to form a redistribution layer RDL1 in region R1 and a compensation line layer COL1 in region R2 simultaneously. Then, a dielectric layer PM1 is formed on the redistribution layer RDL1 and the compensation line layer COL1. The material and formation method of the dielectric layer PM1 can be the same as or different from those of the dielectric layer PM0.

[0022] The redistribution layer RDL1 is a functional circuit layer, which includes a plurality of traces t1. The lengths and shapes of these traces t1 are different from each other. The compensation circuit layer COL1 is a non-functional circuit layer. The compensation circuit layer COL1 is a continuous structure, which is located around the redistribution layer RDL1. In an embodiment of the present invention, the compensation circuit layer COL1 and the redistribution layer RDL1 are electrically insulated from each other. The compensation circuit layer COL1 is, for example, a continuous mesh structure composed of a plurality of compensation circuits that intersect each other, as shown in Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E . The mesh structure can be closed, as shown in Figure 1A , Figure 1B , Figure 1D and Figure 1E . The mesh structure can also be non-closed, as shown in Figure 1C .

[0023] In Figure 1A , Figure 1D and Figure 1E , the compensation circuit layer COL1 is in a mesh structure, and the size or shape of each grid is the same. That is to say, the compensation circuit layer COL1 has a regular pattern. A regular pattern refers to a pattern with a plurality of repeating units. The redistribution layer RDL1 (not shown) of each packaging unit P is located within the grid of each mesh structure. However, the embodiments of the present invention are not limited thereto. The size or shape of each grid of the mesh structure is not limited to being the same, and the size and shape of each grid of the mesh structure can also be different (as shown in Figure 1C ). In addition, a single compensation circuit can be provided in each region R2 (as shown in Figure 1A and Figure 2B ). Multiple compensation circuits can also be provided in each region R2 (as shown in Figure 1C ). In some embodiments, a single compensation circuit is provided in each region R2, so that the redistribution layer RDL1 of each packaging unit P is surrounded by the grid of the compensation circuit layer COL1 (as shown in Figure 1A , Figure 1E ). However, the embodiments of the present invention are not limited thereto. In other embodiments, it is also possible that a single compensation circuit is provided in multiple regions R2, so that the redistribution layers RDL1 of multiple regions R1 are surrounded by the grid of a compensation circuit layer COL1 (as shown in Figure 1D ).

[0024] After that, refer to Figures 2C to 2E, after forming the dielectric layer PM1, a second layer structure T2 is formed on the dielectric layer PM1. The second layer structure T2 includes a redistribution layer RDL2, a compensation line layer COL2, and a dielectric layer PM2. The formation method of the second layer structure T2 is described as follows.

[0025] Referring to Figure 2C , the dielectric layer PM1 is patterned to form via openings VO21 and VO22 in the dielectric layer PM1. In region R1, the dielectric layer PM1 covers most of the top surface of the conductor layer CL1 of the redistribution layer RDL1; the via opening VO21 exposes a small part of the top surface of the conductor layer CL1 of the redistribution layer RDL1. In region R2, the dielectric layer PM1 covers a small part or does not cover the top surface of the conductor layer CL1 of the compensation line layer COL1; the via opening VO22 exposes most or all of the top surface of the conductor layer CL1 of the compensation line layer COL1. The ratio of the area of the top surface of the conductor layer CL1 of the redistribution layer RDL1 exposed by the via opening VO21 to the area of the top surface of all the conductor layers CL1 of the redistribution layer RDL1 is R21. The ratio of the area of the top surface of the conductor layer CL1 of the compensation line layer COL1 exposed by the via opening VO22 to the area of the top surface of all the conductor layers CL1 of the compensation line layer COL1 is R22. The ratio R22 is greater than the ratio R21. The ratio R21 is, for example, 1% to 49%. The ratio R22 is, for example, 50% to 100%.

[0026] Next, referring to Figure 2D , a seed layer SD2 is formed on the dielectric layer PM1 and in the via openings VO21 and VO22. The seed layer SD2 is a continuous layer extending from region R1 to R2. The seed layer SD2 can be a single layer or multiple layers, for example, a titanium / copper layer. The shape of the seed layer SD2 on the bottom surface of the via opening VO22 can be exactly the same as, partially the same as, or completely different from the shape of the conductor layer CL1 in region R2. The seed layer SD2 on the bottom surface of the via opening VO22 and the underlying conductor layer CL1 can be completely overlapped or partially overlapped. The seed layer SD2 on the bottom surface of the via opening VO22 can be a continuous layer or a discontinuous layer. The seed layer SD2 on the bottom surface of the via opening VO22 can have a single width, multiple widths, or a tapered width.

[0027] Figures 3A to 3F The structure of various seed layers SD2 located on the bottom surface of the via opening VO22 is described by taking the conductor layer CL1 of the compensation line layer COL1 in region R2 as a mesh structure, but the embodiments of the present invention are not limited thereto.

[0028] Please refer to Figure 2C , Figure 2D , Figures 3A to 3F, the seed layer SD2 on the bottom surface of the via opening VO22 can completely cover (as shown in Figure 3A ) or partially cover (as shown in Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F ) the conductor layer CL1 of the compensation line layer COL1. The shape of the seed layer SD2 on the bottom surface of the via opening VO22 can be exactly the same as (as shown in Figure 3A ), similar to (as shown in Figure 3B ), partially similar to (as shown in Figure 3C , Figure 3E ) or completely different from (as shown in Figure 3D , Figure 3F ) the shape of the conductor layer CL1 of the compensation line layer COL1.

[0029] The width of the seed layer SD2 on the bottom surface of the via opening VO22 can be exactly the same as (as shown in Figure 3A , Figure 3F ), partially the same and partially different (as shown in Figure 3E ) or completely different from (as shown in Figure 3B , Figure 3C , Figure 3D ) the width of the conductor layer CL1 of the compensation line layer COL1. The seed layer SD2 on the bottom surface of the via opening VO22 can be a continuous layer (as shown in Figure 3A , Figure 3B , Figure 3D , Figure 3E , Figure 3F ) or a discontinuous layer (as shown in Figure 3C ).

[0030] The seed layer SD2 on the bottom surface of the via opening VO22 can have a single width (as shown in Figure 3A , Figure 3B , Figure 3C , Figure 3F ), multiple widths (as shown in Figure 3E ) or a gradually changing width (as shown in Figure 3D ). In Figure 3D , the width of the seed layer SD2 on the bottom surface of the via opening VO22 gradually decreases from the center to the periphery, but is not limited to this. In Figure 3E , the width of the seed layer SD2 on the bottom surface of the via opening VO22 decreases in a gradient from the center to the periphery, but is not limited to this. The width of the seed layer SD2 on the bottom surface of the via opening VO22 can also increase in a gradient from the center to the periphery. The width of the seed layer SD2 on the bottom surface of the via opening VO22 can also gradually increase from the center to the periphery. The shape of the seed layer SD2 on the bottom surface of the via opening VO22 and the situation of its overlap with the underlying conductor layer CL1 are not limited to those described above.

[0031] Next, referring to Figure 2D , after the seed layer SD2 is formed, a patterned mask layer PR2 is formed on the seed layer SD2. The patterned mask layer PR2 is, for example, a patterned photoresist layer. The patterned mask layer PR2 has openings O21 and O22. The opening O21 exposes the seed layer SD2 on the region R1. The opening O22 exposes the seed layer SD2 on the region R2. Thereafter, conductor layers CL2 are respectively formed on the seed layer SD2 in the openings O21 and O22. The material of the conductor layer CL2 is, for example, copper or a copper-aluminum alloy. The method for forming the conductor layer CL2 is, for example, an electroplating method.

[0032] During the process of forming the conductor layer CL2, the seed layer SD2 can be electrically connected to the underlying compensation line layer COL1. Since the thickness of the compensation line layer COL1 is greater than the thickness of the seed layer SD2 and its resistance value is lower than that of the seed layer SD2, it is possible to improve or avoid a large voltage drop due to the fact that the central region is far from the electrode fixture and the seed layer has a large resistance. In other words, the compensation line layer COL1 can reduce the pressure difference between the central region and the edge region of the sample during the electroplating process, thereby reducing the thickness difference between the conductor layer CL2 formed in the central region and the conductor layer CL2 formed in the edge region.

[0033] Referring to Figure 2E , the patterned mask layer PR2 is removed. Thereafter, the seed layer SD2 not covered by the conductor layer CL2 is removed to simultaneously form a redistribution layer RDL2 in the region R1 and a compensation line layer COL2 in the region R2. Then, a dielectric layer PM2 is formed on the dielectric layer PM1, the redistribution layer RDL2, and the compensation line layer COL2.

[0034] The redistribution layer RDL2 is a functional circuit layer, which includes a plurality of traces t2 and a plurality of vias v2. The lengths or shapes of these traces t2 are different from each other. The plurality of vias v2 are connected to the traces t1 of the underlying redistribution layer RDL1 via the vias v2. The compensation line layer COL2 is a non-functional circuit layer. The compensation line layer COL2 is a continuous structure (such as a continuous mesh structure) or a discontinuous structure (such as a discontinuous mesh structure), which is located around the redistribution layer RDL2 and is electrically insulated from the redistribution layer RDL2 and the redistribution layer RDL1. The bottom surface of the compensation line layer COL2 contacts and overlaps with the top surface of the compensation line layer COL1 in a proportion greater than the proportion of the bottom surface of the redistribution layer RDL2 contacting and overlapping with the top surface of the redistribution layer RDL1. In some embodiments, the proportion of the bottom surface of the compensation line layer COL2 contacting and overlapping with the top surface of the compensation line layer COL1 is 50% to 100%.

[0035] After that, referring to Figures 2F to 2I, a pad CP electrically connected to the redistribution layer RDL2 is formed on the dielectric layer PM2. The method for forming the pad CP is described as follows.

[0036] Referring to Figure 2F , the dielectric layer PM2 is patterned to form via openings VO31 and VO32 in the dielectric layer PM2. In region R1, the dielectric layer PM2 covers most of the top surface of the conductor layer CL2 of the redistribution layer RDL2; the via opening VO31 exposes a small part of the top surface of the conductor layer CL2 of the redistribution layer RDL2. In region R2, the dielectric layer PM2 covers a small part or does not cover the top surface of the conductor layer CL2 of the compensation line layer COL2; the via opening VO32 exposes most or all of the top surface of the conductor layer CL2 of the compensation line layer COL2. The ratio of the area of the top surface of the conductor layer CL2 of the redistribution layer RDL2 exposed by the via opening VO31 to the area of the top surface of all the conductor layers CL2 of the redistribution layer RDL2 is R31. The ratio of the area of the top surface of the conductor layer CL2 of the compensation line layer COL2 exposed by the via opening VO32 to the area of the top surface of all the conductor layers CL2 of the compensation line layer COL2 is R32. The ratio R32 is greater than the ratio R31. The ratio R31 is, for example, 1% to 49%. The ratio R32 is, for example, 50% to 100%.

[0037] Next, referring to Figure 2G , a seed layer SD3 is formed on the dielectric layer PM2 and in the via openings VO31 and VO32. The seed layer SD3 is a continuous layer extending from region R1 to R2. The seed layer SD3 can be a single layer or multiple layers, such as a titanium / copper layer. The shape of the seed layer SD3 on the bottom surface of the via opening VO32 can be exactly the same as, partially the same as, or completely different from the shape of the conductor layer CL2 in region R2. The seed layer SD3 on the bottom surface of the via opening VO32 and the underlying conductor layer CL2 can be completely overlapped or partially overlapped. The seed layer SD3 on the bottom surface of the via opening VO32 can be a continuous layer or a discontinuous layer. The seed layer SD3 on the bottom surface of the via opening VO32 can have a single width, multiple widths, or a tapered width.

[0038] Next, referring to Figure 2H , after the seed layer SD3 is formed, a patterned mask layer PR3 is formed on the seed layer SD3. The patterned mask layer PR3 is, for example, a patterned photoresist layer. The patterned mask layer PR3 has an opening O31. The opening O31 exposes the seed layer SD3 on region R1. The seed layer SD3 on region R2 is covered by the patterned mask layer PR3 and not exposed.

[0039] Thereafter, a conductor layer CL3 is formed on the seed layer SD3 of the opening O31. The material of the conductor layer CL3 is, for example, copper or a copper-aluminum alloy. The method of forming the conductor layer CL3 is, for example, electroplating. During the formation of the conductor layer CL3, it can be connected to the underlying compensation line layer COL1 through the seed layer SD3 and the compensation line layer COL2. Since the thickness of the compensation line layer COL2 and the compensation line layer COL1 is greater than the thickness of the seed layer SD3, and its resistance value is lower than that of the seed layer SD3, therefore, the pressure difference between the central region and the edge region of the sample can be reduced, and further the thickness difference between the conductor layer CL3 formed in the central region and the conductor layer CL3 formed in the edge region can be reduced.

[0040] Refer to Figure 2I , remove the patterned mask layer PR3. Thereafter, remove the seed layer SD3 not covered by the conductor layer CL3 to form a pad CP in the region R1, and expose the conductor layer CL2 of the compensation line layer COL2 in the via opening VO32 in the region R2. In some embodiments, the pad CP can protrude from the top surface of the dielectric layer PM2 without covering the top surface of the dielectric layer PM2, which can also be referred to as a bump, as Figure 2I shown. In other embodiments, the pad CP can protrude from the top surface of the dielectric layer PM2 and cover the top surface of the dielectric layer PM2, which can also be referred to as an under-bump metal (UBM), as Figure 2I-1 shown.

[0041] Please refer to Figure 1A and Figure 2B , in the embodiments of the present invention, the compensation line layer COL1 and the redistribution layer RDL1 have substantially the same thickness. The compensation line layer COL2 and the redistribution layer RDL2 have substantially the same thickness. The resistance values of the compensation line layers COL1 and COL2 are inversely proportional to their line widths and thicknesses. When the line widths and thicknesses of the compensation line layers COL1 and COL2 are larger, the resistance values of the compensation line layers COL1 and COL2 are lower. In addition, the line widths of the compensation line layers COL1 and COL2 are related to the width ratio of the compensation line layers COL1 and COL2. For simplicity, the width ratio O of the compensation line layer COL1 is used as an example to illustrate the compensation line layer COL1 below cc .

[0042] Refer to Figure 1A and 2B , the line width W of the compensation line layer COL1 is proportional to the width ratio O of the compensation line layer COL1 cc . When the width ratio O cc is larger, it means that the line width W of the compensation line layer COL1 is larger and the resistance value R of the compensation line layer COL1 is lower. When the width ratio O ccThe smaller the [value], the smaller the line width W of the compensation line layer COL1 and the larger the resistance value R of the compensation line layer COL1. In some embodiments where the sample has a long side and a short side, the width ratio O of the compensation line layer COL1 cc is the sum of the widths W of all the compensation lines of the long side of the compensation line layer COL1 divided by the length L of the long side of the sample. In some embodiments, all the compensation lines on the long side of the compensation line layer COL1 have the same width W, then the width ratio O cc can be defined as follows:

[0043] O cc = W × N / L

[0044] where

[0045] W is the width of each compensation line on the long side of the compensation line layer COL1;

[0046] N is the number of compensation lines of the compensation line layer COL1; and

[0047] L is the length of the long side of the sample.

[0048] The uniformity of the thickness distribution of the conductor layer CL2 formed by electroplating is related to the parameters of the compensation line layer COL1 below it. The parameters of the compensation line layer COL1 include the thickness t of the conductor layer CL1 of the compensation line layer COL1 and the width ratio O cc . The larger the thickness t of the conductor layer CL1 of the compensation line layer COL1, the smaller the reaction current difference and the pressure difference between the central region and the edge region of the sample during electroplating of the conductor layer CL2, so the thickness difference of the conductor layer CL2 formed in the central region and the edge region of the sample is also smaller. The width ratio O of the compensation line layer COL1 cc The larger it is, the smaller the reaction current difference and the pressure difference between the central region and the edge region of the sample during electroplating of the conductor layer CL2, and the smaller the thickness difference of the conductor layer CL2 formed in the central region and the edge region of the sample. In other words, the larger the product of the thickness t and the width ratio O cc , the smaller the reaction current difference and the pressure difference between the central region and the edge region of the sample during electroplating of the conductor layer CL2, and thus the smaller the thickness difference of the conductor layer CL2 formed in the central region and the edge region of the sample. In some embodiments, the width ratio O of the compensation line layer COL1 cc is 0.1 to 5%, the thickness t is 1 to 20 micrometers (μm), and the product of the thickness t and the width ratio O of the compensation line layer COL1 cc is between 0.001 and 1 μm. In other embodiments, the product of the thickness t and the width ratio O of the compensation line layer COL1 ccThe product is between 0.005 and 0.5 μm. In some other embodiments, the thickness t of the compensation line layer COL1 and the width ratio O cc The product is between 0.08 and 0.16 μm.

[0049] Furthermore, the uniformity of the thickness distribution of the conductor layer CL2 is also related to system parameters. System parameters include the resistance value of the seed layer SD2, the size of the sample, and the applied current. The greater the resistance value of the seed layer SD2, the greater the voltage drop difference between the central region and the edge region of the sample during electroplating of the conductor layer CL2, and the greater the thickness difference of the conductor layer CL2 formed in the central region and the edge region of the sample. The larger the size of the sample, the greater the voltage drop difference between the central region and the edge region of the sample during electroplating of the conductor layer CL2, and the greater the thickness difference of the conductor layer CL2 formed in the central region and the edge region of the sample. The greater the applied current, the greater the voltage drop difference between the central region and the edge region, and the greater the thickness difference of the conductor layer CL2 formed in the central region and the edge region. In addition, the greater the conductivity of the plating solution, the smaller the voltage drop difference between the central region and the edge region of the sample during electroplating of the conductor layer CL2, and the smaller the thickness difference of the conductor layer CL2 formed in the central region and the edge region of the sample. In some embodiments, the resistance value of the seed layer SD2 is between 0.1 and 10 Ω / sq. The size of the sample is between 300 millimeters (mm) and 1300 mm. The applied current is 5 to 10 amperes.

[0050] The uniformity of the thickness distribution of the conductor layer CL2 is also related to the parameters of the plating solution. The higher the conductivity of the plating solution, the smaller the voltage drop difference between the central region and the edge region of the sample during electroplating of the conductor layer CL2, and the smaller the thickness difference of the conductor layer CL2 formed in the central region and the edge region of the sample. The conductivity of the plating solution is, for example, between 20 and 50 S / m.

[0051] The thickness t of the conductor layer CL1 of the compensation line layer COL1 and the width ratio O of the compensation line layer COL1 in the embodiments of the present invention cc can be formed according to Figure 4 the flowchart of

[0052] Referring to Figure 4 , in step S10, various parameters are provided. Step S10 may include providing electroplating system parameters, step S11. The electroplating system parameters include the cathode / anode distance, the size of the cathode sample, the resistance value of the seed layer, and the applied current (ASD), etc. In some embodiments, the material parameters of the plating solution are further provided, step S12. The material parameters of the plating solution may include conductivity, Tafel slope, exchange current density, etc. The Tafel slope refers to A in the Tafel equation. The Tafel equation gives the relationship between the reaction rate of the electrode reaction and the overpotential.

[0053]

[0054] Wherein

[0055] η: overpotential

[0056] A: Tafel slope (volts)

[0057] i: current density (A / m 2 )

[0058] i0: exchange current density (A / m 2 )

[0059] Step S14, according to Step S10, calculate the sample voltage difference. The sample voltage difference refers to the voltage difference between the central region and the edge region.

[0060] Step S16, establish the relationship between the thickness t and the width ratio O of the compensation line layer COL1 cc with the sample voltage drop. In some embodiments, the product of the thickness t and the width ratio O cc of the compensation line layer COL1 is between 0.001 and 1 μm, and the sample voltage difference can be controlled between 0.2 and 0.026 V (volts), so that the thickness difference of the electroplated conductor layer between the central region and the edge region is less than 20%.

[0061] Step S18, if there is a predetermined thickness of the compensation line layer COL1, the layout design can be carried out according to the width ratio of the compensation line layer COL1 corresponding to the target thickness of the compensation line layer COL1.

[0062] Step S20, import the designed layout into the process.

[0063] The method for forming the redistribution structure according to the embodiment of the present invention can be used in the front-chip process. The front-chip process means that the redistribution structure according to the embodiment of the present invention can be formed on the chip and the encapsulation layer after the chip is encapsulated by the encapsulation layer. In other words, between Figure 2A the substrate 10 and the dielectric layer PM0, there are further components or chips and an encapsulation layer. The components or chips are electrically connected to the redistribution layer RDL1, but are electrically insulated from the compensation line layer COL1. The method for forming the redistribution structure according to the embodiment of the present invention can also be used in the back-chip process. The back-chip process means that after the redistribution structure according to the embodiment of the present invention is formed on the substrate, the chip and the encapsulation layer are formed on the redistribution structure, as shown in Figures 5A to 5E and Figures 6A to 6C shown.

[0064] In addition, after the above-described redistribution line structure RDLS is bonded to the die and encapsulated, after the dicing process is completed, depending on the position of the defined region R2, the compensation line layer COL2 and the compensation line layer COL1 may be completely retained, partially retained, or completely removed.

[0065] Please refer to Figure 5A , and bond the connection terminal CT1 on the under bump metallization UBM1 of the die D1 to the pad CP of the redistribution line structure RDLS. Then, an underfill UF is filled between the dielectric layer PM2 and the die D1. The underfill UF may cover the under bump metallization UBM1, the connection terminal CT1, and the passivation layer PA of the die D1, and even cover the sidewalls of the die D1. The underfill UF also covers the sidewalls of the pad CP and the top surface of the dielectric layer PM2. In some embodiments, the top surface of the compensation line layer COL2 is not covered by the underfill UF, as shown in Figure 5A . In some other embodiments, the top surface of the compensation line layer COL2 is covered by the underfill UF, as shown in Figure 6A .

[0066] Please refer to Figure 5B and Figure 6B , and an encapsulation layer EC is formed on the pad CP of the redistribution line structure RDLS to laterally encapsulate the sidewalls of the die D1. In some embodiments, the top surfaces of the dielectric layer PM2 and the compensation line layer COL2 are covered by the encapsulation layer EC, and cover the top surface of the die D1, as shown in Figure 5B . In some other embodiments, the top surfaces of the dielectric layer PM2 and the compensation line layer COL2 are covered by the encapsulation layer EC, but the die D1 is exposed. The top surface of the encapsulation layer EC may be flush with the die D1, as shown by the dashed line in Figure 5B . In some embodiments, the top surface of the dielectric layer PM2 is covered by the encapsulation layer EC, and cover the top surface of the die D1, as shown in Figure 6B . In some other embodiments, the top surface of the dielectric layer PM2 is covered by the encapsulation layer EC, but the die D1 is exposed. The top surface of the encapsulation layer EC may be flush with the die D1, as shown by the dashed line in Figure 6B .

[0067] Please refer to Figure 5C , Figure 5D , Figure 5E and Figure 6C , and a dicing process is performed to form a plurality of separated package structures P1. In some embodiments, the compensation line layer COL2 is removed, such that the package structure P1 does not include the compensation line layers COL1 and COL2, as shown in Figure 5CAs shown. In some other embodiments, the compensation line layers COL1 and COL2 are retained such that the encapsulation structure P1 includes the compensation line layer COL2, as Figure 5D and Figure 6C shown. In other embodiments, the compensation line layers COL1 and COL2 are partially removed such that the encapsulation structure P1 includes partial compensation line layers COL1 and COL2, as Figure 5E shown.

[0068] In addition, the substrate 10 can be removed during the manufacturing process or retained in the final encapsulation structure P1. Experimental Examples 1 to 4

[0069] Provide 3.5-generation (G3.5) panel samples. The size of the samples is 600 mm × 720 mm. Mesh compensation line layers and redistribution layers with different thicknesses and different width ratios have been formed on the surfaces of the samples, and dielectric layers have been formed on the compensation line layers and the redistribution layers. In addition, vias exposing the compensation line layers and the redistribution layers have been formed in the dielectric layers. Titanium / copper seed layers with a sheet resistance of 1 Ω / square have been formed in and on the vias and the dielectric layer. Then, a copper plating process is carried out. The copper plating process reacts with an electroplating solution having a conductivity of 35 S / m, a Tafel slope of 1.5, and an exchange current density i0 of 0.3 amperes per square meter (A / m 2 ), and the anodic current output is set to 70 amperes (i.e., full-panel electroplating of the sample at 1.6 ASD), and the overvoltage is 0.45 volts for the reaction. The results are shown in Table 1.

[0070] Comparative Example 1

[0071] The copper plating process is carried out in a method similar to that of Experimental Example 1. However, before the copper plating process, the sample surface has a redistribution layer but no compensation line layer. The results are shown in Table 1.

[0072] Table 1

[0073]

[0074]

[0075] The results in Table 1 show that: for the 3.5-generation sample without a compensation line layer, the obtained pressure difference is 0.854 volts (Comparative Example 1). For the 3.5-generation sample with a compensation line layer, the obtained pressure difference can be reduced from 0.854 volts to 0.401 volts (Experimental Example 1). When the thickness t of the compensation line layer is 10 μm and the width ratio O cc is 1%, the obtained pressure difference is 0.285 volts, and the thickness difference of the formed degree is less than 20% (Experimental Example 2). When the thickness t of the compensation line layer is 10 μm and the width ratio O ccIt is 2%, the resulting pressure difference is 0.199 volts, and the thickness difference of the formed degree is less than 10% (Experimental Example 3).

[0076] Experimental Examples 5 to 9

[0077] Samples of 2.5 generations (G2.5) are provided. The size of the sample is 370 mm × 470 mm. On the surface of the sample, a mesh compensation circuit layer and a redistribution layer with different thicknesses but the same width ratio have been formed, and a dielectric layer has been formed on the compensation circuit layer and the redistribution layer. In addition, vias exposing the compensation circuit layer and the redistribution layer have been formed in the dielectric layer. A titanium / copper seed layer with a sheet resistance of 0.2 Ω / sq has been formed in and on the vias and the dielectric layer. Then, a copper plating process is carried out. The copper plating process reacts with an electroplating solution having a conductivity of 35 S / m, a Tafel slope of 1.5, and an exchange current density i0 of 0.3 A / m 2 and sets the anode current output to 25 amperes and the overvoltage to 0.45 volts for reaction. The results are shown in Table 2.

[0078] Comparative Example 2

[0079] The copper plating process is carried out in a method similar to that of Experimental Example 5. However, before the copper plating process, the sample surface has a redistribution layer but no compensation circuit layer. The results are shown in Table 2.

[0080] Table 2

[0081]

[0082]

[0083] The results in Table 2 show that for the 2.5-generation sample without a compensation circuit layer, the resulting pressure difference is 0.238 volts (Comparative Example 2). For the 2.5-generation sample with a compensation circuit layer, the resulting pressure difference can be reduced from 0.238 volts to 0.0096 volts.

[0084] In the embodiment of the present invention, a compensation circuit layer is formed around the lower redistribution layer so that the seed layer of the subsequently formed upper redistribution layer can be electrically connected to the compensation circuit layer. Compared with the seed layer, since the compensation circuit layer has a larger thickness and a lower resistance value, it is possible to avoid a large voltage drop due to the relatively long distance of the central region from the electrode fixture and the relatively large resistance of the seed layer. In other words, through the compensation circuit layer, the pressure difference between the central region and the edge region of the sample during electroplating can be reduced, thereby improving the thickness uniformity of the conductor layer in the central region and the edge region.

[0085] In summary, the embodiment of the present invention can solve the problem of uneven thickness distribution of the plating layer during large-area electroplating through the compensation circuit layer.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for forming a redistribution structure, characterized in that Comprising: Forming a first redistribution layer and a first compensation circuit layer that are electrically insulated from each other on a substrate, wherein the first compensation circuit layer surrounds the first redistribution layer; Forming a first dielectric layer on the first redistribution layer and the first compensation circuit layer; And Forming a second redistribution layer and a second compensation circuit layer that are electrically insulated from each other on the first dielectric layer, wherein the second compensation circuit layer surrounds the second redistribution layer, the second compensation circuit layer is connected to the first compensation circuit layer, and the second redistribution layer is connected to the first redistribution layer, wherein the product of the thickness of the first compensation circuit layer and the width ratio of the first compensation circuit layer is between 0.001 and 1 μm, and the width ratio of the first compensation circuit layer is the ratio of the sum of the widths of all the compensation circuits on the long side of the first compensation circuit layer to the length of the long side of the first compensation circuit layer.

2. The method for forming a redistribution structure according to claim 1, wherein the first compensation circuit layer and the second compensation circuit layer are disposed in or around a dicing street.

3. The method for forming a redistribution structure according to claim 1, wherein the second compensation circuit layer completely or partially overlaps with the first compensation circuit layer.

4. A method for forming a redistribution structure, characterized in that Comprising: Forming a first redistribution layer and a first compensation circuit layer that are electrically insulated from each other on a substrate, wherein the first compensation circuit layer surrounds the first redistribution layer; Forming a first dielectric layer on the first redistribution layer and the first compensation circuit layer; And Forming a second redistribution layer and a second compensation circuit layer that are electrically insulated from each other on the first dielectric layer, wherein the second compensation circuit layer surrounds the second redistribution layer, the second compensation circuit layer is connected to the first compensation circuit layer, and the second redistribution layer is connected to the first redistribution layer, wherein forming the first redistribution layer and the first compensation circuit layer on the substrate comprises: Forming a dielectric layer on the substrate; Forming a first seed layer on the dielectric layer; Forming a patterned mask layer on the first seed layer, the patterned mask layer having a first opening and a second opening, and forming a first conductor layer of the first redistribution layer and a first conductor layer of the first compensation circuit layer on the first seed layer in the first opening and the second opening respectively; Removing the patterned mask layer; and Removing the first seed layer that is not covered by the first conductor layer of the first redistribution layer and the first conductor layer of the first compensation circuit layer.

5. A method for forming a redistribution structure, characterized in that, Comprising: Forming a first redistribution layer and a first compensation circuit layer that are electrically insulated from each other on a substrate, wherein the first compensation circuit layer surrounds the first redistribution layer; Forming a first dielectric layer on the first redistribution layer and the first compensation circuit layer; And Forming a second redistribution layer and a second compensation circuit layer that are electrically insulated from each other on the first dielectric layer, wherein the second compensation circuit layer surrounds the second redistribution layer, the second compensation circuit layer is connected to the first compensation circuit layer, and the second redistribution layer is connected to the first redistribution layer, Forming the second redistribution layer and the second compensation line layer on the first dielectric layer includes: Forming a first via opening and a second via opening in the first dielectric layer, wherein the first via opening exposes the first redistribution layer and the second via opening exposes the first compensation line layer; Forming a second seed layer on the first dielectric layer and in the first via opening and the second via opening; Forming a first patterned mask layer on the second seed layer, wherein the first patterned mask layer has a third opening and a fourth opening, the third opening exposes the second seed layer on the first redistribution layer, and the fourth opening exposes the second seed layer on the first compensation line layer; Forming a second conductor layer of the second redistribution layer and a second conductor layer of the second compensation line layer on the second seed layer in the third opening and in the fourth opening; Removing the first patterned mask layer; and Removing the second seed layer not covered by the second conductor layer of the second redistribution layer and the second conductor layer of the second compensation line layer.

6. The method of forming a redistribution structure according to claim 5, wherein forming the first redistribution layer and the first compensation line layer on the substrate includes: Forming a dielectric layer on the substrate; Forming a first seed layer on the dielectric layer; Forming a patterned mask layer on the first seed layer, the patterned mask layer having a first opening and a second opening, and forming a first conductor layer of the first redistribution layer and a first conductor layer of the first compensation line layer on the first seed layer in the first opening and the second opening respectively; Removing the patterned mask layer; And Removing the first seed layer not covered by the first conductor layer of the first redistribution layer and the first conductor layer of the first compensation line layer, wherein the second ratio is greater than the first ratio, the second ratio is the ratio of the area of the top surface of the first conductor layer of the first compensation line layer exposed by the second via opening to the area of the top surface of the first conductor layer of the first compensation line layer, and the first ratio is the ratio of the area of the top surface of the first conductor layer of the first redistribution layer exposed by the first via opening to the area of the top surface of the first conductor layer of the first redistribution layer.

7. The method of forming a redistribution structure according to claim 5, further comprising: Forming a second dielectric layer on the second redistribution layer and the second compensation line layer; Forming a third via opening and a fourth via opening in the second dielectric layer, wherein the third via opening exposes the second redistribution layer and the fourth via opening exposes the second compensation line layer; Forming a third seed layer on the second dielectric layer and in the third via opening and the fourth via opening; Forming a second patterned mask layer on the third seed layer, wherein the second patterned mask layer has a fifth opening, and the fifth opening exposes the third seed layer on the second redistribution layer; Form a third conductor layer in the fifth opening; Remove the second patterned mask layer; And Remove the third seed layer not covered by the third conductor layer, exposing the second dielectric layer and the second compensation line layer exposed by the fourth through-hole opening.

8. The method for forming a rewiring structure according to claim 7, wherein the fourth ratio is greater than the third ratio, the fourth ratio is the ratio of the area of the top surface of the second conductor layer of the second compensation line layer exposed by the fourth through-hole opening to the area of the top surface of the second conductor layer of the second compensation line layer, and the third ratio is the ratio of the area of the top surface of the second conductor layer of the second rewiring layer exposed by the third through-hole opening to the area of the top surface of the second conductor layer of the second rewiring layer.

9. A redistribution structure, characterized in that, Comprising: A first rewiring layer and a first compensation line layer, electrically insulated from each other, wherein the first compensation line layer surrounds the first rewiring layer; A first dielectric layer on the first rewiring layer and the first compensation line layer; and A second rewiring layer and a second compensation line layer, electrically insulated from each other, disposed on the first dielectric layer, wherein the second compensation line layer surrounds the second rewiring layer, and the second compensation line layer is connected to the first compensation line layer, and the second rewiring layer is connected to the first rewiring layer, Wherein the product of the thickness of the first compensation line layer and the width ratio of the first compensation line layer is between 0.001 and 1 μm, and the width ratio of the first compensation line layer is the ratio of the sum of the widths of all the compensation lines on the long side of the first compensation line layer to the length of the long side of the first compensation line layer.

10. The rewiring structure according to claim 9, wherein the overlapping ratio of the bottom surface of the second compensation line layer and the top surface of the first compensation line layer is greater than the overlapping ratio of the bottom surface of the second rewiring layer and the top surface of the first rewiring layer.

11. The rewiring structure according to claim 9, wherein the first compensation line layer and the second compensation line layer have regular patterns.

12. The rewiring structure according to claim 9, wherein the first compensation line layer has a continuous mesh structure, and the second compensation line layer has a continuous mesh structure.

13. The rewiring structure according to claim 9, wherein the first compensation line layer has a continuous mesh structure, and the second compensation line layer has a discontinuous mesh structure.

14. The rewiring structure according to claim 9, wherein the first compensation line layer and the second compensation line layer are disposed in or around the scribe lane.

15. The rewiring structure according to claim 9, further comprising: A second dielectric layer on the second rewiring layer, exposing the top surface of the second compensation line layer; And A solder pad on the second dielectric layer, connected to the second rewiring layer.

16. The redistribution structure according to claim 15, wherein the second redistribution layer is connected to the chip through the solder pad, and the chip is electrically insulated from the first compensation circuit layer and the second compensation circuit layer.

17. The redistribution structure according to claim 16, wherein the top surface of the second dielectric layer, the top surface of the second compensation circuit layer, and the sidewalls of the chip are covered by an encapsulation layer.

18. The redistribution structure according to claim 16, wherein the top surface of the second dielectric layer and the top surface of the second compensation circuit layer are covered by underfill.

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